From 7d121a8ea4e0dbf0d7e105b57c3dbd7d8bd2e729 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 28 Oct 2018 14:26:12 -0700 Subject: sunxi: use 6MHz PLL_VIDEO step for DE2 for higher resolution LCD DE2 SoCs can support LCDs up to 1080p (e.g. A64), and 3MHz step won't let PLL_VIDEO be high enough for them. Use 6MHz step for PLL_VIDEO when using DE2, to satisfy 1080p LCD. Signed-off-by: Icenowy Zheng Signed-off-by: Vasily Khoruzhick Tested-by: Vasily Khoruzhick Acked-by: Maxime Ripard Acked-by: Jagan Teki --- arch/arm/mach-sunxi/clock_sun6i.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/mach-sunxi') diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 82f6f7f8e3..1628f3a7b6 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -149,7 +149,11 @@ void clock_set_pll3(unsigned int clk) { struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; +#ifdef CONFIG_SUNXI_DE2 + const int m = 4; /* 6 MHz steps to allow higher frequency for DE2 */ +#else const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */ +#endif if (clk == 0) { clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); -- cgit v1.2.1