From a0410a6ff21ebba29a1ac46db891867dcd21ed82 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 26 Apr 2018 10:09:06 +0200 Subject: ARM: renesas: Add R8A77990 E3 SoC ID Add ID and Kconfig entry for the Renesas R8A77990 E3 SoC. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/mach-rmobile/Kconfig.64 | 3 +++ arch/arm/mach-rmobile/cpu_info.c | 1 + arch/arm/mach-rmobile/include/mach/rmobile.h | 1 + 3 files changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 6112d79f0d..6b93d25358 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -12,6 +12,9 @@ config R8A7796 config R8A77970 bool "Renesas SoC R8A77970" +config R8A77990 + bool "Renesas SoC R8A77990" + config R8A77995 bool "Renesas SoC R8A77995" diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index 4e6a191cb1..e110737471 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -59,6 +59,7 @@ static const struct { { RMOBILE_CPU_TYPE_R8A7796, "R8A7796" }, { RMOBILE_CPU_TYPE_R8A77965, "R8A77965" }, { RMOBILE_CPU_TYPE_R8A77970, "R8A77970" }, + { RMOBILE_CPU_TYPE_R8A77990, "R8A77990" }, { RMOBILE_CPU_TYPE_R8A77995, "R8A77995" }, { 0x0, "CPU" }, }; diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index 94ea366f45..c94b3ff509 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -35,6 +35,7 @@ #define RMOBILE_CPU_TYPE_R8A7796 0x52 #define RMOBILE_CPU_TYPE_R8A77965 0x55 #define RMOBILE_CPU_TYPE_R8A77970 0x54 +#define RMOBILE_CPU_TYPE_R8A77990 0x57 #define RMOBILE_CPU_TYPE_R8A77995 0x58 #ifndef __ASSEMBLY__ -- cgit v1.2.1 From 19df5959d07dc953750fcdaa6446c97358919cd4 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 11 Apr 2018 18:37:41 +0900 Subject: ARM: dts: rmobile: Add Renesas R8A77990 SoC support This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC: - PSCI - CPU (single) - Cache controller - Main clocks and controller - Interrupt controller - Timer - PMU - Reset controller - Product register - System controller - UART for console Inspried by a patch by Takeshi Kihara in the BSP. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/dts/r8a77990.dtsi | 131 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) create mode 100644 arch/arm/dts/r8a77990.dtsi (limited to 'arch/arm') diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi new file mode 100644 index 0000000000..310bfd9d88 --- /dev/null +++ b/arch/arm/dts/r8a77990.dtsi @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device Tree Source for the r8a77990 SoC + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r8a77990"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* 1 core only at this point */ + a53_0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc 5>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + L2_CA53: cache-controller@0 { + compatible = "cache"; + reg = <0>; + power-domains = <&sysc 21>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc 32>; + resets = <&cpg 408>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + interrupt-affinity = <&a53_0>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77990-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77990-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77990-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a77990", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>; + clock-names = "fck"; + power-domains = <&sysc 32>; + resets = <&cpg 310>; + status = "disabled"; + }; + }; +}; -- cgit v1.2.1 From 031fa18f70c38fe53a90f6ab4a1a441bf1a78280 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Wed, 11 Apr 2018 18:37:42 +0900 Subject: ARM: dts: rmobile: Add Renesas Ebisu board support Basic support for the Renesas Ebisu board based on R-Car E3: - Memory, - Main crystal, - Serial console, Signed-off-by: Takeshi Kihara [shimoda: rebase and add SPDX-License-Identifier] Signed-off-by: Yoshihiro Shimoda Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/dts/Makefile | 1 + arch/arm/dts/r8a77990-ebisu.dts | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 arch/arm/dts/r8a77990-ebisu.dts (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a0349a8975..6df8bc2fd6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -439,6 +439,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \ r8a7796-salvator-x.dtb \ r8a77965-salvator-x.dtb \ r8a77970-eagle.dtb \ + r8a77990-ebisu.dtb \ r8a77995-draak.dtb dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts new file mode 100644 index 0000000000..63ee1347bb --- /dev/null +++ b/arch/arm/dts/r8a77990-ebisu.dts @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device Tree Source for the ebisu board + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a77990.dtsi" + +/ { + model = "Renesas Ebisu board based on r8a77990"; + compatible = "renesas,ebisu", "renesas,r8a77990"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; +}; + +&extal_clk { + clock-frequency = <48000000>; +}; + +&scif2 { + status = "okay"; +}; -- cgit v1.2.1 From 63e22517a39046d62b86ebf0f7fe6e0db575f339 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 26 Apr 2018 13:31:39 +0200 Subject: ARM: renesas: Add R8A77990 E3 Ebisu board Add support for the R8A77990 Ebisu board. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/dts/r8a77990-ebisu-u-boot.dts | 10 ++++++++++ arch/arm/dts/r8a77990-u-boot.dtsi | 9 +++++++++ arch/arm/mach-rmobile/Kconfig.64 | 6 ++++++ 3 files changed, 25 insertions(+) create mode 100644 arch/arm/dts/r8a77990-ebisu-u-boot.dts create mode 100644 arch/arm/dts/r8a77990-u-boot.dtsi (limited to 'arch/arm') diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts b/arch/arm/dts/r8a77990-ebisu-u-boot.dts new file mode 100644 index 0000000000..28bc497046 --- /dev/null +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dts @@ -0,0 +1,10 @@ +/* + * Device Tree Source extras for U-Boot for the Ebisu board + * + * Copyright (C) 2018 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include "r8a77990-ebisu.dts" +#include "r8a77990-u-boot.dtsi" diff --git a/arch/arm/dts/r8a77990-u-boot.dtsi b/arch/arm/dts/r8a77990-u-boot.dtsi new file mode 100644 index 0000000000..30a9f0b8ea --- /dev/null +++ b/arch/arm/dts/r8a77990-u-boot.dtsi @@ -0,0 +1,9 @@ +/* + * Device Tree Source extras for U-Boot on RCar R8A77990 SoC + * + * Copyright (C) 2018 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include "r8a779x-u-boot.dtsi" diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 6b93d25358..cb9f569e5f 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -34,6 +34,11 @@ config TARGET_EAGLE help Support for Renesas R-Car Gen3 Eagle platform +config TARGET_EBISU + bool "Ebisu board" + help + Support for Renesas R-Car Gen3 Ebisu platform + config TARGET_SALVATOR_X bool "Salvator-X board" help @@ -51,6 +56,7 @@ config SYS_SOC source "board/renesas/draak/Kconfig" source "board/renesas/eagle/Kconfig" +source "board/renesas/ebisu/Kconfig" source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig" -- cgit v1.2.1 From 0bb5d24852d8051b70b2becc74f3a2c4fb925dbb Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 31 May 2018 18:30:17 +0200 Subject: ARM: dts: rmobile: Sync R8A77990 Ebisu DTS with Linux Import the R8A77990 and Ebisu DTS from linux-next to get the latest version. This makes AVB ethernet work in U-Boot since the ethernet node is now present in DT, as well as GPIOs. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/dts/r8a77990-ebisu.dts | 28 +++++ arch/arm/dts/r8a77990.dtsi | 220 +++++++++++++++++++++++++++++++++------- 2 files changed, 213 insertions(+), 35 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts index 63ee1347bb..7a09d0524f 100644 --- a/arch/arm/dts/r8a77990-ebisu.dts +++ b/arch/arm/dts/r8a77990-ebisu.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "r8a77990.dtsi" +#include / { model = "Renesas Ebisu board based on r8a77990"; @@ -14,6 +15,7 @@ aliases { serial0 = &scif2; + ethernet0 = &avb; }; chosen { @@ -28,10 +30,36 @@ }; }; +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + phy-handle = <&phy0>; + phy-mode = "rgmii-txid"; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + }; +}; + &extal_clk { clock-frequency = <48000000>; }; +&pfc { + avb_pins: avb { + mux { + groups = "avb_link", "avb_mii"; + function = "avb"; + }; + }; +}; + &scif2 { status = "okay"; }; diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi index 310bfd9d88..be4f519711 100644 --- a/arch/arm/dts/r8a77990.dtsi +++ b/arch/arm/dts/r8a77990.dtsi @@ -27,9 +27,8 @@ enable-method = "psci"; }; - L2_CA53: cache-controller@0 { + L2_CA53: cache-controller-0 { compatible = "cache"; - reg = <0>; power-domains = <&sysc 21>; cache-unified; cache-level = <2>; @@ -43,8 +42,14 @@ clock-frequency = <0>; }; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>; + }; + psci { - compatible = "arm,psci-0.2"; + compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; @@ -55,39 +60,114 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 18>; + #interrupt-cells = <2>; interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc 32>; - resets = <&cpg 408>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 23>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc 32>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc 32>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc 32>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 11>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc 32>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 20>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc 32>; + resets = <&cpg 907>; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a77990", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc 32>; + resets = <&cpg 906>; }; - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - interrupt-affinity = <&a53_0>; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77990"; + reg = <0 0xe6060000 0 0x508>; }; cpg: clock-controller@e6150000 { @@ -105,17 +185,57 @@ reg = <0 0xe6160000 0 0x0200>; }; - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - sysc: system-controller@e6180000 { compatible = "renesas,r8a77990-sysc"; reg = <0 0xe6180000 0 0x0400>; #power-domain-cells = <1>; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a77990", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc 32>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif2: serial@e6e88000 { compatible = "renesas,scif-r8a77990", "renesas,rcar-gen3-scif", "renesas,scif"; @@ -127,5 +247,35 @@ resets = <&cpg 310>; status = "disabled"; }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc 32>; + resets = <&cpg 408>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; }; -- cgit v1.2.1