From f53830e74ede7c15740e13d9620dafb335c522ce Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Sat, 9 Jan 2016 17:32:50 +0100 Subject: MIPS: kconfig: add option for MIPS_L1_CACHE_SHIFT Add Kconfig symbol for L1 cache shift like the kernel does. The value of CONFIG_SYS_CACHELINE_SIZE is not a reliable source for ARCH_DMA_MINALIGN anymore, because it is optional on MIPS. If CONFIG_SYS_CACHELINE_SIZE is not defined by a board, the cache sizes are automatically detected and ARCH_DMA_MINALIGN would be set to 128 Bytes. The default value for CONFIG_MIPS_L1_CACHE_SHIFT is 5 which corresponds to 32 Bytes. All current MIPS boards already used that value. While on it, fix the Malta board to use a value of 6 like the kernel port does. Signed-off-by: Daniel Schwierzeck --- arch/mips/include/asm/cache.h | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) (limited to 'arch/mips/include/asm/cache.h') diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 0dfb54ef4d..806bd26ba9 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -7,15 +7,9 @@ #ifndef __MIPS_CACHE_H__ #define __MIPS_CACHE_H__ -/* - * The maximum L1 data cache line size on MIPS seems to be 128 bytes. We use - * that as a default for aligning DMA buffers unless the board config has - * specified another cache line size. - */ -#ifdef CONFIG_SYS_CACHELINE_SIZE -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#else -#define ARCH_DMA_MINALIGN 128 -#endif +#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES) #endif /* __MIPS_CACHE_H__ */ -- cgit v1.2.1