From 3b5b599f171ee66bbb514fddd6361a84f1e198f5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 13:48:08 +0200 Subject: ARM: zynq: Fix sparse warnings in slcr.c Warnings: arch/arm/cpu/armv7/zynq/slcr.c:21:6: warning: symbol 'zynq_slcr_lock' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:27:6: warning: symbol 'zynq_slcr_unlock' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:34:6: warning: symbol 'zynq_slcr_cpu_reset' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:54:6: warning: symbol 'zynq_slcr_gem_clk_setup' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:81:6: warning: symbol 'zynq_slcr_devcfg_disable' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:94:6: warning: symbol 'zynq_slcr_devcfg_enable' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:107:5: warning: symbol 'zynq_slcr_get_boot_mode' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:113:5: warning: symbol 'zynq_slcr_get_idcode' was not declared. Should it be static? Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/slcr.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index d7c1882332..c326a4c5de 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #define SLCR_LOCK_MAGIC 0x767B -- cgit v1.2.1 From ec9638659f5ed9cbb691c09fb72aee12c3426601 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 14:19:00 +0200 Subject: ARM: zynq: Fix sparse warning in ddrc.c Warning: arch/arm/cpu/armv7/zynq/ddrc.c:43:24: warning: Using plain integer as NULL pointer Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/ddrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c index ba6a6aee5c..302654d64a 100644 --- a/arch/arm/cpu/armv7/zynq/ddrc.c +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -40,7 +40,7 @@ void zynq_ddrc_init(void) * first stage bootloader. To get ECC to work all memory has * been initialized by writing any value. */ - memset(0, 0, 1 * 1024 * 1024); + memset((void *)0, 0, 1 * 1024 * 1024); } else { puts("Memory: ECC disabled\n"); } -- cgit v1.2.1 From 96a2859e54c8f6153ddb429ba730b324ab8ff352 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 29 Nov 2013 19:01:25 +0530 Subject: ARM: zynq: Added efuse status register base address Added efuse status register base address. This register is used for determining whether efuse was blown or not. Also, added the zynq_get_silicon_version() to get the silicon version of the zynq board. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/cpu.c | 13 +++++++++++++ arch/arm/include/asm/arch-zynq/hardware.h | 9 +++++++++ arch/arm/include/asm/arch-zynq/sys_proto.h | 1 + 3 files changed, 23 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 7626b5c1a3..816d0c5da7 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -14,6 +14,9 @@ void lowlevel_init(void) { } +#define ZYNQ_SILICON_VER_MASK 0xF0000000 +#define ZYNQ_SILICON_VER_SHIFT 28 + int arch_cpu_init(void) { zynq_slcr_unlock(); @@ -42,6 +45,16 @@ int arch_cpu_init(void) return 0; } +unsigned int zynq_get_silicon_version(void) +{ + unsigned int ver; + + ver = (readl(&devcfg_base->mctrl) & + ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT; + + return ver; +} + void reset_cpu(ulong addr) { zynq_slcr_cpu_reset(); diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 39184da40e..20f62bfc75 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -22,6 +22,7 @@ #define ZYNQ_SPI_BASEADDR0 0xE0006000 #define ZYNQ_SPI_BASEADDR1 0xE0007000 #define ZYNQ_DDRC_BASEADDR 0xF8006000 +#define ZYNQ_EFUSE_BASEADDR 0xF800D000 /* Bootmode setting values */ #define ZYNQ_BM_MASK 0xF @@ -130,4 +131,12 @@ struct ddrc_regs { }; #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR) +struct efuse_reg { + u32 reserved1[4]; + u32 status; + u32 reserved2[3]; +}; + +#define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR) + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index a68e1b3d23..2445a045ce 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -16,6 +16,7 @@ extern void zynq_slcr_devcfg_enable(void); extern u32 zynq_slcr_get_boot_mode(void); extern u32 zynq_slcr_get_idcode(void); extern void zynq_ddrc_init(void); +extern unsigned int zynq_get_silicon_version(void); /* Driver extern functions */ extern int zynq_sdhci_init(u32 regbase); -- cgit v1.2.1 From 10fa49f428b9425f554f64a74a451868cbbfba3a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 4 Sep 2013 16:51:33 +0200 Subject: ARM: zynq: Do not use half memory size for ECC case Memory size should be specified without ECC place. If you need to have half memory size, please change u-boot configuration. Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/ddrc.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c index 302654d64a..e0ed3bfb43 100644 --- a/arch/arm/cpu/armv7/zynq/ddrc.c +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -44,7 +44,4 @@ void zynq_ddrc_init(void) } else { puts("Memory: ECC disabled\n"); } - - if (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT) - gd->ram_size /= 2; } -- cgit v1.2.1 From 1540fb725bb7067f5cacbcc624f8684ed1471815 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 12:15:40 +0200 Subject: ARM: zynq: Call zynq board_init() in SPL Call board_init() if SPL is configured with CONFIG_SPL_BOARD_INIT. Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/spl.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c index fcad762c03..c3ea221549 100644 --- a/arch/arm/cpu/armv7/zynq/spl.c +++ b/arch/arm/cpu/armv7/zynq/spl.c @@ -28,6 +28,13 @@ void board_init_f(ulong dummy) board_init_r(NULL, 0); } +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + board_init(); +} +#endif + u32 spl_boot_device(void) { u32 mode; -- cgit v1.2.1 From 6e04769caf208a9f2da8ef8a85353def2a170176 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 27 Mar 2014 10:06:43 +0100 Subject: ARM: zynq: slcr: Fix incorrect commentary Fix c&p error in zynq_slcr_devcfg_enable() commentary and extending it with description according to Zynq TRM also in zynq_slcr_devcfg_disable(). Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/slcr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index c326a4c5de..1ff1eac06f 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -83,7 +83,7 @@ void zynq_slcr_devcfg_disable(void) { zynq_slcr_unlock(); - /* Disable AXI interface */ + /* Disable AXI interface by asserting FPGA resets */ writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl); /* Set Level Shifters DT618760 */ @@ -99,7 +99,7 @@ void zynq_slcr_devcfg_enable(void) /* Set Level Shifters DT618760 */ writel(0xF, &slcr_base->lvl_shftr_en); - /* Disable AXI interface */ + /* Enable AXI interface by de-asserting FPGA resets */ writel(0x0, &slcr_base->fpga_rst_ctrl); zynq_slcr_lock(); -- cgit v1.2.1 From 2da7a745b6d24eec7be30e7d11ca456d445e30c3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 30 Aug 2013 07:26:08 +0200 Subject: ARM: zynq: Setup correct slcr_lock value The driver should setup slcr state according to slcr operations. Reported-by: Andrey Filippov Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/slcr.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 1ff1eac06f..5ba58fad16 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -21,14 +21,18 @@ static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */ void zynq_slcr_lock(void) { - if (!slcr_lock) + if (!slcr_lock) { writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock); + slcr_lock = 1; + } } void zynq_slcr_unlock(void) { - if (slcr_lock) + if (slcr_lock) { writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock); + slcr_lock = 0; + } } /* Reset the entire system */ -- cgit v1.2.1 From dc4a1a2729f9ccaa473cf017c8bd4be4f242cafe Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Thu, 6 Mar 2014 14:43:36 +0100 Subject: ARM: zynq: Fix bootmode mask Bootmode mask was defined as 0x0F, but documentation mentions 0x07. Experiments show that bit "3" is the JTAG chain configuration. Change the mask to "7" to allow systems with a different chain configuration to boot correctly. Signed-off-by: Mike Looijmans Acked-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/include/asm/arch-zynq/hardware.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 20f62bfc75..a9d091f141 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -25,7 +25,7 @@ #define ZYNQ_EFUSE_BASEADDR 0xF800D000 /* Bootmode setting values */ -#define ZYNQ_BM_MASK 0xF +#define ZYNQ_BM_MASK 0x7 #define ZYNQ_BM_NOR 0x2 #define ZYNQ_BM_SD 0x5 #define ZYNQ_BM_JTAG 0x0 -- cgit v1.2.1 From 3cc3fa8672705e609ccd25348438453bd8de07fd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 12:21:04 +0200 Subject: ARM: zynq: Add MIO detection code Add run-time MIO pin detection to get actual pin configuration for specific periphery. Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/slcr.c | 50 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-zynq/sys_proto.h | 1 + 2 files changed, 51 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 5ba58fad16..51894f9239 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -17,6 +17,26 @@ #define SLCR_IDCODE_MASK 0x1F000 #define SLCR_IDCODE_SHIFT 12 +/* + * zynq_slcr_mio_get_status - Get the status of MIO peripheral. + * + * @peri_name: Name of the peripheral for checking MIO status + * @get_pins: Pointer to array of get pin for this peripheral + * @num_pins: Number of pins for this peripheral + * @mask: Mask value + * @check_val: Required check value to get the status of periph + */ +struct zynq_slcr_mio_get_status { + const char *peri_name; + const int *get_pins; + int num_pins; + u32 mask; + u32 check_val; +}; + +static const struct zynq_slcr_mio_get_status mio_periphs[] = { +}; + static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */ void zynq_slcr_lock(void) @@ -120,3 +140,33 @@ u32 zynq_slcr_get_idcode(void) return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >> SLCR_IDCODE_SHIFT; } + +/* + * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral. + * + * @periph: Name of the peripheral + * + * Returns count to indicate the number of pins configured for the + * given @periph. + */ +int zynq_slcr_get_mio_pin_status(const char *periph) +{ + const struct zynq_slcr_mio_get_status *mio_ptr; + int val, i, j; + int mio = 0; + + for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) { + if (strcmp(periph, mio_periphs[i].peri_name) == 0) { + mio_ptr = &mio_periphs[i]; + for (j = 0; j < mio_ptr->num_pins; j++) { + val = readl(&slcr_base->mio_pin + [mio_ptr->get_pins[j]]); + if ((val & mio_ptr->mask) == mio_ptr->check_val) + mio++; + } + break; + } + } + + return mio; +} diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index 2445a045ce..53c30ec6cf 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -15,6 +15,7 @@ extern void zynq_slcr_devcfg_disable(void); extern void zynq_slcr_devcfg_enable(void); extern u32 zynq_slcr_get_boot_mode(void); extern u32 zynq_slcr_get_idcode(void); +extern int zynq_slcr_get_mio_pin_status(const char *periph); extern void zynq_ddrc_init(void); extern unsigned int zynq_get_silicon_version(void); -- cgit v1.2.1 From eb8c54bfaabec7b8ba65a054f6c3e37572288ae9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 12:21:04 +0200 Subject: ARM: zynq: ehci: Added USB host driver support Added USB host driver for zynq. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/slcr.c | 24 ++++++++++++++++++++++++ arch/arm/include/asm/arch-zynq/hardware.h | 2 ++ 2 files changed, 26 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 51894f9239..934ccc31c8 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -14,6 +14,8 @@ #define SLCR_LOCK_MAGIC 0x767B #define SLCR_UNLOCK_MAGIC 0xDF0D +#define SLCR_USB_L1_SEL 0x04 + #define SLCR_IDCODE_MASK 0x1F000 #define SLCR_IDCODE_SHIFT 12 @@ -34,7 +36,29 @@ struct zynq_slcr_mio_get_status { u32 check_val; }; +static const int usb0_pins[] = { + 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39 +}; + +static const int usb1_pins[] = { + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51 +}; + static const struct zynq_slcr_mio_get_status mio_periphs[] = { + { + "usb0", + usb0_pins, + ARRAY_SIZE(usb0_pins), + SLCR_USB_L1_SEL, + SLCR_USB_L1_SEL, + }, + { + "usb1", + usb1_pins, + ARRAY_SIZE(usb1_pins), + SLCR_USB_L1_SEL, + SLCR_USB_L1_SEL, + }, }; static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */ diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index a9d091f141..2aede0c552 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -23,6 +23,8 @@ #define ZYNQ_SPI_BASEADDR1 0xE0007000 #define ZYNQ_DDRC_BASEADDR 0xF8006000 #define ZYNQ_EFUSE_BASEADDR 0xF800D000 +#define ZYNQ_USB_BASEADDR0 0xE0002000 +#define ZYNQ_USB_BASEADDR1 0xE0003000 /* Bootmode setting values */ #define ZYNQ_BM_MASK 0x7 -- cgit v1.2.1 From 66e6715c5ffe817c70485020508c7b9ec47227b7 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 12 May 2014 12:18:30 +0900 Subject: zynq: treat ps7_init.c/h as external files to ignore them ps7_init.c and ps7_init.h are supposed to be exported by hw project and copied to board/xilinx/zynq/ directory. We want them to be ignored by git. So what we should do is to always treat them as external files rather than replacing ps7_init.c This commit does: - Move a weak function ps7_init() to arch/arm/cpu/armv7/zynq/spl.c and delete board/xilinx/zynq/ps7_init.c - Compile board/xilinx/zynq/ps7_init.c only when it exists - Add .gitignore to ignore ps7_init.c/h Signed-off-by: Masahiro Yamada Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/spl.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c index c3ea221549..d73e5cbaa7 100644 --- a/arch/arm/cpu/armv7/zynq/spl.c +++ b/arch/arm/cpu/armv7/zynq/spl.c @@ -74,3 +74,11 @@ int spl_start_uboot(void) return 0; } #endif + +__weak void ps7_init(void) +{ + /* + * This function is overridden by the one in + * board/xilinx/zynq/ps7_init.c, if it exists. + */ +} -- cgit v1.2.1 From 580a54c5d464d9c23b79e249e7ab0979900f9cf4 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 15 May 2014 20:37:53 +0900 Subject: zynq: import zynq-7000.dtsi from Linux Kernel Our current motivation is to use OF initialization for RAM and UART. But adding full DTS would be helpful in future, for instance, for OF configuration of Ethernet, MMC, USB, etc. This commit imports arch/arm/boot/dts/zynq-7000.dtsi from Linux 3.15-rc5 and adjusts the license comment block for SPDX. Signed-off-by: Masahiro Yamada Suggested-by: Michal Simek Signed-off-by: Michal Simek --- arch/arm/dts/zynq-7000.dtsi | 194 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 194 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index f20b8bd604..2d076f194e 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -10,4 +10,198 @@ / { compatible = "xlnx,zynq-7000"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + clocks = <&clkc 3>; + clock-latency = <1000>; + operating-points = < + /* kHz uV */ + 666667 1000000 + 333334 1000000 + 222223 1000000 + >; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + clocks = <&clkc 3>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 5 4>, <0 6 4>; + interrupt-parent = <&intc>; + reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + i2c0: zynq-i2c@e0004000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <&clkc 38>; + interrupt-parent = <&intc>; + interrupts = <0 25 4>; + reg = <0xe0004000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: zynq-i2c@e0005000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <&clkc 39>; + interrupt-parent = <&intc>; + interrupts = <0 48 4>; + reg = <0xe0005000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + intc: interrupt-controller@f8f01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xF8F01000 0x1000>, + <0xF8F00100 0x100>; + }; + + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xF8F02000 0x1000>; + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-unified; + cache-level = <2>; + }; + + uart0: uart@e0000000 { + compatible = "xlnx,xuartps"; + status = "disabled"; + clocks = <&clkc 23>, <&clkc 40>; + clock-names = "ref_clk", "aper_clk"; + reg = <0xE0000000 0x1000>; + interrupts = <0 27 4>; + }; + + uart1: uart@e0001000 { + compatible = "xlnx,xuartps"; + status = "disabled"; + clocks = <&clkc 24>, <&clkc 41>; + clock-names = "ref_clk", "aper_clk"; + reg = <0xE0001000 0x1000>; + interrupts = <0 50 4>; + }; + + gem0: ethernet@e000b000 { + compatible = "cdns,gem"; + reg = <0xe000b000 0x4000>; + status = "disabled"; + interrupts = <0 22 4>; + clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; + clock-names = "pclk", "hclk", "tx_clk"; + }; + + gem1: ethernet@e000c000 { + compatible = "cdns,gem"; + reg = <0xe000c000 0x4000>; + status = "disabled"; + interrupts = <0 45 4>; + clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; + clock-names = "pclk", "hclk", "tx_clk"; + }; + + sdhci0: ps7-sdhci@e0100000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 21>, <&clkc 32>; + interrupt-parent = <&intc>; + interrupts = <0 24 4>; + reg = <0xe0100000 0x1000>; + } ; + + sdhci1: ps7-sdhci@e0101000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 22>, <&clkc 33>; + interrupt-parent = <&intc>; + interrupts = <0 47 4>; + reg = <0xe0101000 0x1000>; + } ; + + slcr: slcr@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-slcr", "syscon"; + reg = <0xF8000000 0x1000>; + ranges; + clkc: clkc@100 { + #clock-cells = <1>; + compatible = "xlnx,ps7-clkc"; + ps-clk-frequency = <33333333>; + fclk-enable = <0>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", + "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", + "dci", "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", + "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", + "dma", "usb0_aper", "usb1_aper", "gem0_aper", + "gem1_aper", "sdio0_aper", "sdio1_aper", + "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", + "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", + "gpio_aper", "lqspi_aper", "smc_aper", "swdt", + "dbg_trc", "dbg_apb"; + reg = <0x100 0x100>; + }; + }; + + global_timer: timer@f8f00200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xf8f00200 0x20>; + interrupts = <1 11 0x301>; + interrupt-parent = <&intc>; + clocks = <&clkc 4>; + }; + + ttc0: ttc0@f8001000 { + interrupt-parent = <&intc>; + interrupts = < 0 10 4 0 11 4 0 12 4 >; + compatible = "cdns,ttc"; + clocks = <&clkc 6>; + reg = <0xF8001000 0x1000>; + }; + + ttc1: ttc1@f8002000 { + interrupt-parent = <&intc>; + interrupts = < 0 37 4 0 38 4 0 39 4 >; + compatible = "cdns,ttc"; + clocks = <&clkc 6>; + reg = <0xF8002000 0x1000>; + }; + scutimer: scutimer@f8f00600 { + interrupt-parent = <&intc>; + interrupts = < 1 13 0x301 >; + compatible = "arm,cortex-a9-twd-timer"; + reg = < 0xf8f00600 0x20 >; + clocks = <&clkc 4>; + } ; + }; }; -- cgit v1.2.1 From 7d34c5de72ef2f48ac4d17e4faadd952b897b8b3 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 15 May 2014 20:37:54 +0900 Subject: zynq: add memory nodes to device tree to initialize DRAM with OF Commit 9e0e37ac added OF RAM initialization support but memory nodes are missing in device tree. Signed-off-by: Masahiro Yamada Cc: Michal Simek Tested-by: Masahiro Yamada [on ZC706 board] Tested-by: Michal Simek [on ZC702 board] Signed-off-by: Michal Simek --- arch/arm/dts/zynq-microzed.dts | 5 +++++ arch/arm/dts/zynq-zc702.dts | 5 +++++ arch/arm/dts/zynq-zc706.dts | 5 +++++ arch/arm/dts/zynq-zc770-xm010.dts | 5 +++++ arch/arm/dts/zynq-zc770-xm012.dts | 5 +++++ arch/arm/dts/zynq-zc770-xm013.dts | 5 +++++ arch/arm/dts/zynq-zed.dts | 5 +++++ 7 files changed, 35 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index 6da71c116d..842896fbc4 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -11,4 +11,9 @@ / { model = "Zynq MicroZED Board"; compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 667dc28256..a94e331bd2 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -11,4 +11,9 @@ / { model = "Zynq ZC702 Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index 526fc8888b..92de947af3 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -11,4 +11,9 @@ / { model = "Zynq ZC706 Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 8b542a109b..8d68208c12 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -11,4 +11,9 @@ / { model = "Zynq ZC770 XM010 Board"; compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 0379a07068..9ebbddfb46 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -11,4 +11,9 @@ / { model = "Zynq ZC770 XM012 Board"; compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index a4f9e05fc0..b4f7fa2cdf 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -11,4 +11,9 @@ / { model = "Zynq ZC770 XM013 Board"; compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 91a5deba4a..3488a5635b 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -11,4 +11,9 @@ / { model = "Zynq ZED Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0 0x20000000>; + }; }; -- cgit v1.2.1 From 9f9d41bad16efe0674257b4efe4db1a399f93643 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 15 May 2014 20:37:55 +0900 Subject: zynq: add UART nodes to device tree to initialize UART with OF Commit c9416b92 added OF UART initialization support but aliases nodes are missing in device tree. Signed-off-by: Masahiro Yamada Cc: Michal Simek Tested-by: Masahiro Yamada [on ZC706 board] Tested-by: Michal Simek [on ZC702 board] Signed-off-by: Michal Simek --- arch/arm/dts/zynq-microzed.dts | 4 ++++ arch/arm/dts/zynq-zc702.dts | 4 ++++ arch/arm/dts/zynq-zc706.dts | 4 ++++ arch/arm/dts/zynq-zc770-xm010.dts | 4 ++++ arch/arm/dts/zynq-zc770-xm012.dts | 4 ++++ arch/arm/dts/zynq-zc770-xm013.dts | 4 ++++ arch/arm/dts/zynq-zed.dts | 4 ++++ 7 files changed, 28 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index 842896fbc4..c373a2cc31 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -12,6 +12,10 @@ model = "Zynq MicroZED Board"; compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000"; + aliases { + serial0 = &uart1; + }; + memory { device_type = "memory"; reg = <0 0x40000000>; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index a94e331bd2..4fa0b00b31 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -12,6 +12,10 @@ model = "Zynq ZC702 Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; + aliases { + serial0 = &uart1; + }; + memory { device_type = "memory"; reg = <0 0x40000000>; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index 92de947af3..2a80195757 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -12,6 +12,10 @@ model = "Zynq ZC706 Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; + aliases { + serial0 = &uart1; + }; + memory { device_type = "memory"; reg = <0 0x40000000>; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 8d68208c12..5e66174977 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -12,6 +12,10 @@ model = "Zynq ZC770 XM010 Board"; compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; + aliases { + serial0 = &uart1; + }; + memory { device_type = "memory"; reg = <0 0x40000000>; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 9ebbddfb46..127a6619c6 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -12,6 +12,10 @@ model = "Zynq ZC770 XM012 Board"; compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; + aliases { + serial0 = &uart1; + }; + memory { device_type = "memory"; reg = <0 0x40000000>; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index b4f7fa2cdf..c61c7e7592 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -12,6 +12,10 @@ model = "Zynq ZC770 XM013 Board"; compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; + aliases { + serial0 = &uart0; + }; + memory { device_type = "memory"; reg = <0 0x40000000>; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 3488a5635b..70cc8a6c0d 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -12,6 +12,10 @@ model = "Zynq ZED Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; + aliases { + serial0 = &uart1; + }; + memory { device_type = "memory"; reg = <0 0x20000000>; -- cgit v1.2.1