From 64917ca38933d10b3763f61df7a1e58e1e127b52 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Sun, 17 Jan 2010 15:38:26 -0600 Subject: PCIe, USB: Replace 'end point' references with 'endpoint' When referring to PCIe and USB 'endpoint' is the standard naming convention. Signed-off-by: Peter Tyser Acked-by: Stefan Roese Acked-by: Remy Bohmer --- board/freescale/p1_p2_rdb/pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board/freescale/p1_p2_rdb') diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index 6fd6963f0c..aa2f64ca91 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -66,7 +66,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); @@ -85,7 +85,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); -- cgit v1.2.1