From aea02abec59e8ea8e78c7926162c2b0f6073f32c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 12 Feb 2016 14:24:07 +0100 Subject: arm: mvebu: theadorable: Add StratixV FPGA programming support This patch adds support for Altera StratixV bitstream programming. 2 FPGAs are connected to the SPI busses. This patch uses board specific write code to program the bitstream via SPI direct write mode. Signed-off-by: Stefan Roese Cc: Luka Perkov Signed-off-by: Stefan Roese --- board/theadorable/theadorable.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'board/theadorable/theadorable.c') diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index 0e232656fc..ee88a98a24 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -8,9 +8,11 @@ #include #include #include +#include #ifdef CONFIG_NET #include #endif +#include "theadorable.h" #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" @@ -136,6 +138,15 @@ int board_init(void) /* adress of boot parameters */ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + /* + * Map SPI devices via MBUS so that they can be accessed via + * the SPI direct access mode + */ + mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1); + mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2); + return 0; } @@ -143,6 +154,8 @@ int checkboard(void) { puts("Board: theadorable\n"); + board_fpga_add(); + return 0; } -- cgit v1.2.1