From 30b1ecd26533fdd680b66c0ed6767cc4b875fbc6 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 30 Jul 2017 06:23:11 -0700 Subject: x86: kconfig: Let board select BOARD_EARLY_INIT_F CONFIG_BOARD_EARLY_INIT_F literally indicates board-specific codes and should be not 'default y' for all x86 boards. Signed-off-by: Bin Meng Reviewed-by: Andy Shevchenko Reviewed-by: Simon Glass --- board/advantech/som-db5800-som-6867/Kconfig | 1 + board/congatec/conga-qeval20-qa3-e3845/Kconfig | 1 + board/dfi/dfi-bt700/Kconfig | 1 + board/google/chromebook_link/link.c | 5 ----- board/google/chromebook_samus/samus.c | 5 ----- board/google/chromebox_panther/panther.c | 5 ----- board/intel/cougarcanyon2/Kconfig | 1 + board/intel/crownbay/Kconfig | 1 + board/intel/galileo/galileo.c | 5 ----- 9 files changed, 5 insertions(+), 20 deletions(-) (limited to 'board') diff --git a/board/advantech/som-db5800-som-6867/Kconfig b/board/advantech/som-db5800-som-6867/Kconfig index f6f3748fc3..945aa43bd2 100644 --- a/board/advantech/som-db5800-som-6867/Kconfig +++ b/board/advantech/som-db5800-som-6867/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR if !EFI_STUB select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select BOARD_EARLY_INIT_F config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/congatec/conga-qeval20-qa3-e3845/Kconfig b/board/congatec/conga-qeval20-qa3-e3845/Kconfig index 24b8f695ac..f91ffa1325 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/Kconfig +++ b/board/congatec/conga-qeval20-qa3-e3845/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR if !EFI_STUB select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select BOARD_EARLY_INIT_F select BOARD_LATE_INIT config PCIE_ECAM_BASE diff --git a/board/dfi/dfi-bt700/Kconfig b/board/dfi/dfi-bt700/Kconfig index fca8b53d02..59f45efcf7 100644 --- a/board/dfi/dfi-bt700/Kconfig +++ b/board/dfi/dfi-bt700/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR if !EFI_STUB select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select BOARD_EARLY_INIT_F select BOARD_LATE_INIT config PCIE_ECAM_BASE diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 42615e1e23..64e7c1a08d 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -16,8 +16,3 @@ int arch_early_init_r(void) { return 0; } - -int board_early_init_f(void) -{ - return 0; -} diff --git a/board/google/chromebook_samus/samus.c b/board/google/chromebook_samus/samus.c index 3c3f5d4833..356b92a454 100644 --- a/board/google/chromebook_samus/samus.c +++ b/board/google/chromebook_samus/samus.c @@ -11,8 +11,3 @@ int arch_early_init_r(void) { return cpu_run_reference_code(); } - -int board_early_init_f(void) -{ - return 0; -} diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c index e3baf88783..ed60e44264 100644 --- a/board/google/chromebox_panther/panther.c +++ b/board/google/chromebox_panther/panther.c @@ -11,8 +11,3 @@ int arch_early_init_r(void) { return 0; } - -int board_early_init_f(void) -{ - return 0; -} diff --git a/board/intel/cougarcanyon2/Kconfig b/board/intel/cougarcanyon2/Kconfig index 95a617b725..4e7d02161f 100644 --- a/board/intel/cougarcanyon2/Kconfig +++ b/board/intel/cougarcanyon2/Kconfig @@ -21,5 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_IVYBRIDGE select HAVE_FSP select BOARD_ROMSIZE_KB_2048 + select BOARD_EARLY_INIT_F endif diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig index b30701afc8..05626a9e92 100644 --- a/board/intel/crownbay/Kconfig +++ b/board/intel/crownbay/Kconfig @@ -20,5 +20,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR select INTEL_QUEENSBAY select BOARD_ROMSIZE_KB_1024 + select BOARD_EARLY_INIT_F endif diff --git a/board/intel/galileo/galileo.c b/board/intel/galileo/galileo.c index 568bd4db49..2fe1923a9f 100644 --- a/board/intel/galileo/galileo.c +++ b/board/intel/galileo/galileo.c @@ -9,11 +9,6 @@ #include #include -int board_early_init_f(void) -{ - return 0; -} - /* * Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin. * -- cgit v1.2.1 From 5d89b37f71ff1833bdd34eeba6dbac6bec1c9fb2 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 30 Jul 2017 06:23:13 -0700 Subject: x86: kconfig: Select ARCH_EARLY_INIT_R in the platform Kconfig This is architecture-dependent early initialization hence should be put in the platform Kconfig. Signed-off-by: Bin Meng Reviewed-by: Andy Shevchenko Reviewed-by: Simon Glass --- board/advantech/som-db5800-som-6867/som-db5800-som-6867.c | 5 ----- board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c | 5 ----- board/coreboot/coreboot/Makefile | 2 +- board/coreboot/coreboot/coreboot.c | 14 -------------- board/efi/efi-x86/efi.c | 6 ------ board/google/chromebook_link/link.c | 11 ----------- board/google/chromebook_samus/samus.c | 6 ------ board/google/chromebox_panther/panther.c | 6 ------ board/intel/minnowmax/minnowmax.c | 5 ----- 9 files changed, 1 insertion(+), 59 deletions(-) delete mode 100644 board/coreboot/coreboot/coreboot.c (limited to 'board') diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c index 5bed2c1146..615879575c 100644 --- a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c +++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c @@ -17,8 +17,3 @@ int board_early_init_f(void) return 0; } - -int arch_early_init_r(void) -{ - return 0; -} diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c index 7a5b7659ef..1283eebd38 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c +++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c @@ -28,11 +28,6 @@ int board_early_init_f(void) return 0; } -int arch_early_init_r(void) -{ - return 0; -} - int board_late_init(void) { struct udevice *dev; diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile index 27ebe78eb1..4f2ac898eb 100644 --- a/board/coreboot/coreboot/Makefile +++ b/board/coreboot/coreboot/Makefile @@ -12,4 +12,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += coreboot_start.o coreboot.o +obj-y += coreboot_start.o diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c deleted file mode 100644 index bb7f778a8f..0000000000 --- a/board/coreboot/coreboot/coreboot.c +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2013 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -int arch_early_init_r(void) -{ - return 0; -} diff --git a/board/efi/efi-x86/efi.c b/board/efi/efi-x86/efi.c index 1fbe36a399..2adc202be0 100644 --- a/board/efi/efi-x86/efi.c +++ b/board/efi/efi-x86/efi.c @@ -5,9 +5,3 @@ */ #include -#include - -int arch_early_init_r(void) -{ - return 0; -} diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 64e7c1a08d..dc22592095 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -5,14 +5,3 @@ */ #include -#include -#include -#include -#include -#include -#include - -int arch_early_init_r(void) -{ - return 0; -} diff --git a/board/google/chromebook_samus/samus.c b/board/google/chromebook_samus/samus.c index 356b92a454..5b5eb19ee8 100644 --- a/board/google/chromebook_samus/samus.c +++ b/board/google/chromebook_samus/samus.c @@ -5,9 +5,3 @@ */ #include -#include - -int arch_early_init_r(void) -{ - return cpu_run_reference_code(); -} diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c index ed60e44264..2adc202be0 100644 --- a/board/google/chromebox_panther/panther.c +++ b/board/google/chromebox_panther/panther.c @@ -5,9 +5,3 @@ */ #include -#include - -int arch_early_init_r(void) -{ - return 0; -} diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c index 99aed53100..5bdb2fdbc7 100644 --- a/board/intel/minnowmax/minnowmax.c +++ b/board/intel/minnowmax/minnowmax.c @@ -12,11 +12,6 @@ #define GPIO_BANKE_NAME "gpioe" -int arch_early_init_r(void) -{ - return 0; -} - int misc_init_r(void) { struct udevice *dev; -- cgit v1.2.1 From 1df7f0b6a00c2080c50de775b4ef621aad24c47e Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 30 Jul 2017 06:23:26 -0700 Subject: x86: kconfig: Let board select SPI flash Only a specific type of SPI flash exists on a board, having board Kconfig to select the SPI flash seems to make more sense. Other flash types are not necessary except coreboot, which implies all available flash drivers there. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- board/advantech/som-db5800-som-6867/Kconfig | 1 + board/congatec/conga-qeval20-qa3-e3845/Kconfig | 1 + board/coreboot/coreboot/Kconfig | 11 +++++++++++ board/dfi/dfi-bt700/Kconfig | 1 + board/google/chromebook_link/Kconfig | 1 + board/google/chromebook_samus/Kconfig | 1 + board/google/chromebox_panther/Kconfig | 1 + board/intel/bayleybay/Kconfig | 1 + board/intel/cougarcanyon2/Kconfig | 1 + board/intel/crownbay/Kconfig | 1 + board/intel/galileo/Kconfig | 1 + board/intel/minnowmax/Kconfig | 1 + 12 files changed, 22 insertions(+) (limited to 'board') diff --git a/board/advantech/som-db5800-som-6867/Kconfig b/board/advantech/som-db5800-som-6867/Kconfig index 945aa43bd2..fac562ad4f 100644 --- a/board/advantech/som-db5800-som-6867/Kconfig +++ b/board/advantech/som-db5800-som-6867/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 select BOARD_EARLY_INIT_F + select SPI_FLASH_MACRONIX config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/congatec/conga-qeval20-qa3-e3845/Kconfig b/board/congatec/conga-qeval20-qa3-e3845/Kconfig index f91ffa1325..c2649d299f 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/Kconfig +++ b/board/congatec/conga-qeval20-qa3-e3845/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select BOARD_EARLY_INIT_F select BOARD_LATE_INIT + select SPI_FLASH_STMICRO config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig index 3ff64f4084..cfa1d50ee4 100644 --- a/board/coreboot/coreboot/Kconfig +++ b/board/coreboot/coreboot/Kconfig @@ -12,6 +12,17 @@ config SYS_SOC config SYS_TEXT_BASE default 0x01110000 +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + imply SPI_FLASH_ATMEL + imply SPI_FLASH_EON + imply SPI_FLASH_GIGADEVICE + imply SPI_FLASH_MACRONIX + imply SPI_FLASH_SPANSION + imply SPI_FLASH_STMICRO + imply SPI_FLASH_SST + imply SPI_FLASH_WINBOND + comment "coreboot-specific options" config SYS_CONFIG_NAME diff --git a/board/dfi/dfi-bt700/Kconfig b/board/dfi/dfi-bt700/Kconfig index 59f45efcf7..81a2575d11 100644 --- a/board/dfi/dfi-bt700/Kconfig +++ b/board/dfi/dfi-bt700/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select BOARD_EARLY_INIT_F select BOARD_LATE_INIT + select SPI_FLASH_STMICRO config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 8999b58294..944716d002 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_IVYBRIDGE select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_WINBOND config PCIE_ECAM_BASE default 0xf0000000 diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig index f2b9481563..afbfe53deb 100644 --- a/board/google/chromebook_samus/Kconfig +++ b/board/google/chromebook_samus/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_BROADWELL select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_WINBOND config PCIE_ECAM_BASE default 0xf0000000 diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig index 2af3aa9e74..875df9d59f 100644 --- a/board/google/chromebox_panther/Kconfig +++ b/board/google/chromebox_panther/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_IVYBRIDGE select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_WINBOND config SYS_CAR_ADDR hex diff --git a/board/intel/bayleybay/Kconfig b/board/intel/bayleybay/Kconfig index 597228fdbc..a62249936f 100644 --- a/board/intel/bayleybay/Kconfig +++ b/board/intel/bayleybay/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_WINBOND config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/intel/cougarcanyon2/Kconfig b/board/intel/cougarcanyon2/Kconfig index 4e7d02161f..ed764485a5 100644 --- a/board/intel/cougarcanyon2/Kconfig +++ b/board/intel/cougarcanyon2/Kconfig @@ -22,5 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_FSP select BOARD_ROMSIZE_KB_2048 select BOARD_EARLY_INIT_F + select SPI_FLASH_WINBOND endif diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig index 05626a9e92..1eed227c75 100644 --- a/board/intel/crownbay/Kconfig +++ b/board/intel/crownbay/Kconfig @@ -21,5 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_QUEENSBAY select BOARD_ROMSIZE_KB_1024 select BOARD_EARLY_INIT_F + select SPI_FLASH_SST endif diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig index 87a0ec4ccc..1416c891e8 100644 --- a/board/intel/galileo/Kconfig +++ b/board/intel/galileo/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR select INTEL_QUARK select BOARD_ROMSIZE_KB_1024 + select SPI_FLASH_WINBOND config SMBIOS_PRODUCT_NAME default "GalileoGen2" diff --git a/board/intel/minnowmax/Kconfig b/board/intel/minnowmax/Kconfig index 7e975f9c3a..a8668e4efc 100644 --- a/board/intel/minnowmax/Kconfig +++ b/board/intel/minnowmax/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR if !EFI_STUB select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_STMICRO config PCIE_ECAM_BASE default 0xe0000000 -- cgit v1.2.1