From e456a81935aafcecc8e53a7cd35efe9267781041 Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Wed, 21 Aug 2019 21:14:49 +0200 Subject: riscv: qemu: add SPL configuration Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The configurations are meant to help the development of SPL on RISC-V. The configurations enable RAM as the only SPL boot device. Images must be loaded at address 0x80200000. In the default boot flow, U-Boot SPL starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is then started in supervisor mode by OpenSBI. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --- configs/qemu-riscv32_spl_defconfig | 11 +++++++++++ configs/qemu-riscv64_spl_defconfig | 12 ++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 configs/qemu-riscv32_spl_defconfig create mode 100644 configs/qemu-riscv64_spl_defconfig (limited to 'configs') diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig new file mode 100644 index 0000000000..78e755b36a --- /dev/null +++ b/configs/qemu-riscv32_spl_defconfig @@ -0,0 +1,11 @@ +CONFIG_RISCV=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_TARGET_QEMU_VIRT=y +CONFIG_RISCV_SMODE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_CMD_MII is not set +CONFIG_OF_PRIOR_STAGE=y diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig new file mode 100644 index 0000000000..a3f5e29d58 --- /dev/null +++ b/configs/qemu-riscv64_spl_defconfig @@ -0,0 +1,12 @@ +CONFIG_RISCV=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_TARGET_QEMU_VIRT=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_CMD_MII is not set +CONFIG_OF_PRIOR_STAGE=y -- cgit v1.2.1