From f1d8074c08d77270f9117427768874be05b4be94 Mon Sep 17 00:00:00 2001 From: Shaveta Leekha Date: Wed, 12 Nov 2014 16:00:22 +0530 Subject: B4860QDS: SGMII related updates - Enable SGMII support for 0x8d Serdes 2 protocol. - Correct Phy address for DTSECx for 0x8d/0xb2 Serdes 2 protocol. - Updated debug statement - Add Alternate LC VCO protocols(0x8d-->0x8c, 0xb2-->0xb1) - Rename onboard PHY address defines for more readability - Add these new Defines in B4860QDS.h file Signed-off-by: Shaveta Leekha Signed-off-by: Poonam Aggrwal Signed-off-by: Suresh Gupta Reviewed-by: York Sun --- include/configs/B4860QDS.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/configs/B4860QDS.h') diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index dc1a9bc1ef..b47b9decaa 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -713,8 +713,8 @@ unsigned long get_board_ddr_clk(void); #endif /* CONFIG_PCI */ #ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 -#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 +#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 +#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ -- cgit v1.2.1