From d9b94f28a442b0013caef99de084d7b72e2d4607 Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Mon, 25 Jul 2005 14:05:07 -0500
Subject: * Patch by Jon Loeliger, 2005-05-05   Implemented support for
 MPC8548CDS board.   Added DDR II support based on SPD values for MPC85xx
 boards.   This roll-up patch also includes bugfies for the previously  
 published patches:     DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC
 3&4 I/O

---
 include/configs/MPC8541CDS.h | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

(limited to 'include/configs/MPC8541CDS.h')

diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 3ec27b8aae..c96b98b54d 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -41,9 +41,12 @@
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
 
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
@@ -360,7 +363,9 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
@@ -368,7 +373,9 @@ extern unsigned long get_clock_freq(void);
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define FEC_PHYIDX		0
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
 
 #endif	/* CONFIG_TSEC_ENET */
 
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