From dc9cdf859e11de775e75cc233b09d6b6d257a818 Mon Sep 17 00:00:00 2001 From: Ramneek Mehresh Date: Fri, 29 May 2015 14:47:15 +0530 Subject: usb: dwc3: Add DWC3 controller driver support Add support for DWC3 XHCI controller driver Signed-off-by: Ramneek Mehresh --- include/linux/usb/dwc3.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/linux') diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h index 7edc760c7b..ba7f31495f 100644 --- a/include/linux/usb/dwc3.h +++ b/include/linux/usb/dwc3.h @@ -191,4 +191,10 @@ struct dwc3 { /* offset: 0xC100 */ #define DWC3_DCTL_CSFTRST (1 << 30) #define DWC3_DCTL_LSFTRST (1 << 29) +#ifdef CONFIG_USB_XHCI_DWC3 +void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode); +void dwc3_core_soft_reset(struct dwc3 *dwc3_reg); +int dwc3_core_init(struct dwc3 *dwc3_reg); +void usb_phy_reset(struct dwc3 *dwc3_reg); +#endif #endif /* __DWC3_H_ */ -- cgit v1.2.1 From ba92ee06a5b792e5cbc144f95883cc54f4982255 Mon Sep 17 00:00:00 2001 From: Ramneek Mehresh Date: Fri, 29 May 2015 14:47:19 +0530 Subject: usb: fsl: Add XHCI driver support Add xhci driver support for all FSL socs Signed-off-by: Ramneek Mehresh --- include/linux/usb/xhci-fsl.h | 54 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 include/linux/usb/xhci-fsl.h (limited to 'include/linux') diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h new file mode 100644 index 0000000000..8eaab2c10e --- /dev/null +++ b/include/linux/usb/xhci-fsl.h @@ -0,0 +1,54 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * FSL USB HOST xHCI Controller + * + * Author: Ramneek Mehresh + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_XHCI_FSL_H_ +#define _ASM_ARCH_XHCI_FSL_H_ + +/* Default to the FSL XHCI defines */ +#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 +#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC +#define USB3_PHY_PARTIAL_RX_POWERON BIT(6) +#define USB3_PHY_RX_POWERON BIT(14) +#define USB3_PHY_TX_POWERON BIT(15) +#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) +#define USB3_PWRCTL_CLK_CMD_SHIFT 14 +#define USB3_PWRCTL_CLK_FREQ_SHIFT 22 + +/* USBOTGSS_WRAPPER definitions */ +#define USBOTGSS_WRAPRESET BIT(17) +#define USBOTGSS_DMADISABLE BIT(16) +#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) +#define USBOTGSS_STANDBYMODE_SMRT BIT(5) +#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) +#define USBOTGSS_IDLEMODE_NOIDLE BIT(2) +#define USBOTGSS_IDLEMODE_SMRT BIT(3) +#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) + +/* USBOTGSS_IRQENABLE_SET_0 bit */ +#define USBOTGSS_COREIRQ_EN BIT(1) + +/* USBOTGSS_IRQENABLE_SET_1 bits */ +#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) +#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) +#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) +#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) + +struct fsl_xhci { + struct xhci_hccr *hcd; + struct dwc3 *dwc3_reg; +}; + +#endif /* _ASM_ARCH_XHCI_FSL_H_ */ -- cgit v1.2.1 From 667f4dd90f0f40f8d4fde7ef280550ef5f7946f8 Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Tue, 23 Jun 2015 09:17:49 +0530 Subject: drivers: usb: fsl: Implement Erratum A-009116 for XHCI controller This adjusts (micro)frame length to appropriate value thus avoiding USB devices to time out over a longer run Signed-off-by: Nikhil Badola --- include/linux/usb/dwc3.h | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) (limited to 'include/linux') diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h index ba7f31495f..dd934a0e65 100644 --- a/include/linux/usb/dwc3.h +++ b/include/linux/usb/dwc3.h @@ -109,7 +109,11 @@ struct dwc3 { /* offset: 0xC100 */ u32 g_hwparams8; - u32 reserved4[63]; + u32 reserved4[11]; + + u32 g_fladj; + + u32 reserved5[51]; u32 d_cfg; u32 d_ctl; @@ -118,15 +122,15 @@ struct dwc3 { /* offset: 0xC100 */ u32 d_gcmdpar; u32 d_gcmd; - u32 reserved5[2]; + u32 reserved6[2]; u32 d_alepena; - u32 reserved6[55]; + u32 reserved7[55]; struct d_physical_endpoint d_phy_ep_cmd[32]; - u32 reserved7[128]; + u32 reserved8[128]; u32 o_cfg; u32 o_ctl; @@ -134,7 +138,7 @@ struct dwc3 { /* offset: 0xC100 */ u32 o_evten; u32 o_sts; - u32 reserved8[3]; + u32 reserved9[3]; u32 adp_cfg; u32 adp_ctl; @@ -143,7 +147,7 @@ struct dwc3 { /* offset: 0xC100 */ u32 bc_cfg; - u32 reserved9; + u32 reserved10; u32 bc_evt; u32 bc_evten; @@ -191,10 +195,16 @@ struct dwc3 { /* offset: 0xC100 */ #define DWC3_DCTL_CSFTRST (1 << 30) #define DWC3_DCTL_LSFTRST (1 << 29) +/* Global Frame Length Adjustment Register */ +#define GFLADJ_30MHZ_REG_SEL (1 << 7) +#define GFLADJ_30MHZ(n) ((n) & 0x3f) +#define GFLADJ_30MHZ_DEFAULT 0x20 + #ifdef CONFIG_USB_XHCI_DWC3 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode); void dwc3_core_soft_reset(struct dwc3 *dwc3_reg); int dwc3_core_init(struct dwc3 *dwc3_reg); void usb_phy_reset(struct dwc3 *dwc3_reg); +void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val); #endif #endif /* __DWC3_H_ */ -- cgit v1.2.1 From 909a1ab2f05a53b2e5a0c604a88c06adc8b4929c Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Tue, 23 Jun 2015 09:18:03 +0530 Subject: include: usb: Move USB controller base address mapping Move USB controller Base address mapping from ls102xa immap to fsl xhci header. This is required to remove any warnings when controller base addresses are mapped for multiple platforms in their respective files. Signed-off-by: Nikhil Badola --- include/linux/usb/xhci-fsl.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include/linux') diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 8eaab2c10e..b07bf196f2 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -51,4 +51,11 @@ struct fsl_xhci { struct dwc3 *dwc3_reg; }; +#if defined(CONFIG_LS102XA) +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 +#endif + +#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \ + CONFIG_SYS_FSL_XHCI_USB2_ADDR} #endif /* _ASM_ARCH_XHCI_FSL_H_ */ -- cgit v1.2.1 From 2f47324255e6c9d106310ed1a2198ffb24e4891e Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Tue, 23 Jun 2015 09:18:20 +0530 Subject: include: usb: Map USB controller base addresses for LS2085A Map USB XHCI controller base addresses for LS2085A SOC Signed-off-by: Nikhil Badola --- include/linux/usb/xhci-fsl.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/linux') diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index b07bf196f2..602a413ccb 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -54,6 +54,9 @@ struct fsl_xhci { #if defined(CONFIG_LS102XA) #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 +#elif defined(CONFIG_LS2085A) +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2085A_XHCI_USB1_ADDR +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2085A_XHCI_USB2_ADDR #endif #define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \ -- cgit v1.2.1