From 4c52783b3d024e153c4972b97332e314bc3bdc46 Mon Sep 17 00:00:00 2001 From: roy zang Date: Thu, 2 Nov 2006 18:49:51 +0800 Subject: General code modification for mpc7448hpc2 board support. 1. Add 7447A and 7448 processor support. 2. Add the following flags. CFG_CONFIG_BUS_CLK : If the 74xx bus frequency can be configured dynamically (such as by switch on board), this flag should be set. CFG_EXCEPTION_AFTER_RELOCATE: If an exception occurs after the u-boot relocates to RAM, this flag should be set. CFG_SERIAL_HANG_IN_EXCEPTION: If the print out function will cause the system hang in exception, this flag should be set. There is a design issue for tsi108/109 pci configure read. When pci scan the slots, if there is no pci card, the tsi108/9 will cause a machine check exception for mpc7448 processor. Signed-off-by: Alexandre Bounine Signed-off-by: Roy Zang --- include/74xx_7xx.h | 1 + include/asm-ppc/global_data.h | 3 +++ 2 files changed, 4 insertions(+) (limited to 'include') diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h index a6287982a6..7cd2f10b01 100644 --- a/include/74xx_7xx.h +++ b/include/74xx_7xx.h @@ -112,6 +112,7 @@ typedef enum __cpu_t { CPU_7400, CPU_7410, CPU_7450, CPU_7455, CPU_7457, + CPU_7447A, CPU_7448, CPU_UNKNOWN} cpu_t; extern cpu_t get_cpu_type(void); diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index b73af96464..166afbe87a 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -49,6 +49,9 @@ typedef struct global_data { unsigned long scc_clk; unsigned long brg_clk; #endif +#if defined(CONFIG_MPC7448HPC2) + unsigned long mem_clk; +#endif #if defined(CONFIG_MPC83XX) /* There are other clocks in the MPC83XX */ u32 csb_clk; -- cgit v1.2.1 From c6411c0c3bbc79f9ba8aef58296a42d8f9d8a0a6 Mon Sep 17 00:00:00 2001 From: roy zang Date: Thu, 2 Nov 2006 18:55:04 +0800 Subject: Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. The mpc7448hpc2 board support header file. Signed-off-by: Alexandre Bounine Signed-off-by: Roy Zang --- include/configs/mpc7448hpc2.h | 453 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 453 insertions(+) create mode 100644 include/configs/mpc7448hpc2.h (limited to 'include') diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h new file mode 100644 index 0000000000..9243d58097 --- /dev/null +++ b/include/configs/mpc7448hpc2.h @@ -0,0 +1,453 @@ +/* + * Copyright (c) 2005 Freescale Semiconductor, Inc. + * + * (C) Copyright 2006 + * Alex Bounine , Tundra Semiconductor Corp. + * Roy Zang , Freescale Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/**************************************************************** + * + * board specific configuration options for Freescale + * MPC7448HPC2 (High-Performance Computing II) (Taiga) board + * + ****************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* Board Configuration Definitions */ +/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */ + +#define CONFIG_MPC7448HPC2 + +#define CONFIG_74xx +#define CONFIG_750FX /* this option to enable init of extended BATs */ +#define CONFIG_ALTIVEC /* undef to disable */ + +#define CFG_BOARD_NAME "MPC7448 HPC II" +#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II" + +#define CFG_OCN_CLK 133000000 /* 133 MHz */ +#define CFG_CONFIG_BUS_CLK 133000000 + +#define CFG_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */ + +#undef CONFIG_ECC /* disable ECC support */ + +/* Board-specific Initialization Functions to be called */ +#define CFG_BOARD_ASM_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +/* Default MAC Addresses for on-chip GIGE Controller */ + +#define CONFIG_ETHADDR 00:06:D2:00:00:01 + +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:06:D2:00:00:02 + +#define CONFIG_ENV_OVERWRITE + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ + +/*#define CFG_HUSH_PARSER */ +#undef CFG_HUSH_PARSER + +#define CFG_PROMPT_HUSH_PS2 "> " + +/* Pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,7448@0" +#define OF_TSI "tsi108@c0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808" + +/* + * The following defines let you select what serial you want to use + * for your console driver. + * + * what to do: + * If you have hacked a serial cable onto the second DUART channel, change the CFG_DUART port from 1 + * to 0 below. + * + */ + +#define CONFIG_CONS_INDEX 1 +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK CFG_OCN_CLK * 8 + +#define CFG_NS16550_COM1 (CFG_TSI108_CSR_RST_BASE+0x7808) +#define CFG_NS16550_COM2 (CFG_TSI108_CSR_RST_BASE+0x7C08) +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#undef CONFIG_BOOTARGS +/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */ + +#if (CONFIG_BOOTDELAY >= 0) +#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\ + setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ + ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; " + +#define CONFIG_BOOTARGS "console=ttyS0,115200" +#endif + +#undef CONFIG_EXTRA_ENV_SETTINGS + +#define CONFIG_SERIAL "No. 1" + +/* Networking Configuration */ + +#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */ + +#define CONFIG_TSI108_ETH +#define CONFIG_TSI108_ETH_NUM_PORTS 2 + +#define CONFIG_NET_MULTI + +#define CONFIG_IPADDR 172.27.234.48 +#define CONFIG_SERVERIP 172.27.234.10 +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_GATEWAYIP 172.27.255.254 + +#define CONFIG_BOOTFILE zImage.initrd.elf +#define CONFIG_LOADADDR 0x400000 + +#define CONFIG_TESTDRAMDATA y +#define CONFIG_TESTDRAMADDRESS n +#define CONFIG_TESETDRAMWALK n + +/*-------------------------------------------------------------------------- */ + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) + +/* Flash banks JFFS2 should use */ +#define CFG_JFFS2_FIRST_BANK 1 +#define CFG_JFFS2_NUM_BANKS 1 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ + | CFG_CMD_CACHE \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C \ + | CFG_CMD_SDRAM \ + | CFG_CMD_EEPROM \ + | CFG_CMD_NET \ + | CFG_CMD_FLASH \ + | CFG_CMD_ENV \ + | CFG_CMD_BSP \ + | CFG_CMD_DHCP \ + | CFG_CMD_PING \ + | CFG_CMD_DATE) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*set date in u-boot*/ +#define CONFIG_RTC_M48T35A +#define CFG_NVRAM_BASE_ADDR 0xfc000000 +#define CFG_NVRAM_SIZE 0x8000 +/* + * Miscellaneous configurable options + */ +#define CONFIG_VERSION_VARIABLE 1 +#define CONFIG_TSI108_I2C + +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* +#define CFG_DRAM_TEST + * DRAM tests + * CFG_DRAM_TEST - enables the following tests. + * + * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines + * Environment variable 'test_dram_data' must be + * set to 'y'. + * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely + * addressable. Environment variable + * 'test_dram_address' must be set to 'y'. + * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. + * This test takes about 6 minutes to test 64 MB. + * Environment variable 'test_dram_walk' must be + * set to 'y'. + */ +#define CFG_DRAM_TEST +#if defined(CFG_DRAM_TEST) +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ +#define CFG_DRAM_TEST_DATA +#define CFG_DRAM_TEST_ADDRESS +#define CFG_DRAM_TEST_WALK +#endif /* CFG_DRAM_TEST */ + +#define CFG_LOAD_ADDR 0x00400000 /* default load address */ + +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + +/* + * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS + * To an unused memory region. The stack will remain in cache until RAM + * is initialized +*/ +#undef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x07d00000 /* unused memory region */ +#define CFG_INIT_RAM_END 0x4000 /* larger space - we have SDRAM initialized */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ + +#define CFG_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */ +#define CFG_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */ + +#define CFG_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */ +#define CFG_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */ + +#define CFG_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */ + +#define CFG_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */ + +#define CFG_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */ + +#define CFG_FLASH_BASE 0xff000000 /* Base Address of Flash device */ +#define CFG_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */ + +#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */ + +#define PCI0_IO_BASE_BOOTM 0xfd000000 + +#define CFG_RESET_ADDRESS 0x3fffff00 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* u-boot code base */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ + +/* Peripheral Device section */ + +/******************************************************* + * Resources on the Tsi108 + *******************************************************/ + +#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */ +#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */ + +#define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */ + +#undef DISABLE_PBM + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_TSI108_PCI /* include tsi108 pci support */ + +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +/* PCI MEMORY MAP section */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +/* PCI Memory Space */ +#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS) +#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) //CFG_PCI_MEM32_BASE = 0xE0000000 +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */ + +/* PCI I/O Space */ +#define CFG_PCI_IO_BUS 0x00000000 +#define CFG_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */ + +#define CFG_PCI_IO_SIZE 0x01000000 /* 16MB */ + +#define _IO_BASE 0x00000000 /* points to PCI I/O space */ + +/* PCI Config Space mapping */ +#define CFG_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */ +#define CFG_PCI_CFG_SIZE 0x01000000 /* 16MB */ + +#define CFG_IBAT0U 0xFE0003FF +#define CFG_IBAT0L 0xFE000002 + +#define CFG_IBAT1U 0x00007FFF +#define CFG_IBAT1L 0x00000012 + +#define CFG_IBAT2U 0x80007FFF +#define CFG_IBAT2L 0x80000022 + +#define CFG_IBAT3U 0x00000000 +#define CFG_IBAT3L 0x00000000 + +#define CFG_IBAT4U 0x00000000 +#define CFG_IBAT4L 0x00000000 + +#define CFG_IBAT5U 0x00000000 +#define CFG_IBAT5L 0x00000000 + +#define CFG_IBAT6U 0x00000000 +#define CFG_IBAT6L 0x00000000 + +#define CFG_IBAT7U 0x00000000 +#define CFG_IBAT7L 0x00000000 + +#define CFG_DBAT0U 0xE0003FFF +#define CFG_DBAT0L 0xE000002A + +#define CFG_DBAT1U 0x00007FFF +#define CFG_DBAT1L 0x00000012 + +#define CFG_DBAT2U 0x00000000 +#define CFG_DBAT2L 0x00000000 + +#define CFG_DBAT3U 0xC0000003 +#define CFG_DBAT3L 0xC000002A + +#define CFG_DBAT4U 0x00000000 +#define CFG_DBAT4L 0x00000000 + +#define CFG_DBAT5U 0x00000000 +#define CFG_DBAT5L 0x00000000 + +#define CFG_DBAT6U 0x00000000 +#define CFG_DBAT6L 0x00000000 + +#define CFG_DBAT7U 0x00000000 +#define CFG_DBAT7L 0x00000000 + +/* I2C addresses for the two DIMM SPD chips */ +#define DIMM0_I2C_ADDR 0x51 +#define DIMM1_I2C_ADDR 0x52 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */ +#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_SWAP + +#define PHYS_FLASH_SIZE 0x01000000 +#define CFG_MAX_FLASH_SECT (128) + +#define CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_ADDR 0xFC000000 + +#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * L2CR setup -- make sure this is right for your board! + * look in include/mpc74xx.h for the defines used here + */ +#undef CFG_L2 + +#define L2_INIT 0 +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CFG_EXCEPTION_AFTER_RELOCATE +#define CFG_SERIAL_HANG_IN_EXCEPTION +#endif /* __CONFIG_H */ -- cgit v1.2.1 From 78aa0c3427f3ecdeb34aabfbbe2dd23b6ad8f40e Mon Sep 17 00:00:00 2001 From: roy zang Date: Thu, 2 Nov 2006 19:01:33 +0800 Subject: Tundra tsi108 header file. The Tundra Semiconductor Corporation (Tundra) Tsi108 is a host bridge for PowerPC processors that offers numerous system interconnect options for embedded application designers. The Tsi108 can interconnect 60x or MPX processors to PCI/X peripherals, DDR2-400 memory, Gigabit Ethernet, and Flash. Provided the macro define for tsi108 chip. Signed-off-by: Alexandre Bounine Signed-off-by: Roy Zang --- include/tsi108.h | 221 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 221 insertions(+) create mode 100644 include/tsi108.h (limited to 'include') diff --git a/include/tsi108.h b/include/tsi108.h new file mode 100644 index 0000000000..072daa03c3 --- /dev/null +++ b/include/tsi108.h @@ -0,0 +1,221 @@ +/***************************************************************************** + * (C) Copyright 2003; Tundra Semiconductor Corp. + * (C) Copyright 2006; Freescale Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + *****************************************************************************/ + +/* + * FILENAME: tsi108.h + * + * Originator: Alex Bounine + * + * DESCRIPTION: + * Common definitions for the Tundra Tsi108 bridge chip + * + */ + +#ifndef _TSI108_H_ +#define _TSI108_H_ + +#define TSI108_HLP_REG_OFFSET (0x0000) +#define TSI108_PCI_REG_OFFSET (0x1000) +#define TSI108_CLK_REG_OFFSET (0x2000) +#define TSI108_PB_REG_OFFSET (0x3000) +#define TSI108_SD_REG_OFFSET (0x4000) +#define TSI108_MPIC_REG_OFFSET (0x7400) + +#define PB_ID (0x000) +#define PB_RSR (0x004) +#define PB_BUS_MS_SELECT (0x008) +#define PB_ISR (0x00C) +#define PB_ARB_CTRL (0x018) +#define PB_PVT_CTRL2 (0x034) +#define PB_SCR (0x400) +#define PB_ERRCS (0x404) +#define PB_AERR (0x408) +#define PB_REG_BAR (0x410) +#define PB_OCN_BAR1 (0x414) +#define PB_OCN_BAR2 (0x418) +#define PB_SDRAM_BAR1 (0x41C) +#define PB_SDRAM_BAR2 (0x420) +#define PB_MCR (0xC00) +#define PB_MCMD (0xC04) + +#define HLP_B0_ADDR (0x000) +#define HLP_B1_ADDR (0x010) +#define HLP_B2_ADDR (0x020) +#define HLP_B3_ADDR (0x030) + +#define HLP_B0_MASK (0x004) +#define HLP_B1_MASK (0x014) +#define HLP_B2_MASK (0x024) +#define HLP_B3_MASK (0x034) + +#define HLP_B0_CTRL0 (0x008) +#define HLP_B1_CTRL0 (0x018) +#define HLP_B2_CTRL0 (0x028) +#define HLP_B3_CTRL0 (0x038) + +#define HLP_B0_CTRL1 (0x00C) +#define HLP_B1_CTRL1 (0x01C) +#define HLP_B2_CTRL1 (0x02C) +#define HLP_B3_CTRL1 (0x03C) + +#define PCI_CSR (0x004) +#define PCI_P2O_BAR0 (0x010) +#define PCI_P2O_BAR0_UPPER (0x014) +#define PCI_P2O_BAR2 (0x018) +#define PCI_P2O_BAR2_UPPER (0x01C) +#define PCI_P2O_BAR3 (0x020) +#define PCI_P2O_BAR3_UPPER (0x024) + +#define PCI_MISC_CSR (0x040) +#define PCI_P2O_PAGE_SIZES (0x04C) + +#define PCI_PCIX_STAT (0x0F4) + +#define PCI_IRP_STAT (0x184) + +#define PCI_PFAB_BAR0 (0x204) +#define PCI_PFAB_BAR0_UPPER (0x208) +#define PCI_PFAB_IO (0x20C) +#define PCI_PFAB_IO_UPPER (0x210) + +#define PCI_PFAB_MEM32 (0x214) +#define PCI_PFAB_MEM32_REMAP (0x218) +#define PCI_PFAB_MEM32_MASK (0x21C) + +#define CG_PLL0_CTRL0 (0x210) +#define CG_PLL0_CTRL1 (0x214) +#define CG_PLL1_CTRL0 (0x220) +#define CG_PLL1_CTRL1 (0x224) +#define CG_PWRUP_STATUS (0x234) + +#define MPIC_CSR(n) (0x30C + (n * 0x40)) + +#define SD_CTRL (0x000) +#define SD_STATUS (0x004) +#define SD_TIMING (0x008) +#define SD_REFRESH (0x00C) +#define SD_INT_STATUS (0x010) +#define SD_INT_ENABLE (0x014) +#define SD_INT_SET (0x018) +#define SD_D0_CTRL (0x020) +#define SD_D1_CTRL (0x024) +#define SD_D0_BAR (0x028) +#define SD_D1_BAR (0x02C) +#define SD_ECC_CTRL (0x040) +#define SD_DLL_STATUS (0x250) + +#define TS_SD_CTRL_ENABLE (1 << 31) + +#define PB_ERRCS_ES (1 << 1) +#define PB_ISR_PBS_RD_ERR (1 << 8) +#define PCI_IRP_STAT_P_CSR (1 << 23) + +/* + * I2C : Register address offset definitions + */ +#define I2C_CNTRL1 (0x00000000) +#define I2C_CNTRL2 (0x00000004) +#define I2C_RD_DATA (0x00000008) +#define I2C_TX_DATA (0x0000000c) + +/* + * I2C : Register Bit Masks and Reset Values + * definitions for every register + */ + +/* I2C_CNTRL1 : Reset Value */ +#define I2C_CNTRL1_RESET_VALUE (0x0000000a) + +/* I2C_CNTRL1 : Register Bits Masks Definitions */ +#define I2C_CNTRL1_DEVCODE (0x0000000f) +#define I2C_CNTRL1_PAGE (0x00000700) +#define I2C_CNTRL1_BYTADDR (0x00ff0000) +#define I2C_CNTRL1_I2CWRITE (0x01000000) + +/* I2C_CNTRL1 : Read/Write Bit Mask Definition */ +#define I2C_CNTRL1_RWMASK (0x01ff070f) + +/* I2C_CNTRL1 : Unused/Reserved bits Definition */ +#define I2C_CNTRL1_RESERVED (0xfe00f8f0) + +/* I2C_CNTRL2 : Reset Value */ +#define I2C_CNTRL2_RESET_VALUE (0x00000000) + +/* I2C_CNTRL2 : Register Bits Masks Definitions */ +#define I2C_CNTRL2_SIZE (0x00000003) +#define I2C_CNTRL2_LANE (0x0000000c) +#define I2C_CNTRL2_MULTIBYTE (0x00000010) +#define I2C_CNTRL2_START (0x00000100) +#define I2C_CNTRL2_WR_STATUS (0x00010000) +#define I2C_CNTRL2_RD_STATUS (0x00020000) +#define I2C_CNTRL2_I2C_TO_ERR (0x04000000) +#define I2C_CNTRL2_I2C_CFGERR (0x08000000) +#define I2C_CNTRL2_I2C_CMPLT (0x10000000) + +/* I2C_CNTRL2 : Read/Write Bit Mask Definition */ +#define I2C_CNTRL2_RWMASK (0x0000011f) + +/* I2C_CNTRL2 : Unused/Reserved bits Definition */ +#define I2C_CNTRL2_RESERVED (0xe3fcfee0) + +/* I2C_RD_DATA : Reset Value */ +#define I2C_RD_DATA_RESET_VALUE (0x00000000) + +/* I2C_RD_DATA : Register Bits Masks Definitions */ +#define I2C_RD_DATA_RBYTE0 (0x000000ff) +#define I2C_RD_DATA_RBYTE1 (0x0000ff00) +#define I2C_RD_DATA_RBYTE2 (0x00ff0000) +#define I2C_RD_DATA_RBYTE3 (0xff000000) + +/* I2C_RD_DATA : Read/Write Bit Mask Definition */ +#define I2C_RD_DATA_RWMASK (0x00000000) + +/* I2C_RD_DATA : Unused/Reserved bits Definition */ +#define I2C_RD_DATA_RESERVED (0x00000000) + +/* I2C_TX_DATA : Reset Value */ +#define I2C_TX_DATA_RESET_VALUE (0x00000000) + +/* I2C_TX_DATA : Register Bits Masks Definitions */ +#define I2C_TX_DATA_TBYTE0 (0x000000ff) +#define I2C_TX_DATA_TBYTE1 (0x0000ff00) +#define I2C_TX_DATA_TBYTE2 (0x00ff0000) +#define I2C_TX_DATA_TBYTE3 (0xff000000) + +/* I2C_TX_DATA : Read/Write Bit Mask Definition */ +#define I2C_TX_DATA_RWMASK (0xffffffff) + +/* I2C_TX_DATA : Unused/Reserved bits Definition */ +#define I2C_TX_DATA_RESERVED (0x00000000) + +#define TSI108_I2C_OFFSET 0x7000 /* register block offset for general use I2C channel */ +#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* register block offset for SPD I2C channel */ + +#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */ + +/* I2C status codes */ + +#define TSI108_I2C_SUCCESS 0 +#define TSI108_I2C_PARAM_ERR 1 +#define TSI108_I2C_TIMEOUT_ERR 2 +#define TSI108_I2C_IF_BUSY 3 +#define TSI108_I2C_IF_ERROR 4 + +#endif /* _TSI108_H_ */ -- cgit v1.2.1 From 4831c8b8a97799da77923d6bbb4c260c0d45521c Mon Sep 17 00:00:00 2001 From: roy zang Date: Fri, 3 Nov 2006 13:10:00 +0800 Subject: Remove some unused CFG define. undef CFG_DRAM_TEST --- include/configs/mpc7448hpc2.h | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 9243d58097..24cc86bebc 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -149,10 +149,6 @@ #define CONFIG_BOOTFILE zImage.initrd.elf #define CONFIG_LOADADDR 0x400000 -#define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n -#define CONFIG_TESETDRAMWALK n - /*-------------------------------------------------------------------------- */ #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ @@ -163,10 +159,6 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ CONFIG_BOOTP_BOOTFILESIZE) -/* Flash banks JFFS2 should use */ -#define CFG_JFFS2_FIRST_BANK 1 -#define CFG_JFFS2_NUM_BANKS 1 - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_ASKENV \ | CFG_CMD_CACHE \ @@ -174,7 +166,6 @@ | CFG_CMD_I2C \ | CFG_CMD_SDRAM \ | CFG_CMD_EEPROM \ - | CFG_CMD_NET \ | CFG_CMD_FLASH \ | CFG_CMD_ENV \ | CFG_CMD_BSP \ @@ -220,7 +211,7 @@ * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines * Environment variable 'test_dram_data' must be * set to 'y'. - * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely + * CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word is uniquely * addressable. Environment variable * 'test_dram_address' must be set to 'y'. * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. @@ -228,10 +219,10 @@ * Environment variable 'test_dram_walk' must be * set to 'y'. */ -#define CFG_DRAM_TEST -#if defined(CFG_DRAM_TEST) +#undef CFG_DRAM_TEST #define CFG_MEMTEST_START 0x00400000 /* memtest works on */ #define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ +#if defined(CFG_DRAM_TEST) #define CFG_DRAM_TEST_DATA #define CFG_DRAM_TEST_ADDRESS #define CFG_DRAM_TEST_WALK -- cgit v1.2.1 From ee311214e0d216f904feea269599d0934bf71f23 Mon Sep 17 00:00:00 2001 From: roy zang Date: Fri, 1 Dec 2006 11:47:36 +0800 Subject: Clean up the code according to codestyle: (1) remove some C++ comments. (2) remove trailing white space. (3) remove trailing empty line. (4) Indentation by table. (5) remove {} in one line condition. (6) add space before '(' in function call. Remove some weird printf () output. Add necessary comments. Modified Makefile to support building in a separate directory. --- include/configs/mpc7448hpc2.h | 290 +++++++++++++++++++++--------------------- include/tsi108.h | 280 ++++++++++++++++++++-------------------- 2 files changed, 285 insertions(+), 285 deletions(-) (limited to 'include') diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 24cc86bebc..b13b699b59 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -24,12 +24,11 @@ * MA 02111-1307 USA */ -/**************************************************************** - * +/* * board specific configuration options for Freescale * MPC7448HPC2 (High-Performance Computing II) (Taiga) board * - ****************************************************************/ + */ #ifndef __CONFIG_H #define __CONFIG_H @@ -45,11 +44,11 @@ #define CONFIG_750FX /* this option to enable init of extended BATs */ #define CONFIG_ALTIVEC /* undef to disable */ -#define CFG_BOARD_NAME "MPC7448 HPC II" -#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II" +#define CFG_BOARD_NAME "MPC7448 HPC II" +#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II" -#define CFG_OCN_CLK 133000000 /* 133 MHz */ -#define CFG_CONFIG_BUS_CLK 133000000 +#define CFG_OCN_CLK 133000000 /* 133 MHz */ +#define CFG_CONFIG_BUS_CLK 133000000 #define CFG_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */ @@ -63,10 +62,10 @@ /* Default MAC Addresses for on-chip GIGE Controller */ -#define CONFIG_ETHADDR 00:06:D2:00:00:01 +#define CONFIG_ETHADDR 00:06:D2:00:00:01 #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:06:D2:00:00:02 +#define CONFIG_ETH1ADDR 00:06:D2:00:00:02 #define CONFIG_ENV_OVERWRITE @@ -75,12 +74,12 @@ * (easy to change) */ -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ /*#define CFG_HUSH_PARSER */ #undef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " /* Pass open firmware flat tree */ #define CONFIG_OF_FLAT_TREE 1 @@ -99,29 +98,30 @@ * for your console driver. * * what to do: - * If you have hacked a serial cable onto the second DUART channel, change the CFG_DUART port from 1 - * to 0 below. + * If you have hacked a serial cable onto the second DUART channel, + * change the CFG_DUART port from 1 to 0 below. * */ -#define CONFIG_CONS_INDEX 1 +#define CONFIG_CONS_INDEX 1 #define CFG_NS16550 #define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_REG_SIZE 1 #define CFG_NS16550_CLK CFG_OCN_CLK * 8 -#define CFG_NS16550_COM1 (CFG_TSI108_CSR_RST_BASE+0x7808) -#define CFG_NS16550_COM2 (CFG_TSI108_CSR_RST_BASE+0x7C08) +#define CFG_NS16550_COM1 (CFG_TSI108_CSR_RST_BASE+0x7808) +#define CFG_NS16550_COM2 (CFG_TSI108_CSR_RST_BASE+0x7C08) #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #define CONFIG_ZERO_BOOTDELAY_CHECK #undef CONFIG_BOOTARGS -/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */ +/* #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" + * to mount root filesystem over NFS;echo" */ #if (CONFIG_BOOTDELAY >= 0) -#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\ +#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\ setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; " @@ -130,34 +130,34 @@ #undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_SERIAL "No. 1" +#define CONFIG_SERIAL "No. 1" /* Networking Configuration */ -#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */ +#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */ #define CONFIG_TSI108_ETH -#define CONFIG_TSI108_ETH_NUM_PORTS 2 +#define CONFIG_TSI108_ETH_NUM_PORTS 2 #define CONFIG_NET_MULTI -#define CONFIG_IPADDR 172.27.234.48 -#define CONFIG_SERVERIP 172.27.234.10 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_GATEWAYIP 172.27.255.254 +#define CONFIG_IPADDR 172.27.234.48 +#define CONFIG_SERVERIP 172.27.234.10 +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_GATEWAYIP 172.27.255.254 -#define CONFIG_BOOTFILE zImage.initrd.elf -#define CONFIG_LOADADDR 0x400000 +#define CONFIG_BOOTFILE zImage.initrd.elf +#define CONFIG_LOADADDR 0x400000 /*-------------------------------------------------------------------------- */ -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_ASKENV \ @@ -178,59 +178,59 @@ /*set date in u-boot*/ #define CONFIG_RTC_M48T35A -#define CFG_NVRAM_BASE_ADDR 0xfc000000 -#define CFG_NVRAM_SIZE 0x8000 +#define CFG_NVRAM_BASE_ADDR 0xfc000000 +#define CFG_NVRAM_SIZE 0x8000 /* * Miscellaneous configurable options */ -#define CONFIG_VERSION_VARIABLE 1 +#define CONFIG_VERSION_VARIABLE 1 #define CONFIG_TSI108_I2C -#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)/* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ /* #define CFG_DRAM_TEST - * DRAM tests - * CFG_DRAM_TEST - enables the following tests. + * DRAM tests + * CFG_DRAM_TEST - enables the following tests. * - * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. + * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines + * Environment variable 'test_dram_data' must be + * set to 'y'. + * CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word + * is uniquely addressable. Environment variable + * 'test_dram_address' must be set to 'y'. + * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. + * This test takes about 6 minutes to test 64 MB. + * Environment variable 'test_dram_walk' must be + * set to 'y'. */ #undef CFG_DRAM_TEST -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ #if defined(CFG_DRAM_TEST) #define CFG_DRAM_TEST_DATA #define CFG_DRAM_TEST_ADDRESS #define CFG_DRAM_TEST_WALK -#endif /* CFG_DRAM_TEST */ +#endif /* CFG_DRAM_TEST */ -#define CFG_LOAD_ADDR 0x00400000 /* default load address */ +#define CFG_LOAD_ADDR 0x00400000 /* default load address */ -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ /* * Low Level Configuration Settings @@ -246,12 +246,12 @@ * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS * To an unused memory region. The stack will remain in cache until RAM * is initialized -*/ + */ #undef CFG_INIT_RAM_LOCK -#define CFG_INIT_RAM_ADDR 0x07d00000 /* unused memory region */ -#define CFG_INIT_RAM_END 0x4000 /* larger space - we have SDRAM initialized */ +#define CFG_INIT_RAM_ADDR 0x07d00000 /* unused memory region */ +#define CFG_INIT_RAM_END 0x4000/* larger space - we have SDRAM initialized */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ +#define CFG_GBL_DATA_SIZE 128/* size in bytes reserved for init data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) /*----------------------------------------------------------------------- @@ -260,54 +260,54 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */ -#define CFG_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */ +#define CFG_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */ +#define CFG_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */ -#define CFG_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */ -#define CFG_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */ +#define CFG_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */ +#define CFG_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */ -#define CFG_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */ +#define CFG_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */ -#define CFG_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */ +#define CFG_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */ -#define CFG_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */ +#define CFG_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */ -#define CFG_FLASH_BASE 0xff000000 /* Base Address of Flash device */ -#define CFG_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */ +#define CFG_FLASH_BASE 0xff000000 /* Base Address of Flash device */ +#define CFG_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */ #define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */ -#define PCI0_IO_BASE_BOOTM 0xfd000000 +#define PCI0_IO_BASE_BOOTM 0xfd000000 -#define CFG_RESET_ADDRESS 0x3fffff00 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE TEXT_BASE /* u-boot code base */ -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ +#define CFG_RESET_ADDRESS 0x3fffff00 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* u-boot code base */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ /* Peripheral Device section */ -/******************************************************* +/* * Resources on the Tsi108 - *******************************************************/ + */ -#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */ -#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */ +#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */ +#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */ #define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */ #undef DISABLE_PBM -/*----------------------------------------------------------------------- +/* * PCI stuff - *----------------------------------------------------------------------- + * */ #define CONFIG_PCI /* include pci support */ #define CONFIG_TSI108_PCI /* include tsi108 pci support */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ @@ -315,20 +315,20 @@ /* PCI MEMORY MAP section */ /* PCI view of System Memory */ -#define CFG_PCI_MEMORY_BUS 0x00000000 -#define CFG_PCI_MEMORY_PHYS 0x00000000 -#define CFG_PCI_MEMORY_SIZE 0x80000000 +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 /* PCI Memory Space */ -#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS) -#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) //CFG_PCI_MEM32_BASE = 0xE0000000 -#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */ +#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS) +#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) /* 0xE0000000 */ +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */ /* PCI I/O Space */ -#define CFG_PCI_IO_BUS 0x00000000 -#define CFG_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */ +#define CFG_PCI_IO_BUS 0x00000000 +#define CFG_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */ -#define CFG_PCI_IO_SIZE 0x01000000 /* 16MB */ +#define CFG_PCI_IO_SIZE 0x01000000 /* 16MB */ #define _IO_BASE 0x00000000 /* points to PCI I/O space */ @@ -336,91 +336,91 @@ #define CFG_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */ #define CFG_PCI_CFG_SIZE 0x01000000 /* 16MB */ -#define CFG_IBAT0U 0xFE0003FF -#define CFG_IBAT0L 0xFE000002 +#define CFG_IBAT0U 0xFE0003FF +#define CFG_IBAT0L 0xFE000002 -#define CFG_IBAT1U 0x00007FFF -#define CFG_IBAT1L 0x00000012 +#define CFG_IBAT1U 0x00007FFF +#define CFG_IBAT1L 0x00000012 -#define CFG_IBAT2U 0x80007FFF -#define CFG_IBAT2L 0x80000022 +#define CFG_IBAT2U 0x80007FFF +#define CFG_IBAT2L 0x80000022 -#define CFG_IBAT3U 0x00000000 -#define CFG_IBAT3L 0x00000000 +#define CFG_IBAT3U 0x00000000 +#define CFG_IBAT3L 0x00000000 -#define CFG_IBAT4U 0x00000000 -#define CFG_IBAT4L 0x00000000 +#define CFG_IBAT4U 0x00000000 +#define CFG_IBAT4L 0x00000000 -#define CFG_IBAT5U 0x00000000 -#define CFG_IBAT5L 0x00000000 +#define CFG_IBAT5U 0x00000000 +#define CFG_IBAT5L 0x00000000 -#define CFG_IBAT6U 0x00000000 -#define CFG_IBAT6L 0x00000000 +#define CFG_IBAT6U 0x00000000 +#define CFG_IBAT6L 0x00000000 -#define CFG_IBAT7U 0x00000000 -#define CFG_IBAT7L 0x00000000 +#define CFG_IBAT7U 0x00000000 +#define CFG_IBAT7L 0x00000000 -#define CFG_DBAT0U 0xE0003FFF -#define CFG_DBAT0L 0xE000002A +#define CFG_DBAT0U 0xE0003FFF +#define CFG_DBAT0L 0xE000002A -#define CFG_DBAT1U 0x00007FFF -#define CFG_DBAT1L 0x00000012 +#define CFG_DBAT1U 0x00007FFF +#define CFG_DBAT1L 0x00000012 -#define CFG_DBAT2U 0x00000000 -#define CFG_DBAT2L 0x00000000 +#define CFG_DBAT2U 0x00000000 +#define CFG_DBAT2L 0x00000000 -#define CFG_DBAT3U 0xC0000003 -#define CFG_DBAT3L 0xC000002A +#define CFG_DBAT3U 0xC0000003 +#define CFG_DBAT3L 0xC000002A -#define CFG_DBAT4U 0x00000000 -#define CFG_DBAT4L 0x00000000 +#define CFG_DBAT4U 0x00000000 +#define CFG_DBAT4L 0x00000000 -#define CFG_DBAT5U 0x00000000 -#define CFG_DBAT5L 0x00000000 +#define CFG_DBAT5U 0x00000000 +#define CFG_DBAT5L 0x00000000 -#define CFG_DBAT6U 0x00000000 -#define CFG_DBAT6L 0x00000000 +#define CFG_DBAT6U 0x00000000 +#define CFG_DBAT6L 0x00000000 -#define CFG_DBAT7U 0x00000000 -#define CFG_DBAT7L 0x00000000 +#define CFG_DBAT7U 0x00000000 +#define CFG_DBAT7L 0x00000000 /* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x51 -#define DIMM1_I2C_ADDR 0x52 +#define DIMM0_I2C_ADDR 0x51 +#define DIMM1_I2C_ADDR 0x52 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */ -#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ +#define CFG_MAX_FLASH_BANKS 1/* Flash can be at one of two addresses */ +#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_CFI_SWAP -#define PHYS_FLASH_SIZE 0x01000000 -#define CFG_MAX_FLASH_SECT (128) +#define PHYS_FLASH_SIZE 0x01000000 +#define CFG_MAX_FLASH_SECT (128) #define CFG_ENV_IS_IN_NVRAM -#define CFG_ENV_ADDR 0xFC000000 +#define CFG_ENV_ADDR 0xFC000000 -#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */ +#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /*----------------------------------------------------------------------- @@ -429,16 +429,16 @@ */ #undef CFG_L2 -#define L2_INIT 0 -#define L2_ENABLE (L2_INIT | L2CR_L2E) +#define L2_INIT 0 +#define L2_ENABLE (L2_INIT | L2CR_L2E) /* * Internal Definitions * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ #define CFG_EXCEPTION_AFTER_RELOCATE #define CFG_SERIAL_HANG_IN_EXCEPTION -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ diff --git a/include/tsi108.h b/include/tsi108.h index 072daa03c3..ba62e7abe6 100644 --- a/include/tsi108.h +++ b/include/tsi108.h @@ -31,191 +31,191 @@ #ifndef _TSI108_H_ #define _TSI108_H_ -#define TSI108_HLP_REG_OFFSET (0x0000) -#define TSI108_PCI_REG_OFFSET (0x1000) -#define TSI108_CLK_REG_OFFSET (0x2000) -#define TSI108_PB_REG_OFFSET (0x3000) -#define TSI108_SD_REG_OFFSET (0x4000) -#define TSI108_MPIC_REG_OFFSET (0x7400) - -#define PB_ID (0x000) -#define PB_RSR (0x004) -#define PB_BUS_MS_SELECT (0x008) -#define PB_ISR (0x00C) -#define PB_ARB_CTRL (0x018) -#define PB_PVT_CTRL2 (0x034) -#define PB_SCR (0x400) -#define PB_ERRCS (0x404) -#define PB_AERR (0x408) -#define PB_REG_BAR (0x410) -#define PB_OCN_BAR1 (0x414) -#define PB_OCN_BAR2 (0x418) -#define PB_SDRAM_BAR1 (0x41C) -#define PB_SDRAM_BAR2 (0x420) -#define PB_MCR (0xC00) -#define PB_MCMD (0xC04) - -#define HLP_B0_ADDR (0x000) -#define HLP_B1_ADDR (0x010) -#define HLP_B2_ADDR (0x020) -#define HLP_B3_ADDR (0x030) - -#define HLP_B0_MASK (0x004) -#define HLP_B1_MASK (0x014) -#define HLP_B2_MASK (0x024) -#define HLP_B3_MASK (0x034) - -#define HLP_B0_CTRL0 (0x008) -#define HLP_B1_CTRL0 (0x018) -#define HLP_B2_CTRL0 (0x028) -#define HLP_B3_CTRL0 (0x038) - -#define HLP_B0_CTRL1 (0x00C) -#define HLP_B1_CTRL1 (0x01C) -#define HLP_B2_CTRL1 (0x02C) -#define HLP_B3_CTRL1 (0x03C) - -#define PCI_CSR (0x004) -#define PCI_P2O_BAR0 (0x010) -#define PCI_P2O_BAR0_UPPER (0x014) -#define PCI_P2O_BAR2 (0x018) -#define PCI_P2O_BAR2_UPPER (0x01C) -#define PCI_P2O_BAR3 (0x020) -#define PCI_P2O_BAR3_UPPER (0x024) - -#define PCI_MISC_CSR (0x040) -#define PCI_P2O_PAGE_SIZES (0x04C) - -#define PCI_PCIX_STAT (0x0F4) - -#define PCI_IRP_STAT (0x184) - -#define PCI_PFAB_BAR0 (0x204) -#define PCI_PFAB_BAR0_UPPER (0x208) -#define PCI_PFAB_IO (0x20C) -#define PCI_PFAB_IO_UPPER (0x210) - -#define PCI_PFAB_MEM32 (0x214) -#define PCI_PFAB_MEM32_REMAP (0x218) -#define PCI_PFAB_MEM32_MASK (0x21C) - -#define CG_PLL0_CTRL0 (0x210) -#define CG_PLL0_CTRL1 (0x214) -#define CG_PLL1_CTRL0 (0x220) -#define CG_PLL1_CTRL1 (0x224) -#define CG_PWRUP_STATUS (0x234) +#define TSI108_HLP_REG_OFFSET (0x0000) +#define TSI108_PCI_REG_OFFSET (0x1000) +#define TSI108_CLK_REG_OFFSET (0x2000) +#define TSI108_PB_REG_OFFSET (0x3000) +#define TSI108_SD_REG_OFFSET (0x4000) +#define TSI108_MPIC_REG_OFFSET (0x7400) + +#define PB_ID (0x000) +#define PB_RSR (0x004) +#define PB_BUS_MS_SELECT (0x008) +#define PB_ISR (0x00C) +#define PB_ARB_CTRL (0x018) +#define PB_PVT_CTRL2 (0x034) +#define PB_SCR (0x400) +#define PB_ERRCS (0x404) +#define PB_AERR (0x408) +#define PB_REG_BAR (0x410) +#define PB_OCN_BAR1 (0x414) +#define PB_OCN_BAR2 (0x418) +#define PB_SDRAM_BAR1 (0x41C) +#define PB_SDRAM_BAR2 (0x420) +#define PB_MCR (0xC00) +#define PB_MCMD (0xC04) + +#define HLP_B0_ADDR (0x000) +#define HLP_B1_ADDR (0x010) +#define HLP_B2_ADDR (0x020) +#define HLP_B3_ADDR (0x030) + +#define HLP_B0_MASK (0x004) +#define HLP_B1_MASK (0x014) +#define HLP_B2_MASK (0x024) +#define HLP_B3_MASK (0x034) + +#define HLP_B0_CTRL0 (0x008) +#define HLP_B1_CTRL0 (0x018) +#define HLP_B2_CTRL0 (0x028) +#define HLP_B3_CTRL0 (0x038) + +#define HLP_B0_CTRL1 (0x00C) +#define HLP_B1_CTRL1 (0x01C) +#define HLP_B2_CTRL1 (0x02C) +#define HLP_B3_CTRL1 (0x03C) + +#define PCI_CSR (0x004) +#define PCI_P2O_BAR0 (0x010) +#define PCI_P2O_BAR0_UPPER (0x014) +#define PCI_P2O_BAR2 (0x018) +#define PCI_P2O_BAR2_UPPER (0x01C) +#define PCI_P2O_BAR3 (0x020) +#define PCI_P2O_BAR3_UPPER (0x024) + +#define PCI_MISC_CSR (0x040) +#define PCI_P2O_PAGE_SIZES (0x04C) + +#define PCI_PCIX_STAT (0x0F4) + +#define PCI_IRP_STAT (0x184) + +#define PCI_PFAB_BAR0 (0x204) +#define PCI_PFAB_BAR0_UPPER (0x208) +#define PCI_PFAB_IO (0x20C) +#define PCI_PFAB_IO_UPPER (0x210) + +#define PCI_PFAB_MEM32 (0x214) +#define PCI_PFAB_MEM32_REMAP (0x218) +#define PCI_PFAB_MEM32_MASK (0x21C) + +#define CG_PLL0_CTRL0 (0x210) +#define CG_PLL0_CTRL1 (0x214) +#define CG_PLL1_CTRL0 (0x220) +#define CG_PLL1_CTRL1 (0x224) +#define CG_PWRUP_STATUS (0x234) #define MPIC_CSR(n) (0x30C + (n * 0x40)) -#define SD_CTRL (0x000) -#define SD_STATUS (0x004) -#define SD_TIMING (0x008) -#define SD_REFRESH (0x00C) -#define SD_INT_STATUS (0x010) -#define SD_INT_ENABLE (0x014) -#define SD_INT_SET (0x018) -#define SD_D0_CTRL (0x020) -#define SD_D1_CTRL (0x024) -#define SD_D0_BAR (0x028) -#define SD_D1_BAR (0x02C) -#define SD_ECC_CTRL (0x040) -#define SD_DLL_STATUS (0x250) - -#define TS_SD_CTRL_ENABLE (1 << 31) - -#define PB_ERRCS_ES (1 << 1) -#define PB_ISR_PBS_RD_ERR (1 << 8) -#define PCI_IRP_STAT_P_CSR (1 << 23) - -/* +#define SD_CTRL (0x000) +#define SD_STATUS (0x004) +#define SD_TIMING (0x008) +#define SD_REFRESH (0x00C) +#define SD_INT_STATUS (0x010) +#define SD_INT_ENABLE (0x014) +#define SD_INT_SET (0x018) +#define SD_D0_CTRL (0x020) +#define SD_D1_CTRL (0x024) +#define SD_D0_BAR (0x028) +#define SD_D1_BAR (0x02C) +#define SD_ECC_CTRL (0x040) +#define SD_DLL_STATUS (0x250) + +#define TS_SD_CTRL_ENABLE (1 << 31) + +#define PB_ERRCS_ES (1 << 1) +#define PB_ISR_PBS_RD_ERR (1 << 8) +#define PCI_IRP_STAT_P_CSR (1 << 23) + +/* * I2C : Register address offset definitions */ -#define I2C_CNTRL1 (0x00000000) -#define I2C_CNTRL2 (0x00000004) -#define I2C_RD_DATA (0x00000008) -#define I2C_TX_DATA (0x0000000c) +#define I2C_CNTRL1 (0x00000000) +#define I2C_CNTRL2 (0x00000004) +#define I2C_RD_DATA (0x00000008) +#define I2C_TX_DATA (0x0000000c) /* * I2C : Register Bit Masks and Reset Values - * definitions for every register + * definitions for every register */ /* I2C_CNTRL1 : Reset Value */ -#define I2C_CNTRL1_RESET_VALUE (0x0000000a) +#define I2C_CNTRL1_RESET_VALUE (0x0000000a) /* I2C_CNTRL1 : Register Bits Masks Definitions */ -#define I2C_CNTRL1_DEVCODE (0x0000000f) -#define I2C_CNTRL1_PAGE (0x00000700) -#define I2C_CNTRL1_BYTADDR (0x00ff0000) -#define I2C_CNTRL1_I2CWRITE (0x01000000) +#define I2C_CNTRL1_DEVCODE (0x0000000f) +#define I2C_CNTRL1_PAGE (0x00000700) +#define I2C_CNTRL1_BYTADDR (0x00ff0000) +#define I2C_CNTRL1_I2CWRITE (0x01000000) /* I2C_CNTRL1 : Read/Write Bit Mask Definition */ -#define I2C_CNTRL1_RWMASK (0x01ff070f) +#define I2C_CNTRL1_RWMASK (0x01ff070f) /* I2C_CNTRL1 : Unused/Reserved bits Definition */ -#define I2C_CNTRL1_RESERVED (0xfe00f8f0) +#define I2C_CNTRL1_RESERVED (0xfe00f8f0) /* I2C_CNTRL2 : Reset Value */ -#define I2C_CNTRL2_RESET_VALUE (0x00000000) +#define I2C_CNTRL2_RESET_VALUE (0x00000000) /* I2C_CNTRL2 : Register Bits Masks Definitions */ -#define I2C_CNTRL2_SIZE (0x00000003) -#define I2C_CNTRL2_LANE (0x0000000c) -#define I2C_CNTRL2_MULTIBYTE (0x00000010) -#define I2C_CNTRL2_START (0x00000100) -#define I2C_CNTRL2_WR_STATUS (0x00010000) -#define I2C_CNTRL2_RD_STATUS (0x00020000) -#define I2C_CNTRL2_I2C_TO_ERR (0x04000000) -#define I2C_CNTRL2_I2C_CFGERR (0x08000000) -#define I2C_CNTRL2_I2C_CMPLT (0x10000000) +#define I2C_CNTRL2_SIZE (0x00000003) +#define I2C_CNTRL2_LANE (0x0000000c) +#define I2C_CNTRL2_MULTIBYTE (0x00000010) +#define I2C_CNTRL2_START (0x00000100) +#define I2C_CNTRL2_WR_STATUS (0x00010000) +#define I2C_CNTRL2_RD_STATUS (0x00020000) +#define I2C_CNTRL2_I2C_TO_ERR (0x04000000) +#define I2C_CNTRL2_I2C_CFGERR (0x08000000) +#define I2C_CNTRL2_I2C_CMPLT (0x10000000) /* I2C_CNTRL2 : Read/Write Bit Mask Definition */ -#define I2C_CNTRL2_RWMASK (0x0000011f) +#define I2C_CNTRL2_RWMASK (0x0000011f) /* I2C_CNTRL2 : Unused/Reserved bits Definition */ -#define I2C_CNTRL2_RESERVED (0xe3fcfee0) +#define I2C_CNTRL2_RESERVED (0xe3fcfee0) /* I2C_RD_DATA : Reset Value */ -#define I2C_RD_DATA_RESET_VALUE (0x00000000) +#define I2C_RD_DATA_RESET_VALUE (0x00000000) /* I2C_RD_DATA : Register Bits Masks Definitions */ -#define I2C_RD_DATA_RBYTE0 (0x000000ff) -#define I2C_RD_DATA_RBYTE1 (0x0000ff00) -#define I2C_RD_DATA_RBYTE2 (0x00ff0000) -#define I2C_RD_DATA_RBYTE3 (0xff000000) +#define I2C_RD_DATA_RBYTE0 (0x000000ff) +#define I2C_RD_DATA_RBYTE1 (0x0000ff00) +#define I2C_RD_DATA_RBYTE2 (0x00ff0000) +#define I2C_RD_DATA_RBYTE3 (0xff000000) /* I2C_RD_DATA : Read/Write Bit Mask Definition */ -#define I2C_RD_DATA_RWMASK (0x00000000) +#define I2C_RD_DATA_RWMASK (0x00000000) /* I2C_RD_DATA : Unused/Reserved bits Definition */ -#define I2C_RD_DATA_RESERVED (0x00000000) +#define I2C_RD_DATA_RESERVED (0x00000000) /* I2C_TX_DATA : Reset Value */ -#define I2C_TX_DATA_RESET_VALUE (0x00000000) +#define I2C_TX_DATA_RESET_VALUE (0x00000000) /* I2C_TX_DATA : Register Bits Masks Definitions */ -#define I2C_TX_DATA_TBYTE0 (0x000000ff) -#define I2C_TX_DATA_TBYTE1 (0x0000ff00) -#define I2C_TX_DATA_TBYTE2 (0x00ff0000) -#define I2C_TX_DATA_TBYTE3 (0xff000000) +#define I2C_TX_DATA_TBYTE0 (0x000000ff) +#define I2C_TX_DATA_TBYTE1 (0x0000ff00) +#define I2C_TX_DATA_TBYTE2 (0x00ff0000) +#define I2C_TX_DATA_TBYTE3 (0xff000000) /* I2C_TX_DATA : Read/Write Bit Mask Definition */ -#define I2C_TX_DATA_RWMASK (0xffffffff) +#define I2C_TX_DATA_RWMASK (0xffffffff) /* I2C_TX_DATA : Unused/Reserved bits Definition */ -#define I2C_TX_DATA_RESERVED (0x00000000) +#define I2C_TX_DATA_RESERVED (0x00000000) -#define TSI108_I2C_OFFSET 0x7000 /* register block offset for general use I2C channel */ -#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* register block offset for SPD I2C channel */ +#define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */ +#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */ -#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */ +#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */ /* I2C status codes */ -#define TSI108_I2C_SUCCESS 0 -#define TSI108_I2C_PARAM_ERR 1 -#define TSI108_I2C_TIMEOUT_ERR 2 -#define TSI108_I2C_IF_BUSY 3 -#define TSI108_I2C_IF_ERROR 4 +#define TSI108_I2C_SUCCESS 0 +#define TSI108_I2C_PARAM_ERR 1 +#define TSI108_I2C_TIMEOUT_ERR 2 +#define TSI108_I2C_IF_BUSY 3 +#define TSI108_I2C_IF_ERROR 4 #endif /* _TSI108_H_ */ -- cgit v1.2.1 From c9c1eeed7dd193fa65fb194654132040d49d4d3a Mon Sep 17 00:00:00 2001 From: roy zang Date: Fri, 1 Dec 2006 19:01:25 +0800 Subject: Fix the exception occuring in RAM table search issue. The original search_one_table() function code can only processes the search for the exception occurring in FLASH/ROM, because the exception and fixup table usually locate in FLASH. If the exception address is also in FLASH, it will be OK. If the exception occurs in RAM, after the u-boot relocation, a relocation offset should be added. clean up the code in cpu/74xx_7xx/cpu.c Signed-off-by: Roy Zang --- include/configs/mpc7448hpc2.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index b13b699b59..c9131a432c 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -439,6 +439,5 @@ */ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_EXCEPTION_AFTER_RELOCATE #define CFG_SERIAL_HANG_IN_EXCEPTION #endif /* __CONFIG_H */ -- cgit v1.2.1 From 6f12c61cf31ed73d72ddfcfc712a854a3a177aaf Mon Sep 17 00:00:00 2001 From: roy zang Date: Mon, 4 Dec 2006 14:33:08 +0800 Subject: Remove the duplicate memory test code for mpc744ihpc2 board. If a memory test is needed, please use the functions in post/memory.c or memtest command. Signed-off-by: Roy Zang --- include/configs/mpc7448hpc2.h | 22 ---------------------- 1 file changed, 22 deletions(-) (limited to 'include') diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index c9131a432c..38c382cf7c 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -203,30 +203,8 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -/* -#define CFG_DRAM_TEST - * DRAM tests - * CFG_DRAM_TEST - enables the following tests. - * - * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word - * is uniquely addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#undef CFG_DRAM_TEST #define CFG_MEMTEST_START 0x00400000 /* memtest works on */ #define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#if defined(CFG_DRAM_TEST) -#define CFG_DRAM_TEST_DATA -#define CFG_DRAM_TEST_ADDRESS -#define CFG_DRAM_TEST_WALK -#endif /* CFG_DRAM_TEST */ #define CFG_LOAD_ADDR 0x00400000 /* default load address */ -- cgit v1.2.1 From 4efe20c9579011d9987f62ed7d35ee8cdc1cf0e0 Mon Sep 17 00:00:00 2001 From: roy zang Date: Mon, 4 Dec 2006 14:46:23 +0800 Subject: Remove the static MAC address, ip address, server ip, netmask and gateway ip for network setting. Signed-off-by: Roy Zang --- include/configs/mpc7448hpc2.h | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) (limited to 'include') diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 38c382cf7c..6bad515477 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -3,7 +3,7 @@ * * (C) Copyright 2006 * Alex Bounine , Tundra Semiconductor Corp. - * Roy Zang , Freescale Corp. + * Roy Zang , Freescale Corp. * * See file CREDITS for list of people who contributed to this * project. @@ -60,12 +60,7 @@ #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R -/* Default MAC Addresses for on-chip GIGE Controller */ - -#define CONFIG_ETHADDR 00:06:D2:00:00:01 - #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:06:D2:00:00:02 #define CONFIG_ENV_OVERWRITE @@ -141,11 +136,6 @@ #define CONFIG_NET_MULTI -#define CONFIG_IPADDR 172.27.234.48 -#define CONFIG_SERVERIP 172.27.234.10 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_GATEWAYIP 172.27.255.254 - #define CONFIG_BOOTFILE zImage.initrd.elf #define CONFIG_LOADADDR 0x400000 -- cgit v1.2.1 From 9d27b3a0685ff99fc477983f315c04d49f657a8a Mon Sep 17 00:00:00 2001 From: roy zang Date: Mon, 4 Dec 2006 17:56:59 +0800 Subject: Slight code clean up. Add comments, delete duplicate define and remove spaces. Signed-off-by: Roy Zang --- include/74xx_7xx.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h index 8eccac8d59..ba73bae9e5 100644 --- a/include/74xx_7xx.h +++ b/include/74xx_7xx.h @@ -111,9 +111,8 @@ typedef enum __cpu_t { CPU_750CX, CPU_750FX, CPU_750GX, CPU_7400, CPU_7410, - CPU_7448, - CPU_7450, CPU_7455, CPU_7457, CPU_7447A, CPU_7448, + CPU_7450, CPU_7455, CPU_7457, CPU_UNKNOWN} cpu_t; extern cpu_t get_cpu_type(void); -- cgit v1.2.1 From fdef388758506765d4d6a7155c8f1584c63ff581 Mon Sep 17 00:00:00 2001 From: roy zang Date: Mon, 22 Jan 2007 13:19:21 +0800 Subject: use CFG_WRITE_SWAPPED_DATA define instead of define CFG_FLASH_CFI_SWAP The patch by Heiko Schocher on Jan, 19, 2007 fixes cfi_driver bug for mpc7448hpc2 board. The default cfi_driver can support mpc7448hpc2 board. --- include/configs/mpc7448hpc2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 6bad515477..eb528dfaf4 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -372,7 +372,7 @@ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_SWAP +#define CFG_WRITE_SWAPPED_DATA #define PHYS_FLASH_SIZE 0x01000000 #define CFG_MAX_FLASH_SECT (128) -- cgit v1.2.1 From 2605e90bf676d48123afe5719a846d2b52b24aac Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 16 Feb 2007 07:57:42 +0100 Subject: [PATCH] Added support for the jupiter board. Signed-off-by: Heiko Schocher --- include/configs/jupiter.h | 277 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 277 insertions(+) create mode 100644 include/configs/jupiter.h (limited to 'include') diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h new file mode 100644 index 0000000000..0a6dba6721 --- /dev/null +++ b/include/configs/jupiter.h @@ -0,0 +1,277 @@ +/* + * (C) Copyright 2007 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* especially an MPC5200 */ +#define CONFIG_JUPITER 1 /* ... on Jupiter board */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define CONFIG_BOARD_EARLY_INIT_R 1 +#define CONFIG_BOARD_EARLY_INIT_F 1 + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +//#define CONFIG_PCI + +#if defined(CONFIG_PCI) +#define CONFIG_PCI_PNP 1 +#define CONFIG_PCI_SCAN_SHOW 1 + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 +#define ADD_PCI_CMD CFG_CMD_PCI +#endif + +#define CFG_XLB_PIPELINING 1 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "bootfile=/tftpboot/jupiter/uImage\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ + +#if 0 +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,5200@0" +#define OF_SOC "soc5200@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" +#endif + +#if 0 +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 +#endif + +/* + * Flash configuration + */ +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_FLASH_SIZE 0x01000000 + +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#define CFG_ENV_ADDR (TEXT_BASE + 0x40000) /* third sector */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CFG_UPDATE_FLASH_SIZE 1 +#define CFG_FLASH_USE_BUFFER_WRITE 1 + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x20000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_OVERWRITE 1 + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x10000004 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ +#define CFG_ALT_MEMTEST 1 + +#define CFG_LOAD_ADDR 0x200000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00047801 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +#endif /* __CONFIG_H */ -- cgit v1.2.1 From e080313c32322e15ab5a18eb896a252858c57284 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Thu, 7 Dec 2006 21:11:58 +0800 Subject: mpc83xx: streamline the 83xx immr head file For better format and style, I streamlined the 83xx head files, including immap_83xx.h and mpc83xx.h. In the old head files, 1) duplicated macro definition appear in the both files; 2) the structure of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The macro definition put inside the each structure. So, I cleaned up the structure of QE immr from immap_83xx.h, deleted the duplicated stuff and moved the macro definition to mpc83xx.h, Just like MPC8260. CHANGELOG *streamline the 83xx immr head file Signed-off-by: Dave Liu --- include/asm-ppc/immap_83xx.h | 1892 +++++------------------------------------- include/mpc83xx.h | 1263 ++++++++++++++++++++-------- 2 files changed, 1108 insertions(+), 2047 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 43cde5e28e..67b035c614 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -3,20 +3,11 @@ * * MPC83xx Internal Memory Map * - * History : - * 20060601: Daveliu (daveliu@freescale.com) - * TanyaJiang (tanya.jiang@freescale.com) - * Unified variable names for mpc83xx - * 2005 : Mandy Lavi (mandy.lavi@freescale.com) - * support for mpc8360e - * 2004 : Eran Liberty (liberty@freescale.com) - * Initialized for mpc8349 - * based on: - * MPC8260 Internal Memory Map - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * MPC85xx Internal Memory Map - * Copyright(c) 2002,2003 Motorola Inc. - * Xianghua Xiao (x.xiao@motorola.com) + * Contributors: + * Dave Liu + * Tanya Jiang + * Mandy Lavi + * Eran Liberty * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -25,7 +16,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -37,36 +28,24 @@ #ifndef __IMMAP_83xx__ #define __IMMAP_83xx__ -#include #include #include /* - * Local Access Window. + * Local Access Window */ typedef struct law83xx { u32 bar; /* LBIU local access window base address register */ -/* Identifies the 20 most-significant address bits of the base of local - * access window n. The specified base address should be aligned to the - * window size, as defined by LBLAWARn[SIZE]. - */ -#define LAWBAR_BAR 0xFFFFF000 -#define LAWBAR_RES ~(LAWBAR_BAR) u32 ar; /* LBIU local access window attribute register */ } law83xx_t; /* - * System configuration registers. + * System configuration registers */ typedef struct sysconf83xx { u32 immrbar; /* Internal memory map base address register */ u8 res0[0x04]; u32 altcbar; /* Alternate configuration base address register */ -/* Identifies the12 most significant address bits of an alternate base - * address used for boot sequencer configuration accesses. - */ -#define ALTCBAR_BASE_ADDR 0xFFF00000 -#define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */ u8 res1[0x14]; law83xx_t lblaw[4]; /* LBIU local access window */ u8 res2[0x20]; @@ -77,115 +56,10 @@ typedef struct sysconf83xx { u32 sgprl; /* System General Purpose Register Low */ u32 sgprh; /* System General Purpose Register High */ u32 spridr; /* System Part and Revision ID Register */ -#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */ -#define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */ u8 res5[0x04]; u32 spcr; /* System Priority Configuration Register */ -#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */ -#define SPCR_PCIHPE_SHIFT (31-3) -#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */ -#define SPCR_PCIPR_SHIFT (31-7) -#define SPCR_OPT 0x00800000 /* Optimize */ -#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */ -#define SPCR_TBEN_SHIFT (31-9) -#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */ -#define SPCR_COREPR_SHIFT (31-11) -#if defined (CONFIG_MPC8349) -#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */ -#define SPCR_TSEC1DP_SHIFT (31-19) -#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */ -#define SPCR_TSEC1BDP_SHIFT (31-21) -#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority. */ -#define SPCR_TSEC1EP_SHIFT (31-23) -#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */ -#define SPCR_TSEC2DP_SHIFT (31-27) -#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */ -#define SPCR_TSEC2BDP_SHIFT (31-29) -#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */ -#define SPCR_TSEC2EP_SHIFT (31-31) -#define SPCR_RES ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \ - | SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \ - | SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP) -#elif defined (CONFIG_MPC8360) -#define SPCR_RES ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_OPT|SPCR_TBEN|SPCR_COREPR) -#endif - u32 sicrl; /* System General Purpose Register Low */ -#if defined (CONFIG_MPC8349) -#define SICRL_LDP_A 0x80000000 -#define SICRL_USB1 0x40000000 -#define SICRL_USB0 0x20000000 -#define SICRL_UART 0x0C000000 -#define SICRL_GPIO1_A 0x02000000 -#define SICRL_GPIO1_B 0x01000000 -#define SICRL_GPIO1_C 0x00800000 -#define SICRL_GPIO1_D 0x00400000 -#define SICRL_GPIO1_E 0x00200000 -#define SICRL_GPIO1_F 0x00180000 -#define SICRL_GPIO1_G 0x00040000 -#define SICRL_GPIO1_H 0x00020000 -#define SICRL_GPIO1_I 0x00010000 -#define SICRL_GPIO1_J 0x00008000 -#define SICRL_GPIO1_K 0x00004000 -#define SICRL_GPIO1_L 0x00003000 -#define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \ - | SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \ - | SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \ - | SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \ - | SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L ) -#elif defined (CONFIG_MPC8360) -#define SICRL_LDP_A 0xC0000000 -#define SICRL_LCLK_1 0x10000000 -#define SICRL_LCLK_2 0x08000000 -#define SICRL_SRCID_A 0x03000000 -#define SICRL_IRQ_CKSTP_A 0x00C00000 -#define SICRL_RES ~(SICRL_LDP_A | SICRL_LCLK_1 | SICRL_LCLK_2 | \ - SICRL_SRCID_A | SICRL_IRQ_CKSTP_A) -#endif - u32 sicrh; /* System General Purpose Register High */ -#define SICRH_DDR 0x80000000 -#if defined (CONFIG_MPC8349) -#define SICRH_TSEC1_A 0x10000000 -#define SICRH_TSEC1_B 0x08000000 -#define SICRH_TSEC1_C 0x04000000 -#define SICRH_TSEC1_D 0x02000000 -#define SICRH_TSEC1_E 0x01000000 -#define SICRH_TSEC1_F 0x00800000 -#define SICRH_TSEC2_A 0x00400000 -#define SICRH_TSEC2_B 0x00200000 -#define SICRH_TSEC2_C 0x00100000 -#define SICRH_TSEC2_D 0x00080000 -#define SICRH_TSEC2_E 0x00040000 -#define SICRH_TSEC2_F 0x00020000 -#define SICRH_TSEC2_G 0x00010000 -#define SICRH_TSEC2_H 0x00008000 -#define SICRH_GPIO2_A 0x00004000 -#define SICRH_GPIO2_B 0x00002000 -#define SICRH_GPIO2_C 0x00001000 -#define SICRH_GPIO2_D 0x00000800 -#define SICRH_GPIO2_E 0x00000400 -#define SICRH_GPIO2_F 0x00000200 -#define SICRH_GPIO2_G 0x00000180 -#define SICRH_GPIO2_H 0x00000060 -#define SICRH_TSOBI1 0x00000002 -#define SICRH_TSOBI2 0x00000001 -#define SICRH_RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \ - | SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \ - | SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \ - | SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \ - | SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \ - | SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \ - | SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \ - | SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \ - | SICRH_TSOBI2) -#elif defined (CONFIG_MPC8360) -#define SICRH_SECONDARY_DDR 0x40000000 -#define SICRH_SDDROE 0x02000000 /* SDDRIOE bit from reset configuration word high. */ -#define SICRH_UC1EOBI 0x00000004 /* UCC1 Ethernet Output Buffer Impedance. */ -#define SICRH_UC2E1OBI 0x00000002 /* UCC2 Ethernet pin option 1 Output Buffer Impedance. */ -#define SICRH_UC2E2OBI 0x00000001 /* UCC2 Ethernet pin option 2 Output Buffer Impedance. */ -#define SICRH_RES ~(SICRH_DDR | SICRH_SECONDARY_DDR | SICRH_SDDROE | \ - SICRH_UC2E1OBI | SICRH_UC2E2OBI | SICRH_UC2E2OBI) -#endif + u32 sicrl; /* System I/O Configuration Register Low */ + u32 sicrh; /* System I/O Configuration Register High */ u8 res6[0xE4]; } sysconf83xx_t; @@ -196,11 +70,8 @@ typedef struct wdt83xx { u8 res0[4]; u32 swcrr; /* System watchdog control register */ u32 swcnr; /* System watchdog count register */ -#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. -#define SWCNR_RES ~(SWCNR_SWCN) u8 res1[2]; u16 swsrr; /* System watchdog service register */ -#define SWSRR_WS 0x0000FFFF /* Software Watchdog Service Field. */ u8 res2[0xF0]; } wdt83xx_t; @@ -209,91 +80,46 @@ typedef struct wdt83xx { */ typedef struct rtclk83xx { u32 cnr; /* control register */ -#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */ -#define CNR_CLIN 0x00000040 /* Input Clock Control Bit */ -#define CNR_AIM 0x00000002 /* Alarm Interrupt Mask Bit */ -#define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */ -#define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM) u32 ldr; /* load register */ -#define LDR_CLDV 0xFFFFFFFF /* Contains the 32-bit value to be - * loaded in a 32-bit RTC counter.*/ u32 psr; /* prescale register */ -#define PSR_PRSC 0xFFFFFFFF /* RTC Prescaler bits. */ - u32 ctr; /* Counter value field register */ -#define CRT_CNTV 0xFFFFFFFF /* RTC Counter value field. */ + u32 ctr; /* counter value field register */ u32 evr; /* event register */ -#define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */ -#define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */ -#define RTEVR_RES ~(RTEVR_SIF | RTEVR_AIF) -#define PTEVR_PIF 0x00000001 /* Periodic interrupt flag bit. */ -#define PTEVR_RES ~(PTEVR_PIF) u32 alr; /* alarm register */ u8 res0[0xE8]; } rtclk83xx_t; /* - * Global timper module + * Global timer module */ - typedef struct gtm83xx { - u8 cfr1; /* Timer1/2 Configuration */ -#define CFR1_PCAS 0x80 /* Pair Cascade mode */ -#define CFR1_BCM 0x40 /* Backward compatible mode */ -#define CFR1_STP2 0x20 /* Stop timer */ -#define CFR1_RST2 0x10 /* Reset timer */ -#define CFR1_GM2 0x08 /* Gate mode for pin 2 */ -#define CFR1_GM1 0x04 /* Gate mode for pin 1 */ -#define CFR1_STP1 0x02 /* Stop timer */ -#define CFR1_RST1 0x01 /* Reset timer */ -#define CFR1_RES ~(CFR1_PCAS | CFR1_STP2 | CFR1_RST2 | CFR1_GM2 |\ - CFR1_GM1 | CFR1_STP1 | CFR1_RST1) + u8 cfr1; /* Timer1/2 Configuration */ u8 res0[3]; - u8 cfr2; /* Timer3/4 Configuration */ -#define CFR2_PCAS 0x80 /* Pair Cascade mode */ -#define CFR2_SCAS 0x40 /* Super Cascade mode */ -#define CFR2_STP4 0x20 /* Stop timer */ -#define CFR2_RST4 0x10 /* Reset timer */ -#define CFR2_GM4 0x08 /* Gate mode for pin 4 */ -#define CFR2_GM3 0x04 /* Gate mode for pin 3 */ -#define CFR2_STP3 0x02 /* Stop timer */ -#define CFR2_RST3 0x01 /* Reset timer */ + u8 cfr2; /* Timer3/4 Configuration */ u8 res1[10]; - u16 mdr1; /* Timer1 Mode Register */ -#define MDR_SPS 0xff00 /* Secondary Prescaler value */ -#define MDR_CE 0x00c0 /* Capture edge and enable interrupt */ -#define MDR_OM 0x0020 /* Output mode */ -#define MDR_ORI 0x0010 /* Output reference interrupt enable */ -#define MDR_FRR 0x0008 /* Free run/restart */ -#define MDR_ICLK 0x0006 /* Input clock source for the timer */ -#define MDR_GE 0x0001 /* Gate enable */ - u16 mdr2; /* Timer2 Mode Register */ - u16 rfr1; /* Timer1 Reference Register */ - u16 rfr2; /* Timer2 Reference Register */ - u16 cpr1; /* Timer1 Capture Register */ - u16 cpr2; /* Timer2 Capture Register */ - u16 cnr1; /* Timer1 Counter Register */ - u16 cnr2; /* Timer2 Counter Register */ - u16 mdr3; /* Timer3 Mode Register */ - u16 mdr4; /* Timer4 Mode Register */ - u16 rfr3; /* Timer3 Reference Register */ - u16 rfr4; /* Timer4 Reference Register */ - u16 cpr3; /* Timer3 Capture Register */ - u16 cpr4; /* Timer4 Capture Register */ - u16 cnr3; /* Timer3 Counter Register */ - u16 cnr4; /* Timer4 Counter Register */ - u16 evr1; /* Timer1 Event Register */ - u16 evr2; /* Timer2 Event Register */ - u16 evr3; /* Timer3 Event Register */ - u16 evr4; /* Timer4 Event Register */ -#define GTEVR_REF 0x0002 /* Output reference event */ -#define GTEVR_CAP 0x0001 /* Counter Capture event */ -#define GTEVR_RES ~(EVR_CAP|EVR_REF) - u16 psr1; /* Timer1 Prescaler Register */ - u16 psr2; /* Timer2 Prescaler Register */ - u16 psr3; /* Timer3 Prescaler Register */ - u16 psr4; /* Timer4 Prescaler Register */ -#define GTPSR_PPS 0x00FF /* Primary Prescaler Bits. */ -#define GTPSR_RES ~(GTPSR_PPS) + u16 mdr1; /* Timer1 Mode Register */ + u16 mdr2; /* Timer2 Mode Register */ + u16 rfr1; /* Timer1 Reference Register */ + u16 rfr2; /* Timer2 Reference Register */ + u16 cpr1; /* Timer1 Capture Register */ + u16 cpr2; /* Timer2 Capture Register */ + u16 cnr1; /* Timer1 Counter Register */ + u16 cnr2; /* Timer2 Counter Register */ + u16 mdr3; /* Timer3 Mode Register */ + u16 mdr4; /* Timer4 Mode Register */ + u16 rfr3; /* Timer3 Reference Register */ + u16 rfr4; /* Timer4 Reference Register */ + u16 cpr3; /* Timer3 Capture Register */ + u16 cpr4; /* Timer4 Capture Register */ + u16 cnr3; /* Timer3 Counter Register */ + u16 cnr4; /* Timer4 Counter Register */ + u16 evr1; /* Timer1 Event Register */ + u16 evr2; /* Timer2 Event Register */ + u16 evr3; /* Timer3 Event Register */ + u16 evr4; /* Timer4 Event Register */ + u16 psr1; /* Timer1 Prescaler Register */ + u16 psr2; /* Timer2 Prescaler Register */ + u16 psr3; /* Timer3 Prescaler Register */ + u16 psr4; /* Timer4 Prescaler Register */ u8 res[0xC0]; } gtm83xx_t; @@ -301,188 +127,31 @@ typedef struct gtm83xx { * Integrated Programmable Interrupt Controller */ typedef struct ipic83xx { - u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */ -#define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */ -#define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */ -#define SICFR_MPSA 0x00200000 /* Mixed interrupts Priority Scheme for group A */ -#define SICFR_IPSD 0x00080000 /* Internal interrupts Priority Scheme for group D */ -#define SICFR_IPSA 0x00010000 /* Internal interrupts Priority Scheme for group A */ -#define SICFR_HPIT 0x00000300 /* HPI priority position IPIC output interrupt Type */ -#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT) - u32 sivcr; /* System Global Interrupt Vector Register (SIVCR) */ -#define SICVR_IVECX 0xfc000000 /* Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation) */ -#define SICVR_IVEC 0x0000007f /* Interrupt vector */ -#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC) - u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */ -#if defined (CONFIG_MPC8349) -#define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */ -#define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */ -#define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */ -#define SIIH_TSEC2TX 0x10000000 /* TSEC2 Tx interrupt */ -#define SIIH_TSEC2RX 0x08000000 /* TSEC2 Rx interrupt */ -#define SIIH_TSEC2ER 0x04000000 /* TSEC2 Eror interrupt */ -#define SIIH_USB2DR 0x02000000 /* USB2 DR interrupt */ -#define SIIH_USB2MPH 0x01000000 /* USB2 MPH interrupt */ -#endif -#if defined (CONFIG_MPC8360) -#define SIIH_H_QE_H 0x80000000 /* QE high interrupt */ -#define SIIH_H_QE_L 0x40000000 /* QE low interrupt */ -#endif -#define SIIH_UART1 0x00000080 /* UART1 interrupt */ -#define SIIH_UART2 0x00000040 /* UART2 interrupt */ -#define SIIH_SEC 0x00000020 /* SEC interrupt */ -#define SIIH_I2C1 0x00000004 /* I2C1 interrupt */ -#define SIIH_I2C2 0x00000002 /* I2C2 interrupt */ -#if defined (CONFIG_MPC8349) -#define SIIH_SPI 0x00000001 /* SPI interrupt */ -#define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \ - | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \ - | SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \ - | SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \ - | SIIH_I2C2 | SIIH_SPI) -#endif -#if defined (CONFIG_MPC8360) -#define SIIH_RES ~(SIIH_H_QE_H | SIIH_H_QE_L | SIIH_H_UART1 | \ - SIIH_H_UART2| SIIH_H_SEC | SIIH_H_I2C1 |SIIH_H_I2C2) -#endif - u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */ -#define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */ -#define SIIL_PIT 0x40000000 /* PIT interrupt */ -#define SIIL_PCI1 0x20000000 /* PCI1 interrupt */ -#if defined (CONFIG_MPC8349) -#define SIIL_PCI2 0x10000000 /* PCI2 interrupt */ -#endif -#define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */ -#define SIIL_MU 0x04000000 /* Message Unit interrupt */ -#define SIIL_SBA 0x02000000 /* System Bus Arbiter interrupt */ -#define SIIL_DMA 0x01000000 /* DMA interrupt */ -#define SIIL_GTM4 0x00800000 /* GTM4 interrupt */ -#define SIIL_GTM8 0x00400000 /* GTM8 interrupt */ -#if defined (CONFIG_MPC8349) -#define SIIL_GPIO1 0x00200000 /* GPIO1 interrupt */ -#define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */ -#endif -#if defined (CONFIG_MPC8360) -#define SIIL_QEP 0x00200000 /* QE ports interrupt */ -#define SIIL_SDDR 0x00100000 /* SDDR interrupt */ -#endif -#define SIIL_DDR 0x00080000 /* DDR interrupt */ -#define SIIL_LBC 0x00040000 /* LBC interrupt */ -#define SIIL_GTM2 0x00020000 /* GTM2 interrupt */ -#define SIIL_GTM6 0x00010000 /* GTM6 interrupt */ -#define SIIL_PMC 0x00008000 /* PMC interrupt */ -#define SIIL_GTM3 0x00000800 /* GTM3 interrupt */ -#define SIIL_GTM7 0x00000400 /* GTM7 interrupt */ -#define SIIL_GTM1 0x00000020 /* GTM1 interrupt */ -#define SIIL_GTM5 0x00000010 /* GTM5 interrupt */ -#define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */ -#if defined (CONFIG_MPC8349) -#define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \ - | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \ - | SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \ - | SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \ - | SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \ - | SIIL_GTM5 |SIIL_DPTC ) -#endif -#if defined (CONFIG_MPC8360) -#define SIIL_RES ~(SIIL_RTCS |SIIL_PIT |SIIL_PCI1 |SIIL_RTCALR \ - |SIIL_MU |SIIL_SBA |SIIL_DMA |SIIL_GTM4 |SIIL_GTM8 \ - |SIIL_QEP | SIIL_SDDR| SIIL_DDR |SIIL_LBC |SIIL_GTM2 \ - |SIIL_GTM6 |SIIL_PMC |SIIL_GTM3 |SIIL_GTM7 |SIIL_GTM1 \ - |SIIL_GTM5 ) -#endif - u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */ + u32 sicfr; /* System Global Interrupt Configuration Register */ + u32 sivcr; /* System Global Interrupt Vector Register */ + u32 sipnr_h; /* System Internal Interrupt Pending Register - High */ + u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */ + u32 siprr_a; /* System Internal Interrupt Group A Priority Register */ u8 res0[8]; - u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */ - u32 simsr_h; /* System Internal Interrupt Mask Register - High (SIIH) */ - u32 simsr_l; /* System Internal Interrupt Mask Register - Low (SIIL) */ + u32 siprr_d; /* System Internal Interrupt Group D Priority Register */ + u32 simsr_h; /* System Internal Interrupt Mask Register - High */ + u32 simsr_l; /* System Internal Interrupt Mask Register - Low */ u8 res1[4]; - u32 sepnr; /* System External Interrupt Pending Register (SEI) */ - u32 smprr_a; /* System Mixed Interrupt Group A Priority Register (PRR) */ - u32 smprr_b; /* System Mixed Interrupt Group B Priority Register (PRR) */ -#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */ -#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */ -#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */ -#define PRR_3 0x00700000 /* Priority Register, Position 3 programming */ -#define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */ -#define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */ -#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */ -#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */ -#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7) - u32 semsr; /* System External Interrupt Mask Register (SEI) */ -#define SEI_IRQ0 0x80000000 /* IRQ0 external interrupt */ -#define SEI_IRQ1 0x40000000 /* IRQ1 external interrupt */ -#define SEI_IRQ2 0x20000000 /* IRQ2 external interrupt */ -#define SEI_IRQ3 0x10000000 /* IRQ3 external interrupt */ -#define SEI_IRQ4 0x08000000 /* IRQ4 external interrupt */ -#define SEI_IRQ5 0x04000000 /* IRQ5 external interrupt */ -#define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */ -#define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */ -#define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */ -#define SEI_RES ~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \ - | SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \ - | SEI_SIRQ0) - u32 secnr; /* System External Interrupt Control Register (SECNR) */ -#define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */ -#define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */ -#define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */ -#define SECNR_SYSA1T 0x00300000 /* MIXA1 priority position IPIC output interrupt type */ -#define SECNR_EDI0 0x00008000 /* IRQ0 external interrupt edge/level detect */ -#define SECNR_EDI1 0x00004000 /* IRQ1 external interrupt edge/level detect */ -#define SECNR_EDI2 0x00002000 /* IRQ2 external interrupt edge/level detect */ -#define SECNR_EDI3 0x00001000 /* IRQ3 external interrupt edge/level detect */ -#define SECNR_EDI4 0x00000800 /* IRQ4 external interrupt edge/level detect */ -#define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */ -#define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */ -#define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */ -#define SECNR_RES ~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \ - | SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \ - | SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \ - | SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7) - u32 sersr; /* System Error Status Register (SERR) */ - u32 sermr; /* System Error Mask Register (SERR) */ -#define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */ -#define SERR_WDT 0x40000000 /* WDT MCP request */ -#define SERR_SBA 0x20000000 /* SBA MCP request */ -#if defined (CONFIG_MPC8349) -#define SERR_DDR 0x10000000 /* DDR MCP request */ -#define SERR_LBC 0x08000000 /* LBC MCP request */ -#define SERR_PCI1 0x04000000 /* PCI1 MCP request */ -#define SERR_PCI2 0x02000000 /* PCI2 MCP request */ -#endif -#if defined (CONFIG_MPC8360) -#define SERR_CIEE 0x10000000 /* CIEE MCP request */ -#define SERR_CMEE 0x08000000 /* CMEEMCP request */ -#define SERR_PCI 0x04000000 /* PCI MCP request */ -#endif -#define SERR_MU 0x01000000 /* MU MCP request */ -#define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */ -#if defined (CONFIG_MPC8349) -#define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \ - |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \ - |SERR_RNC ) -#elif defined (CONFIG_MPC8360) -#define SERR_RES ~( SERR_IRQ0|SERR_WDT |SERR_SBA |SERR_CIEE\ - |SERR_CMEE|SERR_PCI|SERR_MU) -#endif - u32 sercr; /* System Error Control Register (SERCR) */ -#define SERCR_MCPR 0x00000001 /* MCP Route */ -#define SERCR_RES ~(SERCR_MCPR) + u32 sepnr; /* System External Interrupt Pending Register */ + u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */ + u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */ + u32 semsr; /* System External Interrupt Mask Register */ + u32 secnr; /* System External Interrupt Control Register */ + u32 sersr; /* System Error Status Register */ + u32 sermr; /* System Error Mask Register */ + u32 sercr; /* System Error Control Register */ u8 res2[4]; - u32 sifcr_h; /* System Internal Interrupt Force Register - High (SIIH) */ - u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */ - u32 sefcr; /* System External Interrupt Force Register (SEI) */ - u32 serfr; /* System Error Force Register (SERR) */ + u32 sifcr_h; /* System Internal Interrupt Force Register - High */ + u32 sifcr_l; /* System Internal Interrupt Force Register - Low */ + u32 sefcr; /* System External Interrupt Force Register */ + u32 serfr; /* System Error Force Register */ u32 scvcr; /* System Critical Interrupt Vector Register */ -#define SCVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible - critical interrupt vector. */ -#define SCVCR_CVEC 0x0000007F /* Critical interrupt vector */ -#define SCVCR_RES ~(SCVCR_CVECX|SCVCR_CVEC) u32 smvcr; /* System Management Interrupt Vector Register */ -#define SMVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible - critical interrupt vector. */ -#define SMVCR_CVEC 0x0000007F /* Critical interrupt vector */ -#define SMVCR_RES ~(SMVCR_CVECX|SMVCR_CVEC) u8 res3[0x98]; } ipic83xx_t; @@ -491,43 +160,14 @@ typedef struct ipic83xx { */ typedef struct arbiter83xx { u32 acr; /* Arbiter Configuration Register */ -#define ACR_COREDIS 0x10000000 /* Core disable. */ -#define ACR_COREDIS_SHIFT (31-7) -#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */ -#define ACR_PIPE_DEP_SHIFT (31-15) -#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */ -#define ACR_PCI_RPTCNT_SHIFT (31-19) -#define ACR_RPTCNT 0x00000700 /* Repeat count. */ -#define ACR_RPTCNT_SHIFT (31-23) -#define ACR_APARK 0x00000030 /* Address parking. */ -#define ACR_APARK_SHIFT (31-27) -#define ACR_PARKM 0x0000000F /* Parking master. */ -#define ACR_PARKM_SHIFT (31-31) -#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM) u32 atr; /* Arbiter Timers Register */ -#define ATR_DTO 0x00FF0000 /* Data time out. */ -#define ATR_ATO 0x000000FF /* Address time out. */ -#define ATR_RES ~(ATR_DTO|ATR_ATO) u8 res[4]; - u32 aer; /* Arbiter Event Register (AE) */ - u32 aidr; /* Arbiter Interrupt Definition Register (AE) */ - u32 amr; /* Arbiter Mask Register (AE) */ + u32 aer; /* Arbiter Event Register */ + u32 aidr; /* Arbiter Interrupt Definition Register */ + u32 amr; /* Arbiter Mask Register */ u32 aeatr; /* Arbiter Event Attributes Register */ -#define AEATR_EVENT 0x07000000 /* Event type. */ -#define AEATR_MSTR_ID 0x001F0000 /* Master Id. */ -#define AEATR_TBST 0x00000800 /* Transfer burst. */ -#define AEATR_TSIZE 0x00000700 /* Transfer Size. */ -#define AEATR_TTYPE 0x0000001F /* Transfer Type. */ -#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE) u32 aeadr; /* Arbiter Event Address Register */ - u32 aerr; /* Arbiter Event Response Register (AE) */ -#define AE_ETEA 0x00000020 /* Transfer error. */ -#define AE_RES_ 0x00000010 /* Reserved transfer type. */ -#define AE_ECW 0x00000008 /* External control word transfer type. */ -#define AE_AO 0x00000004 /* Address Only transfer type. */ -#define AE_DTO 0x00000002 /* Data time out. */ -#define AE_ATO 0x00000001 /* Address time out. */ -#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO) + u32 aerr; /* Arbiter Event Response Register */ u8 res1[0xDC]; } arbiter83xx_t; @@ -535,184 +175,24 @@ typedef struct arbiter83xx { * Reset Module */ typedef struct reset83xx { - u32 rcwl; /* RCWL Register */ -#define RCWL_LBIUCM 0x80000000 /* LBIUCM */ -#define RCWL_LBIUCM_SHIFT 31 -#define RCWL_DDRCM 0x40000000 /* DDRCM */ -#define RCWL_DDRCM_SHIFT 30 -#if defined (CONFIG_MPC8349) -#define RCWL_SVCOD 0x30000000 /* SVCOD */ -#endif -#define RCWL_SPMF 0x0f000000 /* SPMF */ -#define RCWL_SPMF_SHIFT 24 -#define RCWL_COREPLL 0x007F0000 /* COREPLL */ -#define RCWL_COREPLL_SHIFT 16 -#define RCWL_CEVCOD 0x000000C0 /* CEVCOD */ -#define RCWL_CEPDF 0x00000020 /* CEPDF */ -#define RCWL_CEPDF_SHIFT 5 -#define RCWL_CEPMF 0x0000001F /* CEPMF */ -#define RCWL_CEPMF_SHIFT 0 -#if defined (CONFIG_MPC8349) -#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF) -#elif defined (CONFIG_MPC8360) -#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SPMF|RCWL_COREPLL|RCWL_CEPDF|RCWL_CEPMF) -#endif - u32 rcwh; /* RCHL Register */ -#define RCWH_PCIHOST 0x80000000 /* PCIHOST */ -#define RCWH_PCIHOST_SHIFT 31 -#if defined (CONFIG_MPC8349) -#define RCWH_PCI64 0x40000000 /* PCI64 */ -#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */ -#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */ -#elif defined (CONFIG_MPC8360) -#define RCWH_PCIARB 0x20000000 /* PCI internal arbiter mode. */ -#define RCWH_PCICKDRV 0x10000000 /* PCI clock output drive. */ -#endif -#define RCWH_COREDIS 0x08000000 /* COREDIS */ -#define RCWH_BMS 0x04000000 /* BMS */ -#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */ -#define RCWH_SWEN 0x00800000 /* SWEN */ -#define RCWH_ROMLOC 0x00700000 /* ROMLOC */ -#if defined (CONFIG_MPC8349) -#define RCWH_TSEC1M 0x0000c000 /* TSEC1M */ -#define RCWH_TSEC2M 0x00003000 /* TSEC2M */ -#define RCWH_TPR 0x00000100 /* TPR */ -#elif defined (CONFIG_MPC8360) -#define RCWH_SDDRIOE 0x00000010 /* Secondary DDR IO Enable. */ -#endif -#define RCWH_TLE 0x00000008 /* TLE */ -#define RCWH_LALE 0x00000004 /* LALE */ -#if defined (CONFIG_MPC8349) -#define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \ - | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \ - | RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \ - | RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \ - | RCWH_TLE | RCWH_LALE) -#elif defined (CONFIG_MPC8360) -#define RCWH_RES ~(RCWH_PCIHOST|RCWH_PCIARB|RCWH_PCICKDRV \ - |RCWH_COREDIS|RCWH_BMS|RCWH_BOOTSEQ|RCWH_SWEN \ - |RCWH_SDDRIOE |RCWH_TLE) -#endif + u32 rcwl; /* Reset Configuration Word Low Register */ + u32 rcwh; /* Reset Configuration Word High Register */ u8 res0[8]; - u32 rsr; /* Reset status Register */ -#define RSR_RSTSRC 0xE0000000 /* Reset source */ -#define RSR_RSTSRC_SHIFT 29 -#define RSR_BSF 0x00010000 /* Boot seq. fail */ -#define RSR_BSF_SHIFT 16 -#define RSR_SWSR 0x00002000 /* software soft reset */ -#define RSR_SWSR_SHIFT 13 -#define RSR_SWHR 0x00001000 /* software hard reset */ -#define RSR_SWHR_SHIFT 12 -#define RSR_JHRS 0x00000200 /* jtag hreset */ -#define RSR_JHRS_SHIFT 9 -#define RSR_JSRS 0x00000100 /* jtag sreset status */ -#define RSR_JSRS_SHIFT 8 -#define RSR_CSHR 0x00000010 /* checkstop reset status */ -#define RSR_CSHR_SHIFT 4 -#define RSR_SWRS 0x00000008 /* software watchdog reset status */ -#define RSR_SWRS_SHIFT 3 -#define RSR_BMRS 0x00000004 /* bus monitop reset status */ -#define RSR_BMRS_SHIFT 2 -#define RSR_SRS 0x00000002 /* soft reset status */ -#define RSR_SRS_SHIFT 1 -#define RSR_HRS 0x00000001 /* hard reset status */ -#define RSR_HRS_SHIFT 0 -#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS) - u32 rmr; /* Reset mode Register */ -#define RMR_CSRE 0x00000001 /* checkstop reset enable */ -#define RMR_CSRE_SHIFT 0 -#define RMR_RES ~(RMR_CSRE) - u32 rpr; /* Reset protection Register */ - u32 rcr; /* Reset Control Register */ -#define RCR_SWHR 0x00000002 /* software hard reset */ -#define RCR_SWSR 0x00000001 /* software soft reset */ -#define RCR_RES ~(RCR_SWHR | RCR_SWSR) - u32 rcer; /* Reset Control Enable Register */ -#define RCER_CRE 0x00000001 /* software hard reset */ -#define RCER_RES ~(RCER_CRE) + u32 rsr; /* Reset Status Register */ + u32 rmr; /* Reset Mode Register */ + u32 rpr; /* Reset protection Register */ + u32 rcr; /* Reset Control Register */ + u32 rcer; /* Reset Control Enable Register */ u8 res1[0xDC]; } reset83xx_t; +/* + * Clock Module + */ typedef struct clk83xx { - u32 spmr; /* system PLL mode Register */ -#define SPMR_LBIUCM 0x80000000 /* LBIUCM */ -#define SPMR_DDRCM 0x40000000 /* DDRCM */ -#if defined (CONFIG_MPC8349) -#define SPMR_SVCOD 0x30000000 /* SVCOD */ -#endif -#define SPMR_SPMF 0x0F000000 /* SPMF */ -#define SPMR_CKID 0x00800000 /* CKID */ -#define SPMR_CKID_SHIFT 23 -#define SPMR_COREPLL 0x007F0000 /* COREPLL */ -#define SPMR_CEVCOD 0x000000C0 /* CEVCOD */ -#define SPMR_CEPDF 0x00000020 /* CEPDF */ -#define SPMR_CEPMF 0x0000001F /* CEPMF */ -#if defined (CONFIG_MPC8349) -#define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \ - | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \ - | SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF) -#elif defined (CONFIG_MPC8360) -#define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SPMF \ - | SPMR_CKID | SPMR_COREPLL | SPMR_CEVCOD \ - | SPMR_CEPDF | SPMR_CEPMF) -#endif - u32 occr; /* output clock control Register */ -#define OCCR_PCICOE0 0x80000000 /* PCICOE0 */ -#define OCCR_PCICOE1 0x40000000 /* PCICOE1 */ -#define OCCR_PCICOE2 0x20000000 /* PCICOE2 */ -#if defined (CONFIG_MPC8349) -#define OCCR_PCICOE3 0x10000000 /* PCICOE3 */ -#define OCCR_PCICOE4 0x08000000 /* PCICOE4 */ -#define OCCR_PCICOE5 0x04000000 /* PCICOE5 */ -#define OCCR_PCICOE6 0x02000000 /* PCICOE6 */ -#define OCCR_PCICOE7 0x01000000 /* PCICOE7 */ -#endif -#define OCCR_PCICD0 0x00800000 /* PCICD0 */ -#define OCCR_PCICD1 0x00400000 /* PCICD1 */ -#define OCCR_PCICD2 0x00200000 /* PCICD2 */ -#if defined (CONFIG_MPC8349) -#define OCCR_PCICD3 0x00100000 /* PCICD3 */ -#define OCCR_PCICD4 0x00080000 /* PCICD4 */ -#define OCCR_PCICD5 0x00040000 /* PCICD5 */ -#define OCCR_PCICD6 0x00020000 /* PCICD6 */ -#define OCCR_PCICD7 0x00010000 /* PCICD7 */ -#define OCCR_PCI1CR 0x00000002 /* PCI1CR */ -#define OCCR_PCI2CR 0x00000001 /* PCI2CR */ -#define OCCR_RES ~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \ - | OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \ - | OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \ - | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICD3 \ - | OCCR_PCICD4 | OCCR_PCICD5 | OCCR_PCICD6 \ - | OCCR_PCICD7 | OCCR_PCI1CR | OCCR_PCI2CR ) -#endif -#if defined (CONFIG_MPC8360) -#define OCCR_PCICR 0x00000002 /* PCI clock rate */ -#define OCCR_RES ~(OCCR_PCICOE0|OCCR_PCICOE1|OCCR_PCICOE2 \ - |OCCR_PCICD0|OCCR_PCICD1|OCCR_PCICD2|OCCR_PCICR ) -#endif - u32 sccr; /* system clock control Register */ -#if defined (CONFIG_MPC8349) -#define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */ -#define SCCR_TSEC1CM_SHIFT 30 -#define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */ -#define SCCR_TSEC2CM_SHIFT 28 -#endif -#define SCCR_ENCCM 0x03000000 /* ENCCM */ -#define SCCR_ENCCM_SHIFT 24 -#if defined (CONFIG_MPC8349) -#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM */ -#define SCCR_USBMPHCM_SHIFT 22 -#define SCCR_USBDRCM 0x00300000 /* USBDRCM */ -#define SCCR_USBDRCM_SHIFT 20 -#endif -#define SCCR_PCICM 0x00010000 /* PCICM */ -#if defined (CONFIG_MPC8349) -#define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \ - | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM) -#endif -#if defined (CONFIG_MPC8360) -#define SCCR_RES ~(SCCR_ENCCM | SCCR_PCICM) -#endif + u32 spmr; /* system PLL mode Register */ + u32 occr; /* output clock control Register */ + u32 sccr; /* system clock control Register */ u8 res0[0xF4]; } clk83xx_t; @@ -720,27 +200,14 @@ typedef struct clk83xx { * Power Management Control Module */ typedef struct pmc83xx { - u32 pmccr; /* PMC Configuration Register */ -#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */ -#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */ -#if defined (CONFIG_MPC8360) -#define PMCCR_SDLPEN 0x00000004 /* Secondary DDR SDRAM Low Power Enable */ -#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN | PMCCR_SDLPEN) -#elif defined (CONFIG_MPC8349) -#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN) -#endif - u32 pmcer; /* PMC Event Register */ -#define PMCER_PMCI 0x00000001 /* PMC Interrupt */ -#define PMCER_RES ~(PMCER_PMCI) - u32 pmcmr; /* PMC Mask Register */ -#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */ -#define PMCMR_RES ~(PMCMR_PMCIE) + u32 pmccr; /* PMC Configuration Register */ + u32 pmcer; /* PMC Event Register */ + u32 pmcmr; /* PMC Mask Register */ u8 res0[0xF4]; } pmc83xx_t; -#if defined (CONFIG_MPC8349) /* - * general purpose I/O module + * General purpose I/O module */ typedef struct gpio83xx { u32 dir; /* direction register */ @@ -751,124 +218,20 @@ typedef struct gpio83xx { u32 icr; /* external interrupt control register */ u8 res0[0xE8]; } gpio83xx_t; -#endif -#if defined (CONFIG_MPC8360) /* * QE Ports Interrupts Registers */ typedef struct qepi83xx { u8 res0[0xC]; u32 qepier; /* QE Ports Interrupt Event Register */ -#define QEPIER_PA15 0x80000000 -#define QEPIER_PA16 0x40000000 -#define QEPIER_PA29 0x20000000 -#define QEPIER_PA30 0x10000000 -#define QEPIER_PB3 0x08000000 -#define QEPIER_PB5 0x04000000 -#define QEPIER_PB12 0x02000000 -#define QEPIER_PB13 0x01000000 -#define QEPIER_PB26 0x00800000 -#define QEPIER_PB27 0x00400000 -#define QEPIER_PC27 0x00200000 -#define QEPIER_PC28 0x00100000 -#define QEPIER_PC29 0x00080000 -#define QEPIER_PD12 0x00040000 -#define QEPIER_PD13 0x00020000 -#define QEPIER_PD16 0x00010000 -#define QEPIER_PD17 0x00008000 -#define QEPIER_PD26 0x00004000 -#define QEPIER_PD27 0x00002000 -#define QEPIER_PE12 0x00001000 -#define QEPIER_PE13 0x00000800 -#define QEPIER_PE24 0x00000400 -#define QEPIER_PE25 0x00000200 -#define QEPIER_PE26 0x00000100 -#define QEPIER_PE27 0x00000080 -#define QEPIER_PE31 0x00000040 -#define QEPIER_PF20 0x00000020 -#define QEPIER_PG31 0x00000010 -#define QEPIER_RES ~(QEPIER_PA15|QEPIER_PA16|QEPIER_PA29|QEPIER_PA30|QEPIER_PB3 \ - |QEPIER_PB5|QEPIER_PB12|QEPIER_PB13|QEPIER_PB26|QEPIER_PB27 \ - |QEPIER_PC27|QEPIER_PC28|QEPIER_PC29|QEPIER_PD12|QEPIER_PD13 \ - |QEPIER_PD16|QEPIER_PD17|QEPIER_PD26|QEPIER_PD27|QEPIER_PE12 \ - |QEPIER_PE13|QEPIER_PE24|QEPIER_PE25|QEPIER_PE26|QEPIER_PE27 \ - |QEPIER_PE31|QEPIER_PF20|QEPIER_PG31) u32 qepimr; /* QE Ports Interrupt Mask Register */ -#define QEPIMR_PA15 0x80000000 -#define QEPIMR_PA16 0x40000000 -#define QEPIMR_PA29 0x20000000 -#define QEPIMR_PA30 0x10000000 -#define QEPIMR_PB3 0x08000000 -#define QEPIMR_PB5 0x04000000 -#define QEPIMR_PB12 0x02000000 -#define QEPIMR_PB13 0x01000000 -#define QEPIMR_PB26 0x00800000 -#define QEPIMR_PB27 0x00400000 -#define QEPIMR_PC27 0x00200000 -#define QEPIMR_PC28 0x00100000 -#define QEPIMR_PC29 0x00080000 -#define QEPIMR_PD12 0x00040000 -#define QEPIMR_PD13 0x00020000 -#define QEPIMR_PD16 0x00010000 -#define QEPIMR_PD17 0x00008000 -#define QEPIMR_PD26 0x00004000 -#define QEPIMR_PD27 0x00002000 -#define QEPIMR_PE12 0x00001000 -#define QEPIMR_PE13 0x00000800 -#define QEPIMR_PE24 0x00000400 -#define QEPIMR_PE25 0x00000200 -#define QEPIMR_PE26 0x00000100 -#define QEPIMR_PE27 0x00000080 -#define QEPIMR_PE31 0x00000040 -#define QEPIMR_PF20 0x00000020 -#define QEPIMR_PG31 0x00000010 -#define QEPIMR_RES ~(QEPIMR_PA15|QEPIMR_PA16|QEPIMR_PA29|QEPIMR_PA30|QEPIMR_PB3 \ - |QEPIMR_PB5|QEPIMR_PB12|QEPIMR_PB13|QEPIMR_PB26|QEPIMR_PB27 \ - |QEPIMR_PC27|QEPIMR_PC28|QEPIMR_PC29|QEPIMR_PD12|QEPIMR_PD13 \ - |QEPIMR_PD16|QEPIMR_PD17|QEPIMR_PD26|QEPIMR_PD27|QEPIMR_PE12 \ - |QEPIMR_PE13|QEPIMR_PE24|QEPIMR_PE25|QEPIMR_PE26|QEPIMR_PE27 \ - |QEPIMR_PE31|QEPIMR_PF20|QEPIMR_PG31) u32 qepicr; /* QE Ports Interrupt Control Register */ -#define QEPICR_PA15 0x80000000 -#define QEPICR_PA16 0x40000000 -#define QEPICR_PA29 0x20000000 -#define QEPICR_PA30 0x10000000 -#define QEPICR_PB3 0x08000000 -#define QEPICR_PB5 0x04000000 -#define QEPICR_PB12 0x02000000 -#define QEPICR_PB13 0x01000000 -#define QEPICR_PB26 0x00800000 -#define QEPICR_PB27 0x00400000 -#define QEPICR_PC27 0x00200000 -#define QEPICR_PC28 0x00100000 -#define QEPICR_PC29 0x00080000 -#define QEPICR_PD12 0x00040000 -#define QEPICR_PD13 0x00020000 -#define QEPICR_PD16 0x00010000 -#define QEPICR_PD17 0x00008000 -#define QEPICR_PD26 0x00004000 -#define QEPICR_PD27 0x00002000 -#define QEPICR_PE12 0x00001000 -#define QEPICR_PE13 0x00000800 -#define QEPICR_PE24 0x00000400 -#define QEPICR_PE25 0x00000200 -#define QEPICR_PE26 0x00000100 -#define QEPICR_PE27 0x00000080 -#define QEPICR_PE31 0x00000040 -#define QEPICR_PF20 0x00000020 -#define QEPICR_PG31 0x00000010 -#define QEPICR_RES ~(QEPICR_PA15|QEPICR_PA16|QEPICR_PA29|QEPICR_PA30|QEPICR_PB3 \ - |QEPICR_PB5|QEPICR_PB12|QEPICR_PB13|QEPICR_PB26|QEPICR_PB27 \ - |QEPICR_PC27|QEPICR_PC28|QEPICR_PC29|QEPICR_PD12|QEPICR_PD13 \ - |QEPICR_PD16|QEPICR_PD17|QEPICR_PD26|QEPICR_PD27|QEPICR_PE12 \ - |QEPICR_PE13|QEPICR_PE24|QEPICR_PE25|QEPICR_PE26|QEPICR_PE27 \ - |QEPICR_PE31|QEPICR_PF20|QEPICR_PG31) u8 res1[0xE8]; } qepi83xx_t; /* - * general purpose I/O module + * QE Parallel I/O Ports */ typedef struct gpio_n { u32 podr; /* Open Drain Register */ @@ -879,238 +242,83 @@ typedef struct gpio_n { u32 ppar2; /* Pin Assignment Register 2 */ } gpio_n_t; -typedef struct gpio83xx { +typedef struct qegpio83xx { gpio_n_t ioport[0x7]; u8 res0[0x358]; -} gpio83xx_t; +} qepio83xx_t; /* * QE Secondary Bus Access Windows */ - typedef struct qesba83xx { u32 lbmcsar; /* Local bus memory controller start address */ -#define LBMCSAR_SA 0x000FFFFF /* 20 most-significant bits of the start address */ -#define LBMCSAR_RES ~(LBMCSAR_SA) u32 sdmcsar; /* Secondary DDR memory controller start address */ -#define SDMCSAR_SA 0x000FFFFF /* 20 most-significant bits of the start address */ -#define SDMCSAR_RES ~(SDMCSAR_SA) u8 res0[0x38]; u32 lbmcear; /* Local bus memory controller end address */ -#define LBMCEAR_EA 0x000FFFFF /* 20 most-significant bits of the end address */ -#define LBMCEAR_RES ~(LBMCEAR_EA) u32 sdmcear; /* Secondary DDR memory controller end address */ -#define SDMCEAR_EA 0x000FFFFF /* 20 most-significant bits of the end address */ -#define SDMCEAR_RES ~(SDMCEAR_EA) u8 res1[0x38]; - u32 lbmcar; /* Local bus memory controller attributes */ -#define LBMCAR_WEN 0x00000001 /* Forward transactions to the QE local bus */ -#define LBMCAR_RES ~(LBMCAR_WEN) + u32 lbmcar; /* Local bus memory controller attributes */ u32 sdmcar; /* Secondary DDR memory controller attributes */ -#define SDMCAR_WEN 0x00000001 /* Forward transactions to the second DDR bus */ -#define SDMCAR_RES ~(SDMCAR_WEN) - u8 res2[0x778]; + u8 res2[0x378]; } qesba83xx_t; -#endif /* * DDR Memory Controller Memory Map */ typedef struct ddr_cs_bnds { u32 csbnds; -#define CSBNDS_SA 0x00FF0000 -#define CSBNDS_SA_SHIFT 8 -#define CSBNDS_EA 0x000000FF -#define CSBNDS_EA_SHIFT 24 u8 res0[4]; } ddr_cs_bnds_t; typedef struct ddr83xx { - ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */ + ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */ u8 res0[0x60]; - u32 cs_config[4]; /**< Chip Select x Configuration */ -#define CSCONFIG_EN 0x80000000 -#define CSCONFIG_AP 0x00800000 -#define CSCONFIG_ROW_BIT 0x00000700 -#define CSCONFIG_ROW_BIT_12 0x00000000 -#define CSCONFIG_ROW_BIT_13 0x00000100 -#define CSCONFIG_ROW_BIT_14 0x00000200 -#define CSCONFIG_COL_BIT 0x00000007 -#define CSCONFIG_COL_BIT_8 0x00000000 -#define CSCONFIG_COL_BIT_9 0x00000001 -#define CSCONFIG_COL_BIT_10 0x00000002 -#define CSCONFIG_COL_BIT_11 0x00000003 + u32 cs_config[4]; /* Chip Select x Configuration */ u8 res1[0x78]; - u32 timing_cfg_1; /**< SDRAM Timing Configuration 1 */ -#define TIMING_CFG1_PRETOACT 0x70000000 -#define TIMING_CFG1_PRETOACT_SHIFT 28 -#define TIMING_CFG1_ACTTOPRE 0x0F000000 -#define TIMING_CFG1_ACTTOPRE_SHIFT 24 -#define TIMING_CFG1_ACTTORW 0x00700000 -#define TIMING_CFG1_ACTTORW_SHIFT 20 -#define TIMING_CFG1_CASLAT 0x00070000 -#define TIMING_CFG1_CASLAT_SHIFT 16 -#define TIMING_CFG1_REFREC 0x0000F000 -#define TIMING_CFG1_REFREC_SHIFT 12 -#define TIMING_CFG1_WRREC 0x00000700 -#define TIMING_CFG1_WRREC_SHIFT 8 -#define TIMING_CFG1_ACTTOACT 0x00000070 -#define TIMING_CFG1_ACTTOACT_SHIFT 4 -#define TIMING_CFG1_WRTORD 0x00000007 -#define TIMING_CFG1_WRTORD_SHIFT 0 -#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ -#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ - - u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */ -#define TIMING_CFG2_CPO 0x0F000000 -#define TIMING_CFG2_CPO_SHIFT 24 -#define TIMING_CFG2_ACSM 0x00080000 -#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 -#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 -#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ - - u32 sdram_cfg; /**< SDRAM Control Configuration */ -#define SDRAM_CFG_MEM_EN 0x80000000 -#define SDRAM_CFG_SREN 0x40000000 -#define SDRAM_CFG_ECC_EN 0x20000000 -#define SDRAM_CFG_RD_EN 0x10000000 -#define SDRAM_CFG_SDRAM_TYPE 0x03000000 -#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 -#define SDRAM_CFG_DYN_PWR 0x00200000 -#define SDRAM_CFG_32_BE 0x00080000 -#define SDRAM_CFG_8_BE 0x00040000 -#define SDRAM_CFG_NCAP 0x00020000 -#define SDRAM_CFG_2T_EN 0x00008000 -#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 - + u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ + u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ + u32 sdram_cfg; /* SDRAM Control Configuration */ u8 res2[4]; - u32 sdram_mode; /**< SDRAM Mode Configuration */ -#define SDRAM_MODE_ESD 0xFFFF0000 -#define SDRAM_MODE_ESD_SHIFT 16 -#define SDRAM_MODE_SD 0x0000FFFF -#define SDRAM_MODE_SD_SHIFT 0 -#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ -#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ -#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ -#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ -#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ -#define DDR_MODE_WEAK 0x0002 /* weak drivers */ -#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ -#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ -#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ -#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ -#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ -#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ -#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ -#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ -#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ -#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ -#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */ -#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ -#define DDR_MODE_MODEREG 0x0000 /* select mode register */ - + u32 sdram_mode; /* SDRAM Mode Configuration */ u8 res3[8]; - u32 sdram_interval; /**< SDRAM Interval Configuration */ -#define SDRAM_INTERVAL_REFINT 0x3FFF0000 -#define SDRAM_INTERVAL_REFINT_SHIFT 16 -#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF -#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 + u32 sdram_interval; /* SDRAM Interval Configuration */ u8 res9[8]; u32 sdram_clk_cntl; -#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 -#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 -#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 -#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 -#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 - u8 res4[0xCCC]; - u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */ - u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */ - u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */ -#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ -#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ -#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ -#define ECC_ERR_INJECT_EEIM_SHIFT 0 + u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */ + u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */ + u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */ u8 res5[0x14]; - u32 capture_data_hi; /**< Memory Data Path Read Capture High */ - u32 capture_data_lo; /**< Memory Data Path Read Capture Low */ - u32 capture_ecc; /**< Memory Data Path Read Capture ECC */ -#define CAPTURE_ECC_ECE (0xff000000>>24) -#define CAPTURE_ECC_ECE_SHIFT 0 + u32 capture_data_hi; /* Memory Data Path Read Capture High */ + u32 capture_data_lo; /* Memory Data Path Read Capture Low */ + u32 capture_ecc; /* Memory Data Path Read Capture ECC */ u8 res6[0x14]; - u32 err_detect; /**< Memory Error Detect */ -#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ -#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ -#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ -#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ - u32 err_disable; /**< Memory Error Disable */ -#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ -#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ -#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ -#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED|ECC_ERROR_DISABLE_SBED|ECC_ERROR_DISABLE_MBED) - u32 err_int_en; /**< Memory Error Interrupt Enable */ -#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ -#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ -#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ -#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE) - u32 capture_attributes; /**< Memory Error Attributes Capture */ -#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ -#define ECC_CAPT_ATTR_BNUM_SHIFT 28 -#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ -#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 -#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 -#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 -#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 -#define ECC_CAPT_ATTR_TSIZ_SHIFT 24 -#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ -#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 -#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 -#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 -#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 -#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) -#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 -#define ECC_CAPT_ATTR_TSRC_I2C 0x9 -#define ECC_CAPT_ATTR_TSRC_JTAG 0xA -#define ECC_CAPT_ATTR_TSRC_PCI1 0xD -#define ECC_CAPT_ATTR_TSRC_PCI2 0xE -#define ECC_CAPT_ATTR_TSRC_DMA 0xF -#define ECC_CAPT_ATTR_TSRC_SHIFT 16 -#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ -#define ECC_CAPT_ATTR_TTYP_WRITE 0x1 -#define ECC_CAPT_ATTR_TTYP_READ 0x2 -#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 -#define ECC_CAPT_ATTR_TTYP_SHIFT 12 -#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ - u32 capture_address; /**< Memory Error Address Capture */ - u32 capture_ext_address;/**< Memory Error Extended Address Capture */ - u32 err_sbe; /**< Memory Single-Bit ECC Error Management */ -#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ -#define ECC_ERROR_MAN_SBET_SHIFT 16 -#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ -#define ECC_ERROR_MAN_SBEC_SHIFT 0 + u32 err_detect; /* Memory Error Detect */ + u32 err_disable; /* Memory Error Disable */ + u32 err_int_en; /* Memory Error Interrupt Enable */ + u32 capture_attributes; /* Memory Error Attributes Capture */ + u32 capture_address; /* Memory Error Address Capture */ + u32 capture_ext_address;/* Memory Error Extended Address Capture */ + u32 err_sbe; /* Memory Single-Bit ECC Error Management */ u8 res7[0xA4]; u32 debug_reg; u8 res8[0xFC]; } ddr83xx_t; -/* - * I2C1 Controller - */ - /* * DUART */ typedef struct duart83xx { - u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */ - u8 uier_udmb; /**< combined register for UIER and UDMB */ - u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */ - u8 ulcr; /**< line control register */ - u8 umcr; /**< MODEM control register */ - u8 ulsr; /**< line status register */ - u8 umsr; /**< MODEM status register */ - u8 uscr; /**< scratch register */ + u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */ + u8 uier_udmb; /* combined register for UIER and UDMB */ + u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */ + u8 ulcr; /* line control register */ + u8 umcr; /* MODEM control register */ + u8 ulsr; /* line status register */ + u8 umsr; /* MODEM status register */ + u8 uscr; /* scratch register */ u8 res0[8]; - u8 udsr; /**< DMA status register */ + u8 udsr; /* DMA status register */ u8 res1[3]; u8 res2[0xEC]; } duart83xx_t; @@ -1119,75 +327,52 @@ typedef struct duart83xx { * Local Bus Controller Registers */ typedef struct lbus_bank { - u32 br; /**< Base Register */ - u32 or; /**< Base Register */ + u32 br; /* Base Register */ + u32 or; /* Option Register */ } lbus_bank_t; typedef struct lbus83xx { lbus_bank_t bank[8]; u8 res0[0x28]; - u32 mar; /**< UPM Address Register */ + u32 mar; /* UPM Address Register */ u8 res1[0x4]; - u32 mamr; /**< UPMA Mode Register */ - u32 mbmr; /**< UPMB Mode Register */ - u32 mcmr; /**< UPMC Mode Register */ + u32 mamr; /* UPMA Mode Register */ + u32 mbmr; /* UPMB Mode Register */ + u32 mcmr; /* UPMC Mode Register */ u8 res2[0x8]; - u32 mrtpr; /**< Memory Refresh Timer Prescaler Register */ - u32 mdr; /**< UPM Data Register */ + u32 mrtpr; /* Memory Refresh Timer Prescaler Register */ + u32 mdr; /* UPM Data Register */ u8 res3[0x8]; - u32 lsdmr; /**< SDRAM Mode Register */ + u32 lsdmr; /* SDRAM Mode Register */ u8 res4[0x8]; - u32 lurt; /**< UPM Refresh Timer */ - u32 lsrt; /**< SDRAM Refresh Timer */ + u32 lurt; /* UPM Refresh Timer */ + u32 lsrt; /* SDRAM Refresh Timer */ u8 res5[0x8]; - u32 ltesr; /**< Transfer Error Status Register */ - u32 ltedr; /**< Transfer Error Disable Register */ - u32 lteir; /**< Transfer Error Interrupt Register */ - u32 lteatr; /**< Transfer Error Attributes Register */ - u32 ltear; /**< Transfer Error Address Register */ + u32 ltesr; /* Transfer Error Status Register */ + u32 ltedr; /* Transfer Error Disable Register */ + u32 lteir; /* Transfer Error Interrupt Register */ + u32 lteatr; /* Transfer Error Attributes Register */ + u32 ltear; /* Transfer Error Address Register */ u8 res6[0xC]; - u32 lbcr; /**< Configuration Register */ -#define LBCR_LDIS 0x80000000 -#define LBCR_LDIS_SHIFT 31 -#define LBCR_BCTLC 0x00C00000 -#define LBCR_BCTLC_SHIFT 22 -#define LBCR_LPBSE 0x00020000 -#define LBCR_LPBSE_SHIFT 17 -#define LBCR_EPAR 0x00010000 -#define LBCR_EPAR_SHIFT 16 -#define LBCR_BMT 0x0000FF00 -#define LBCR_BMT_SHIFT 8 - u32 lcrr; /**< Clock Ratio Register */ -#define LCRR_DBYP 0x80000000 -#define LCRR_DBYP_SHIFT 31 -#define LCRR_BUFCMDC 0x30000000 -#define LCRR_BUFCMDC_SHIFT 28 -#define LCRR_ECL 0x03000000 -#define LCRR_ECL_SHIFT 24 -#define LCRR_EADC 0x00030000 -#define LCRR_EADC_SHIFT 16 -#define LCRR_CLKDIV 0x0000000F -#define LCRR_CLKDIV_SHIFT 0 - + u32 lbcr; /* Configuration Register */ + u32 lcrr; /* Clock Ratio Register */ u8 res7[0x28]; u8 res8[0xF00]; } lbus83xx_t; -#if defined (CONFIG_MPC8349) /* * Serial Peripheral Interface */ typedef struct spi83xx { - u32 mode; /**< mode register */ - u32 event; /**< event register */ - u32 mask; /**< mask register */ - u32 com; /**< command register */ + u32 mode; /* mode register */ + u32 event; /* event register */ + u32 mask; /* mask register */ + u32 com; /* command register */ u8 res0[0x10]; - u32 tx; /**< transmit register */ - u32 rx; /**< receive register */ - u8 res1[0xD8]; + u32 tx; /* transmit register */ + u32 rx; /* receive register */ + u8 res1[0xFD8]; } spi83xx_t; -#endif /* * DMA/Messaging Unit @@ -1197,21 +382,17 @@ typedef struct dma83xx { u32 omisr; /* 0x30 Outbound message interrupt status register */ u32 omimr; /* 0x34 Outbound message interrupt mask register */ u32 res1[0x6]; /* 0x38-0x49 reserved */ - u32 imr0; /* 0x50 Inbound message register 0 */ u32 imr1; /* 0x54 Inbound message register 1 */ u32 omr0; /* 0x58 Outbound message register 0 */ u32 omr1; /* 0x5C Outbound message register 1 */ - u32 odr; /* 0x60 Outbound doorbell register */ u32 res2; /* 0x64-0x67 reserved */ u32 idr; /* 0x68 Inbound doorbell register */ u32 res3[0x5]; /* 0x6C-0x79 reserved */ - u32 imisr; /* 0x80 Inbound message interrupt status register */ u32 imimr; /* 0x84 Inbound message interrupt mask register */ u32 res4[0x1E]; /* 0x88-0x99 reserved */ - u32 dmamr0; /* 0x100 DMA 0 mode register */ u32 dmasr0; /* 0x104 DMA 0 status register */ u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */ @@ -1223,7 +404,6 @@ typedef struct dma83xx { u32 dmabcr0; /* 0x120 DMA 0 byte count register */ u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */ u32 res8[0x16]; /* 0x128-0x179 reserved */ - u32 dmamr1; /* 0x180 DMA 1 mode register */ u32 dmasr1; /* 0x184 DMA 1 status register */ u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */ @@ -1235,7 +415,6 @@ typedef struct dma83xx { u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */ u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */ u32 res12[0x16]; /* 0x1A8-0x199 reserved */ - u32 dmamr2; /* 0x200 DMA 2 mode register */ u32 dmasr2; /* 0x204 DMA 2 status register */ u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */ @@ -1247,7 +426,6 @@ typedef struct dma83xx { u32 dmabcr2; /* 0x220 DMA 2 byte count register */ u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */ u32 res16[0x16]; /* 0x228-0x279 reserved */ - u32 dmamr3; /* 0x280 DMA 3 mode register */ u32 dmasr3; /* 0x284 DMA 3 status register */ u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */ @@ -1258,39 +436,15 @@ typedef struct dma83xx { u32 res19; /* 0x29C reserved */ u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */ u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */ - u32 dmagsr; /* 0x2A8 DMA general status register */ u32 res20[0x15]; /* 0x2AC-0x2FF reserved */ } dma83xx_t; -/* DMAMRn bits */ -#define DMA_CHANNEL_START (0x00000001) /* Bit - DMAMRn CS */ -#define DMA_CHANNEL_TRANSFER_MODE_DIRECT (0x00000004) /* Bit - DMAMRn CTM */ -#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN (0x00001000) /* Bit - DMAMRn SAHE */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B (0x00000000) /* 2Bit- DMAMRn SAHTS 1byte */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B (0x00004000) /* 2Bit- DMAMRn SAHTS 2bytes */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B (0x00008000) /* 2Bit- DMAMRn SAHTS 4bytes */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B (0x0000c000) /* 2Bit- DMAMRn SAHTS 8bytes */ -#define DMA_CHANNEL_SNOOP (0x00010000) /* Bit - DMAMRn DMSEN */ - -/* DMASRn bits */ -#define DMA_CHANNEL_BUSY (0x00000004) /* Bit - DMASRn CB */ -#define DMA_CHANNEL_TRANSFER_ERROR (0x00000080) /* Bit - DMASRn TE */ - /* * PCI Software Configuration Registers */ typedef struct pciconf83xx { u32 config_address; -#define PCI_CONFIG_ADDRESS_EN 0x80000000 -#define PCI_CONFIG_ADDRESS_BN_SHIFT 16 -#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 -#define PCI_CONFIG_ADDRESS_DN_SHIFT 11 -#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 -#define PCI_CONFIG_ADDRESS_FN_SHIFT 8 -#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 -#define PCI_CONFIG_ADDRESS_RN_SHIFT 0 -#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc u32 config_data; u32 int_ack; u8 res[116]; @@ -1313,34 +467,6 @@ typedef struct pci_outbound_window { */ typedef struct ios83xx { pot83xx_t pot[6]; -#define POTAR_TA_MASK 0x000fffff -#define POBAR_BA_MASK 0x000fffff -#define POCMR_EN 0x80000000 -#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */ -#define POCMR_SE 0x20000000 /* streaming enable */ -#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */ -#define POCMR_CM_MASK 0x000fffff -#define POCMR_CM_4G 0x00000000 -#define POCMR_CM_2G 0x00080000 -#define POCMR_CM_1G 0x000C0000 -#define POCMR_CM_512M 0x000E0000 -#define POCMR_CM_256M 0x000F0000 -#define POCMR_CM_128M 0x000F8000 -#define POCMR_CM_64M 0x000FC000 -#define POCMR_CM_32M 0x000FE000 -#define POCMR_CM_16M 0x000FF000 -#define POCMR_CM_8M 0x000FF800 -#define POCMR_CM_4M 0x000FFC00 -#define POCMR_CM_2M 0x000FFE00 -#define POCMR_CM_1M 0x000FFF00 -#define POCMR_CM_512K 0x000FFF80 -#define POCMR_CM_256K 0x000FFFC0 -#define POCMR_CM_128K 0x000FFFE0 -#define POCMR_CM_64K 0x000FFFF0 -#define POCMR_CM_32K 0x000FFFF8 -#define POCMR_CM_16K 0x000FFFFC -#define POCMR_CM_8K 0x000FFFFE -#define POCMR_CM_4K 0x000FFFFF u8 res0[0x60]; u32 pmcr; u8 res1[4]; @@ -1353,74 +479,13 @@ typedef struct ios83xx { */ typedef struct pcictrl83xx { u32 esr; -#define ESR_MERR 0x80000000 -#define ESR_APAR 0x00000400 -#define ESR_PCISERR 0x00000200 -#define ESR_MPERR 0x00000100 -#define ESR_TPERR 0x00000080 -#define ESR_NORSP 0x00000040 -#define ESR_TABT 0x00000020 u32 ecdr; -#define ECDR_APAR 0x00000400 -#define ECDR_PCISERR 0x00000200 -#define ECDR_MPERR 0x00000100 -#define ECDR_TPERR 0x00000080 -#define ECDR_NORSP 0x00000040 -#define ECDR_TABT 0x00000020 u32 eer; -#define EER_APAR 0x00000400 -#define EER_PCISERR 0x00000200 -#define EER_MPERR 0x00000100 -#define EER_TPERR 0x00000080 -#define EER_NORSP 0x00000040 -#define EER_TABT 0x00000020 u32 eatcr; -#define EATCR_ERRTYPR_MASK 0x70000000 -#define EATCR_ERRTYPR_APR 0x00000000 /* address parity error */ -#define EATCR_ERRTYPR_WDPR 0x10000000 /* write data parity error */ -#define EATCR_ERRTYPR_RDPR 0x20000000 /* read data parity error */ -#define EATCR_ERRTYPR_MA 0x30000000 /* master abort */ -#define EATCR_ERRTYPR_TA 0x40000000 /* target abort */ -#define EATCR_ERRTYPR_SE 0x50000000 /* system error indication received */ -#define EATCR_ERRTYPR_PEA 0x60000000 /* parity error indication received on a read */ -#define EATCR_ERRTYPR_PEW 0x70000000 /* parity error indication received on a write */ -#define EATCR_BN_MASK 0x0f000000 /* beat number */ -#define EATCR_BN_1st 0x00000000 -#define EATCR_BN_2ed 0x01000000 -#define EATCR_BN_3rd 0x02000000 -#define EATCR_BN_4th 0x03000000 -#define EATCR_BN_5th 0x0400000 -#define EATCR_BN_6th 0x05000000 -#define EATCR_BN_7th 0x06000000 -#define EATCR_BN_8th 0x07000000 -#define EATCR_BN_9th 0x08000000 -#define EATCR_TS_MASK 0x00300000 /* transaction size */ -#define EATCR_TS_4 0x00000000 -#define EATCR_TS_1 0x00100000 -#define EATCR_TS_2 0x00200000 -#define EATCR_TS_3 0x00300000 -#define EATCR_ES_MASK 0x000f0000 /* error source */ -#define EATCR_ES_EM 0x00000000 /* external master */ -#define EATCR_ES_DMA 0x00050000 -#define EATCR_CMD_MASK 0x0000f000 -#if defined (CONFIG_MPC8349) -#define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable */ -#endif -#define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */ -#if defined (CONFIG_MPC8349) -#define EATCR_HPB 0x00000004 /* high parity bit */ -#endif -#define EATCR_PB 0x00000002 /* parity bit */ -#define EATCR_VI 0x00000001 /* error information valid */ u32 eacr; u32 eeacr; -#if defined (CONFIG_MPC8349) u32 edlcr; u32 edhcr; -#elif defined (CONFIG_MPC8360) - u32 edcr; /* was edlcr */ - u8 res_edcr[0x4]; -#endif u32 gcr; u32 ecr; u32 gsr; @@ -1443,41 +508,8 @@ typedef struct pcictrl83xx { u8 res6[4]; u32 piwar0; u8 res7[132]; -#define PITAR_TA_MASK 0x000fffff -#define PIBAR_MASK 0xffffffff -#define PIEBAR_EBA_MASK 0x000fffff -#define PIWAR_EN 0x80000000 -#define PIWAR_PF 0x20000000 -#define PIWAR_RTT_MASK 0x000f0000 -#define PIWAR_RTT_NO_SNOOP 0x00040000 -#define PIWAR_RTT_SNOOP 0x00050000 -#define PIWAR_WTT_MASK 0x0000f000 -#define PIWAR_WTT_NO_SNOOP 0x00004000 -#define PIWAR_WTT_SNOOP 0x00005000 -#define PIWAR_IWS_MASK 0x0000003F -#define PIWAR_IWS_4K 0x0000000B -#define PIWAR_IWS_8K 0x0000000C -#define PIWAR_IWS_16K 0x0000000D -#define PIWAR_IWS_32K 0x0000000E -#define PIWAR_IWS_64K 0x0000000F -#define PIWAR_IWS_128K 0x00000010 -#define PIWAR_IWS_256K 0x00000011 -#define PIWAR_IWS_512K 0x00000012 -#define PIWAR_IWS_1M 0x00000013 -#define PIWAR_IWS_2M 0x00000014 -#define PIWAR_IWS_4M 0x00000015 -#define PIWAR_IWS_8M 0x00000016 -#define PIWAR_IWS_16M 0x00000017 -#define PIWAR_IWS_32M 0x00000018 -#define PIWAR_IWS_64M 0x00000019 -#define PIWAR_IWS_128M 0x0000001A -#define PIWAR_IWS_256M 0x0000001B -#define PIWAR_IWS_512M 0x0000001C -#define PIWAR_IWS_1G 0x0000001D -#define PIWAR_IWS_2G 0x0000001E } pcictrl83xx_t; -#if defined (CONFIG_MPC8349) /* * USB */ @@ -1491,7 +523,6 @@ typedef struct usb83xx { typedef struct tsec83xx { u8 fixme[0x1000]; } tsec83xx_t; -#endif /* * Security @@ -1500,581 +531,82 @@ typedef struct security83xx { u8 fixme[0x10000]; } security83xx_t; -#if defined (CONFIG_MPC8360) -/* - * iram - */ -typedef struct iram83xx { - u32 iadd; /* I-RAM address register */ - u32 idata; /* I-RAM data register */ - u8 res0[0x78]; -} iram83xx_t; - -/* - * Interrupt Controller - */ -typedef struct irq83xx { - u32 cicr; /* QE system interrupt configuration */ - u32 civec; /* QE system interrupt vector register */ - u32 cripnr; /* QE RISC interrupt pending register */ - u32 cipnr; /* QE system interrupt pending register */ - u32 cipxcc; /* QE interrupt priority register */ - u32 cipycc; /* QE interrupt priority register */ - u32 cipwcc; /* QE interrupt priority register */ - u32 cipzcc; /* QE interrupt priority register */ - u32 cimr; /* QE system interrupt mask register */ - u32 crimr; /* QE RISC interrupt mask register */ - u32 cicnr; /* QE system interrupt control register */ - u8 res0[0x4]; - u32 ciprta; /* QE system interrupt priority register for RISC tasks A */ - u32 ciprtb; /* QE system interrupt priority register for RISC tasks B */ - u8 res1[0x4]; - u32 cricr; /* QE system RISC interrupt control */ - u8 res2[0x20]; - u32 chivec; /* QE high system interrupt vector */ - u8 res3[0x1C]; -} irq83xx_t; - -/* - * Communications Processor - */ -typedef struct cp83xx { - u32 cecr; /* QE command register */ - u32 ceccr; /* QE controller configuration register */ - u32 cecdr; /* QE command data register */ - u8 res0[0xA]; - u16 ceter; /* QE timer event register */ - u8 res1[0x2]; - u16 cetmr; /* QE timers mask register */ - u32 cetscr; /* QE time-stamp timer control register */ - u32 cetsr1; /* QE time-stamp register 1 */ - u32 cetsr2; /* QE time-stamp register 2 */ - u8 res2[0x8]; - u32 cevter; /* QE virtual tasks event register */ - u32 cevtmr; /* QE virtual tasks mask register */ - u16 cercr; /* QE RAM control register */ - u8 res3[0x2]; - u8 res4[0x24]; - u16 ceexe1; /* QE external request 1 event register */ - u8 res5[0x2]; - u16 ceexm1; /* QE external request 1 mask register */ - u8 res6[0x2]; - u16 ceexe2; /* QE external request 2 event register */ - u8 res7[0x2]; - u16 ceexm2; /* QE external request 2 mask register */ - u8 res8[0x2]; - u16 ceexe3; /* QE external request 3 event register */ - u8 res9[0x2]; - u16 ceexm3; /* QE external request 3 mask register */ - u8 res10[0x2]; - u16 ceexe4; /* QE external request 4 event register */ - u8 res11[0x2]; - u16 ceexm4; /* QE external request 4 mask register */ - u8 res12[0x2]; - u8 res13[0x280]; -} cp83xx_t; - -/* - * QE Multiplexer - */ - -typedef struct qmx83xx { - u32 cmxgcr; /* CMX general clock route register */ - u32 cmxsi1cr_l; /* CMX SI1 clock route low register */ - u32 cmxsi1cr_h; /* CMX SI1 clock route high register */ - u32 cmxsi1syr; /* CMX SI1 SYNC route register */ - u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */ - u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */ - u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */ - u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */ - u32 cmxupcr; /* CMX UPC clock route register */ - u8 res0[0x1C]; -} qmx83xx_t; - -/* -* QE Timers -*/ - -typedef struct qet83xx { - u8 gtcfr1; /* Timer 1 and Timer 2 global configuration register */ - u8 res0[0x3]; - u8 gtcfr2; /* Timer 3 and timer 4 global configuration register */ - u8 res1[0xB]; - u16 gtmdr1; /* Timer 1 mode register */ - u16 gtmdr2; /* Timer 2 mode register */ - u16 gtrfr1; /* Timer 1 reference register */ - u16 gtrfr2; /* Timer 2 reference register */ - u16 gtcpr1; /* Timer 1 capture register */ - u16 gtcpr2; /* Timer 2 capture register */ - u16 gtcnr1; /* Timer 1 counter */ - u16 gtcnr2; /* Timer 2 counter */ - u16 gtmdr3; /* Timer 3 mode register */ - u16 gtmdr4; /* Timer 4 mode register */ - u16 gtrfr3; /* Timer 3 reference register */ - u16 gtrfr4; /* Timer 4 reference register */ - u16 gtcpr3; /* Timer 3 capture register */ - u16 gtcpr4; /* Timer 4 capture register */ - u16 gtcnr3; /* Timer 3 counter */ - u16 gtcnr4; /* Timer 4 counter */ - u16 gtevr1; /* Timer 1 event register */ - u16 gtevr2; /* Timer 2 event register */ - u16 gtevr3; /* Timer 3 event register */ - u16 gtevr4; /* Timer 4 event register */ - u16 gtps; /* Timer 1 prescale register */ - u8 res2[0x46]; -} qet83xx_t; - -/* -* spi -*/ - -typedef struct spi83xx { - u8 res0[0x20]; - u32 spmode; /* SPI mode register */ - u8 res1[0x2]; - u8 spie; /* SPI event register */ - u8 res2[0x1]; - u8 res3[0x2]; - u8 spim; /* SPI mask register */ - u8 res4[0x1]; - u8 res5[0x1]; - u8 spcom; /* SPI command register */ - u8 res6[0x2]; - u32 spitd; /* SPI transmit data register (cpu mode) */ - u32 spird; /* SPI receive data register (cpu mode) */ - u8 res7[0x8]; -} spi83xx_t; - -/* -* mcc -*/ - -typedef struct mcc83xx { - u32 mcce; /* MCC event register */ - u32 mccm; /* MCC mask register */ - u32 mccf; /* MCC configuration register */ - u32 merl; /* MCC emergency request level register */ - u8 res0[0xF0]; -} mcc83xx_t; - -/* -* brg -*/ - -typedef struct brg83xx { - u32 brgc1; /* BRG1 configuration register */ - u32 brgc2; /* BRG2 configuration register */ - u32 brgc3; /* BRG3 configuration register */ - u32 brgc4; /* BRG4 configuration register */ - u32 brgc5; /* BRG5 configuration register */ - u32 brgc6; /* BRG6 configuration register */ - u32 brgc7; /* BRG7 configuration register */ - u32 brgc8; /* BRG8 configuration register */ - u32 brgc9; /* BRG9 configuration register */ - u32 brgc10; /* BRG10 configuration register */ - u32 brgc11; /* BRG11 configuration register */ - u32 brgc12; /* BRG12 configuration register */ - u32 brgc13; /* BRG13 configuration register */ - u32 brgc14; /* BRG14 configuration register */ - u32 brgc15; /* BRG15 configuration register */ - u32 brgc16; /* BRG16 configuration register */ - u8 res0[0x40]; -} brg83xx_t; - -/* -* USB -*/ - -typedef struct usb83xx { - u8 usmod; /* USB mode register */ - u8 usadd; /* USB address register */ - u8 uscom; /* USB command register */ - u8 res0[0x1]; - u16 usep0; /* USB endpoint register 0 */ - u16 usep1; /* USB endpoint register 1 */ - u16 usep2; /* USB endpoint register 2 */ - u16 usep3; /* USB endpoint register 3 */ - u8 res1[0x4]; - u16 usber; /* USB event register */ - u8 res2[0x2]; - u16 usbmr; /* USB mask register */ - u8 res3[0x1]; - u8 usbs; /* USB status register */ - u32 ussft; /* USB start of frame timer */ - u8 res4[0x24]; -} usb83xx_t; - -/* -* SI -*/ - -typedef struct si1_83xx { - u16 siamr1; /* SI1 TDMA mode register */ - u16 sibmr1; /* SI1 TDMB mode register */ - u16 sicmr1; /* SI1 TDMC mode register */ - u16 sidmr1; /* SI1 TDMD mode register */ - u8 siglmr1_h; /* SI1 global mode register high */ - u8 res0[0x1]; - u8 sicmdr1_h; /* SI1 command register high */ - u8 res2[0x1]; - u8 sistr1_h; /* SI1 status register high */ - u8 res3[0x1]; - u16 sirsr1_h; /* SI1 RAM shadow address register high */ - u8 sitarc1; /* SI1 RAM counter Tx TDMA */ - u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ - u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ - u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ - u8 sirarc1; /* SI1 RAM counter Rx TDMA */ - u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ - u8 sircrc1; /* SI1 RAM counter Rx TDMC */ - u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ - u8 res4[0x8]; - u16 siemr1; /* SI1 TDME mode register 16 bits */ - u16 sifmr1; /* SI1 TDMF mode register 16 bits */ - u16 sigmr1; /* SI1 TDMG mode register 16 bits */ - u16 sihmr1; /* SI1 TDMH mode register 16 bits */ - u8 siglmg1_l; /* SI1 global mode register low 8 bits */ - u8 res5[0x1]; - u8 sicmdr1_l; /* SI1 command register low 8 bits */ - u8 res6[0x1]; - u8 sistr1_l; /* SI1 status register low 8 bits */ - u8 res7[0x1]; - u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */ - u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ - u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ - u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ - u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ - u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ - u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ - u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ - u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ - u8 res8[0x8]; - u32 siml1; /* SI1 multiframe limit register */ - u8 siedm1; /* SI1 extended diagnostic mode register */ - u8 res9[0xBB]; -} si1_83xx_t; - -/* -* SI Routing Tables -*/ - -typedef struct sir83xx { - u8 tx[0x400]; - u8 rx[0x400]; - u8 res0[0x800]; -} sir83xx_t; - -/* -* ucc -*/ - -typedef struct uslow { - u32 gumr_l; /* UCCx general mode register (low) */ - u32 gumr_h; /* UCCx general mode register (high) */ - u16 upsmr; /* UCCx protocol-specific mode register */ - u8 res0[0x2]; - u16 utodr; /* UCCx transmit on demand register */ - u16 udsr; /* UCCx data synchronization register */ - u16 ucce; /* UCCx event register */ - u8 res1[0x2]; - u16 uccm; /* UCCx mask register */ - u8 res2[0x1]; - u8 uccs; /* UCCx status register */ - u8 res3[0x1E8]; -} uslow_t; - -typedef struct ufast { - u32 gumr; /* UCCx general mode register */ - u32 upsmr; /* UCCx protocol-specific mode register */ - u16 utodr; /* UCCx transmit on demand register */ - u8 res0[0x2]; - u16 udsr; /* UCCx data synchronization register */ - u8 res1[0x2]; - u32 ucce; /* UCCx event register */ - u32 uccm; /* UCCx mask register. */ - u8 uccs; /* UCCx status register */ - u8 res2[0x7]; - u32 urfb; /* UCC receive FIFO base */ - u16 urfs; /* UCC receive FIFO size */ - u8 res3[0x2]; - u16 urfet; /* UCC receive FIFO emergency threshold */ - u16 urfset; /* UCC receive FIFO special emergency threshold */ - u32 utfb; /* UCC transmit FIFO base */ - u16 utfs; /* UCC transmit FIFO size */ - u8 res4[0x2]; - u16 utfet; /* UCC transmit FIFO emergency threshold */ - u8 res5[0x2]; - u16 utftt; /* UCC transmit FIFO transmit threshold */ - u8 res6[0x2]; - u16 utpt; /* UCC transmit polling timer */ - u32 urtry; /* UCC retry counter register */ - u8 res7[0x4C]; - u8 guemr; /* UCC general extended mode register */ - u8 res8[0x3]; - u8 res9[0x6C]; - u32 maccfg1; /* Mac configuration register #1 */ - u32 maccfg2; /* Mac configuration register #2 */ - u16 ipgifg; /* Interframe gap register */ - u8 res10[0x2]; - u32 hafdup; /* Half-duplex register */ - u8 res11[0xC]; - u32 emtr; /* Ethernet MAC test register */ - u32 miimcfg; /* MII mgmt configuration register */ - u32 miimcom; /* MII mgmt command register */ - u32 miimadd; /* MII mgmt address register */ - u32 miimcon; /* MII mgmt control register */ - u32 miistat; /* MII mgmt status register */ - u32 miimnd; /* MII mgmt indication register */ - u32 ifctl; /* Interface control register */ - u32 ifstat; /* Interface status register */ - u32 macstnaddr1; /* Station address part 1 register */ - u32 macstnaddr2; /* Station address part 2 register */ - u8 res12[0x8]; - u32 uempr; /* UCC Ethernet MAC parameter register */ - u32 utbipa; /* UCC TBI address */ - u16 uescr; /* UCC Ethernet statistics control register */ - u8 res13[0x26]; - u32 tx64; /* Transmit and receive 64-byte frame counter */ - u32 tx127; /* Transmit and receive 65- to 127-byte frame counter */ - u32 tx255; /* Transmit and receive 128- to 255-byte frame counter */ - u32 rx64; /* Receive and receive 64-byte frame counter */ - u32 rx127; /* Receive and receive 65- to 127-byte frame counter */ - u32 rx255; /* Receive and receive 128- to 255-byte frame counter */ - u32 txok; /* Transmit good bytes counter */ - u32 txcf; /* Transmit control frame counter */ - u32 tmca; /* Transmit multicast control frame counter */ - u32 tbca; /* Transmit broadcast packet counter */ - u32 rxfok; /* Receive frame OK counter */ - u32 rbyt; /* Receive good and bad bytes counter */ - u32 rxbok; /* Receive bytes OK counter */ - u32 rmca; /* Receive multicast packet counter */ - u32 rbca; /* Receive broadcast packet counter */ - u32 scar; /* Statistics carry register */ - u32 scam; /* Statistics carry mask register */ - u8 res14[0x3C]; -} ufast_t; - -typedef struct ucc83xx { - union { - uslow_t slow; - ufast_t fast; - }; -} ucc83xx_t; - -/* -* MultiPHY UTOPIA POS Controllers -*/ - -typedef struct upc83xx { - u32 upgcr; /* UTOPIA/POS general configuration register */ -#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ -#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ -#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */ -#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing: */ -#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ - u32 uplpa; /* UTOPIA/POS last PHY address */ - u32 uphec; /* ATM HEC register */ - u32 upuc; /* UTOPIA/POS UCC configuration */ - u32 updc1; /* UTOPIA/POS device 1 configuration */ - u32 updc2; /* UTOPIA/POS device 2 configuration */ - u32 updc3; /* UTOPIA/POS device 3 configuration */ - u32 updc4; /* UTOPIA/POS device 4 configuration */ - u32 upstpa; /* UTOPIA/POS STPA threshold */ - u8 res0[0xC]; - u32 updrs1_h; /* UTOPIA/POS device 1 rate select */ - u32 updrs1_l; /* UTOPIA/POS device 1 rate select */ - u32 updrs2_h; /* UTOPIA/POS device 2 rate select */ - u32 updrs2_l; /* UTOPIA/POS device 2 rate select */ - u32 updrs3_h; /* UTOPIA/POS device 3 rate select */ - u32 updrs3_l; /* UTOPIA/POS device 3 rate select */ - u32 updrs4_h; /* UTOPIA/POS device 4 rate select */ - u32 updrs4_l; /* UTOPIA/POS device 4 rate select */ - u32 updrp1; /* UTOPIA/POS device 1 receive priority low */ - u32 updrp2; /* UTOPIA/POS device 2 receive priority low */ - u32 updrp3; /* UTOPIA/POS device 3 receive priority low */ - u32 updrp4; /* UTOPIA/POS device 4 receive priority low */ - u32 upde1; /* UTOPIA/POS device 1 event */ - u32 upde2; /* UTOPIA/POS device 2 event */ - u32 upde3; /* UTOPIA/POS device 3 event */ - u32 upde4; /* UTOPIA/POS device 4 event */ - u16 uprp1; - u16 uprp2; - u16 uprp3; - u16 uprp4; - u8 res1[0x8]; - u16 uptirr1_0; /* Device 1 transmit internal rate 0 */ - u16 uptirr1_1; /* Device 1 transmit internal rate 1 */ - u16 uptirr1_2; /* Device 1 transmit internal rate 2 */ - u16 uptirr1_3; /* Device 1 transmit internal rate 3 */ - u16 uptirr2_0; /* Device 2 transmit internal rate 0 */ - u16 uptirr2_1; /* Device 2 transmit internal rate 1 */ - u16 uptirr2_2; /* Device 2 transmit internal rate 2 */ - u16 uptirr2_3; /* Device 2 transmit internal rate 3 */ - u16 uptirr3_0; /* Device 3 transmit internal rate 0 */ - u16 uptirr3_1; /* Device 3 transmit internal rate 1 */ - u16 uptirr3_2; /* Device 3 transmit internal rate 2 */ - u16 uptirr3_3; /* Device 3 transmit internal rate 3 */ - u16 uptirr4_0; /* Device 4 transmit internal rate 0 */ - u16 uptirr4_1; /* Device 4 transmit internal rate 1 */ - u16 uptirr4_2; /* Device 4 transmit internal rate 2 */ - u16 uptirr4_3; /* Device 4 transmit internal rate 3 */ - u32 uper1; /* Device 1 port enable register */ - u32 uper2; /* Device 2 port enable register */ - u32 uper3; /* Device 3 port enable register */ - u32 uper4; /* Device 4 port enable register */ - u8 res2[0x150]; -} upc83xx_t; - -/* -* SDMA -*/ - -typedef struct sdma83xx { - u32 sdsr; /* Serial DMA status register */ - u32 sdmr; /* Serial DMA mode register */ - u32 sdtr1; /* SDMA system bus threshold register */ - u32 sdtr2; /* SDMA secondary bus threshold register */ - u32 sdhy1; /* SDMA system bus hysteresis register */ - u32 sdhy2; /* SDMA secondary bus hysteresis register */ - u32 sdta1; /* SDMA system bus address register */ - u32 sdta2; /* SDMA secondary bus address register */ - u32 sdtm1; /* SDMA system bus MSNUM register */ - u32 sdtm2; /* SDMA secondary bus MSNUM register */ - u8 res0[0x10]; - u32 sdaqr; /* SDMA address bus qualify register */ - u32 sdaqmr; /* SDMA address bus qualify mask register */ - u8 res1[0x4]; - u32 sdwbcr; /* SDMA CAM entries base register */ - u8 res2[0x38]; -} sdma83xx_t; - -/* -* Debug Space -*/ - -typedef struct dbg83xx { - u32 bpdcr; /* Breakpoint debug command register */ - u32 bpdsr; /* Breakpoint debug status register */ - u32 bpdmr; /* Breakpoint debug mask register */ - u32 bprmrr0; /* Breakpoint request mode risc register 0 */ - u32 bprmrr1; /* Breakpoint request mode risc register 1 */ - u8 res0[0x8]; - u32 bprmtr0; /* Breakpoint request mode trb register 0 */ - u32 bprmtr1; /* Breakpoint request mode trb register 1 */ - u8 res1[0x8]; - u32 bprmir; /* Breakpoint request mode immediate register */ - u32 bprmsr; /* Breakpoint request mode serial register */ - u32 bpemr; /* Breakpoint exit mode register */ - u8 res2[0x48]; -} dbg83xx_t; - -/* -* RISC Special Registers (Trap and Breakpoint) -*/ - -typedef struct rsp83xx { - u8 fixme[0x100]; -} rsp83xx_t; -#endif +#if defined(CONFIG_MPC8349) +typedef struct immap { + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + gtm83xx_t gtm[2]; /* Global Timers Module */ + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + gpio83xx_t gpio[2]; /* General purpose I/O module */ + u8 res0[0x200]; + u8 dll_ddr[0x100]; + u8 dll_lbc[0x100]; + u8 res1[0xE00]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res2[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res3[0x900]; + lbus83xx_t lbus; /* Local Bus Controller Registers */ + u8 res4[0x1000]; + spi83xx_t spi; /* Serial Peripheral Interface */ + dma83xx_t dma; /* DMA */ + pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ + ios83xx_t ios; /* Sequencer */ + pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ + u8 res5[0x19900]; + usb83xx_t usb; + tsec83xx_t tsec[2]; + u8 res6[0xA000]; + security83xx_t security; + u8 res7[0xC0000]; +} immap_t; +#elif defined(CONFIG_MPC8360) typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - gtm83xx_t gtm[2]; /* Global Timers Module */ - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ -#if defined (CONFIG_MPC8349) - gpio83xx_t pgio[2]; /* general purpose I/O module */ -#elif defined (CONFIG_MPC8360) - qepi83xx_t qepi; /* QE Ports Interrupts Registers */ -#endif - u8 res0[0x200]; -#if defined (CONFIG_MPC8360) - u8 DLL_LBDDR[0x100]; -#endif - u8 DDL_DDR[0x100]; - u8 DDL_LBIU[0x100]; -#if defined (CONFIG_MPC8349) - u8 res1[0xE00]; -#elif defined (CONFIG_MPC8360) - u8 res1[0x200]; - gpio83xx_t gpio; /* General purpose I/O module */ - qesba83xx_t qesba; /* QE Secondary Bus Access Windows */ -#endif - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res2[0x1300]; - duart83xx_t duart[2]; /* DUART */ -#if defined (CONFIG_MPC8349) - u8 res3[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ - u8 res4[0x1000]; - spi83xx_t spi; /* Serial Peripheral Interface */ - u8 res5[0xF00]; -#elif defined (CONFIG_MPC8360) - u8 res3[0x900]; - lbus83xx_t lbus; /* Local Bus Controller */ - u8 res4[0x2000]; -#endif - dma83xx_t dma; /* DMA */ -#if defined (CONFIG_MPC8349) - pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ - ios83xx_t ios; /* Sequencer */ - pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ - u8 res6[0x19900]; - usb83xx_t usb; - tsec83xx_t tsec[2]; - u8 res7[0xA000]; - security83xx_t security; -#elif defined (CONFIG_MPC8360) - pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ - u8 res_5[128]; - ios83xx_t ios; /* Sequencer (IOS) */ - pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ - u8 res6[0x4A00]; - ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */ - u8 res7[0x22000]; - security83xx_t security; - u8 res8[0xC0000]; - iram83xx_t iram; /* IRAM */ - irq83xx_t irq; /* Interrupt Controller */ - cp83xx_t cp; /* Communications Processor */ - qmx83xx_t qmx; /* QE Multiplexer */ - qet83xx_t qet; /* QE Timers */ - spi83xx_t spi[0x2]; /* spi */ - mcc83xx_t mcc; /* mcc */ - brg83xx_t brg; /* brg */ - usb83xx_t usb; /* USB */ - si1_83xx_t si1; /* SI */ - u8 res9[0x800]; - sir83xx_t sir; /* SI Routing Tables */ - ucc83xx_t ucc1; /* ucc1 */ - ucc83xx_t ucc3; /* ucc3 */ - ucc83xx_t ucc5; /* ucc5 */ - ucc83xx_t ucc7; /* ucc7 */ - u8 res10[0x600]; - upc83xx_t upc1; /* MultiPHY UTOPIA POS Controller 1 */ - ucc83xx_t ucc2; /* ucc2 */ - ucc83xx_t ucc4; /* ucc4 */ - ucc83xx_t ucc6; /* ucc6 */ - ucc83xx_t ucc8; /* ucc8 */ - u8 res11[0x600]; - upc83xx_t upc2; /* MultiPHY UTOPIA POS Controller 2 */ - sdma83xx_t sdma; /* SDMA */ - dbg83xx_t dbg; /* Debug Space */ - rsp83xx_t rsp[0x2]; /* RISC Special Registers (Trap and Breakpoint) */ - u8 res12[0x300]; - u8 res13[0x3A00]; - u8 res14[0x8000]; /* 0x108000 - 0x110000 */ - u8 res15[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ - u8 res16[0x24000]; /* 0x11C000 - 0x140000 */ - u8 res17[0xC0000]; /* 0x140000 - 0x200000 */ -#endif + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + u8 res0[0x200]; + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + qepi83xx_t qepi; /* QE Ports Interrupts Registers */ + u8 res1[0x300]; + u8 dll_ddr[0x100]; + u8 dll_lbc[0x100]; + u8 res2[0x200]; + qepio83xx_t qepio; /* QE Parallel I/O ports */ + qesba83xx_t qesba; /* QE Secondary Bus Access Windows */ + u8 res3[0x400]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res4[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res5[0x900]; + lbus83xx_t lbus; /* Local Bus Controller Registers */ + u8 res6[0x2000]; + dma83xx_t dma; /* DMA */ + pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ + u8 res7[128]; + ios83xx_t ios; /* Sequencer (IOS) */ + pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ + u8 res8[0x4A00]; + ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */ + u8 res9[0x22000]; + security83xx_t security; + u8 res10[0xC0000]; + u8 qe[0x100000]; /* QE block */ } immap_t; +#endif #endif /* __IMMAP_83xx__ */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 03dd0cafd2..504b6a97bc 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -10,12 +10,6 @@ * the License, or (at your option) any later version. */ -/* - * mpc83xx.h - * - * MPC83xx specific definitions - */ - #ifndef __MPC83XX_H__ #define __MPC83XX_H__ @@ -24,406 +18,941 @@ #include #endif -/* - * MPC83xx cpu provide RCR register to do reset thing specially. easier - * to implement +/* MPC83xx cpu provide RCR register to do reset thing specially */ - #define MPC83xx_RESET -/* - * System reset offset (PowerPC standard) +/* System reset offset (PowerPC standard) */ -#define EXC_OFF_SYS_RESET 0x0100 +#define EXC_OFF_SYS_RESET 0x0100 -/* - * Default Internal Memory Register Space (Freescale recomandation) +/* IMMRBAR - Internal Memory Register Base Address */ -#define CONFIG_DEFAULT_IMMR 0xFF400000 +#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ +#define IMMRBAR 0x0000 /* Register offset to immr */ +#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ +#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) -/* - * Watchdog +/* LAWBAR - Local Access Window Base Address Register */ -#define SWCRR 0x0204 -#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ -#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ -#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */ -#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ -#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) +#define LBLAWBAR0 0x0020 /* Register offset to immr */ +#define LBLAWAR0 0x0024 +#define LBLAWBAR1 0x0028 +#define LBLAWAR1 0x002C +#define LBLAWBAR2 0x0030 +#define LBLAWAR2 0x0034 +#define LBLAWBAR3 0x0038 +#define LBLAWAR3 0x003C +#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ + +/* SPRIDR - System Part and Revision ID Register + */ +#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ +#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ + +#define SPR_8349E_REV10 0x80300100 +#define SPR_8349_REV10 0x80310100 +#define SPR_8347E_REV10_TBGA 0x80320100 +#define SPR_8347_REV10_TBGA 0x80330100 +#define SPR_8347E_REV10_PBGA 0x80340100 +#define SPR_8347_REV10_PBGA 0x80350100 +#define SPR_8343E_REV10 0x80360100 +#define SPR_8343_REV10 0x80370100 + +#define SPR_8349E_REV11 0x80300101 +#define SPR_8349_REV11 0x80310101 +#define SPR_8347E_REV11_TBGA 0x80320101 +#define SPR_8347_REV11_TBGA 0x80330101 +#define SPR_8347E_REV11_PBGA 0x80340101 +#define SPR_8347_REV11_PBGA 0x80350101 +#define SPR_8343E_REV11 0x80360101 +#define SPR_8343_REV11 0x80370101 + +#define SPR_8360E_REV10 0x80480010 +#define SPR_8360_REV10 0x80490010 +#define SPR_8360E_REV11 0x80480011 +#define SPR_8360_REV11 0x80490011 +#define SPR_8360E_REV12 0x80480012 +#define SPR_8360_REV12 0x80490012 + +/* SPCR - System Priority Configuration Register + */ +#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ +#define SPCR_PCIHPE_SHIFT (31-3) +#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ +#define SPCR_PCIPR_SHIFT (31-7) +#define SPCR_OPT 0x00800000 /* Optimize */ +#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ +#define SPCR_TBEN_SHIFT (31-9) +#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ +#define SPCR_COREPR_SHIFT (31-11) + +#if defined(CONFIG_MPC8349) +/* SPCR bits - MPC8349 specific */ +#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ +#define SPCR_TSEC1DP_SHIFT (31-19) +#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ +#define SPCR_TSEC1BDP_SHIFT (31-21) +#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ +#define SPCR_TSEC1EP_SHIFT (31-23) +#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ +#define SPCR_TSEC2DP_SHIFT (31-27) +#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ +#define SPCR_TSEC2BDP_SHIFT (31-29) +#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ +#define SPCR_TSEC2EP_SHIFT (31-31) +#endif -#define SWCNR 0x0208 -#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. -#define SWCNR_RES ~(SWCNR_SWCN) +/* SICRL/H - System I/O Configuration Register Low/High + */ +#if defined(CONFIG_MPC8349) +/* SICRL bits - MPC8349 specific */ +#define SICRL_LDP_A 0x80000000 +#define SICRL_USB1 0x40000000 +#define SICRL_USB0 0x20000000 +#define SICRL_UART 0x0C000000 +#define SICRL_GPIO1_A 0x02000000 +#define SICRL_GPIO1_B 0x01000000 +#define SICRL_GPIO1_C 0x00800000 +#define SICRL_GPIO1_D 0x00400000 +#define SICRL_GPIO1_E 0x00200000 +#define SICRL_GPIO1_F 0x00180000 +#define SICRL_GPIO1_G 0x00040000 +#define SICRL_GPIO1_H 0x00020000 +#define SICRL_GPIO1_I 0x00010000 +#define SICRL_GPIO1_J 0x00008000 +#define SICRL_GPIO1_K 0x00004000 +#define SICRL_GPIO1_L 0x00003000 + +/* SICRH bits - MPC8349 specific */ +#define SICRH_DDR 0x80000000 +#define SICRH_TSEC1_A 0x10000000 +#define SICRH_TSEC1_B 0x08000000 +#define SICRH_TSEC1_C 0x04000000 +#define SICRH_TSEC1_D 0x02000000 +#define SICRH_TSEC1_E 0x01000000 +#define SICRH_TSEC1_F 0x00800000 +#define SICRH_TSEC2_A 0x00400000 +#define SICRH_TSEC2_B 0x00200000 +#define SICRH_TSEC2_C 0x00100000 +#define SICRH_TSEC2_D 0x00080000 +#define SICRH_TSEC2_E 0x00040000 +#define SICRH_TSEC2_F 0x00020000 +#define SICRH_TSEC2_G 0x00010000 +#define SICRH_TSEC2_H 0x00008000 +#define SICRH_GPIO2_A 0x00004000 +#define SICRH_GPIO2_B 0x00002000 +#define SICRH_GPIO2_C 0x00001000 +#define SICRH_GPIO2_D 0x00000800 +#define SICRH_GPIO2_E 0x00000400 +#define SICRH_GPIO2_F 0x00000200 +#define SICRH_GPIO2_G 0x00000180 +#define SICRH_GPIO2_H 0x00000060 +#define SICRH_TSOBI1 0x00000002 +#define SICRH_TSOBI2 0x00000001 + +#elif defined(CONFIG_MPC8360) +/* SICRL bits - MPC8360 specific */ +#define SICRL_LDP_A 0xC0000000 +#define SICRL_LCLK_1 0x10000000 +#define SICRL_LCLK_2 0x08000000 +#define SICRL_SRCID_A 0x03000000 +#define SICRL_IRQ_CKSTP_A 0x00C00000 + +/* SICRH bits - MPC8360 specific */ +#define SICRH_DDR 0x80000000 +#define SICRH_SECONDARY_DDR 0x40000000 +#define SICRH_SDDROE 0x20000000 +#define SICRH_IRQ3 0x10000000 +#define SICRH_UC1EOBI 0x00000004 +#define SICRH_UC2E1OBI 0x00000002 +#define SICRH_UC2E2OBI 0x00000001 +#endif -#define SWSRR 0x020E +/* SWCRR - System Watchdog Control Register + */ +#define SWCRR 0x0204 /* Register offset to immr */ +#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ +#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ +#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ +#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ +#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) + +/* SWCNR - System Watchdog Counter Register + */ +#define SWCNR 0x0208 /* Register offset to immr */ +#define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ +#define SWCNR_RES ~(SWCNR_SWCN) -/* - * Default Internal Memory Register Space (Freescale recomandation) +/* SWSRR - System Watchdog Service Register */ -#define IMMRBAR 0x0000 -#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */ -#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) +#define SWSRR 0x020E /* Register offset to immr */ -/* - * Default Internal Memory Register Space (Freescale recomandation) +/* ACR - Arbiter Configuration Register */ -#define LBLAWBAR0 0x0020 -#define LBLAWAR0 0x0024 -#define LBLAWBAR1 0x0028 -#define LBLAWAR1 0x002C -#define LBLAWBAR2 0x0030 -#define LBLAWAR2 0x0034 -#define LBLAWBAR3 0x0038 -#define LBLAWAR3 0x003C +#define ACR_COREDIS 0x10000000 /* Core disable */ +#define ACR_COREDIS_SHIFT (31-7) +#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ +#define ACR_PIPE_DEP_SHIFT (31-15) +#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ +#define ACR_PCI_RPTCNT_SHIFT (31-19) +#define ACR_RPTCNT 0x00000700 /* Repeat count */ +#define ACR_RPTCNT_SHIFT (31-23) +#define ACR_APARK 0x00000030 /* Address parking */ +#define ACR_APARK_SHIFT (31-27) +#define ACR_PARKM 0x0000000F /* Parking master */ +#define ACR_PARKM_SHIFT (31-31) + +/* ATR - Arbiter Timers Register + */ +#define ATR_DTO 0x00FF0000 /* Data time out */ +#define ATR_ATO 0x000000FF /* Address time out */ -/* - * The device ID and revision numbers - */ -#define SPR_8349E_REV10 0x80300100 -#define SPR_8349_REV10 0x80310100 -#define SPR_8347E_REV10_TBGA 0x80320100 -#define SPR_8347_REV10_TBGA 0x80330100 -#define SPR_8347E_REV10_PBGA 0x80340100 -#define SPR_8347_REV10_PBGA 0x80350100 -#define SPR_8343E_REV10 0x80360100 -#define SPR_8343_REV10 0x80370100 - -#define SPR_8349E_REV11 0x80300101 -#define SPR_8349_REV11 0x80310101 -#define SPR_8347E_REV11_TBGA 0x80320101 -#define SPR_8347_REV11_TBGA 0x80330101 -#define SPR_8347E_REV11_PBGA 0x80340101 -#define SPR_8347_REV11_PBGA 0x80350101 -#define SPR_8343E_REV11 0x80360101 -#define SPR_8343_REV11 0x80370101 - -#define SPR_8360E_REV10 0x80480010 -#define SPR_8360_REV10 0x80490010 -#define SPR_8360E_REV11 0x80480011 -#define SPR_8360_REV11 0x80490011 -#define SPR_8360E_REV12 0x80480012 -#define SPR_8360_REV12 0x80490012 +/* AER - Arbiter Event Register + */ +#define AER_ETEA 0x00000020 /* Transfer error */ +#define AER_RES 0x00000010 /* Reserved transfer type */ +#define AER_ECW 0x00000008 /* External control word transfer type */ +#define AER_AO 0x00000004 /* Address Only transfer type */ +#define AER_DTO 0x00000002 /* Data time out */ +#define AER_ATO 0x00000001 /* Address time out */ + +/* AEATR - Arbiter Event Address Register + */ +#define AEATR_EVENT 0x07000000 /* Event type */ +#define AEATR_MSTR_ID 0x001F0000 /* Master Id */ +#define AEATR_TBST 0x00000800 /* Transfer burst */ +#define AEATR_TSIZE 0x00000700 /* Transfer Size */ +#define AEATR_TTYPE 0x0000001F /* Transfer Type */ -/* - * Base Registers & Option Registers - */ -#define BR0 0x5000 -#define BR1 0x5008 -#define BR2 0x5010 -#define BR3 0x5018 -#define BR4 0x5020 -#define BR5 0x5028 -#define BR6 0x5030 -#define BR7 0x5038 - -#define BR_BA 0xFFFF8000 -#define BR_BA_SHIFT 15 -#define BR_PS 0x00001800 -#define BR_PS_SHIFT 11 -#define BR_PS_8 0x00000800 /* Port Size 8 bit */ -#define BR_PS_16 0x00001000 /* Port Size 16 bit */ -#define BR_PS_32 0x00001800 /* Port Size 32 bit */ -#define BR_DECC 0x00000600 -#define BR_DECC_SHIFT 9 -#define BR_WP 0x00000100 -#define BR_WP_SHIFT 8 -#define BR_MSEL 0x000000E0 -#define BR_MSEL_SHIFT 5 -#define BR_MS_GPCM 0x00000000 /* GPCM */ -#define BR_MS_SDRAM 0x00000060 /* SDRAM */ -#define BR_MS_UPMA 0x00000080 /* UPMA */ -#define BR_MS_UPMB 0x000000A0 /* UPMB */ -#define BR_MS_UPMC 0x000000C0 /* UPMC */ -#if defined (CONFIG_MPC8360) -#define BR_ATOM 0x0000000C -#define BR_ATOM_SHIFT 2 -#endif -#define BR_V 0x00000001 -#define BR_V_SHIFT 0 -#if defined (CONFIG_MPC8349) -#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) -#elif defined (CONFIG_MPC8360) -#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_ATOM|BR_V) +/* HRCWL - Hard Reset Configuration Word Low + */ +#define HRCWL_LBIUCM 0x80000000 +#define HRCWL_LBIUCM_SHIFT 31 +#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 +#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 + +#define HRCWL_DDRCM 0x40000000 +#define HRCWL_DDRCM_SHIFT 30 +#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 +#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 + +#define HRCWL_SPMF 0x0f000000 +#define HRCWL_SPMF_SHIFT 24 +#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 +#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 +#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 +#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 +#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 +#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 +#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 +#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 +#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 +#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 +#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 +#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 +#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 +#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 +#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 +#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 + +#define HRCWL_VCO_BYPASS 0x00000000 +#define HRCWL_VCO_1X2 0x00000000 +#define HRCWL_VCO_1X4 0x00200000 +#define HRCWL_VCO_1X8 0x00400000 + +#define HRCWL_COREPLL 0x007F0000 +#define HRCWL_COREPLL_SHIFT 16 +#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 +#define HRCWL_CORE_TO_CSB_1X1 0x00020000 +#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 +#define HRCWL_CORE_TO_CSB_2X1 0x00040000 +#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 +#define HRCWL_CORE_TO_CSB_3X1 0x00060000 + +#if defined(CONFIG_MPC8360) +#define HRCWL_CEVCOD 0x000000C0 +#define HRCWL_CEVCOD_SHIFT 6 +#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 +#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 +#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 + +#define HRCWL_CEPDF 0x00000020 +#define HRCWL_CEPDF_SHIFT 5 +#define HRCWL_CE_PLL_DIV_1X1 0x00000000 +#define HRCWL_CE_PLL_DIV_2X1 0x00000020 + +#define HRCWL_CEPMF 0x0000001F +#define HRCWL_CEPMF_SHIFT 0 +#define HRCWL_CE_TO_PLL_1X16_ 0x00000000 +#define HRCWL_CE_TO_PLL_1X2 0x00000002 +#define HRCWL_CE_TO_PLL_1X3 0x00000003 +#define HRCWL_CE_TO_PLL_1X4 0x00000004 +#define HRCWL_CE_TO_PLL_1X5 0x00000005 +#define HRCWL_CE_TO_PLL_1X6 0x00000006 +#define HRCWL_CE_TO_PLL_1X7 0x00000007 +#define HRCWL_CE_TO_PLL_1X8 0x00000008 +#define HRCWL_CE_TO_PLL_1X9 0x00000009 +#define HRCWL_CE_TO_PLL_1X10 0x0000000A +#define HRCWL_CE_TO_PLL_1X11 0x0000000B +#define HRCWL_CE_TO_PLL_1X12 0x0000000C +#define HRCWL_CE_TO_PLL_1X13 0x0000000D +#define HRCWL_CE_TO_PLL_1X14 0x0000000E +#define HRCWL_CE_TO_PLL_1X15 0x0000000F +#define HRCWL_CE_TO_PLL_1X16 0x00000010 +#define HRCWL_CE_TO_PLL_1X17 0x00000011 +#define HRCWL_CE_TO_PLL_1X18 0x00000012 +#define HRCWL_CE_TO_PLL_1X19 0x00000013 +#define HRCWL_CE_TO_PLL_1X20 0x00000014 +#define HRCWL_CE_TO_PLL_1X21 0x00000015 +#define HRCWL_CE_TO_PLL_1X22 0x00000016 +#define HRCWL_CE_TO_PLL_1X23 0x00000017 +#define HRCWL_CE_TO_PLL_1X24 0x00000018 +#define HRCWL_CE_TO_PLL_1X25 0x00000019 +#define HRCWL_CE_TO_PLL_1X26 0x0000001A +#define HRCWL_CE_TO_PLL_1X27 0x0000001B +#define HRCWL_CE_TO_PLL_1X28 0x0000001C +#define HRCWL_CE_TO_PLL_1X29 0x0000001D +#define HRCWL_CE_TO_PLL_1X30 0x0000001E +#define HRCWL_CE_TO_PLL_1X31 0x0000001F #endif -#define OR0 0x5004 -#define OR1 0x500C -#define OR2 0x5014 -#define OR3 0x501C -#define OR4 0x5024 -#define OR5 0x502C -#define OR6 0x5034 -#define OR7 0x503C - -#define OR_GPCM_AM 0xFFFF8000 -#define OR_GPCM_AM_SHIFT 15 -#define OR_GPCM_BCTLD 0x00001000 -#define OR_GPCM_BCTLD_SHIFT 12 -#define OR_GPCM_CSNT 0x00000800 -#define OR_GPCM_CSNT_SHIFT 11 -#define OR_GPCM_ACS 0x00000600 -#define OR_GPCM_ACS_SHIFT 9 -#define OR_GPCM_ACS_0b10 0x00000400 -#define OR_GPCM_ACS_0b11 0x00000600 -#define OR_GPCM_XACS 0x00000100 -#define OR_GPCM_XACS_SHIFT 8 -#define OR_GPCM_SCY 0x000000F0 -#define OR_GPCM_SCY_SHIFT 4 -#define OR_GPCM_SCY_1 0x00000010 -#define OR_GPCM_SCY_2 0x00000020 -#define OR_GPCM_SCY_3 0x00000030 -#define OR_GPCM_SCY_4 0x00000040 -#define OR_GPCM_SCY_5 0x00000050 -#define OR_GPCM_SCY_6 0x00000060 -#define OR_GPCM_SCY_7 0x00000070 -#define OR_GPCM_SCY_8 0x00000080 -#define OR_GPCM_SCY_9 0x00000090 -#define OR_GPCM_SCY_10 0x000000a0 -#define OR_GPCM_SCY_11 0x000000b0 -#define OR_GPCM_SCY_12 0x000000c0 -#define OR_GPCM_SCY_13 0x000000d0 -#define OR_GPCM_SCY_14 0x000000e0 -#define OR_GPCM_SCY_15 0x000000f0 -#define OR_GPCM_SETA 0x00000008 -#define OR_GPCM_SETA_SHIFT 3 -#define OR_GPCM_TRLX 0x00000004 -#define OR_GPCM_TRLX_SHIFT 2 -#define OR_GPCM_EHTR 0x00000002 -#define OR_GPCM_EHTR_SHIFT 1 -#define OR_GPCM_EAD 0x00000001 -#define OR_GPCM_EAD_SHIFT 0 - -#define OR_UPM_AM 0xFFFF8000 -#define OR_UPM_AM_SHIFT 15 -#define OR_UPM_XAM 0x00006000 -#define OR_UPM_XAM_SHIFT 13 -#define OR_UPM_BCTLD 0x00001000 -#define OR_UPM_BCTLD_SHIFT 12 -#define OR_UPM_BI 0x00000100 -#define OR_UPM_BI_SHIFT 8 -#define OR_UPM_TRLX 0x00000004 -#define OR_UPM_TRLX_SHIFT 2 -#define OR_UPM_EHTR 0x00000002 -#define OR_UPM_EHTR_SHIFT 1 -#define OR_UPM_EAD 0x00000001 -#define OR_UPM_EAD_SHIFT 0 - -#define OR_SDRAM_AM 0xFFFF8000 -#define OR_SDRAM_AM_SHIFT 15 -#define OR_SDRAM_XAM 0x00006000 -#define OR_SDRAM_XAM_SHIFT 13 -#define OR_SDRAM_COLS 0x00001C00 -#define OR_SDRAM_COLS_SHIFT 10 -#define OR_SDRAM_ROWS 0x000001C0 -#define OR_SDRAM_ROWS_SHIFT 6 -#define OR_SDRAM_PMSEL 0x00000020 -#define OR_SDRAM_PMSEL_SHIFT 5 -#define OR_SDRAM_EAD 0x00000001 -#define OR_SDRAM_EAD_SHIFT 0 - -/* - * Hard Reset Configration Word - High +/* HRCWH - Hardware Reset Configuration Word High */ -#define HRCWH_PCI_AGENT 0x00000000 -#define HRCWH_PCI_HOST 0x80000000 +#define HRCWH_PCI_HOST 0x80000000 +#define HRCWH_PCI_HOST_SHIFT 31 +#define HRCWH_PCI_AGENT 0x00000000 -#if defined (CONFIG_MPC8349) -#define HRCWH_32_BIT_PCI 0x00000000 -#define HRCWH_64_BIT_PCI 0x40000000 +#if defined(CONFIG_MPC8349) +#define HRCWH_32_BIT_PCI 0x00000000 +#define HRCWH_64_BIT_PCI 0x40000000 #endif -#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 -#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 +#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 +#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 + +#define HRCWH_PCI_ARBITER_DISABLE 0x00000000 +#define HRCWH_PCI_ARBITER_ENABLE 0x20000000 -#if defined (CONFIG_MPC8349) -#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 -#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 -#elif defined (CONFIG_MPC8360) -#define HRCWH_PCICKDRV_DISABLE 0x00000000 -#define HRCWH_PCICKDRV_ENABLE 0x10000000 +#if defined(CONFIG_MPC8349) +#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 +#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 + +#elif defined(CONFIG_MPC8360) +#define HRCWH_PCICKDRV_DISABLE 0x00000000 +#define HRCWH_PCICKDRV_ENABLE 0x10000000 #endif -#define HRCWH_CORE_DISABLE 0x08000000 -#define HRCWH_CORE_ENABLE 0x00000000 +#define HRCWH_CORE_DISABLE 0x08000000 +#define HRCWH_CORE_ENABLE 0x00000000 -#define HRCWH_FROM_0X00000100 0x00000000 -#define HRCWH_FROM_0XFFF00100 0x04000000 +#define HRCWH_FROM_0X00000100 0x00000000 +#define HRCWH_FROM_0XFFF00100 0x04000000 -#define HRCWH_BOOTSEQ_DISABLE 0x00000000 -#define HRCWH_BOOTSEQ_NORMAL 0x01000000 -#define HRCWH_BOOTSEQ_EXTENDED 0x02000000 +#define HRCWH_BOOTSEQ_DISABLE 0x00000000 +#define HRCWH_BOOTSEQ_NORMAL 0x01000000 +#define HRCWH_BOOTSEQ_EXTENDED 0x02000000 -#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 -#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 +#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 +#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 -#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 -#define HRCWH_ROM_LOC_PCI1 0x00100000 -#if defined (CONFIG_MPC8349) -#define HRCWH_ROM_LOC_PCI2 0x00200000 +#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 +#define HRCWH_ROM_LOC_PCI1 0x00100000 +#if defined(CONFIG_MPC8349) +#define HRCWH_ROM_LOC_PCI2 0x00200000 #endif -#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 -#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 -#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 - -#if defined (CONFIG_MPC8349) -#define HRCWH_TSEC1M_IN_RGMII 0x00000000 -#define HRCWH_TSEC1M_IN_RTBI 0x00004000 -#define HRCWH_TSEC1M_IN_GMII 0x00008000 -#define HRCWH_TSEC1M_IN_TBI 0x0000C000 - -#define HRCWH_TSEC2M_IN_RGMII 0x00000000 -#define HRCWH_TSEC2M_IN_RTBI 0x00001000 -#define HRCWH_TSEC2M_IN_GMII 0x00002000 -#define HRCWH_TSEC2M_IN_TBI 0x00003000 +#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 +#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 +#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 + +#if defined(CONFIG_MPC8349) +#define HRCWH_TSEC1M_IN_RGMII 0x00000000 +#define HRCWH_TSEC1M_IN_RTBI 0x00004000 +#define HRCWH_TSEC1M_IN_GMII 0x00008000 +#define HRCWH_TSEC1M_IN_TBI 0x0000C000 +#define HRCWH_TSEC2M_IN_RGMII 0x00000000 +#define HRCWH_TSEC2M_IN_RTBI 0x00001000 +#define HRCWH_TSEC2M_IN_GMII 0x00002000 +#define HRCWH_TSEC2M_IN_TBI 0x00003000 #endif -#if defined (CONFIG_MPC8360) -#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 -#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 +#if defined(CONFIG_MPC8360) +#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 +#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 #endif -#define HRCWH_BIG_ENDIAN 0x00000000 -#define HRCWH_LITTLE_ENDIAN 0x00000008 +#define HRCWH_BIG_ENDIAN 0x00000000 +#define HRCWH_LITTLE_ENDIAN 0x00000008 -#define HRCWH_LALE_NORMAL 0x00000000 -#define HRCWH_LALE_EARLY 0x00000004 +#define HRCWH_LALE_NORMAL 0x00000000 +#define HRCWH_LALE_EARLY 0x00000004 -#define HRCWH_LDP_SET 0x00000000 -#define HRCWH_LDP_CLEAR 0x00000002 +#define HRCWH_LDP_SET 0x00000000 +#define HRCWH_LDP_CLEAR 0x00000002 -/* - * Hard Reset Configration Word - Low - */ -#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 -#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 - -#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 -#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 - -#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 -#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 -#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 -#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 -#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 -#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 -#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 -#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 -#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 -#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 -#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 -#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 -#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 -#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 -#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 -#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 - -#define HRCWL_VCO_BYPASS 0x00000000 -#define HRCWL_VCO_1X2 0x00000000 -#define HRCWL_VCO_1X4 0x00200000 -#define HRCWL_VCO_1X8 0x00400000 - -#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 -#define HRCWL_CORE_TO_CSB_1X1 0x00020000 -#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 -#define HRCWL_CORE_TO_CSB_2X1 0x00040000 -#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 -#define HRCWL_CORE_TO_CSB_3X1 0x00060000 - -#if defined (CONFIG_MPC8360) -#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 -#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 -#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 - -#define HRCWL_CE_PLL_DIV_1X1 0x00000000 -#define HRCWL_CE_PLL_DIV_2X1 0x00000020 - -#define HRCWL_CE_TO_PLL_1X16_ 0x00000000 -#define HRCWL_CE_TO_PLL_1X2 0x00000002 -#define HRCWL_CE_TO_PLL_1X3 0x00000003 -#define HRCWL_CE_TO_PLL_1X4 0x00000004 -#define HRCWL_CE_TO_PLL_1X5 0x00000005 -#define HRCWL_CE_TO_PLL_1X6 0x00000006 -#define HRCWL_CE_TO_PLL_1X7 0x00000007 -#define HRCWL_CE_TO_PLL_1X8 0x00000008 -#define HRCWL_CE_TO_PLL_1X9 0x00000009 -#define HRCWL_CE_TO_PLL_1X10 0x0000000A -#define HRCWL_CE_TO_PLL_1X11 0x0000000B -#define HRCWL_CE_TO_PLL_1X12 0x0000000C -#define HRCWL_CE_TO_PLL_1X13 0x0000000D -#define HRCWL_CE_TO_PLL_1X14 0x0000000E -#define HRCWL_CE_TO_PLL_1X15 0x0000000F -#define HRCWL_CE_TO_PLL_1X16 0x00000010 -#define HRCWL_CE_TO_PLL_1X17 0x00000011 -#define HRCWL_CE_TO_PLL_1X18 0x00000012 -#define HRCWL_CE_TO_PLL_1X19 0x00000013 -#define HRCWL_CE_TO_PLL_1X20 0x00000014 -#define HRCWL_CE_TO_PLL_1X21 0x00000015 -#define HRCWL_CE_TO_PLL_1X22 0x00000016 -#define HRCWL_CE_TO_PLL_1X23 0x00000017 -#define HRCWL_CE_TO_PLL_1X24 0x00000018 -#define HRCWL_CE_TO_PLL_1X25 0x00000019 -#define HRCWL_CE_TO_PLL_1X26 0x0000001A -#define HRCWL_CE_TO_PLL_1X27 0x0000001B -#define HRCWL_CE_TO_PLL_1X28 0x0000001C -#define HRCWL_CE_TO_PLL_1X29 0x0000001D -#define HRCWL_CE_TO_PLL_1X30 0x0000001E -#define HRCWL_CE_TO_PLL_1X31 0x0000001F +/* RSR - Reset Status Register + */ +#define RSR_RSTSRC 0xE0000000 /* Reset source */ +#define RSR_RSTSRC_SHIFT 29 +#define RSR_BSF 0x00010000 /* Boot seq. fail */ +#define RSR_BSF_SHIFT 16 +#define RSR_SWSR 0x00002000 /* software soft reset */ +#define RSR_SWSR_SHIFT 13 +#define RSR_SWHR 0x00001000 /* software hard reset */ +#define RSR_SWHR_SHIFT 12 +#define RSR_JHRS 0x00000200 /* jtag hreset */ +#define RSR_JHRS_SHIFT 9 +#define RSR_JSRS 0x00000100 /* jtag sreset status */ +#define RSR_JSRS_SHIFT 8 +#define RSR_CSHR 0x00000010 /* checkstop reset status */ +#define RSR_CSHR_SHIFT 4 +#define RSR_SWRS 0x00000008 /* software watchdog reset status */ +#define RSR_SWRS_SHIFT 3 +#define RSR_BMRS 0x00000004 /* bus monitop reset status */ +#define RSR_BMRS_SHIFT 2 +#define RSR_SRS 0x00000002 /* soft reset status */ +#define RSR_SRS_SHIFT 1 +#define RSR_HRS 0x00000001 /* hard reset status */ +#define RSR_HRS_SHIFT 0 +#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ + RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ + RSR_BMRS | RSR_SRS | RSR_HRS) +/* RMR - Reset Mode Register + */ +#define RMR_CSRE 0x00000001 /* checkstop reset enable */ +#define RMR_CSRE_SHIFT 0 +#define RMR_RES ~(RMR_CSRE) + +/* RCR - Reset Control Register + */ +#define RCR_SWHR 0x00000002 /* software hard reset */ +#define RCR_SWSR 0x00000001 /* software soft reset */ +#define RCR_RES ~(RCR_SWHR | RCR_SWSR) + +/* RCER - Reset Control Enable Register + */ +#define RCER_CRE 0x00000001 /* software hard reset */ +#define RCER_RES ~(RCER_CRE) + +/* SPMR - System PLL Mode Register + */ +#define SPMR_LBIUCM 0x80000000 +#define SPMR_DDRCM 0x40000000 +#define SPMR_SPMF 0x0F000000 +#define SPMR_CKID 0x00800000 +#define SPMR_CKID_SHIFT 23 +#define SPMR_COREPLL 0x007F0000 +#define SPMR_CEVCOD 0x000000C0 +#define SPMR_CEPDF 0x00000020 +#define SPMR_CEPMF 0x0000001F + +/* OCCR - Output Clock Control Register + */ +#define OCCR_PCICOE0 0x80000000 +#define OCCR_PCICOE1 0x40000000 +#define OCCR_PCICOE2 0x20000000 +#define OCCR_PCICOE3 0x10000000 +#define OCCR_PCICOE4 0x08000000 +#define OCCR_PCICOE5 0x04000000 +#define OCCR_PCICOE6 0x02000000 +#define OCCR_PCICOE7 0x01000000 +#define OCCR_PCICD0 0x00800000 +#define OCCR_PCICD1 0x00400000 +#define OCCR_PCICD2 0x00200000 +#define OCCR_PCICD3 0x00100000 +#define OCCR_PCICD4 0x00080000 +#define OCCR_PCICD5 0x00040000 +#define OCCR_PCICD6 0x00020000 +#define OCCR_PCICD7 0x00010000 +#define OCCR_PCI1CR 0x00000002 +#define OCCR_PCI2CR 0x00000001 +#define OCCR_PCICR OCCR_PCI1CR + +/* SCCR - System Clock Control Register + */ +#define SCCR_ENCCM 0x03000000 +#define SCCR_ENCCM_SHIFT 24 +#define SCCR_ENCCM_0 0x00000000 +#define SCCR_ENCCM_1 0x01000000 +#define SCCR_ENCCM_2 0x02000000 +#define SCCR_ENCCM_3 0x03000000 + +#define SCCR_PCICM 0x00010000 +#define SCCR_PCICM_SHIFT 16 + +/* SCCR bits - MPC8349 specific */ +#define SCCR_TSEC1CM 0xc0000000 +#define SCCR_TSEC1CM_SHIFT 30 +#define SCCR_TSEC1CM_0 0x00000000 +#define SCCR_TSEC1CM_1 0x40000000 +#define SCCR_TSEC1CM_2 0x80000000 +#define SCCR_TSEC1CM_3 0xC0000000 + +#define SCCR_TSEC2CM 0x30000000 +#define SCCR_TSEC2CM_SHIFT 28 +#define SCCR_TSEC2CM_0 0x00000000 +#define SCCR_TSEC2CM_1 0x10000000 +#define SCCR_TSEC2CM_2 0x20000000 +#define SCCR_TSEC2CM_3 0x30000000 + +#define SCCR_USBMPHCM 0x00c00000 +#define SCCR_USBMPHCM_SHIFT 22 +#define SCCR_USBDRCM 0x00300000 +#define SCCR_USBDRCM_SHIFT 20 + +#define SCCR_USBCM_0 0x00000000 +#define SCCR_USBCM_1 0x00500000 +#define SCCR_USBCM_2 0x00A00000 +#define SCCR_USBCM_3 0x00F00000 + +#define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \ + | SCCR_TSEC2CM_3 \ + | SCCR_ENCCM_3 \ + | SCCR_USBCM_3 ) + +#define SCCR_DEFAULT 0xFFFFFFFF + +/* CSn_BDNS - Chip Select memory Bounds Register + */ +#define CSBNDS_SA 0x00FF0000 +#define CSBNDS_SA_SHIFT 8 +#define CSBNDS_EA 0x000000FF +#define CSBNDS_EA_SHIFT 24 + +/* CSn_CONFIG - Chip Select Configuration Register + */ +#define CSCONFIG_EN 0x80000000 +#define CSCONFIG_AP 0x00800000 +#define CSCONFIG_ROW_BIT 0x00000700 +#define CSCONFIG_ROW_BIT_12 0x00000000 +#define CSCONFIG_ROW_BIT_13 0x00000100 +#define CSCONFIG_ROW_BIT_14 0x00000200 +#define CSCONFIG_COL_BIT 0x00000007 +#define CSCONFIG_COL_BIT_8 0x00000000 +#define CSCONFIG_COL_BIT_9 0x00000001 +#define CSCONFIG_COL_BIT_10 0x00000002 +#define CSCONFIG_COL_BIT_11 0x00000003 + +/* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 + */ +#define TIMING_CFG1_PRETOACT 0x70000000 +#define TIMING_CFG1_PRETOACT_SHIFT 28 +#define TIMING_CFG1_ACTTOPRE 0x0F000000 +#define TIMING_CFG1_ACTTOPRE_SHIFT 24 +#define TIMING_CFG1_ACTTORW 0x00700000 +#define TIMING_CFG1_ACTTORW_SHIFT 20 +#define TIMING_CFG1_CASLAT 0x00070000 +#define TIMING_CFG1_CASLAT_SHIFT 16 +#define TIMING_CFG1_REFREC 0x0000F000 +#define TIMING_CFG1_REFREC_SHIFT 12 +#define TIMING_CFG1_WRREC 0x00000700 +#define TIMING_CFG1_WRREC_SHIFT 8 +#define TIMING_CFG1_ACTTOACT 0x00000070 +#define TIMING_CFG1_ACTTOACT_SHIFT 4 +#define TIMING_CFG1_WRTORD 0x00000007 +#define TIMING_CFG1_WRTORD_SHIFT 0 +#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ +#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ + +/* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 + */ +#define TIMING_CFG2_CPO 0x0F000000 +#define TIMING_CFG2_CPO_SHIFT 24 +#define TIMING_CFG2_ACSM 0x00080000 +#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 +#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 +#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ + +/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration + */ +#define SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG_SREN 0x40000000 +#define SDRAM_CFG_ECC_EN 0x20000000 +#define SDRAM_CFG_RD_EN 0x10000000 +#define SDRAM_CFG_SDRAM_TYPE 0x03000000 +#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 +#define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_8_BE 0x00040000 +#define SDRAM_CFG_NCAP 0x00020000 +#define SDRAM_CFG_2T_EN 0x00008000 +#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 + +/* DDR_SDRAM_MODE - DDR SDRAM Mode Register + */ +#define SDRAM_MODE_ESD 0xFFFF0000 +#define SDRAM_MODE_ESD_SHIFT 16 +#define SDRAM_MODE_SD 0x0000FFFF +#define SDRAM_MODE_SD_SHIFT 0 +#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ +#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ +#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ +#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ +#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ +#define DDR_MODE_WEAK 0x0002 /* weak drivers */ +#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ +#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ +#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ +#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ +#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ +#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ +#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ +#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ +#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ +#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ +#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ +#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ +#define DDR_MODE_MODEREG 0x0000 /* select mode register */ + +/* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register + */ +#define SDRAM_INTERVAL_REFINT 0x3FFF0000 +#define SDRAM_INTERVAL_REFINT_SHIFT 16 +#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF +#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 + +/* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register + */ +#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 + +/* ECC_ERR_INJECT - Memory data path error injection mask ECC + */ +#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ +#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ +#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ +#define ECC_ERR_INJECT_EEIM_SHIFT 0 + +/* CAPTURE_ECC - Memory data path read capture ECC + */ +#define CAPTURE_ECC_ECE (0xff000000>>24) +#define CAPTURE_ECC_ECE_SHIFT 0 + +/* ERR_DETECT - Memory error detect + */ +#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ +#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ +#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ +#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ + +/* ERR_DISABLE - Memory error disable + */ +#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ +#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ +#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ +#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ + ECC_ERROR_DISABLE_MBED) +/* ERR_INT_EN - Memory error interrupt enable + */ +#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ +#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ +#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ +#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ + ECC_ERR_INT_EN_MSEE) +/* CAPTURE_ATTRIBUTES - Memory error attributes capture + */ +#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ +#define ECC_CAPT_ATTR_BNUM_SHIFT 28 +#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ +#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 +#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 +#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 +#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 +#define ECC_CAPT_ATTR_TSIZ_SHIFT 24 +#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ +#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 +#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 +#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 +#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 +#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) +#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 +#define ECC_CAPT_ATTR_TSRC_I2C 0x9 +#define ECC_CAPT_ATTR_TSRC_JTAG 0xA +#define ECC_CAPT_ATTR_TSRC_PCI1 0xD +#define ECC_CAPT_ATTR_TSRC_PCI2 0xE +#define ECC_CAPT_ATTR_TSRC_DMA 0xF +#define ECC_CAPT_ATTR_TSRC_SHIFT 16 +#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ +#define ECC_CAPT_ATTR_TTYP_WRITE 0x1 +#define ECC_CAPT_ATTR_TTYP_READ 0x2 +#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 +#define ECC_CAPT_ATTR_TTYP_SHIFT 12 +#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ + +/* ERR_SBE - Single bit ECC memory error management + */ +#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ +#define ECC_ERROR_MAN_SBET_SHIFT 16 +#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ +#define ECC_ERROR_MAN_SBEC_SHIFT 0 + +/* BR - Base Registers + */ +#define BR0 0x5000 /* Register offset to immr */ +#define BR1 0x5008 +#define BR2 0x5010 +#define BR3 0x5018 +#define BR4 0x5020 +#define BR5 0x5028 +#define BR6 0x5030 +#define BR7 0x5038 + +#define BR_BA 0xFFFF8000 +#define BR_BA_SHIFT 15 +#define BR_PS 0x00001800 +#define BR_PS_SHIFT 11 +#define BR_PS_8 0x00000800 /* Port Size 8 bit */ +#define BR_PS_16 0x00001000 /* Port Size 16 bit */ +#define BR_PS_32 0x00001800 /* Port Size 32 bit */ +#define BR_DECC 0x00000600 +#define BR_DECC_SHIFT 9 +#define BR_WP 0x00000100 +#define BR_WP_SHIFT 8 +#define BR_MSEL 0x000000E0 +#define BR_MSEL_SHIFT 5 +#define BR_MS_GPCM 0x00000000 /* GPCM */ +#define BR_MS_SDRAM 0x00000060 /* SDRAM */ +#define BR_MS_UPMA 0x00000080 /* UPMA */ +#define BR_MS_UPMB 0x000000A0 /* UPMB */ +#define BR_MS_UPMC 0x000000C0 /* UPMC */ +#if defined(CONFIG_MPC8360) +#define BR_ATOM 0x0000000C +#define BR_ATOM_SHIFT 2 #endif +#define BR_V 0x00000001 +#define BR_V_SHIFT 0 -/* - * LCRR - Clock Ratio Register (10.3.1.16) - */ -#define LCRR_DBYP 0x80000000 -#define LCRR_DBYP_SHIFT 31 -#define LCRR_BUFCMDC 0x30000000 -#define LCRR_BUFCMDC_1 0x10000000 -#define LCRR_BUFCMDC_2 0x20000000 -#define LCRR_BUFCMDC_3 0x30000000 -#define LCRR_BUFCMDC_4 0x00000000 -#define LCRR_BUFCMDC_SHIFT 28 -#define LCRR_ECL 0x03000000 -#define LCRR_ECL_4 0x00000000 -#define LCRR_ECL_5 0x01000000 -#define LCRR_ECL_6 0x02000000 -#define LCRR_ECL_7 0x03000000 -#define LCRR_ECL_SHIFT 24 -#define LCRR_EADC 0x00030000 -#define LCRR_EADC_1 0x00010000 -#define LCRR_EADC_2 0x00020000 -#define LCRR_EADC_3 0x00030000 -#define LCRR_EADC_4 0x00000000 -#define LCRR_EADC_SHIFT 16 -#define LCRR_CLKDIV 0x0000000F -#define LCRR_CLKDIV_2 0x00000002 -#define LCRR_CLKDIV_4 0x00000004 -#define LCRR_CLKDIV_8 0x00000008 -#define LCRR_CLKDIV_SHIFT 0 +#if defined(CONFIG_MPC8349) +#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) +#elif defined(CONFIG_MPC8360) +#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) +#endif -/* - * SCCR-System Clock Control Register - */ -#define SCCR_TSEC1CM_0 0x00000000 -#define SCCR_TSEC1CM_1 0x40000000 -#define SCCR_TSEC1CM_2 0x80000000 -#define SCCR_TSEC1CM_3 0xC0000000 -#define SCCR_TSEC2CM_0 0x00000000 -#define SCCR_TSEC2CM_1 0x10000000 -#define SCCR_TSEC2CM_2 0x20000000 -#define SCCR_TSEC2CM_3 0x30000000 -#define SCCR_ENCCM_0 0x00000000 -#define SCCR_ENCCM_1 0x01000000 -#define SCCR_ENCCM_2 0x02000000 -#define SCCR_ENCCM_3 0x03000000 -#define SCCR_USBCM_0 0x00000000 -#define SCCR_USBCM_1 0x00500000 -#define SCCR_USBCM_2 0x00A00000 -#define SCCR_USBCM_3 0x00F00000 - -#define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \ - | SCCR_TSEC2CM_3 \ - | SCCR_ENCCM_3 \ - | SCCR_USBCM_3 ) - -#define SCCR_DEFAULT 0xFFFFFFFF +/* OR - Option Registers + */ +#define OR0 0x5004 /* Register offset to immr */ +#define OR1 0x500C +#define OR2 0x5014 +#define OR3 0x501C +#define OR4 0x5024 +#define OR5 0x502C +#define OR6 0x5034 +#define OR7 0x503C + +#define OR_GPCM_AM 0xFFFF8000 +#define OR_GPCM_AM_SHIFT 15 +#define OR_GPCM_BCTLD 0x00001000 +#define OR_GPCM_BCTLD_SHIFT 12 +#define OR_GPCM_CSNT 0x00000800 +#define OR_GPCM_CSNT_SHIFT 11 +#define OR_GPCM_ACS 0x00000600 +#define OR_GPCM_ACS_SHIFT 9 +#define OR_GPCM_ACS_0b10 0x00000400 +#define OR_GPCM_ACS_0b11 0x00000600 +#define OR_GPCM_XACS 0x00000100 +#define OR_GPCM_XACS_SHIFT 8 +#define OR_GPCM_SCY 0x000000F0 +#define OR_GPCM_SCY_SHIFT 4 +#define OR_GPCM_SCY_1 0x00000010 +#define OR_GPCM_SCY_2 0x00000020 +#define OR_GPCM_SCY_3 0x00000030 +#define OR_GPCM_SCY_4 0x00000040 +#define OR_GPCM_SCY_5 0x00000050 +#define OR_GPCM_SCY_6 0x00000060 +#define OR_GPCM_SCY_7 0x00000070 +#define OR_GPCM_SCY_8 0x00000080 +#define OR_GPCM_SCY_9 0x00000090 +#define OR_GPCM_SCY_10 0x000000a0 +#define OR_GPCM_SCY_11 0x000000b0 +#define OR_GPCM_SCY_12 0x000000c0 +#define OR_GPCM_SCY_13 0x000000d0 +#define OR_GPCM_SCY_14 0x000000e0 +#define OR_GPCM_SCY_15 0x000000f0 +#define OR_GPCM_SETA 0x00000008 +#define OR_GPCM_SETA_SHIFT 3 +#define OR_GPCM_TRLX 0x00000004 +#define OR_GPCM_TRLX_SHIFT 2 +#define OR_GPCM_EHTR 0x00000002 +#define OR_GPCM_EHTR_SHIFT 1 +#define OR_GPCM_EAD 0x00000001 +#define OR_GPCM_EAD_SHIFT 0 + +#define OR_UPM_AM 0xFFFF8000 +#define OR_UPM_AM_SHIFT 15 +#define OR_UPM_XAM 0x00006000 +#define OR_UPM_XAM_SHIFT 13 +#define OR_UPM_BCTLD 0x00001000 +#define OR_UPM_BCTLD_SHIFT 12 +#define OR_UPM_BI 0x00000100 +#define OR_UPM_BI_SHIFT 8 +#define OR_UPM_TRLX 0x00000004 +#define OR_UPM_TRLX_SHIFT 2 +#define OR_UPM_EHTR 0x00000002 +#define OR_UPM_EHTR_SHIFT 1 +#define OR_UPM_EAD 0x00000001 +#define OR_UPM_EAD_SHIFT 0 + +#define OR_SDRAM_AM 0xFFFF8000 +#define OR_SDRAM_AM_SHIFT 15 +#define OR_SDRAM_XAM 0x00006000 +#define OR_SDRAM_XAM_SHIFT 13 +#define OR_SDRAM_COLS 0x00001C00 +#define OR_SDRAM_COLS_SHIFT 10 +#define OR_SDRAM_ROWS 0x000001C0 +#define OR_SDRAM_ROWS_SHIFT 6 +#define OR_SDRAM_PMSEL 0x00000020 +#define OR_SDRAM_PMSEL_SHIFT 5 +#define OR_SDRAM_EAD 0x00000001 +#define OR_SDRAM_EAD_SHIFT 0 + +/* LBCR - Local Bus Configuration Register + */ +#define LBCR_LDIS 0x80000000 +#define LBCR_LDIS_SHIFT 31 +#define LBCR_BCTLC 0x00C00000 +#define LBCR_BCTLC_SHIFT 22 +#define LBCR_LPBSE 0x00020000 +#define LBCR_LPBSE_SHIFT 17 +#define LBCR_EPAR 0x00010000 +#define LBCR_EPAR_SHIFT 16 +#define LBCR_BMT 0x0000FF00 +#define LBCR_BMT_SHIFT 8 + +/* LCRR - Clock Ratio Register + */ +#define LCRR_DBYP 0x80000000 +#define LCRR_DBYP_SHIFT 31 +#define LCRR_BUFCMDC 0x30000000 +#define LCRR_BUFCMDC_SHIFT 28 +#define LCRR_BUFCMDC_1 0x10000000 +#define LCRR_BUFCMDC_2 0x20000000 +#define LCRR_BUFCMDC_3 0x30000000 +#define LCRR_BUFCMDC_4 0x00000000 +#define LCRR_ECL 0x03000000 +#define LCRR_ECL_SHIFT 24 +#define LCRR_ECL_4 0x00000000 +#define LCRR_ECL_5 0x01000000 +#define LCRR_ECL_6 0x02000000 +#define LCRR_ECL_7 0x03000000 +#define LCRR_EADC 0x00030000 +#define LCRR_EADC_SHIFT 16 +#define LCRR_EADC_1 0x00010000 +#define LCRR_EADC_2 0x00020000 +#define LCRR_EADC_3 0x00030000 +#define LCRR_EADC_4 0x00000000 +#define LCRR_CLKDIV 0x0000000F +#define LCRR_CLKDIV_SHIFT 0 +#define LCRR_CLKDIV_2 0x00000002 +#define LCRR_CLKDIV_4 0x00000004 +#define LCRR_CLKDIV_8 0x00000008 + +/* DMAMR - DMA Mode Register + */ +#define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ +#define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ +#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ +#define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ + +/* DMASR - DMA Status Register + */ +#define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ +#define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ + +/* CONFIG_ADDRESS - PCI Config Address Register + */ +#define PCI_CONFIG_ADDRESS_EN 0x80000000 +#define PCI_CONFIG_ADDRESS_BN_SHIFT 16 +#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 +#define PCI_CONFIG_ADDRESS_DN_SHIFT 11 +#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 +#define PCI_CONFIG_ADDRESS_FN_SHIFT 8 +#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 +#define PCI_CONFIG_ADDRESS_RN_SHIFT 0 +#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc + +/* POTAR - PCI Outbound Translation Address Register + */ +#define POTAR_TA_MASK 0x000fffff + +/* POBAR - PCI Outbound Base Address Register + */ +#define POBAR_BA_MASK 0x000fffff + +/* POCMR - PCI Outbound Comparision Mask Register + */ +#define POCMR_EN 0x80000000 +#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ +#define POCMR_SE 0x20000000 /* streaming enable */ +#define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ +#define POCMR_CM_MASK 0x000fffff +#define POCMR_CM_4G 0x00000000 +#define POCMR_CM_2G 0x00080000 +#define POCMR_CM_1G 0x000C0000 +#define POCMR_CM_512M 0x000E0000 +#define POCMR_CM_256M 0x000F0000 +#define POCMR_CM_128M 0x000F8000 +#define POCMR_CM_64M 0x000FC000 +#define POCMR_CM_32M 0x000FE000 +#define POCMR_CM_16M 0x000FF000 +#define POCMR_CM_8M 0x000FF800 +#define POCMR_CM_4M 0x000FFC00 +#define POCMR_CM_2M 0x000FFE00 +#define POCMR_CM_1M 0x000FFF00 +#define POCMR_CM_512K 0x000FFF80 +#define POCMR_CM_256K 0x000FFFC0 +#define POCMR_CM_128K 0x000FFFE0 +#define POCMR_CM_64K 0x000FFFF0 +#define POCMR_CM_32K 0x000FFFF8 +#define POCMR_CM_16K 0x000FFFFC +#define POCMR_CM_8K 0x000FFFFE +#define POCMR_CM_4K 0x000FFFFF + +/* PITAR - PCI Inbound Translation Address Register + */ +#define PITAR_TA_MASK 0x000fffff + +/* PIBAR - PCI Inbound Base/Extended Address Register + */ +#define PIBAR_MASK 0xffffffff +#define PIEBAR_EBA_MASK 0x000fffff + +/* PIWAR - PCI Inbound Windows Attributes Register + */ +#define PIWAR_EN 0x80000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_RTT_MASK 0x000f0000 +#define PIWAR_RTT_NO_SNOOP 0x00040000 +#define PIWAR_RTT_SNOOP 0x00050000 +#define PIWAR_WTT_MASK 0x0000f000 +#define PIWAR_WTT_NO_SNOOP 0x00004000 +#define PIWAR_WTT_SNOOP 0x00005000 +#define PIWAR_IWS_MASK 0x0000003F +#define PIWAR_IWS_4K 0x0000000B +#define PIWAR_IWS_8K 0x0000000C +#define PIWAR_IWS_16K 0x0000000D +#define PIWAR_IWS_32K 0x0000000E +#define PIWAR_IWS_64K 0x0000000F +#define PIWAR_IWS_128K 0x00000010 +#define PIWAR_IWS_256K 0x00000011 +#define PIWAR_IWS_512K 0x00000012 +#define PIWAR_IWS_1M 0x00000013 +#define PIWAR_IWS_2M 0x00000014 +#define PIWAR_IWS_4M 0x00000015 +#define PIWAR_IWS_8M 0x00000016 +#define PIWAR_IWS_16M 0x00000017 +#define PIWAR_IWS_32M 0x00000018 +#define PIWAR_IWS_64M 0x00000019 +#define PIWAR_IWS_128M 0x0000001A +#define PIWAR_IWS_256M 0x0000001B +#define PIWAR_IWS_512M 0x0000001C +#define PIWAR_IWS_1G 0x0000001D +#define PIWAR_IWS_2G 0x0000001E #endif /* __MPC83XX_H__ */ -- cgit v1.2.1 From 24c3aca3f1358b113d3215adb5433b156e99f72b Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Thu, 7 Dec 2006 21:13:15 +0800 Subject: mpc83xx: Add support for the MPC832XEMDS board This patch supports DUART, ETH3/4 and PCI etc. Signed-off-by: Dave Liu --- include/asm-ppc/e300.h | 5 + include/asm-ppc/immap_83xx.h | 72 ++++- include/asm-ppc/immap_qe.h | 6 + include/configs/MPC832XEMDS.h | 629 ++++++++++++++++++++++++++++++++++++++++++ include/mpc83xx.h | 21 +- 5 files changed, 720 insertions(+), 13 deletions(-) create mode 100644 include/configs/MPC832XEMDS.h (limited to 'include') diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h index 79dcae416f..ff9512f203 100644 --- a/include/asm-ppc/e300.h +++ b/include/asm-ppc/e300.h @@ -15,6 +15,11 @@ #define PVR_8360_REV10 (PVR_83xx | 0x0020) #define PVR_8360_REV11 (PVR_83xx | 0x0020) +#if defined(CONFIG_MPC832X) +#undef PVR_83xx +#define PVR_83xx 0x80840000 +#endif + /* * Hardware Implementation-Dependent Register 0 (HID0) */ diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 67b035c614..77a079f44e 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -60,7 +60,10 @@ typedef struct sysconf83xx { u32 spcr; /* System Priority Configuration Register */ u32 sicrl; /* System I/O Configuration Register Low */ u32 sicrh; /* System I/O Configuration Register High */ - u8 res6[0xE4]; + u8 res6[0x0C]; + u32 ddrcdr; /* DDR Control Driver Register */ + u32 ddrdsr; /* DDR Debug Status Register */ + u8 res7[0xD0]; } sysconf83xx_t; /* @@ -274,25 +277,35 @@ typedef struct ddr83xx { ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */ u8 res0[0x60]; u32 cs_config[4]; /* Chip Select x Configuration */ - u8 res1[0x78]; + u8 res1[0x70]; + u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ + u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ u32 sdram_cfg; /* SDRAM Control Configuration */ - u8 res2[4]; + u32 sdram_cfg2; /* SDRAM Control Configuration 2 */ u32 sdram_mode; /* SDRAM Mode Configuration */ - u8 res3[8]; + u32 sdram_mode2; /* SDRAM Mode Configuration 2 */ + u32 sdram_md_cntl; /* SDRAM Mode Control */ u32 sdram_interval; /* SDRAM Interval Configuration */ - u8 res9[8]; - u32 sdram_clk_cntl; - u8 res4[0xCCC]; + u32 ddr_data_init; /* SDRAM Data Initialization */ + u8 res2[4]; + u32 sdram_clk_cntl; /* SDRAM Clock Control */ + u8 res3[0x14]; + u32 ddr_init_addr; /* DDR training initialization address */ + u32 ddr_init_ext_addr; /* DDR training initialization extended address */ + u8 res4[0xAA8]; + u32 ddr_ip_rev1; /* DDR IP block revision 1 */ + u32 ddr_ip_rev2; /* DDR IP block revision 2 */ + u8 res5[0x200]; u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */ u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */ u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */ - u8 res5[0x14]; + u8 res6[0x14]; u32 capture_data_hi; /* Memory Data Path Read Capture High */ u32 capture_data_lo; /* Memory Data Path Read Capture Low */ u32 capture_ecc; /* Memory Data Path Read Capture ECC */ - u8 res6[0x14]; + u8 res7[0x14]; u32 err_detect; /* Memory Error Detect */ u32 err_disable; /* Memory Error Disable */ u32 err_int_en; /* Memory Error Interrupt Enable */ @@ -300,9 +313,9 @@ typedef struct ddr83xx { u32 capture_address; /* Memory Error Address Capture */ u32 capture_ext_address;/* Memory Error Extended Address Capture */ u32 err_sbe; /* Memory Single-Bit ECC Error Management */ - u8 res7[0xA4]; + u8 res8[0xA4]; u32 debug_reg; - u8 res8[0xFC]; + u8 res9[0xFC]; } ddr83xx_t; /* @@ -607,6 +620,43 @@ typedef struct immap { u8 res10[0xC0000]; u8 qe[0x100000]; /* QE block */ } immap_t; + +#elif defined(CONFIG_MPC832X) +typedef struct immap { + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + gtm83xx_t gtm[2]; /* Global Timers Module */ + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + qepi83xx_t qepi; /* QE Ports Interrupts Registers */ + u8 res0[0x300]; + u8 dll_ddr[0x100]; + u8 dll_lbc[0x100]; + u8 res1[0x200]; + qepio83xx_t qepio; /* QE Parallel I/O ports */ + u8 res2[0x800]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res3[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res4[0x900]; + lbus83xx_t lbus; /* Local Bus Controller Registers */ + u8 res5[0x2000]; + dma83xx_t dma; /* DMA */ + pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ + u8 res6[128]; + ios83xx_t ios; /* Sequencer (IOS) */ + pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ + u8 res7[0x27A00]; + security83xx_t security; + u8 res8[0xC0000]; + u8 qe[0x100000]; /* QE block */ +} immap_t; #endif #endif /* __IMMAP_83xx__ */ diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h index f38503206c..950b9497f8 100644 --- a/include/asm-ppc/immap_qe.h +++ b/include/asm-ppc/immap_qe.h @@ -547,4 +547,10 @@ typedef struct qe_immap { extern qe_map_t *qe_immr; +#if defined(CONFIG_MPC8360) +#define QE_MURAM_SIZE 0xc000UL +#elif defined(CONFIG_MPC832X) +#define QE_MURAM_SIZE 0x4000UL +#endif + #endif /* __IMMAP_QE_H__ */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h new file mode 100644 index 0000000000..b8bf00f861 --- /dev/null +++ b/include/configs/MPC832XEMDS.h @@ -0,0 +1,629 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ +#define CONFIG_MPC83XX 1 /* MPC83xx family */ +#define CONFIG_MPC832X 1 /* MPC832x CPU specific */ +#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ + +/* + * System Clock Setup + */ +#ifdef CONFIG_PCISLAVE +#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ +#else +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 66000000 +#endif + +/* + * Hardware Reset Configuration Word + */ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_VCO_1X2 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CORE_TO_CSB_2X1 |\ + HRCWL_CE_PLL_VCO_DIV_2 |\ + HRCWL_CE_PLL_DIV_1X1 |\ + HRCWL_CE_TO_PLL_1X3) + +#ifdef CONFIG_PCISLAVE +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_AGENT |\ + HRCWH_PCI1_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) +#endif + +/* + * System IO Config + */ +#define CFG_SICRL 0x00000000 + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +/* + * IMMR new address + */ +#define CFG_IMMR 0xE0000000 + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ + +#undef CONFIG_SPD_EEPROM +#if defined(CONFIG_SPD_EEPROM) +/* Determine DDR configuration from I2C interface + */ +#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ +#else +/* Manually set up DDR parameters + */ +#define CFG_DDR_SIZE 128 /* MB */ +#define CFG_DDR_CS0_CONFIG 0x80840102 +#define CFG_DDR_TIMING_0 0x00220802 +#define CFG_DDR_TIMING_1 0x3935d322 +#define CFG_DDR_TIMING_2 0x0f9048ca +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_CLK_CNTL 0x02000000 +#define CFG_DDR_MODE 0x44400232 +#define CFG_DDR_MODE2 0x8000c000 +#define CFG_DDR_INTERVAL 0x03200064 +#define CFG_DDR_CS0_BNDS 0x00000007 +#define CFG_DDR_SDRAM_CFG 0x43080000 +#define CFG_DDR_SDRAM_CFG2 0x00401000 +#endif + +/* + * Memory test + */ +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 /* memtest region */ +#define CFG_MEMTEST_END 0x00100000 + +/* + * The reserved memory + */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CFG_LBC_LBCR 0x00000000 + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ + +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM + +/* + * BCSR on the Local Bus + */ +#define CFG_BCSR 0xF8000000 +#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ +#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ + +#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ +#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ + +/* + * SDRAM on the Local Bus + */ +#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */ + +#ifdef CFG_LB_SDRAM +#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE +#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ + +/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON 0x0063b723 + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) + +#endif + +/* + * Windows to access PIB via local bus + */ +#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ +#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ + +/* + * CS2 on Local Bus, to PIB + */ +#define CFG_BR2_PRELIM 0xf8008801 /* CS2 base address at 0xf8008000 */ +#define CFG_OR2_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ + +/* + * CS3 on Local Bus, to PIB + */ +#define CFG_BR3_PRELIM 0xf8010801 /* CS3 base address at 0xf8010000 */ +#define CFG_OR3_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8323@0" +#define OF_SOC "soc8323@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500" + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 + +/* + * Config on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI_MEM_BASE 0x80000000 +#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_MMIO_BASE 0x90000000 +#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE +#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_IO_BASE 0xE0300000 +#define CFG_PCI_IO_PHYS 0xE0300000 +#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ + +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE +#define CFG_PCI_SLV_MEM_BUS 0x00000000 +#define CFG_PCI_SLV_MEM_SIZE 0x80000000 + + +#ifdef CONFIG_PCI + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "Freescale GETH" + +#define CONFIG_UEC_ETH1 /* ETH3 */ + +#ifdef CONFIG_UEC_ETH1 +#define CFG_UEC1_UCC_NUM 2 /* UCC3 */ +#define CFG_UEC1_RX_CLK QE_CLK9 +#define CFG_UEC1_TX_CLK QE_CLK10 +#define CFG_UEC1_ETH_TYPE FAST_ETH +#define CFG_UEC1_PHY_ADDR 3 +#define CFG_UEC1_INTERFACE_MODE ENET_100_MII +#endif + +#define CONFIG_UEC_ETH2 /* ETH4 */ + +#ifdef CONFIG_UEC_ETH2 +#define CFG_UEC2_UCC_NUM 3 /* UCC4 */ +#define CFG_UEC2_RX_CLK QE_CLK7 +#define CFG_UEC2_TX_CLK QE_CLK8 +#define CFG_UEC2_ETH_TYPE FAST_ETH +#define CFG_UEC2_PHY_ADDR 4 +#define CFG_UEC2_INTERFACE_MODE ENET_100_MII +#endif + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#endif +#else +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C ) +#endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CFG_HID2 HID2_HBE + +/* + * Cache Config + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ +#endif + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* BCSR: cache-inhibit and guarded */ +#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U + +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) +#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else +#define CFG_IBAT6L (0) +#define CFG_IBAT6U (0) +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_ETHADDR 00:04:9f:ef:03:01 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=ramfs.83xx\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc832xemds.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 504b6a97bc..52e4369151 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -75,6 +75,15 @@ #define SPR_8360E_REV12 0x80480012 #define SPR_8360_REV12 0x80490012 +#define SPR_8323E_REV10 0x80620010 +#define SPR_8323_REV10 0x80630010 +#define SPR_8321E_REV10 0x80660010 +#define SPR_8321_REV10 0x80670010 +#define SPR_8323E_REV11 0x80620011 +#define SPR_8323_REV11 0x80630011 +#define SPR_8321E_REV11 0x80660011 +#define SPR_8321_REV11 0x80670011 + /* SPCR - System Priority Configuration Register */ #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ @@ -167,6 +176,14 @@ #define SICRH_UC1EOBI 0x00000004 #define SICRH_UC2E1OBI 0x00000002 #define SICRH_UC2E2OBI 0x00000001 + +#elif defined(CONFIG_MPC832X) +/* SICRL bits - MPC832X specific */ +#define SICRL_LDP_LCS_A 0x80000000 +#define SICRL_IRQ_CKS 0x20000000 +#define SICRL_PCI_MSRC 0x10000000 +#define SICRL_URT_CTPR 0x06000000 +#define SICRL_IRQ_CTPR 0x00C00000 #endif /* SWCRR - System Watchdog Control Register @@ -270,7 +287,7 @@ #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) #define HRCWL_CEVCOD 0x000000C0 #define HRCWL_CEVCOD_SHIFT 6 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 @@ -718,7 +735,7 @@ #define BR_MS_UPMA 0x00000080 /* UPMA */ #define BR_MS_UPMB 0x000000A0 /* UPMB */ #define BR_MS_UPMC 0x000000C0 /* UPMC */ -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) #define BR_ATOM 0x0000000C #define BR_ATOM_SHIFT 2 #endif -- cgit v1.2.1 From 91e25769771c1164ed63ffca0add49f934ae3343 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Tue, 16 Jan 2007 11:38:14 -0500 Subject: mpc83xx: U-Boot support for Wind River SBC8349 I've redone the SBC8349 support to match git-current, which incorporates all the MPC834x updates from Freescale since the 1.1.6 release, including the DDR changes. I've kept all the SBC8349 files as parallel as possible to the MPC8349EMDS ones for ease of maintenance and to allow for easy inspection of what was changed to support this board. Hence the SBC8349 U-Boot has FDT support and everything else that the MPC8349EMDS has. Fortunately the Freescale updates added support for boards using CS0, but I had to change spd_sdram.c to allow for board specific settings for the sdram_clk_cntl (it is/was hard coded to zero, and that remains the default if the board doesn't specify a value.) Hopefully this should be mergeable as-is and require no whitespace cleanups or similar, but if something doesn't measure up then let me know and I'll fix it. Thanks, Paul. --- include/configs/sbc8349.h | 744 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 744 insertions(+) create mode 100644 include/configs/sbc8349.h (limited to 'include') diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h new file mode 100644 index 0000000000..2e6685d90b --- /dev/null +++ b/include/configs/sbc8349.h @@ -0,0 +1,744 @@ +/* + * WindRiver SBC8349 U-Boot configuration file. + * Copyright (c) 2006, 2007 Wind River Systems, Inc. + * + * Paul Gortmaker + * Based on the MPC8349EMDS config. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * sbc8349 board configuration file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC834X 1 /* MPC834X family */ +#define CONFIG_MPC8349 1 /* MPC8349 specific */ +#define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ + +#undef CONFIG_PCI +/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ +#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ + +#define PCI_66M +#ifdef PCI_66M +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#ifdef PCI_66M +#define CONFIG_SYS_CLK_FREQ 66000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 +#else +#define CONFIG_SYS_CLK_FREQ 33000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 +#endif +#endif + +#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK)) +#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */ +#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */ +#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */ +#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */ +#define CFG_SCCR_VAL ( CFG_SCCR_INIT \ + | CFG_SCCR_TSEC1CM \ + | CFG_SCCR_TSEC2CM \ + | CFG_SCCR_ENCCM \ + | CFG_SCCR_USBCM ) + +#undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +#define CFG_IMMR 0xE0000000 + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 /* memtest region */ +#define CFG_MEMTEST_END 0x00100000 + +/* + * DDR Setup + */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ +#define CFG_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ + +/* + * 32-bit data path mode. + * + * Please note that using this mode for devices with the real density of 64-bit + * effectively reduces the amount of available memory due to the effect of + * wrapping around while translating address to row/columns, for example in the + * 256MB module the upper 128MB get aliased with contents of the lower + * 128MB); normally this define should be used for devices with real 32-bit + * data path. + */ +#undef CONFIG_DDR_32BIT + +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) +#define CONFIG_DDR_2T_TIMING + +#if defined(CONFIG_SPD_EEPROM) +/* + * Determine DDR configuration from I2C interface. + */ +#define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ + +#else +/* + * Manually set up DDR parameters + * NB: manual DDR setup untested on sbc834x + */ +#define CFG_DDR_SIZE 256 /* MB */ +#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) +#define CFG_DDR_TIMING_1 0x36332321 +#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ + +#if defined(CONFIG_DDR_32BIT) +/* set burst length to 8 for 32-bit data path */ +#define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ +#else +/* the default burst length is 4 - for 64-bit data path */ +#define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ +#endif +#endif + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFF800000 /* start of FLASH */ +#define CFG_FLASH_SIZE 8 /* flash size in MB */ +/* #define CFG_FLASH_USE_BUFFER_WRITE */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ + BR_V) /* valid */ + +#define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MID_FLASH_JUMP 0x7F000000 +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + * LCRR: DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CFG_LBC_LBCR 0x00000000 + +#undef CFG_LB_SDRAM /* if board has SDRAM on local bus */ + +#ifdef CFG_LB_SDRAM +/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 + * + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ +#define CFG_LBLAWBAR2_PRELIM 0xF0000000 +#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 + */ + +#define CFG_OR2_PRELIM 0xFC006901 + +#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ + | CFG_LBC_LSDMR_BSMA1516 \ + | CFG_LBC_LSDMR_RFCR8 \ + | CFG_LBC_LSDMR_PRETOACT6 \ + | CFG_LBC_LSDMR_ACTTORW3 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC3 \ + | CFG_LBC_LSDMR_CL3 \ + ) + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) +#endif + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8349@0" +#define OF_SOC "soc8349@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ +#define CFG_I2C1_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 +#define CFG_I2C_OFFSET CFG_I2C2_OFFSET +/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ + +/* TSEC */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MMIO_BASE 0x90000000 +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xE2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CFG_PCI2_MEM_BASE 0xA0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_MMIO_BASE 0xB0000000 +#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE +#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xE2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + +#define PCI_64BIT +#define PCI_ONE_PCI1 +#if defined(PCI_64BIT) +#undef PCI_ALL_PCI1 +#undef PCI_TWO_PCI1 +#undef PCI_ONE_PCI1 +#endif + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0xFIXME +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + +/* + * TSEC configuration + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ + +#if defined(CONFIG_TSEC_ENET) +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MPC83XX_TSEC1 1 +#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC83XX_TSEC2 1 +#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_PHY_BCM5421S 1 +#define TSEC1_PHY_ADDR 0x19 +#define TSEC2_PHY_ADDR 0x1a +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#endif +#else +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + ) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII \ + ) +#endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#if 1 /*528/264*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X2 |\ + HRCWL_CORE_TO_CSB_2X1) +#elif 0 /*396/132*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_3X1) +#elif 0 /*264/132*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_2X1) +#elif 0 /*132/132*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_1X1) +#elif 0 /*264/264 */ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_1X1) +#endif + +#if defined(PCI_64BIT) +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#endif + +/* System IO Config */ +#define CFG_SICRH SICRH_TSOBI1 +#define CFG_SICRL SICRL_LDP_A + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK + +/* #define CFG_HID0_FINAL (\ + HID0_ENABLE_INSTRUCTION_CACHE |\ + HID0_ENABLE_M_BIT |\ + HID0_ENABLE_ADDRESS_BROADCAST ) */ + + +#define CFG_HID2 HID2_HBE + +/* DDR @ 0x00000000 */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#ifdef CONFIG_PCI +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT1L (0) +#define CFG_IBAT1U (0) +#define CFG_IBAT2L (0) +#define CFG_IBAT2U (0) +#endif + +#ifdef CONFIG_MPC83XX_PCI2 +#define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT3L (0) +#define CFG_IBAT3U (0) +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) +#endif + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:a0:1e:a0:13:8d +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e +#endif + +#define CONFIG_IPADDR 192.168.1.234 + +#define CONFIG_HOSTNAME SBC8349 +#define CONFIG_ROOTPATH /tftpboot/rootfs +#define CONFIG_BOOTFILE uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=sbc8349\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ + "update=protect off fff00000 fff3ffff; " \ + "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ + "upd=run load;run update\0" \ + "fdtaddr=400000\0" \ + "fdtfile=sbc8349.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#endif /* __CONFIG_H */ -- cgit v1.2.1 From 3e78a31cfe3d3022f46f67eb88e1281d5cc2eb89 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 30 Jan 2007 14:08:30 -0600 Subject: mpc83xx: Replace CONFIG_MPC8349 and use CONFIG_MPC834X instead The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all MPC834X class processors. Change the protections from CONFIG_MPC8349 to CONFIG_MPC834X so they are more generic. Signed-off-by: Kumar Gala --- include/asm-ppc/global_data.h | 4 ++-- include/asm-ppc/immap_83xx.h | 2 +- include/mpc83xx.h | 14 +++++++------- 3 files changed, 10 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 8bc61b63a8..c113b7ee0e 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -52,12 +52,12 @@ typedef struct global_data { #if defined(CONFIG_MPC83XX) /* There are other clocks in the MPC83XX */ u32 csb_clk; -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) u32 tsec1_clk; u32 tsec2_clk; u32 usbmph_clk; u32 usbdr_clk; -#endif /* CONFIG_MPC8349 */ +#endif /* CONFIG_MPC834X */ u32 core_clk; u32 i2c1_clk; u32 i2c2_clk; diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 77a079f44e..5e088d67d2 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -544,7 +544,7 @@ typedef struct security83xx { u8 fixme[0x10000]; } security83xx_t; -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 52e4369151..c1c6ad1e71 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -96,7 +96,7 @@ #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ #define SPCR_COREPR_SHIFT (31-11) -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) /* SPCR bits - MPC8349 specific */ #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ #define SPCR_TSEC1DP_SHIFT (31-19) @@ -114,7 +114,7 @@ /* SICRL/H - System I/O Configuration Register Low/High */ -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) /* SICRL bits - MPC8349 specific */ #define SICRL_LDP_A 0x80000000 #define SICRL_USB1 0x40000000 @@ -340,7 +340,7 @@ #define HRCWH_PCI_HOST_SHIFT 31 #define HRCWH_PCI_AGENT 0x00000000 -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) #define HRCWH_32_BIT_PCI 0x00000000 #define HRCWH_64_BIT_PCI 0x40000000 #endif @@ -351,7 +351,7 @@ #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 @@ -375,14 +375,14 @@ #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 #define HRCWH_ROM_LOC_PCI1 0x00100000 -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) #define HRCWH_ROM_LOC_PCI2 0x00200000 #endif #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) #define HRCWH_TSEC1M_IN_RGMII 0x00000000 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 #define HRCWH_TSEC1M_IN_GMII 0x00008000 @@ -742,7 +742,7 @@ #define BR_V 0x00000001 #define BR_V_SHIFT 0 -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) #elif defined(CONFIG_MPC8360) #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) -- cgit v1.2.1 From 6752ed088c75c26a89b70c46b7326a4cd6015f29 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Tue, 30 Jan 2007 16:15:04 -0600 Subject: mpc83xx: make 8360 default environment fdt be 8360 (not 8349) make 8360 default environment fdt be 8360 (not 8349) --- include/configs/MPC8360EMDS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 8ad6551de7..fd61ea51ab 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -609,7 +609,7 @@ "ramdiskaddr=1000000\0" \ "ramdiskfile=ramfs.83xx\0" \ "fdtaddr=400000\0" \ - "fdtfile=mpc8349emds.dtb\0" \ + "fdtfile=mpc8360emds.dtb\0" \ "" #define CONFIG_NFSBOOTCOMMAND \ -- cgit v1.2.1 From a87c856eb411b9365937d0d4b9c21e46adbe1c14 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Fri, 19 Jan 2007 10:43:26 +0800 Subject: mpc83xx: Fix the LAW1/3 bug The patch solves the alignment problem of the local bus access windows to render accessible the memory bank and PHY registers of UPC 1 (starting at 0xf801 0000). What we actually did was to adjust the sizes of the bus access windows so that the base address alignment requirement would be met. Signed-off-by: Chereji Marian Signed-off-by: Gridish Shlomi Signed-off-by: Dave Liu --- include/configs/MPC8360EMDS.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index fd61ea51ab..d613618f5c 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -188,7 +188,7 @@ */ #define CFG_BCSR 0xF8000000 #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ -#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ +#define CFG_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */ #define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ #define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ @@ -278,8 +278,8 @@ /* * Windows to access PIB via local bus */ -#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ -#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ +#define CFG_LBLAWBAR3_PRELIM 0xf8010000 /* windows base 0xf8010000 */ +#define CFG_LBLAWAR3_PRELIM 0x8000000e /* windows size 32KB */ /* * CS4 on Local Bus, to PIB -- cgit v1.2.1 From 7a78f148d6a7298e4fface680dc7eacd877b1aba Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Wed, 31 Jan 2007 15:54:29 -0600 Subject: mpc83xx: Add support for the MPC8349E-mITX-GP Add support for the MPC8349E-mITX-GP, a stripped-down version of the MPC8349E-mITX. Bonus features include support for low-boot (BMS bit in HRCW is 0) for the ITX and a README for the ITX and the ITX-GP. Signed-off-by: Timur Tabi --- include/configs/MPC8349ITX.h | 459 +++++++++++++++++-------------------------- include/mpc83xx.h | 41 ++++ 2 files changed, 220 insertions(+), 280 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index cbdbb2921d..37bbfb336d 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -21,7 +21,7 @@ */ /* - MPC8349E-mITX board configuration file + MPC8349E-mITX and MPC8349E-mITX-GP board configuration file Memory map: @@ -31,11 +31,11 @@ 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) - 0xF000_0000-0xF000_FFFF Compact Flash + 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 0xF001_0000-0xF001_FFFF Local bus expansion slot - 0xF800_0000-0xF801_FFFF GBE L2 Switch VSC7385 - 0xFF00_0000-0xFF7F_FFFF Alternative bank of Flash memory (8MB) - 0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB) + 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) + 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory + 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) I2C address list: Align. Board @@ -56,7 +56,9 @@ #ifndef __CONFIG_H #define __CONFIG_H -#undef DEBUG +#if (TEXT_BASE == 0xFE000000) +#define CFG_LOWBOOT +#endif /* * High Level Configuration Options @@ -64,14 +66,26 @@ #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ #define CONFIG_MPC8349 /* MPC8349 specific */ -#define CONFIG_PCI +#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ + + +/* On-board devices */ +#ifdef CONFIG_MPC8349ITX #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ -#define CONFIG_RTC_DS1337 +#define CONFIG_VSC7385 /* The Vitesse 7385 5-port switch */ +#endif -/* I2C */ +#define CONFIG_PCI +#define CONFIG_RTC_DS1337 #define CONFIG_HARD_I2C +#define CONFIG_TSEC_ENET /* TSEC Ethernet support */ +/* + * Device configurations + */ + +/* I2C */ #ifdef CONFIG_HARD_I2C #define CONFIG_MISC_INIT_F @@ -111,59 +125,40 @@ #endif -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE +/* Compact Flash */ +#ifdef CONFIG_COMPACT_FLASH -#define PCI_66M -#ifdef PCI_66M -#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#endif +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 1 -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef PCI_66M -#define CONFIG_SYS_CLK_FREQ 66666666 -#else -#define CONFIG_SYS_CLK_FREQ 33333333 -#endif -#endif +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_BASE_ADDR CFG_CF_BASE +#define CFG_ATA_DATA_OFFSET 0x0000 +#define CFG_ATA_REG_OFFSET 0 +#define CFG_ATA_ALT_OFFSET 0x0200 +#define CFG_ATA_STRIDE 2 -#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ +#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00003000 /* memtest region */ -#define CFG_MEMTEST_END 0x07100000 /* only has 128M */ +#define CONFIG_DOS_PARTITION -/* - * DDR Setup - */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ +#endif /* - * 32-bit data path mode. - * - * Please note that using this mode for devices with the real density of 64-bit - * effectively reduces the amount of available memory due to the effect of - * wrapping around while translating address to row/columns, for example in the - * 256MB module the upper 128MB get aliased with contents of the lower - * 128MB); normally this define should be used for devices with real 32-bit - * data path. + * DDR Setup */ -#undef CONFIG_DDR_32BIT - -#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_BASE -#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE -#undef CONFIG_DDR_2T_TIMING +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE #define CFG_83XX_DDR_USES_CS0 +#define CFG_MEMTEST_START 0x1000 /* memtest region */ +#define CFG_MEMTEST_END 0x2000 -#ifndef CONFIG_SPD_EEPROM -/* - * Manually set up DDR parameters - */ +#ifdef CONFIG_HARD_I2C +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ +#endif + +#ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ #define CFG_DDR_SIZE 256 /* Mb */ #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) @@ -171,46 +166,65 @@ #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ #endif -/* FLASH on the Local Bus */ +/* + *Flash on the Local Bus + */ + #define CFG_FLASH_CFI /* use the Common Flash Interface */ #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CFG_FLASH_SIZE 16 /* FLASH size in MB */ #define CFG_FLASH_EMPTY_INFO +#define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +/* The ITX has two flash chips, but the ITX-GP has only one. To support both +boards, we say we have two, but don't display a message if we find only one. */ +#define CFG_FLASH_QUIET_TEST +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} +#define CFG_FLASH_SIZE 16 /* FLASH size in MB */ +#define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ + +/* + * BRx, ORx, LBLAWBARx, and LBLAWARx + */ + +/* Flash */ #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) -#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ -#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16Mb window bytes */ +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE +#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) -/* VSC7385 on the Local Bus */ -#define CFG_VSC7385_BASE 0xF8000000 /* start of VSC7385 */ +/* Vitesse 7385 */ -#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) -#define CFG_OR1_PRELIM (0xFFFE0000 /* 128KB */ | \ - OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ - OR_GPCM_SETA | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +#ifdef CONFIG_VSC7385 -#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE /* Access window base at VSC7385 base */ -#define CFG_LBLAWAR1_PRELIM 0x80000010 /* Access window size 128K */ +#define CFG_VSC7385_BASE 0xF8000000 -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 135 /* sectors per device */ +#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) +#define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ + OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ + OR_GPCM_EHTR | OR_GPCM_EAD) -#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} +#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE +#define CFG_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#endif -#define CFG_LED_BASE 0xF9000000 /* start of LED and Board ID */ +/* LED */ + +#define CFG_LED_BASE 0xF9000000 #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) -#define CFG_OR2_PRELIM (0xFFE00000 /* 2MB */ | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | \ - OR_GPCM_SCY_9 | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ + OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ + OR_GPCM_EHTR | OR_GPCM_EAD) + +/* Compact Flash */ #ifdef CONFIG_COMPACT_FLASH @@ -219,32 +233,16 @@ #define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) #define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) -#define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */ -#define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */ - -#undef CONFIG_IDE_RESET -#undef CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 -#define CFG_IDE_MAXDEVICE 1 - -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_BASE_ADDR CFG_CF_BASE -#define CFG_ATA_DATA_OFFSET 0x0000 -#define CFG_ATA_REG_OFFSET 0 -#define CFG_ATA_ALT_OFFSET 0x0200 -#define CFG_ATA_STRIDE 2 - -#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ +#define CFG_LBLAWBAR3_PRELIM CFG_CF_BASE +#define CFG_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) #endif -#define CONFIG_DOS_PARTITION - -#define CFG_MID_FLASH_JUMP 0x7F000000 +/* + * U-Boot memory configuration + */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT #else @@ -253,10 +251,10 @@ #define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK -#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ -#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -272,97 +270,9 @@ #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) #define CFG_LBC_LBCR 0x00000000 -#undef CFG_LB_SDRAM /* if board has SRDAM on local bus */ - -#ifdef CFG_LB_SDRAM -/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - */ - -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CFG_LBLAWBAR2_PRELIM 0xF0000000 -#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ - -#define CFG_BR2_PRELIM (CFG_LBC_SDRAM_BASE | BR_PS_32 | BR_MS_SDRAM | BR_V) -#define CFG_OR2_PRELIM (0xFC000000 /* 64 MB */ | \ - OR_SDRAM_XAM | \ - ((9 - 7) << OR_SDRAM_COLS_SHIFT) | \ - ((13 - 9) << OR_SDRAM_ROWS_SHIFT) | \ - OR_SDRAM_EAD) - #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ - | CFG_LBC_LSDMR_BSMA1516 \ - | CFG_LBC_LSDMR_RFCR8 \ - | CFG_LBC_LSDMR_PRETOACT6 \ - | CFG_LBC_LSDMR_ACTTORW3 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC3 \ - | CFG_LBC_LSDMR_CL3 \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) -#endif - /* * Serial Port */ @@ -374,20 +284,16 @@ #define CFG_NS16550_CLK get_bus_freq(0) #define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_BAUDRATE 115200 #define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_FLAT_TREE +#define CONFIG_OF_BOARD_SETUP /* maximum size of the flat tree (8K) */ #define OF_FLAT_TREE_MAX_SIZE 8192 @@ -397,6 +303,9 @@ #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" +/* + * PCI + */ #ifdef CONFIG_PCI #define CONFIG_MPC83XX_PCI2 @@ -447,14 +356,18 @@ #endif +#define PCI_66M +#ifdef PCI_66M +#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#endif + /* TSEC */ #ifdef CONFIG_TSEC_ENET -#ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI -#endif - #define CONFIG_MII #define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ @@ -468,6 +381,7 @@ #endif #ifdef CONFIG_MPC83XX_TSEC2 +#define CONFIG_HAS_ETH1 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" #define CFG_TSEC2_OFFSET 0x25000 #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ @@ -479,14 +393,15 @@ #endif - /* * Environment */ +#define CONFIG_ENV_OVERWRITE + #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE)) #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH /* Flash is not usable now */ @@ -533,16 +448,23 @@ /* Watchdog */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#ifdef CONFIG_WATCHDOG -#define CFG_WATCHDOG_VALUE 0xFFFFFFC3 -#endif /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CFG_HUSH_PARSER /* Use the HUSH parser */ +#define CFG_PROMPT_HUSH_PS2 "> " + #define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#ifdef CONFIG_MPC8349ITX +#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ +#endif #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -562,15 +484,15 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ +/* + * Cache Configuration + */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ #endif -#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - #define CFG_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ HRCWL_DDR_TO_SCB_CLK_1X1 |\ @@ -578,12 +500,12 @@ HRCWL_VCO_1X2 |\ HRCWL_CORE_TO_CSB_2X1) -#ifdef PCI_64BIT +#ifdef CFG_LOWBOOT #define CFG_HRCW_HIGH (\ HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ + HRCWH_32_BIT_PCI |\ HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ HRCWH_CORE_ENABLE |\ HRCWH_FROM_0X00000100 |\ HRCWH_BOOTSEQ_DISABLE |\ @@ -596,7 +518,7 @@ HRCWH_PCI_HOST |\ HRCWH_32_BIT_PCI |\ HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ HRCWH_CORE_ENABLE |\ HRCWH_FROM_0XFFF00100 |\ HRCWH_BOOTSEQ_DISABLE |\ @@ -606,30 +528,32 @@ HRCWH_TSEC2M_IN_GMII ) #endif -/* System performance */ +/* + * System performance + */ #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ #define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ -#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */ -/* System IO Config */ +/* + * System IO Config + */ #define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ #define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) -#define CFG_HID0_INIT 0x000000000 - -#define CFG_HID0_FINAL CFG_HID0_INIT +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 HID2_HBE -/* DDR @ 0x00000000 */ +/* DDR */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -/* PCI @ 0x80000000 */ +/* PCI */ #ifdef CONFIG_PCI #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) @@ -706,97 +630,72 @@ #endif #ifdef CONFIG_MPC83XX_TSEC2 -#define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 #endif -#if 1 -#define CONFIG_IPADDR 10.82.19.159 -#define CONFIG_SERVERIP 10.82.48.106 -#define CONFIG_GATEWAYIP 10.82.19.254 -#define CONFIG_NETMASK 255.255.252.0 -#define CONFIG_NETDEV eth0 - -#define CONFIG_HOSTNAME mpc8349emitx -#define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs -#define CONFIG_BOOTFILE timur/uImage - -#define CONFIG_UBOOTPATH timur/u-boot.bin -#else #define CONFIG_IPADDR 192.168.1.253 #define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.252.0 #define CONFIG_NETDEV eth0 +#ifdef CONFIG_MPC8349ITX #define CONFIG_HOSTNAME mpc8349emitx -#define CONFIG_ROOTPATH /nfsroot/rootfs -#define CONFIG_BOOTFILE uImage - -#define CONFIG_UBOOTPATH u-boot.bin +#else +#define CONFIG_HOSTNAME mpc8349emitxgp #endif -#define CONFIG_UBOOTSTART fe700000 -#define CONFIG_UBOOTEND fe77ffff - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BAUDRATE 115200 +/* Default path and filenames */ +#define CONFIG_ROOTPATH /nfsroot/rootfs +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTDELAY 6 +#ifdef CONFIG_MPC8349ITX +#define CONFIG_FDTFILE mpc8349emitx.dtb #else -#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ +#define CONFIG_FDTFILE mpc8349emitxgp.dtb #endif +#define CONFIG_BOOTDELAY 0 + #define XMK_STR(x) #x #define MK_STR(x) XMK_STR(x) #define CONFIG_BOOTARGS \ "root=/dev/nfs rw" \ " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ - " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ + " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ " console=ttyS0," MK_STR(CONFIG_BAUDRATE) #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ - "tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ - "erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ - "cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \ - "cmp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize\0" \ - "tftpupdate=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ - "protect off FEF00000 FEF7FFFF; " \ - "erase FEF00000 FEF7FFFF; " \ - "cp.b $loadaddr FEF00000 $filesize; " \ - "protect on FEF00000 FEF7FFFF; " \ - "cmp.b $loadaddr FEF00000 $filesize\0" \ - "tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \ - "copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ - "cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "fdtaddr=400000\0" \ - "fdtfile=mpc8349emitx.dtb\0" \ - "" + "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" #define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" + "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ + " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + " console=$console,$baudrate $othbootargs; " \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - + "setenv bootargs root=/dev/ram rw" \ + " console=$console,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #undef MK_STR #undef XMK_STR diff --git a/include/mpc83xx.h b/include/mpc83xx.h index c1c6ad1e71..1b62f81293 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -825,6 +825,47 @@ #define OR_SDRAM_EAD 0x00000001 #define OR_SDRAM_EAD_SHIFT 0 +#define OR_AM_32KB 0xFFFF8000 +#define OR_AM_64KB 0xFFFF0000 +#define OR_AM_128KB 0xFFFE0000 +#define OR_AM_256KB 0xFFFC0000 +#define OR_AM_512KB 0xFFF80000 +#define OR_AM_1MB 0xFFF00000 +#define OR_AM_2MB 0xFFE00000 +#define OR_AM_4MB 0xFFC00000 +#define OR_AM_8MB 0xFF800000 +#define OR_AM_16MB 0xFF000000 +#define OR_AM_32MB 0xFE000000 +#define OR_AM_64MB 0xFC000000 +#define OR_AM_128MB 0xF8000000 +#define OR_AM_256MB 0xF0000000 +#define OR_AM_512MB 0xE0000000 +#define OR_AM_1GB 0xC0000000 +#define OR_AM_2GB 0x80000000 +#define OR_AM_4GB 0x00000000 + +#define LBLAWAR_EN 0x80000000 +#define LBLAWAR_4KB 0x0000000B +#define LBLAWAR_8KB 0x0000000C +#define LBLAWAR_16KB 0x0000000D +#define LBLAWAR_32KB 0x0000000E +#define LBLAWAR_64KB 0x0000000F +#define LBLAWAR_128KB 0x00000010 +#define LBLAWAR_256KB 0x00000011 +#define LBLAWAR_512KB 0x00000012 +#define LBLAWAR_1MB 0x00000013 +#define LBLAWAR_2MB 0x00000014 +#define LBLAWAR_4MB 0x00000015 +#define LBLAWAR_8MB 0x00000016 +#define LBLAWAR_16MB 0x00000017 +#define LBLAWAR_32MB 0x00000018 +#define LBLAWAR_64MB 0x00000019 +#define LBLAWAR_128MB 0x0000001A +#define LBLAWAR_256MB 0x0000001B +#define LBLAWAR_512MB 0x0000001C +#define LBLAWAR_1GB 0x0000001D +#define LBLAWAR_2GB 0x0000001E + /* LBCR - Local Bus Configuration Register */ #define LBCR_LDIS 0x80000000 -- cgit v1.2.1 From 8d172c0f0d85998a256a95b7459a5403a30380ed Mon Sep 17 00:00:00 2001 From: Xie Xiaobo Date: Wed, 14 Feb 2007 18:26:44 +0800 Subject: mpc83xx: Add the cpu and board specific code for MPC8349E rev3.1 MDS MPC8349E rev3.1 have new spridr,and PVR value, The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM. Signed-off-by: Xie Xiaobo --- include/configs/MPC8349EMDS.h | 44 +++++++++++++++++++++++++++++++++++-------- include/mpc83xx.h | 13 +++++++++++-- 2 files changed, 47 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 5bed2d0a29..861de72e28 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -82,7 +82,7 @@ /* * DDR Setup */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_ECC /* support DDR ECC function */ #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ @@ -101,8 +101,15 @@ #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_BASE #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING +/* + * DDRCDR - DDR Control Driver Register + */ +#define CFG_DDRCDR_VALUE 0x80080001 + #if defined(CONFIG_SPD_EEPROM) /* * Determine DDR configuration from I2C interface. @@ -113,6 +120,21 @@ * Manually set up DDR parameters */ #define CFG_DDR_SIZE 256 /* MB */ +#if defined(CONFIG_DDR_II) +#define CFG_DDRCDR 0x80080001 +#define CFG_DDR_CS2_BNDS 0x0000000f +#define CFG_DDR_CS2_CONFIG 0x80330102 +#define CFG_DDR_TIMING_0 0x00220802 +#define CFG_DDR_TIMING_1 0x38357322 +#define CFG_DDR_TIMING_2 0x2f9048c8 +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_CLK_CNTL 0x02000000 +#define CFG_DDR_MODE 0x47d00432 +#define CFG_DDR_MODE2 0x8000c000 +#define CFG_DDR_INTERVAL 0x03cf0080 +#define CFG_DDR_SDRAM_CFG 0x43000000 +#define CFG_DDR_SDRAM_CFG2 0x00401000 +#else #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) #define CFG_DDR_TIMING_1 0x36332321 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ @@ -127,6 +149,7 @@ #define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ #endif #endif +#endif /* * SDRAM on the Local Bus @@ -140,19 +163,20 @@ #define CFG_FLASH_CFI /* use the Common Flash Interface */ #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CFG_FLASH_SIZE 8 /* flash size in MB */ +#define CFG_FLASH_SIZE 32 /* max flash size in MB */ /* #define CFG_FLASH_USE_BUFFER_WRITE */ #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ - -#define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ -#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ +#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ +#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ @@ -197,7 +221,11 @@ #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) #define CFG_LBC_LBCR 0x00000000 -#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ +/* + * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. + * if board has SRDAM on local bus, you can define CFG_LB_SDRAM + */ +#undef CFG_LB_SDRAM #ifdef CFG_LB_SDRAM /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 1b62f81293..73f2721619 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -68,6 +68,15 @@ #define SPR_8343E_REV11 0x80360101 #define SPR_8343_REV11 0x80370101 +#define SPR_8349E_REV31 0x80300300 +#define SPR_8349_REV31 0x80310300 +#define SPR_8347E_REV31_TBGA 0x80320300 +#define SPR_8347_REV31_TBGA 0x80330300 +#define SPR_8347E_REV31_PBGA 0x80340300 +#define SPR_8347_REV31_PBGA 0x80350300 +#define SPR_8343E_REV31 0x80360300 +#define SPR_8343_REV31 0x80370300 + #define SPR_8360E_REV10 0x80480010 #define SPR_8360_REV10 0x80490010 #define SPR_8360E_REV11 0x80480011 @@ -573,8 +582,8 @@ /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 */ -#define TIMING_CFG2_CPO 0x0F000000 -#define TIMING_CFG2_CPO_SHIFT 24 +#define TIMING_CFG2_CPO 0x0F800000 +#define TIMING_CFG2_CPO_SHIFT 23 #define TIMING_CFG2_ACSM 0x00080000 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 -- cgit v1.2.1 From b110f40bd180c6b560276589beedf753e97c46ce Mon Sep 17 00:00:00 2001 From: Xie Xiaobo Date: Wed, 14 Feb 2007 18:27:06 +0800 Subject: mpc83xx: Add the cpu specific code for MPC8360E rev2.0 MDS MPC8360E rev2.0 have new spridr,and PVR value, The MDS board for MPC8360E rev2.0 has 32M bytes Flash and 256M DDR2 DIMM. Signed-off-by: Xie Xiaobo --- include/configs/MPC8360EMDS.h | 33 +++++++++++++++++++++++++++++---- include/mpc83xx.h | 2 ++ 2 files changed, 31 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index d613618f5c..3ad00c127d 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -100,12 +100,19 @@ #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ #define CFG_SDRAM_BASE CFG_DDR_BASE #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #define CFG_83XX_DDR_USES_CS0 -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_ECC /* support DDR ECC function */ #define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ +/* + * DDRCDR - DDR Control Driver Register + */ +#define CFG_DDRCDR_VALUE 0x80080001 + #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #if defined(CONFIG_SPD_EEPROM) /* @@ -117,6 +124,21 @@ * Manually set up DDR parameters */ #define CFG_DDR_SIZE 256 /* MB */ +#if defined(CONFIG_DDR_II) +#define CFG_DDRCDR 0x80080001 +#define CFG_DDR_CS0_BNDS 0x0000000f +#define CFG_DDR_CS0_CONFIG 0x80330102 +#define CFG_DDR_TIMING_0 0x00220802 +#define CFG_DDR_TIMING_1 0x38357322 +#define CFG_DDR_TIMING_2 0x2f9048c8 +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_CLK_CNTL 0x02000000 +#define CFG_DDR_MODE 0x47d00432 +#define CFG_DDR_MODE2 0x8000c000 +#define CFG_DDR_INTERVAL 0x03cf0080 +#define CFG_DDR_SDRAM_CFG 0x43000000 +#define CFG_DDR_SDRAM_CFG2 0x00401000 +#else #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) #define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ #define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */ @@ -124,6 +146,7 @@ #define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ #define CFG_DDR_INTERVAL 0x045b0100 /* page mode */ #endif +#endif /* * Memory test @@ -168,7 +191,7 @@ #define CFG_FLASH_CFI /* use the Common Flash Interface */ #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ +#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ @@ -176,10 +199,12 @@ #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ -#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ +#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ #undef CFG_FLASH_CHECKSUM diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 73f2721619..33f02ef07d 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -83,6 +83,8 @@ #define SPR_8360_REV11 0x80490011 #define SPR_8360E_REV12 0x80480012 #define SPR_8360_REV12 0x80490012 +#define SPR_8360E_REV20 0x80480020 +#define SPR_8360_REV20 0x80490020 #define SPR_8323E_REV10 0x80620010 #define SPR_8323_REV10 0x80630010 -- cgit v1.2.1 From 22d71a71f57fd5d38b27ac3848e50d790360a598 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Tue, 27 Feb 2007 18:41:08 -0600 Subject: mpc83xx: add command line editing by default --- include/configs/MPC832XEMDS.h | 1 + include/configs/MPC8349EMDS.h | 1 + include/configs/MPC8360EMDS.h | 1 + include/configs/sbc8349.h | 1 + 4 files changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index b8bf00f861..1155cbd4af 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -307,6 +307,7 @@ #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ /* Use the HUSH parser */ #define CFG_HUSH_PARSER #ifdef CFG_HUSH_PARSER diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 861de72e28..a6d82b98f3 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -342,6 +342,7 @@ #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ /* Use the HUSH parser */ #define CFG_HUSH_PARSER #ifdef CFG_HUSH_PARSER diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 3ad00c127d..ef4871bb69 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -334,6 +334,7 @@ #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ /* Use the HUSH parser */ #define CFG_HUSH_PARSER #ifdef CFG_HUSH_PARSER diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 2e6685d90b..62606b302d 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -313,6 +313,7 @@ #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ /* Use the HUSH parser */ #define CFG_HUSH_PARSER #ifdef CFG_HUSH_PARSER -- cgit v1.2.1 From d51b3cf371cd441030460ef19d36b2924c361b1a Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Thu, 22 Feb 2007 20:06:57 -0600 Subject: mpc83xx: update [local-]mac-address properties on UEC based devices 8360 and 832x weren't updating their [local-]mac-address properties. This patch fixes that. Signed-off-by: Kim Phillips --- include/configs/MPC832XEMDS.h | 1 + include/configs/MPC8360EMDS.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 1155cbd4af..cecb2258ff 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -323,6 +323,7 @@ #define OF_CPU "PowerPC,8323@0" #define OF_SOC "soc8323@e0000000" +#define OF_QE "qe@e0100000" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500" diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index ef4871bb69..d2af0e1dfc 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -350,6 +350,7 @@ #define OF_CPU "PowerPC,8360@0" #define OF_SOC "soc8360@e0000000" +#define OF_QE "qe@e0100000" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc8360@e0000000/serial@4500" -- cgit v1.2.1 From 4feab4de7bfc2cb2fed36ad76f93c3a69659bbaf Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 27 Feb 2007 23:51:42 -0600 Subject: mpc83xx: Fix config of Arbiter, System Priority, and Clock Mode The config value for: * CFG_ACR_PIPE_DEP * CFG_ACR_RPTCNT * CFG_SPCR_TSEC1EP * CFG_SPCR_TSEC2EP * CFG_SCCR_TSEC1CM * CFG_SCCR_TSEC2CM Were not being used when setting the appropriate register Added: * CFG_SCCR_USBMPHCM * CFG_SCCR_USBDRCM * CFG_SCCR_PCICM * CFG_SCCR_ENCCM To allow full config of the SCCR. Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349 that were just bogus. Signed-off-by: Kumar Gala --- include/configs/MPC8349EMDS.h | 11 ----------- include/configs/TQM834x.h | 11 ----------- include/configs/sbc8349.h | 11 ----------- include/mpc83xx.h | 9 ++------- 4 files changed, 2 insertions(+), 40 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index a6d82b98f3..0460be9e56 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -60,17 +60,6 @@ #endif #endif -#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK)) -#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */ -#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */ -#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */ -#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */ -#define CFG_SCCR_VAL ( CFG_SCCR_INIT \ - | CFG_SCCR_TSEC1CM \ - | CFG_SCCR_TSEC2CM \ - | CFG_SCCR_ENCCM \ - | CFG_SCCR_USBCM ) - #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ #define CFG_IMMR 0xE0000000 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 728083b304..ed0357791b 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -57,17 +57,6 @@ */ #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) -#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK)) -#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */ -#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */ -#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */ -#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */ -#define CFG_SCCR_VAL ( CFG_SCCR_INIT \ - | CFG_SCCR_TSEC1CM \ - | CFG_SCCR_TSEC2CM \ - | CFG_SCCR_ENCCM \ - | CFG_SCCR_USBCM ) - /* board pre init: do not call, nothing to do */ #undef CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 62606b302d..65aac5cefd 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -63,17 +63,6 @@ #endif #endif -#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK)) -#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */ -#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */ -#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */ -#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */ -#define CFG_SCCR_VAL ( CFG_SCCR_INIT \ - | CFG_SCCR_TSEC1CM \ - | CFG_SCCR_TSEC2CM \ - | CFG_SCCR_ENCCM \ - | CFG_SCCR_USBCM ) - #undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ #define CFG_IMMR 0xE0000000 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 33f02ef07d..c2a4ff5877 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -509,6 +509,7 @@ #define SCCR_PCICM_SHIFT 16 /* SCCR bits - MPC8349 specific */ +#ifdef CONFIG_MPC834X #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 #define SCCR_TSEC1CM_0 0x00000000 @@ -522,6 +523,7 @@ #define SCCR_TSEC2CM_1 0x10000000 #define SCCR_TSEC2CM_2 0x20000000 #define SCCR_TSEC2CM_3 0x30000000 +#endif #define SCCR_USBMPHCM 0x00c00000 #define SCCR_USBMPHCM_SHIFT 22 @@ -533,13 +535,6 @@ #define SCCR_USBCM_2 0x00A00000 #define SCCR_USBCM_3 0x00F00000 -#define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \ - | SCCR_TSEC2CM_3 \ - | SCCR_ENCCM_3 \ - | SCCR_USBCM_3 ) - -#define SCCR_DEFAULT 0xFFFFFFFF - /* CSn_BDNS - Chip Select memory Bounds Register */ #define CSBNDS_SA 0x00FF0000 -- cgit v1.2.1 From 647d3c3eed0da1d1505eecabe0b0fab96f956e68 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 4 Mar 2007 01:36:05 +0100 Subject: Some code cleanup. --- include/configs/mpc7448hpc2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index eb528dfaf4..243a3f6c8f 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -285,7 +285,7 @@ /* PCI view of System Memory */ #define CFG_PCI_MEMORY_BUS 0x00000000 #define CFG_PCI_MEMORY_PHYS 0x00000000 -#define CFG_PCI_MEMORY_SIZE 0x80000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 /* PCI Memory Space */ #define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS) -- cgit v1.2.1 From 07b7b0037aac5102939917d7cbe561b5c0d5aa44 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 6 Mar 2007 07:47:04 +0100 Subject: [PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setup As provided by the AMCC applications team, this patch optimizes the DDR2 setup for 166MHz bus speed. The values provided are also save to use on a "normal" 133MHz PLB bus system. Only the refresh counter setup has to be adjusted as done in this patch. For this the NAND booting version had to include the "speed.c" file from the cpu/ppc4xx directory. With this addition the NAND SPL image will just fit into the 4kbytes of program space. gcc version 4.x as provided with ELDK 4.x is needed to generate this optimized code. Signed-off-by: Stefan Roese --- include/ppc440.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/ppc440.h b/include/ppc440.h index 1c7f11c488..25e338fb10 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -3293,26 +3293,26 @@ typedef struct { unsigned long add; /* gpio core base address */ /* * Macros for accessing the indirect EBC registers */ -#define mtebc(reg, data) { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); } -#define mfebc(reg, data) { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); } +#define mtebc(reg, data) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); } while (0) +#define mfebc(reg, data) do { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); } while (0) /* * Macros for accessing the indirect SDRAM controller registers */ -#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } -#define mfsdram(reg, data) { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } +#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0) +#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0) /* * Macros for accessing the indirect clocking controller registers */ -#define mtclk(reg, data) { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); } -#define mfclk(reg, data) { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); } +#define mtclk(reg, data) do { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); } while (0) +#define mfclk(reg, data) do { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); } while (0) /* * Macros for accessing the sdr controller registers */ -#define mtsdr(reg, data) { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } -#define mfsdr(reg, data) { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } +#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0) +#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0) #ifndef __ASSEMBLY__ -- cgit v1.2.1 From 8d7e2732221bc2d64df14f700c64c23e0a4c3dce Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 7 Mar 2007 16:19:46 +0100 Subject: HMI1001: fix build error, cleanup compiler warnings. --- include/configs/hmi1001.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index cfaf153223..095b5f6dc2 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -210,6 +210,7 @@ */ #define CONFIG_MPC5xxx_FEC 1 #define CONFIG_PHY_ADDR 0x00 +#define CONFIG_MII 1 /* MII PHY management */ /* * GPIO configuration -- cgit v1.2.1 From fa1aef15bcd47736687be1af544506e90fba545d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 7 Mar 2007 16:43:00 +0100 Subject: [PATCH] Use dynamic SDRAM TLB setup on AMCC Ocotea eval board Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the DDR memory are dynamically programmed matching the total size of the equipped memory (DIMM modules). Signed-off-by: Stefan Roese --- include/configs/ocotea.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 0e3660ba2d..fe4e63810e 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -148,8 +148,9 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ #define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ +#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/ /*----------------------------------------------------------------------- * I2C -- cgit v1.2.1 From df294497479b1dca6dd86318b2a912f72fede0df Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 8 Mar 2007 10:06:09 +0100 Subject: ppc4xx: Update 440SP/440SPe DDR SPD setup code to support 440SP Signed-off-by: Stefan Roese --- include/ppc440.h | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/ppc440.h b/include/ppc440.h index 1c7f11c488..5fe407626b 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -417,7 +417,9 @@ #define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */ #define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */ #define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */ +#endif /* CONFIG_440SPE */ +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) /*----------------------------------------------------------------------------+ | SDRAM Controller +----------------------------------------------------------------------------*/ @@ -453,9 +455,16 @@ /*-----------------------------------------------------------------------------+ | Memory Bank 0-7 configuration +-----------------------------------------------------------------------------*/ -#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */ +#if defined(CONFIG_440SPE) +#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2) +#endif /* CONFIG_440SPE */ +#if defined(CONFIG_440SP) +#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */ +#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFF800000)) +#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFF800000)) +#endif /* CONFIG_440SP */ #define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */ #define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6) #define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF) @@ -2167,6 +2176,20 @@ /*-----------------------------------------------------------------------------+ | SDR0 Bit Settings +-----------------------------------------------------------------------------*/ +#if defined(CONFIG_440SP) +#define SDR0_SRST 0x0200 + +#define SDR0_DDR0 0x00E1 +#define SDR0_DDR0_DPLLRST 0x80000000 +#define SDR0_DDR0_DDRM_MASK 0x60000000 +#define SDR0_DDR0_DDRM_DDR1 0x20000000 +#define SDR0_DDR0_DDRM_DDR2 0x40000000 +#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29) +#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03) +#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0) +#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) +#endif + #if defined(CONFIG_440SPE) #define SDR0_CP440 0x0180 #define SDR0_CP440_ERPN_MASK 0x30000000 -- cgit v1.2.1 From 2721a68a9ea91f1e494649ce68b2577261f578e2 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 8 Mar 2007 10:07:18 +0100 Subject: ppc4xx: Small AMCC Katmai 440SPe update Signed-off-by: Stefan Roese --- include/configs/katmai.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/katmai.h b/include/configs/katmai.h index f350155c83..1606d0da17 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -108,6 +108,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ #define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/ +#define CONFIG_DDR_ECC 1 /* with ECC support */ #undef CONFIG_STRESS /*----------------------------------------------------------------------- -- cgit v1.2.1 From 2f5df47351910a2936c7741cf111855829200943 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 8 Mar 2007 10:10:18 +0100 Subject: [PATCH] Update AMCC Yucca 440SPe eval board support The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. Signed-off-by: Stefan Roese --- include/configs/yucca.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 6417ed891d..eb4859c3e9 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -45,11 +45,11 @@ #define EXTCLK_50 50000000 #define EXTCLK_83 83333333 -#define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ #undef CONFIG_SHOW_BOOT_PROGRESS #undef CONFIG_STRESS -#undef ENABLE_ECC + /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) @@ -118,10 +118,9 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses */ -#define IIC0_DIMM0_ADDR 0x53 -#define IIC0_DIMM1_ADDR 0x52 +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ +#undef CONFIG_DDR_ECC /* no ECC support for now */ /*----------------------------------------------------------------------- * I2C @@ -211,6 +210,7 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include +#define CONFIG_IBM_EMAC4_V4 1 #define CONFIG_MII 1 /* MII PHY management */ #undef CONFIG_NET_MULTI #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ -- cgit v1.2.1 From 00cdb4ce5e1b42248e7e6522ad0da3421b988afa Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 8 Mar 2007 10:13:16 +0100 Subject: [PATCH] Update AMCC Luan 440SP eval board support The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese --- include/configs/luan.h | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/include/configs/luan.h b/include/configs/luan.h index 5c9d208feb..9c8769b200 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -37,8 +37,9 @@ #define CONFIG_440 1 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -132,10 +133,9 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* SPD EEPROM init doesn't support DDR2 */ -#define SPD_EEPROM_ADDRESS {0x52,0x53} /* I2C SPD addresses */ -#define IIC0_DIMM0_ADDR 0x52 -#define IIC0_DIMM1_ADDR 0x53 +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ +#undef CONFIG_DDR_ECC /* no ECC support for now */ /*----------------------------------------------------------------------- * I2C @@ -206,11 +206,6 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_NET_MULTI /* needed for NetConsole */ -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - #ifdef DEBUG #define CONFIG_PANIC_HANG #else @@ -219,9 +214,7 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ - CFG_CMD_CACHE | \ CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ CFG_CMD_ELF | \ CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ @@ -232,7 +225,6 @@ CFG_CMD_PCI | \ CFG_CMD_PING | \ CFG_CMD_REGINFO | \ - CFG_CMD_SETGETDCR | \ CFG_CMD_SDRAM | \ 0) -- cgit v1.2.1 From 769104c9356594deb2092e204a39c05b33202d6c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 8 Mar 2007 21:49:27 +0100 Subject: Minor cleanup --- include/configs/jupiter.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 0a6dba6721..48056a3a16 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -58,7 +58,7 @@ * 0x40000000 - 0x4fffffff - PCI Memory * 0x50000000 - 0x50ffffff - PCI IO Space */ -//#define CONFIG_PCI +/*#define CONFIG_PCI */ #if defined(CONFIG_PCI) #define CONFIG_PCI_PNP 1 -- cgit v1.2.1 From f9fc6a5852a6335840882fa2111925010eea1abe Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Wed, 7 Mar 2007 15:32:01 +0100 Subject: fixed ethernet phy configuration for plu405 board Signed-off-by: Matthias Fuchs --- include/configs/PLU405.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index dd5d831680..d02c39b28f 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -51,17 +51,13 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#if 0 /* test-only */ #define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY1_ADDR 1 /* PHY address */ -#else -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#endif #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ -- cgit v1.2.1 From d8a8ea5c476d37006fc7f85b7f903142795c8b14 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Thu, 8 Mar 2007 16:20:32 +0100 Subject: [PATCH] I2C: Add missing default CFG_SPD_BUS_NUM Signed-off-by: Matthias Fuchs --- include/i2c.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/i2c.h b/include/i2c.h index d31c72d247..6e6c845312 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -63,6 +63,9 @@ #if !defined(CFG_DTT_BUS_NUM) #define CFG_DTT_BUS_NUM 0 #endif +#if !defined(CFG_SPD_BUS_NUM) +#define CFG_SPD_BUS_NUM 0 +#endif /* * Initialization, must be called once on start up, may be called -- cgit v1.2.1 From 3f0606ad0b5639f7f22848fe5b4574e754d0470f Mon Sep 17 00:00:00 2001 From: "Aubrey.Li" Date: Fri, 9 Mar 2007 13:38:44 +0800 Subject: [Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform support --- include/asm-blackfin/arch-bf533/anomaly.h | 172 +++ include/asm-blackfin/arch-bf533/bf533_serial.h | 78 ++ include/asm-blackfin/arch-bf533/bf5xx_rtc.h | 46 + include/asm-blackfin/arch-bf533/cdefBF531.h | 24 + include/asm-blackfin/arch-bf533/cdefBF532.h | 398 +++++++ include/asm-blackfin/arch-bf533/cdefBF533.h | 24 + include/asm-blackfin/arch-bf533/cplbtab.h | 482 ++++++++ include/asm-blackfin/arch-bf533/defBF531.h | 24 + include/asm-blackfin/arch-bf533/defBF532.h | 1159 ++++++++++++++++++++ include/asm-blackfin/arch-bf533/defBF533.h | 24 + include/asm-blackfin/arch-bf533/defBF533_extn.h | 77 ++ include/asm-blackfin/arch-bf533/irq.h | 137 +++ include/asm-blackfin/arch-common/bf53x_rtc.h | 46 + include/asm-blackfin/arch-common/cdefBF5xx.h | 40 + include/asm-blackfin/arch-common/cdef_LPBlackfin.h | 177 +++ include/asm-blackfin/arch-common/def_LPBlackfin.h | 445 ++++++++ include/asm-blackfin/bitops.h | 42 +- include/asm-blackfin/blackfin.h | 20 +- include/asm-blackfin/cplb.h | 38 +- include/asm-blackfin/cplbtab.h | 572 ---------- include/asm-blackfin/cpu/bf533_irq.h | 137 --- include/asm-blackfin/cpu/bf533_rtc.h | 46 - include/asm-blackfin/cpu/bf533_serial.h | 79 -- include/asm-blackfin/cpu/cdefBF531.h | 24 - include/asm-blackfin/cpu/cdefBF532.h | 398 ------- include/asm-blackfin/cpu/cdefBF533.h | 24 - include/asm-blackfin/cpu/cdefBF53x.h | 32 - include/asm-blackfin/cpu/cdef_LPBlackfin.h | 185 ---- include/asm-blackfin/cpu/defBF531.h | 24 - include/asm-blackfin/cpu/defBF532.h | 1159 -------------------- include/asm-blackfin/cpu/defBF533.h | 24 - include/asm-blackfin/cpu/defBF533_extn.h | 76 -- include/asm-blackfin/cpu/def_LPBlackfin.h | 445 -------- include/asm-blackfin/delay.h | 6 +- include/asm-blackfin/entry.h | 6 +- include/asm-blackfin/global_data.h | 13 +- include/asm-blackfin/hw_irq.h | 10 +- include/asm-blackfin/io-kernel.h | 9 +- include/asm-blackfin/io.h | 15 +- include/asm-blackfin/irq.h | 6 +- include/asm-blackfin/machdep.h | 3 +- include/asm-blackfin/mem_init.h | 38 +- include/asm-blackfin/page.h | 5 - include/asm-blackfin/processor.h | 3 +- include/asm-blackfin/setup.h | 3 +- include/asm-blackfin/string.h | 9 +- include/asm-blackfin/u-boot.h | 2 +- include/asm-blackfin/uaccess.h | 10 +- include/configs/bf533-ezkit.h | 228 ++++ include/configs/bf533-stamp.h | 475 ++++++++ include/configs/ezkit533.h | 188 ---- include/configs/stamp.h | 333 ------ 52 files changed, 4207 insertions(+), 3833 deletions(-) create mode 100644 include/asm-blackfin/arch-bf533/anomaly.h create mode 100644 include/asm-blackfin/arch-bf533/bf533_serial.h create mode 100644 include/asm-blackfin/arch-bf533/bf5xx_rtc.h create mode 100644 include/asm-blackfin/arch-bf533/cdefBF531.h create mode 100644 include/asm-blackfin/arch-bf533/cdefBF532.h create mode 100644 include/asm-blackfin/arch-bf533/cdefBF533.h create mode 100644 include/asm-blackfin/arch-bf533/cplbtab.h create mode 100644 include/asm-blackfin/arch-bf533/defBF531.h create mode 100644 include/asm-blackfin/arch-bf533/defBF532.h create mode 100644 include/asm-blackfin/arch-bf533/defBF533.h create mode 100644 include/asm-blackfin/arch-bf533/defBF533_extn.h create mode 100644 include/asm-blackfin/arch-bf533/irq.h create mode 100644 include/asm-blackfin/arch-common/bf53x_rtc.h create mode 100644 include/asm-blackfin/arch-common/cdefBF5xx.h create mode 100644 include/asm-blackfin/arch-common/cdef_LPBlackfin.h create mode 100644 include/asm-blackfin/arch-common/def_LPBlackfin.h delete mode 100644 include/asm-blackfin/cplbtab.h delete mode 100644 include/asm-blackfin/cpu/bf533_irq.h delete mode 100644 include/asm-blackfin/cpu/bf533_rtc.h delete mode 100644 include/asm-blackfin/cpu/bf533_serial.h delete mode 100644 include/asm-blackfin/cpu/cdefBF531.h delete mode 100644 include/asm-blackfin/cpu/cdefBF532.h delete mode 100644 include/asm-blackfin/cpu/cdefBF533.h delete mode 100644 include/asm-blackfin/cpu/cdefBF53x.h delete mode 100644 include/asm-blackfin/cpu/cdef_LPBlackfin.h delete mode 100644 include/asm-blackfin/cpu/defBF531.h delete mode 100644 include/asm-blackfin/cpu/defBF532.h delete mode 100644 include/asm-blackfin/cpu/defBF533.h delete mode 100644 include/asm-blackfin/cpu/defBF533_extn.h delete mode 100644 include/asm-blackfin/cpu/def_LPBlackfin.h create mode 100644 include/configs/bf533-ezkit.h create mode 100644 include/configs/bf533-stamp.h delete mode 100644 include/configs/ezkit533.h delete mode 100644 include/configs/stamp.h (limited to 'include') diff --git a/include/asm-blackfin/arch-bf533/anomaly.h b/include/asm-blackfin/arch-bf533/anomaly.h new file mode 100644 index 0000000000..0e5f919438 --- /dev/null +++ b/include/asm-blackfin/arch-bf533/anomaly.h @@ -0,0 +1,172 @@ +/* + * File: include/asm-blackfin/arch-bf533/anomaly.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* This file shoule be up to date with: + * - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List + * - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List + * - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List + */ + +#ifndef _MACH_ANOMALY_H_ +#define _MACH_ANOMALY_H_ + +/* We do not support 0.1 or 0.2 silicon - sorry */ +#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2)) +#error Kernel will not work on BF533 Version 0.1 or 0.2 +#endif + +/* Issues that are common to 0.5, 0.4, and 0.3 silicon */ +#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) +#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in + slot1 and store of a P register in slot 2 is not + supported */ +#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on + every corresponding match */ +#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive + Channel DMA stops */ +#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR + registers. */ +#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out + upper bits*/ +#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ +#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame + syncs */ +#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not + functional */ +#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable + state */ +#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */ +#define ANOMALY_05000272 /* Certain data cache write through modes fail for + VDDint <=0.9V */ +#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */ +#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after + an edge is detected may clear interrupt */ +#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause + DMA system instability */ +#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is + not restored */ +#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic + control */ +#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when + killed in a particular stage*/ +#endif + +/* These issues only occur on 0.3 or 0.4 BF533 */ +#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) +#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not + updated at the same time. */ +#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data + Cache Fill can be corrupted after or during + Instruction DMA if certain core stalls exist */ +#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General + Purpose TX or RX modes */ +#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by + preceding memory read */ +#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during + inactive channels in certain conditions */ +#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag + situation */ +#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */ +#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */ +#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect + data*/ +#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate + Differences in certain Conditions */ +#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */ +#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to + hardware reset */ +#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or + IDLE around a Change of Control causes + unpredictable results */ +#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the + shadow of a conditional branch */ +#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware + errors */ +#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ +#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event + interrupt not functional */ +#define ANOMALY_05000257 /* An interrupt or exception during short Hardware + loops may cause the instruction fetch unit to + malfunction */ +#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of + the ICPLB Data registers differ */ +#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ +#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ +#define ANOMALY_05000262 /* Stores to data cache may be lost */ +#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */ +#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE + instruction will cause an infinite stall in the + second to last instruction in a hardware loop */ +#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on + SPORT external receive and transmit clocks. */ +#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the + internal voltage regulator (VDDint) to increase. */ +#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the + internal voltage regulator (VDDint) to decrease */ +#endif + +/* These issues are only on 0.4 silicon */ +#if (defined(CONFIG_BF_REV_0_4)) +#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */ +#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel + (TDM) */ +#endif + +/* These issues are only on 0.3 silicon */ +#if defined(CONFIG_BF_REV_0_3) +#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with + External Frame Syncs */ +#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative + Instruction or Data Fetches, or by Fetches at the + boundary of reserved memory space */ +#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs + when polarity setting is changed */ +#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data + corruption */ +#define ANOMALY_05000199 /* DMA current address shows wrong value during carry + fix */ +#define ANOMALY_05000201 /* Receive frame sync not ignored during active + frames in sport MCM */ +#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA + stopping */ +#if defined(CONFIG_BF533) +#define ANOMALY_05000204 /* Incorrect data read with write-through cache and + allocate cache lines on reads only mode */ +#endif /* CONFIG_BF533 */ +#define ANOMALY_05000207 /* Recovery from "brown-out" condition */ +#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain + instructions */ +#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame + Sync Transmit Mode */ +#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */ +#endif + +#endif /* _MACH_ANOMALY_H_ */ diff --git a/include/asm-blackfin/arch-bf533/bf533_serial.h b/include/asm-blackfin/arch-bf533/bf533_serial.h new file mode 100644 index 0000000000..ce58863b10 --- /dev/null +++ b/include/asm-blackfin/arch-bf533/bf533_serial.h @@ -0,0 +1,78 @@ +/* + * U-boot bf533_serial.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BF533_SERIAL_H_ +#define _BF533_SERIAL_H_ + +#define BYTE_REF(addr) (*((volatile char*)addr)) +#define HALFWORD_REF(addr) (*((volatile short*)addr)) +#define WORD_REF(addr) (*((volatile long*)addr)) + +#define UART_THR_LO HALFWORD_REF(UART_THR) +#define UART_RBR_LO HALFWORD_REF(UART_RBR) +#define UART_DLL_LO HALFWORD_REF(UART_DLL) +#define UART_IER_LO HALFWORD_REF(UART_IER) +#define UART_IER_ERBFI 0x01 +#define UART_IER_ETBEI 0x02 +#define UART_IER_ELSI 0x04 +#define UART_IER_EDDSI 0x08 + +#define UART_DLH_LO HALFWORD_REF(UART_DLH) +#define UART_IIR_LO HALFWORD_REF(UART_IIR) +#define UART_IIR_NOINT 0x01 +#define UART_IIR_STATUS 0x06 +#define UART_IIR_LSR 0x06 +#define UART_IIR_RBR 0x04 +#define UART_IIR_THR 0x02 +#define UART_IIR_MSR 0x00 + +#define UART_LCR_LO HALFWORD_REF(UART_LCR) +#define UART_LCR_WLS5 0 +#define UART_LCR_WLS6 0x01 +#define UART_LCR_WLS7 0x02 +#define UART_LCR_WLS8 0x03 +#define UART_LCR_STB 0x04 +#define UART_LCR_PEN 0x08 +#define UART_LCR_EPS 0x10 +#define UART_LCR_SP 0x20 +#define UART_LCR_SB 0x40 +#define UART_LCR_DLAB 0x80 + +#define UART_MCR_LO HALFWORD_REF(UART_MCR) + +#define UART_LSR_LO HALFWORD_REF(UART_LSR) +#define UART_LSR_DR 0x01 +#define UART_LSR_OE 0x02 +#define UART_LSR_PE 0x04 +#define UART_LSR_FE 0x08 +#define UART_LSR_BI 0x10 +#define UART_LSR_THRE 0x20 +#define UART_LSR_TEMT 0x40 + +#define UART_MSR_LO HALFWORD_REF(UART_MSR) +#define UART_SCR_LO HALFWORD_REF(UART_SCR) +#define UART_GCTL_LO HALFWORD_REF(UART_GCTL) +#define UART_GCTL_UCEN 0x01 + +#endif diff --git a/include/asm-blackfin/arch-bf533/bf5xx_rtc.h b/include/asm-blackfin/arch-bf533/bf5xx_rtc.h new file mode 100644 index 0000000000..bc09922a5e --- /dev/null +++ b/include/asm-blackfin/arch-bf533/bf5xx_rtc.h @@ -0,0 +1,46 @@ +/* + * U-boot - bf533_rtc.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BF533_RTC_H_ +#define _BF533_RTC_H_ + +void rtc_init(void); +void wait_for_complete(void); +void rtc_reset(void); + +#define MIN_TO_SECS(_x_) (60 * _x_) +#define HRS_TO_SECS(_x_) (60 * 60 * _x_) +#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_) + +#define NUM_SECS_IN_DAY (24 * 3600) +#define NUM_SECS_IN_HOUR (3600) +#define NUM_SECS_IN_MIN (60) + +/* Shift values for RTC_STAT register */ +#define DAY_BITS_OFF 17 +#define HOUR_BITS_OFF 12 +#define MIN_BITS_OFF 6 +#define SEC_BITS_OFF 0 + +#endif diff --git a/include/asm-blackfin/arch-bf533/cdefBF531.h b/include/asm-blackfin/arch-bf533/cdefBF531.h new file mode 100644 index 0000000000..3877db89e2 --- /dev/null +++ b/include/asm-blackfin/arch-bf533/cdefBF531.h @@ -0,0 +1,24 @@ +/* + * cdefBF531.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _CDEFBF531_H +#define _CDEFBF531_H + +#include + +#endif /* _CDEFBF531_H */ diff --git a/include/asm-blackfin/arch-bf533/cdefBF532.h b/include/asm-blackfin/arch-bf533/cdefBF532.h new file mode 100644 index 0000000000..bca1ed1ac1 --- /dev/null +++ b/include/asm-blackfin/arch-bf533/cdefBF532.h @@ -0,0 +1,398 @@ +/* + * cdefBF532.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _CDEF_BF532_H +#define _CDEF_BF532_H + +/* + * #if !defined(__ADSPLPBLACKFIN__) + * #warning cdefBF532.h should only be included for 532 compatible chips. + * #endif + */ + +/* include all Core registers and bit definitions */ +#include + +/* include core specific register pointer definitions */ +#include + +/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ +#define pPLL_CTL ((volatile unsigned short *)PLL_CTL) +#define pPLL_STAT ((volatile unsigned short *)PLL_STAT) +#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT) +#define pCHIPID ((volatile unsigned long *)CHIPID) +#define pSWRST ((volatile unsigned short *)SWRST) +#define pSYSCR ((volatile unsigned short *)SYSCR) +#define pPLL_DIV ((volatile unsigned short *)PLL_DIV) +#define pVR_CTL ((volatile unsigned short *)VR_CTL) + +/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ +#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0) +#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1) +#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2) +#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3) +#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK) +#define pSIC_ISR ((volatile unsigned long *)SIC_ISR) +#define pSIC_IWR ((volatile unsigned long *)SIC_IWR) + +/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */ +#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL) +#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT) +#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT) + +/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */ +#define pRTC_STAT ((volatile unsigned long *)RTC_STAT) +#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL) +#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT) +#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT) +#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM) +#define pRTC_FAST ((volatile unsigned short *)RTC_FAST) +#define pRTC_PREN ((volatile unsigned short *)RTC_PREN) + +/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ +#define pFIO_DIR ((volatile unsigned short *)FIO_DIR) +#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C) +#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S) +#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C) +#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S) +#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C) +#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S) +#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR) +#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE) +#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH) +#define pFIO_INEN ((volatile unsigned short *)FIO_INEN) +#define pFIO_FLAG_D ((volatile unsigned short *)FIO_FLAG_D) +#define pFIO_FLAG_T ((volatile unsigned short *)FIO_FLAG_T) +#define pFIO_MASKA_D ((volatile unsigned short *)FIO_MASKA_D) +#define pFIO_MASKA_T ((volatile unsigned short *)FIO_MASKA_T) +#define pFIO_MASKB_D ((volatile unsigned short *)FIO_MASKB_D) +#define pFIO_MASKB_T ((volatile unsigned short *)FIO_MASKB_T) + +/* DMA Test Registers */ +#define pDMA_CCOMP ((volatile unsigned long *)DMA_CCOMP) +#define pDMA_ACOMP ((volatile unsigned long *)DMA_ACOMP) +#define pDMA_MISR ((volatile unsigned long *)DMA_MISR) +#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER) +#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT) +#define pDMA_TMODE ((volatile unsigned short *)DMA_TMODE) +#define pDMA_TMCHAN ((volatile unsigned short *)DMA_TMCHAN) +#define pDMA_TMSTAT ((volatile unsigned short *)DMA_TMSTAT) +#define pDMA_TMBD ((volatile unsigned short *)DMA_TMBD) +#define pDMA_TMM0D ((volatile unsigned short *)DMA_TMM0D) +#define pDMA_TMM1D ((volatile unsigned short *)DMA_TMM1D) +#define pDMA_TMMA ((volatile void **)DMA_TMMA) + +/* DMA Controller */ +#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG) +#define pDMA0_NEXT_DESC_PTR ((volatile void **)DMA0_NEXT_DESC_PTR) +#define pDMA0_START_ADDR ((volatile void **)DMA0_START_ADDR) +#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT) +#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT) +#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY) +#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY) +#define pDMA0_CURR_DESC_PTR ((volatile void **)DMA0_CURR_DESC_PTR) +#define pDMA0_CURR_ADDR ((volatile void **)DMA0_CURR_ADDR) +#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT) +#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT) +#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS) +#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP) + +#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG) +#define pDMA1_NEXT_DESC_PTR ((volatile void **)DMA1_NEXT_DESC_PTR) +#define pDMA1_START_ADDR ((volatile void **)DMA1_START_ADDR) +#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT) +#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT) +#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY) +#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY) +#define pDMA1_CURR_DESC_PTR ((volatile void **)DMA1_CURR_DESC_PTR) +#define pDMA1_CURR_ADDR ((volatile void **)DMA1_CURR_ADDR) +#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT) +#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT) +#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS) +#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP) + +#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG) +#define pDMA2_NEXT_DESC_PTR ((volatile void **)DMA2_NEXT_DESC_PTR) +#define pDMA2_START_ADDR ((volatile void **)DMA2_START_ADDR) +#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT) +#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT) +#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY) +#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY) +#define pDMA2_CURR_DESC_PTR ((volatile void **)DMA2_CURR_DESC_PTR) +#define pDMA2_CURR_ADDR ((volatile void **)DMA2_CURR_ADDR) +#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT) +#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT) +#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS) +#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP) + +#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG) +#define pDMA3_NEXT_DESC_PTR ((volatile void **)DMA3_NEXT_DESC_PTR) +#define pDMA3_START_ADDR ((volatile void **)DMA3_START_ADDR) +#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT) +#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT) +#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY) +#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY) +#define pDMA3_CURR_DESC_PTR ((volatile void **)DMA3_CURR_DESC_PTR) +#define pDMA3_CURR_ADDR ((volatile void **)DMA3_CURR_ADDR) +#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT) +#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT) +#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS) +#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP) + +#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG) +#define pDMA4_NEXT_DESC_PTR ((volatile void **)DMA4_NEXT_DESC_PTR) +#define pDMA4_START_ADDR ((volatile void **)DMA4_START_ADDR) +#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT) +#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT) +#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY) +#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY) +#define pDMA4_CURR_DESC_PTR ((volatile void **)DMA4_CURR_DESC_PTR) +#define pDMA4_CURR_ADDR ((volatile void **)DMA4_CURR_ADDR) +#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT) +#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT) +#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS) +#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP) + +#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG) +#define pDMA5_NEXT_DESC_PTR ((volatile void **)DMA5_NEXT_DESC_PTR) +#define pDMA5_START_ADDR ((volatile void **)DMA5_START_ADDR) +#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT) +#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT) +#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY) +#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY) +#define pDMA5_CURR_DESC_PTR ((volatile void **)DMA5_CURR_DESC_PTR) +#define pDMA5_CURR_ADDR ((volatile void **)DMA5_CURR_ADDR) +#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT) +#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT) +#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS) +#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP) + +#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG) +#define pDMA6_NEXT_DESC_PTR ((volatile void **)DMA6_NEXT_DESC_PTR) +#define pDMA6_START_ADDR ((volatile void **)DMA6_START_ADDR) +#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT) +#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT) +#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY) +#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY) +#define pDMA6_CURR_DESC_PTR ((volatile void **)DMA6_CURR_DESC_PTR) +#define pDMA6_CURR_ADDR ((volatile void **)DMA6_CURR_ADDR) +#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT) +#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT) +#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS) +#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP) + +#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG) +#define pDMA7_NEXT_DESC_PTR ((volatile void **)DMA7_NEXT_DESC_PTR) +#define pDMA7_START_ADDR ((volatile void **)DMA7_START_ADDR) +#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT) +#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT) +#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY) +#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY) +#define pDMA7_CURR_DESC_PTR ((volatile void **)DMA7_CURR_DESC_PTR) +#define pDMA7_CURR_ADDR ((volatile void **)DMA7_CURR_ADDR) +#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT) +#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT) +#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS) +#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP) + +#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG) +#define pMDMA_D1_NEXT_DESC_PTR ((volatile void **)MDMA_D1_NEXT_DESC_PTR) +#define pMDMA_D1_START_ADDR ((volatile void **)MDMA_D1_START_ADDR) +#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT) +#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT) +#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY) +#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY) +#define pMDMA_D1_CURR_DESC_PTR ((volatile void **)MDMA_D1_CURR_DESC_PTR) +#define pMDMA_D1_CURR_ADDR ((volatile void **)MDMA_D1_CURR_ADDR) +#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT) +#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT) +#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS) +#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP) + +#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG) +#define pMDMA_S1_NEXT_DESC_PTR ((volatile void **)MDMA_S1_NEXT_DESC_PTR) +#define pMDMA_S1_START_ADDR ((volatile void **)MDMA_S1_START_ADDR) +#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT) +#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT) +#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY) +#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY) +#define pMDMA_S1_CURR_DESC_PTR ((volatile void **)MDMA_S1_CURR_DESC_PTR) +#define pMDMA_S1_CURR_ADDR ((volatile void **)MDMA_S1_CURR_ADDR) +#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT) +#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT) +#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS) +#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP) + +#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG) +#define pMDMA_D0_NEXT_DESC_PTR ((volatile void **)MDMA_D0_NEXT_DESC_PTR) +#define pMDMA_D0_START_ADDR ((volatile void **)MDMA_D0_START_ADDR) +#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT) +#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT) +#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY) +#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY) +#define pMDMA_D0_CURR_DESC_PTR ((volatile void **)MDMA_D0_CURR_DESC_PTR) +#define pMDMA_D0_CURR_ADDR ((volatile void **)MDMA_D0_CURR_ADDR) +#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT) +#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT) +#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS) +#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP) + +#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG) +#define pMDMA_S0_NEXT_DESC_PTR ((volatile void **)MDMA_S0_NEXT_DESC_PTR) +#define pMDMA_S0_START_ADDR ((volatile void **)MDMA_S0_START_ADDR) +#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT) +#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT) +#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY) +#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY) +#define pMDMA_S0_CURR_DESC_PTR ((volatile void **)MDMA_S0_CURR_DESC_PTR) +#define pMDMA_S0_CURR_ADDR ((volatile void **)MDMA_S0_CURR_ADDR) +#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT) +#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT) +#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS) +#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP) + +/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */ +#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL) +#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0) +#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1) + +/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */ +/* #define L1SBAR 0xFFC04840 */ /* L1 SRAM Base Address Register */ +/* #define L1CSR 0xFFC04844 */ /* L1 SRAM Control Initialization Register */ + +/* + * #define pDB_ACOMP ((volatile void **)DB_ACOMP) + * #define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP) + */ + +/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */ +#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL) +#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC) +#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT) +#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL) + +/* UART Controller */ +#define pUART_THR ((volatile unsigned short *)UART_THR) +#define pUART_RBR ((volatile unsigned short *)UART_RBR) +#define pUART_DLL ((volatile unsigned short *)UART_DLL) +#define pUART_IER ((volatile unsigned short *)UART_IER) +#define pUART_DLH ((volatile unsigned short *)UART_DLH) +#define pUART_IIR ((volatile unsigned short *)UART_IIR) +#define pUART_LCR ((volatile unsigned short *)UART_LCR) +#define pUART_MCR ((volatile unsigned short *)UART_MCR) +#define pUART_LSR ((volatile unsigned short *)UART_LSR) + +/* + * #define UART_MSR + */ +#define pUART_SCR ((volatile unsigned short *)UART_SCR) +#define pUART_GCTL ((volatile unsigned short *)UART_GCTL) + +/* SPI Controller */ +#define pSPI_CTL ((volatile unsigned short *)SPI_CTL) +#define pSPI_FLG ((volatile unsigned short *)SPI_FLG) +#define pSPI_STAT ((volatile unsigned short *)SPI_STAT) +#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR) +#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR) +#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD) +#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW) + +/* TIMER 0, 1, 2 Registers */ +#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG) +#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER) +#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD) +#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH) + +#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG) +#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER) +#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD) +#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH) + +#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG) +#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER) +#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD) +#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH) + +#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE) +#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE) +#define pTIMER_STATUS ((volatile unsigned short *)TIMER_STATUS) + +/* SPORT0 Controller */ +#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1) +#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2) +#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV) +#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV) +#define pSPORT0_TX ((volatile long *)SPORT0_TX) +#define pSPORT0_RX ((volatile long *)SPORT0_RX) +#define pSPORT0_TX32 ((volatile long *)SPORT0_TX) +#define pSPORT0_RX32 ((volatile long *)SPORT0_RX) +#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX) +#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX) +#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1) +#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2) +#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV) +#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV) +#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT) +#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL) +#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1) +#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2) +#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0) +#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1) +#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2) +#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3) +#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0) +#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1) +#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2) +#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3) + +/* SPORT1 Controller */ +#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1) +#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2) +#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV) +#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV) +#define pSPORT1_TX ((volatile long *)SPORT1_TX) +#define pSPORT1_RX ((volatile long *)SPORT1_RX) +#define pSPORT1_TX32 ((volatile long *)SPORT1_TX) +#define pSPORT1_RX32 ((volatile long *)SPORT1_RX) +#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX) +#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX) +#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1) +#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2) +#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV) +#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV) +#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT) +#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL) +#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1) +#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2) +#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0) +#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1) +#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2) +#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3) +#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0) +#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1) +#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2) +#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3) + +/* Parallel Peripheral Interface (PPI) */ +#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL) +#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS) +#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY) +#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT) +#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME) + +#endif /* _CDEF_BF532_H */ diff --git a/include/asm-blackfin/arch-bf533/cdefBF533.h b/include/asm-blackfin/arch-bf533/cdefBF533.h new file mode 100644 index 0000000000..c72bac91e0 --- /dev/null +++ b/include/asm-blackfin/arch-bf533/cdefBF533.h @@ -0,0 +1,24 @@ +/* + * cdefBF533.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _CDEFBF533_H +#define _CDEFBF533_H + +#include + +#endif /* _CDEFBF533_H */ diff --git a/include/asm-blackfin/arch-bf533/cplbtab.h b/include/asm-blackfin/arch-bf533/cplbtab.h new file mode 100644 index 0000000000..89f0325381 --- /dev/null +++ b/include/asm-blackfin/arch-bf533/cplbtab.h @@ -0,0 +1,482 @@ +/*This file is subject to the terms and conditions of the GNU General Public + * License. + * + * Blackfin BF533/2.6 support : LG Soft India + * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd + * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's + * shouldn't be victimized. cplbmgr.S search logic is corrected + * to findout the appropriate victim. + * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC + * : LG Soft India + */ +#include + +#ifndef __ARCH_BFINNOMMU_CPLBTAB_H +#define __ARCH_BFINNOMMU_CPLBTAB_H + +/************************************************************************* + * ICPLB TABLE + *************************************************************************/ + +.data +/* This table is configurable */ + .align 4; + +/* Data Attibutes*/ + +#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) + +/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ + +#define ANOMALY_05000158 0x200 +#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) +#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) + +#else /*Write Through */ +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) +#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) +#endif + +.align 4; +.global _ipdt_table _ipdt_table:.byte4 0x00000000; +.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */ +.byte4 0x00400000; +.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */ +.byte4 0x00800000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */ +.byte4 0x00C00000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */ +.byte4 0x01000000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */ +.byte4 0x01400000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */ +.byte4 0x01800000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */ +.byte4 0x01C00000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */ +#ifndef CONFIG_EZKIT /*STAMP Memory regions */ +.byte4 0x02000000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */ +.byte4 0x02400000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */ +.byte4 0x02800000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */ +.byte4 0x02C00000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */ +.byte4 0x03000000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */ +.byte4 0x03400000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */ +.byte4 0x03800000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */ +.byte4 0x03C00000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */ +#endif +.byte4 0x20000000; +.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */ + +#ifdef CONFIG_STAMP +.byte4 0x04000000; +.byte4(SDRAM_IGENERIC); +.byte4 0x04400000; +.byte4(SDRAM_IGENERIC); +.byte4 0x04800000; +.byte4(SDRAM_IGENERIC); +.byte4 0x04C00000; +.byte4(SDRAM_IGENERIC); +.byte4 0x05000000; +.byte4(SDRAM_IGENERIC); +.byte4 0x05400000; +.byte4(SDRAM_IGENERIC); +.byte4 0x05800000; +.byte4(SDRAM_IGENERIC); +.byte4 0x05C00000; +.byte4(SDRAM_IGENERIC); +.byte4 0x06000000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page25 */ +.byte4 0x06400000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page26 */ +.byte4 0x06800000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page27 */ +.byte4 0x06C00000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page28 */ +.byte4 0x07000000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page29 */ +.byte4 0x07400000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page30 */ +.byte4 0x07800000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page31 */ +.byte4 0x07C00000; +.byte4(SDRAM_IKERNEL); /*SDRAM_Page32 */ +#endif +.byte4 0xffffffff; /* end of section - termination */ + +/********************************************************************** + * PAGE DESCRIPTOR TABLE + * + **********************************************************************/ + +/* Till here we are discussing about the static memory management model. + * However, the operating envoronments commonly define more CPLB + * descriptors to cover the entire addressable memory than will fit into + * the available on-chip 16 CPLB MMRs. When this happens, the below table + * will be used which will hold all the potentially required CPLB descriptors + * + * This is how Page descriptor Table is implemented in uClinux/Blackfin. + */ +.global _dpdt_table _dpdt_table:.byte4 0x00000000; +.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */ +.byte4 0x00400000; +.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */ +.byte4 0x00800000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */ +.byte4 0x00C00000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */ +.byte4 0x01000000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */ +.byte4 0x01400000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */ +.byte4 0x01800000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */ +.byte4 0x01C00000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */ + +#ifndef CONFIG_EZKIT +.byte4 0x02000000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */ +.byte4 0x02400000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */ +.byte4 0x02800000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */ +.byte4 0x02C00000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */ +.byte4 0x03000000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */ +.byte4 0x03400000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */ +.byte4 0x03800000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */ +.byte4 0x03C00000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */ +#endif + +#ifdef CONFIG_STAMP +.byte4 0x04000000; +.byte4(SDRAM_DGENERIC); +.byte4 0x04400000; +.byte4(SDRAM_DGENERIC); +.byte4 0x04800000; +.byte4(SDRAM_DGENERIC); +.byte4 0x04C00000; +.byte4(SDRAM_DGENERIC); +.byte4 0x05000000; +.byte4(SDRAM_DGENERIC); +.byte4 0x05400000; +.byte4(SDRAM_DGENERIC); +.byte4 0x05800000; +.byte4(SDRAM_DGENERIC); +.byte4 0x05C00000; +.byte4(SDRAM_DGENERIC); +.byte4 0x06000000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page25 */ +.byte4 0x06400000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page26 */ +.byte4 0x06800000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page27 */ +.byte4 0x06C00000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page28 */ +.byte4 0x07000000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page29 */ +.byte4 0x07400000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page30 */ +.byte4 0x07800000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page31 */ +.byte4 0x07C00000; +.byte4(SDRAM_DKERNEL); /*SDRAM_Page32 */ +#endif + +.byte4 0x20000000; +.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */ + +#if (BFIN_CPU == ADSP_BF533) +.byte4 0xFF800000; +.byte4(L1_DMEMORY); +.byte4 0xFF801000; +.byte4(L1_DMEMORY); +.byte4 0xFF802000; +.byte4(L1_DMEMORY); +.byte4 0xFF803000; +.byte4(L1_DMEMORY); +#endif +.byte4 0xFF804000; +.byte4(L1_DMEMORY); +.byte4 0xFF805000; +.byte4(L1_DMEMORY); +.byte4 0xFF806000; +.byte4(L1_DMEMORY); +.byte4 0xFF807000; +.byte4(L1_DMEMORY); +#if (BFIN_CPU == ADSP_BF533) +.byte4 0xFF900000; +.byte4(L1_DMEMORY); +.byte4 0xFF901000; +.byte4(L1_DMEMORY); +.byte4 0xFF902000; +.byte4(L1_DMEMORY); +.byte4 0xFF903000; +.byte4(L1_DMEMORY); +#endif +#if ((BFIN_CPU == ADSP_BF532) || (BFIN_CPU == ADSP_BF533)) +.byte4 0xFF904000; +.byte4(L1_DMEMORY); +.byte4 0xFF905000; +.byte4(L1_DMEMORY); +.byte4 0xFF906000; +.byte4(L1_DMEMORY); +.byte4 0xFF907000; +.byte4(L1_DMEMORY); +#endif +.byte4 0xFFB00000; +.byte4(L1_DMEMORY); + +.byte4 0xffffffff; /*end of section - termination */ + +#ifdef CONFIG_CPLB_INFO +.global _ipdt_swapcount_table; /* swapin count first, then swapout count */ +_ipdt_swapcount_table: +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 10 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 20 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 30 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 40 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 50 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 60 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 70 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 80 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 90 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 100 */ + +.global _dpdt_swapcount_table; /* swapin count first, then swapout count */ +_dpdt_swapcount_table: +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 10 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 20 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 30 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 40 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 50 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 60 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 70 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 80 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 80 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 100 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 110 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 120 */ +#endif + +#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/ diff --git a/include/asm-blackfin/arch-bf533/defBF531.h b/include/asm-blackfin/arch-bf533/defBF531.h new file mode 100644 index 0000000000..6c7cd5a6db --- /dev/null +++ b/include/asm-blackfin/arch-bf533/defBF531.h @@ -0,0 +1,24 @@ +/* + * defBF531.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _DEFBF531_H +#define _DEFBF531_H + +#include + +#endif /* _DEFBF531_H */ diff --git a/include/asm-blackfin/arch-bf533/defBF532.h b/include/asm-blackfin/arch-bf533/defBF532.h new file mode 100644 index 0000000000..312ff2bf5c --- /dev/null +++ b/include/asm-blackfin/arch-bf533/defBF532.h @@ -0,0 +1,1159 @@ +/* + * defBF532.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */ + +#ifndef _DEF_BF532_H +#define _DEF_BF532_H + +/* + * #if !defined(__ADSPLPBLACKFIN__) + * #warning defBF532.h should only be included for 532 compatible chips + * #endif + */ + +/* include all Core registers and bit definitions */ +#include + +/* Helper macros + * usage: + * P0.H = HI(UART_THR); + * P0.L = LO(UART_THR); + */ + +#define LO(con32) ((con32) & 0xFFFF) +#define lo(con32) ((con32) & 0xFFFF) +#define HI(con32) (((con32) >> 16) & 0xFFFF) +#define hi(con32) (((con32) >> 16) & 0xFFFF) + +/* + * System MMR Register Map + */ + +/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ +#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ +#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ +#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ +#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ +#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ +#define CHIPID 0xFFC00014 /* Chip ID register (32-bit) */ +#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ +#define SYSCR 0xFFC00104 /* System Configuration register */ + +/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ +#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ +#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ +#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ +#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ +#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ + +/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ +#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ +#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ +#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ + +/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ +#define RTC_STAT 0xFFC00300 /* RTC Status Register */ +#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ +#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ +#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ +#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ +#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ +#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ + +/* UART Controller (0xFFC00400 - 0xFFC004FF) */ +#define UART_THR 0xFFC00400 /* Transmit Holding register */ +#define UART_RBR 0xFFC00400 /* Receive Buffer register */ +#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ +#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ +#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ +#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ +#define UART_LCR 0xFFC0040C /* Line Control Register */ +#define UART_MCR 0xFFC00410 /* Modem Control Register */ +#define UART_LSR 0xFFC00414 /* Line Status Register */ +/* #define UART_MSR 0xFFC00418 *//* Modem Status Register (UNUSED in ADSP-BF532) */ +#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ +#define UART_GCTL 0xFFC00424 /* Global Control Register */ + +/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define SPI_CTL 0xFFC00500 /* SPI Control Register */ +#define SPI_FLG 0xFFC00504 /* SPI Flag register */ +#define SPI_STAT 0xFFC00508 /* SPI Status register */ +#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ +#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ +#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ +#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ + +/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ +#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ +#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ +#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ +#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ + +#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ +#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ +#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ +#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ + +#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ +#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ +#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ +#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ + +#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ +#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ +#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ + +/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */ +#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ +#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ +#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ +#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ +#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ +#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ +#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ +#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ +#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ +#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ +#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ +#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ +#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ +#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ +#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ +#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ +#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ + +/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ +#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ +#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ +#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ +#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ +#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ +#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ +#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ + +/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ +#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ +#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ +#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ +#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ +#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ +#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ +#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ +#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ +#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ +#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ +#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ +#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ +#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ +#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ +#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ +#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ +#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ +#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ + +/* Asynchronous Memory Controller - External Bus Interface Unit */ +#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ +#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ +#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ + +/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ +#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ +#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ +#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ +#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ + +/* DMA Test Registers */ +#define DMA_CCOMP 0xFFC00B04 /* DMA Cycle Count Register */ +#define DMA_ACOMP 0xFFC00B00 /* Debug Compare Address Register */ +#define DMA_MISR 0xFFC00B08 /* MISR Register */ +#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ +#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ +#define DMA_TMODE 0xFFC00B14 /* DMA Test Modes Register */ +#define DMA_TMCHAN 0xFFC00B18 /* DMA Testmode Selected Channel Register */ +#define DMA_TMSTAT 0xFFC00B1C /* DMA Testmode Channel Status Register */ +#define DMA_TMBD 0xFFC00B20 /* DMA Testmode DAB Bus Data Register */ +#define DMA_TMM0D 0xFFC00B24 /* DMA Testmode Mem0 Data Register */ +#define DMA_TMM1D 0xFFC00B28 /* DMA Testmode Mem1 Data Register */ +#define DMA_TMMA 0xFFC00B2C /* DMA Testmode Memory Address Register */ + +/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ +#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ +#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ +#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ +#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ +#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ +#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ +#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ +#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ +#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ +#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ +#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ +#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ +#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ + +#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ +#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ +#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ +#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ +#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ +#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ +#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ +#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ +#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ +#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ +#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ +#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ +#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ + +#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ +#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ +#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ +#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ +#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ +#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ +#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ +#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ +#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ +#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ +#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ +#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ +#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ + +#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ +#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ +#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ +#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ +#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ +#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ +#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ +#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ +#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ +#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ +#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ +#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ +#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ + +#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ +#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ +#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ +#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ +#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ +#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ +#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ +#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ +#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ +#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ +#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ +#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ +#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ + +#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ +#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ +#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ +#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ +#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ +#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ +#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ +#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ +#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ +#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ +#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ +#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ +#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ + +#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ +#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ +#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ +#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ +#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ +#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ +#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ +#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ +#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ +#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ +#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ +#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ +#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ + +#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ +#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ +#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ +#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ +#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ +#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ +#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ +#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ +#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ +#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ +#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ +#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ +#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ + +#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ +#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ +#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */ +#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */ +#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */ +#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */ +#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */ +#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ +#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */ +#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */ +#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */ +#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ +#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */ + +#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */ +#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ +#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */ +#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */ +#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */ +#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */ +#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */ +#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ +#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */ +#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */ +#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */ +#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ +#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */ + +#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */ +#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ +#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */ +#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */ +#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */ +#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */ +#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */ +#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ +#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */ +#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */ +#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */ +#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ +#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */ + +#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */ +#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ +#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */ +#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */ +#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */ +#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */ +#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */ +#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ +#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */ +#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */ +#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */ +#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */ +#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */ + +/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ +#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ +#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ +#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ +#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ +#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ + +/* + * System MMR Register Bits + */ +/* + * PLL AND RESET MASKS + */ + +/* PLL_CTL Masks */ +#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ +#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ +#define PLL_OFF 0x00000002 /* Shut off PLL clocks */ +#define STOPCK_OFF 0x00000008 /* Core clock off */ +#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ +#define BYPASS 0x00000100 /* Bypass the PLL */ + +/* PLL_DIV Masks */ +#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ + +#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ + +/* SWRST Mask */ +#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ + +/* + * SYSTEM INTERRUPT CONTROLLER MASKS + */ + +/* SIC_IAR0 Masks */ +#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */ +#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ +#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ +#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */ +#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ +#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ +#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ +#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ + +/* SIC_IAR1 Masks */ +#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */ +#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ +#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ +#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */ +#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ +#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ +#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ +#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ + +/* SIC_IAR2 Masks */ +#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */ +#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ +#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ +#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */ +#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ +#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ +#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ +#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ + +/* SIC_IMASK Masks */ +#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ +#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ +#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ +#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ + +/* SIC_IWR Masks */ +#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ +#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ +#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ +#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ + +/* + * WATCHDOG TIMER MASKS + */ +/* Watchdog Timer WDOG_CTL Register */ +#define ICTL(x) ((x<<1) & 0x0006) +#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */ +#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */ +#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */ +#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */ + +#define TMR_EN 0x0000 +#define TMR_DIS 0x0AD0 +#define TRO 0x8000 + +#define ICTL_P0 0x01 +#define ICTL_P1 0x02 +#define TRO_P 0x0F + +/* RTC_STAT and RTC_ALARM register */ +#define RTSEC 0x0000003F /* Real-Time Clock Seconds */ +#define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */ +#define RTHR 0x0001F000 /* Real-Time Clock Hours */ +#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */ + +/* RTC_ICTL register */ +#define SWIE 0x0001 /* Stopwatch Interrupt Enable */ +#define AIE 0x0002 /* Alarm Interrupt Enable */ +#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */ +#define MIE 0x0008 /* Minutes Interrupt Enable */ +#define HIE 0x0010 /* Hours Interrupt Enable */ +#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */ +#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ +#define WCIE 0x8000 /* Write Complete Interrupt Enable */ + +/* RTC_ISTAT register */ +#define SWEF 0x0001 /* Stopwatch Event Flag */ +#define AEF 0x0002 /* Alarm Event Flag */ +#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */ +#define MEF 0x0008 /* Minutes Event Flag */ +#define HEF 0x0010 /* Hours Event Flag */ +#define DEF 0x0020 /* 24 Hours (Days) Event Flag */ +#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */ +#define WPS 0x4000 /* Write Pending Status (RO) */ +#define WCOM 0x8000 /* Write Complete */ + +/* RTC_FAST Mask (RTC_PREN Mask) */ +#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */ +#define PREN 0x00000001 /* ** Must be set after power-up for proper operation of RTC */ + +/* + * UART CONTROLLER MASKS + */ + +/* UART_LCR Register */ +#define DLAB 0x80 +#define SB 0x40 +#define STP 0x20 +#define EPS 0x10 +#define PEN 0x08 +#define STB 0x04 +#define WLS(x) ((x-5) & 0x03) + +#define DLAB_P 0x07 +#define SB_P 0x06 +#define STP_P 0x05 +#define EPS_P 0x04 +#define PEN_P 0x03 +#define STB_P 0x02 +#define WLS_P1 0x01 +#define WLS_P0 0x00 + +/* UART_MCR Register */ +#define LOOP_ENA 0x10 +#define LOOP_ENA_P 0x04 + +/* UART_LSR Register */ +#define TEMT 0x40 +#define THRE 0x20 +#define BI 0x10 +#define FE 0x08 +#define PE 0x04 +#define OE 0x02 +#define DR 0x01 + +#define TEMP_P 0x06 +#define THRE_P 0x05 +#define BI_P 0x04 +#define FE_P 0x03 +#define PE_P 0x02 +#define OE_P 0x01 +#define DR_P 0x00 + +/* UART_IER Register */ +#define ELSI 0x04 +#define ETBEI 0x02 +#define ERBFI 0x01 + +#define ELSI_P 0x02 +#define ETBEI_P 0x01 +#define ERBFI_P 0x00 + +/* UART_IIR Register */ +#define STATUS(x) ((x << 1) & 0x06) +#define NINT 0x01 +#define STATUS_P1 0x02 +#define STATUS_P0 0x01 +#define NINT_P 0x00 + +/* UART_GCTL Register */ +#define FFE 0x20 +#define FPE 0x10 +#define RPOLC 0x08 +#define TPOLC 0x04 +#define IREN 0x02 +#define UCEN 0x01 + +#define FFE_P 0x05 +#define FPE_P 0x04 +#define RPOLC_P 0x03 +#define TPOLC_P 0x02 +#define IREN_P 0x01 +#define UCEN_P 0x00 + +/* + * SERIAL PORT MASKS + */ +/* SPORTx_TCR1 Masks */ +#define TSPEN 0x0001 /* TX enable */ +#define ITCLK 0x0002 /* Internal TX Clock Select */ +#define TDTYPE 0x000C /* TX Data Formatting Select */ +#define TLSBIT 0x0010 /* TX Bit Order */ +#define ITFS 0x0200 /* Internal TX Frame Sync Select */ +#define TFSR 0x0400 /* TX Frame Sync Required Select */ +#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ +#define LTFS 0x1000 /* Low TX Frame Sync Select */ +#define LATFS 0x2000 /* Late TX Frame Sync Select */ +#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ + +/* SPORTx_TCR2 Masks */ +#define SLEN 0x001F /*TX Word Length */ +#define TXSE 0x0100 /*TX Secondary Enable */ +#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ +#define TRFST 0x0400 /*TX Right-First Data Order */ + +/* SPORTx_RCR1 Masks */ +#define RSPEN 0x0001 /* RX enable */ +#define IRCLK 0x0002 /* Internal RX Clock Select */ +#define RDTYPE 0x000C /* RX Data Formatting Select */ +#define RULAW 0x0008 /* u-Law enable */ +#define RALAW 0x000C /* A-Law enable */ +#define RLSBIT 0x0010 /* RX Bit Order */ +#define IRFS 0x0200 /* Internal RX Frame Sync Select */ +#define RFSR 0x0400 /* RX Frame Sync Required Select */ +#define LRFS 0x1000 /* Low RX Frame Sync Select */ +#define LARFS 0x2000 /* Late RX Frame Sync Select */ +#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ + +/* SPORTx_RCR2 Masks */ +#define SLEN 0x001F /* RX Word Length */ +#define RXSE 0x0100 /* RX Secondary Enable */ +#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ +#define RRFST 0x0400 /* Right-First Data Order */ + +/* SPORTx_STAT Masks */ +#define RXNE 0x0001 /* RX FIFO Not Empty Status */ +#define RUVF 0x0002 /* RX Underflow Status */ +#define ROVF 0x0004 /* RX Overflow Status */ +#define TXF 0x0008 /* TX FIFO Full Status */ +#define TUVF 0x0010 /* TX Underflow Status */ +#define TOVF 0x0020 /* TX Overflow Status */ +#define TXHRE 0x0040 /* TX Hold Register Empty */ + +/* SPORTx_MCMC1 Masks */ +#define WSIZE 0x0000F000 /* Multichannel Window Size Field */ +#define WOFF 0x000003FF /* /Multichannel Window Offset Field */ + +/* SPORTx_MCMC2 Masks */ +#define MCCRM 0x00000003 /* Multichannel Clock Recovery Mode */ +#define MCDTXPE 0x00000004 /* Multichannel DMA Transmit Packing */ +#define MCDRXPE 0x00000008 /* Multichannel DMA Receive Packing */ +#define MCMEN 0x00000010 /* Multichannel Frame Mode Enable */ +#define FSDR 0x00000080 /* Multichannel Frame Sync to Data Relationship */ +#define MFD 0x0000F000 /* Multichannel Frame Delay */ + +/* + * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS + */ + +/* PPI_CONTROL Masks */ +#define PORT_EN 0x00000001 /* PPI Port Enable */ +#define PORT_DIR 0x00000002 /* PPI Port Direction */ +#define XFR_TYPE 0x0000000C /* PPI Transfer Type */ +#define PORT_CFG 0x00000030 /* PPI Port Configuration */ +#define FLD_SEL 0x00000040 /* PPI Active Field Select */ +#define PACK_EN 0x00000080 /* PPI Packing Mode */ +#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ +#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ +#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ +#define DLENGTH 0x00003800 /* PPI Data Length */ +#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ +#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ +#define POL 0x0000C000 /* PPI Signal Polarities */ + +/* PPI_STATUS Masks */ +#define FLD 0x00000400 /* Field Indicator */ +#define FT_ERR 0x00000800 /* Frame Track Error */ +#define OVR 0x00001000 /* FIFO Overflow Error */ +#define UNDR 0x00002000 /* FIFO Underrun Error */ +#define ERR_DET 0x00004000 /* Error Detected Indicator */ +#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ + +/* + * DMA CONTROLLER MASKS + */ + +/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ +#define DMAEN 0x00000001 /* Channel Enable */ +#define WNR 0x00000002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x00000000 /* Word Size 8 bits */ +#define WDSIZE_16 0x00000004 /* Word Size 16 bits */ +#define WDSIZE_32 0x00000008 /* Word Size 32 bits */ +#define DMA2D 0x00000010 /* 2D/1D* Mode */ +#define RESTART 0x00000020 /* Restart */ +#define DI_SEL 0x00000040 /* Data Interrupt Select */ +#define DI_EN 0x00000080 /* Data Interrupt Enable */ +#define NDSIZE 0x00000900 /* Next Descriptor Size */ +#define FLOW 0x00007000 /* Flow Control */ + +#define DMAEN_P 0 /* Channel Enable */ +#define WNR_P 1 /* Channel Direction (W/R*) */ +#define DMA2D_P 4 /* 2D/1D* Mode */ +#define RESTART_P 5 /* Restart */ +#define DI_SEL_P 6 /* Data Interrupt Select */ +#define DI_EN_P 7 /* Data Interrupt Enable */ + +/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ +#define DMA_DONE 0x00000001 /* DMA Done Indicator */ +#define DMA_ERR 0x00000002 /* DMA Error Indicator */ +#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ +#define DMA_RUN 0x00000008 /* DMA Running Indicator */ + +#define DMA_DONE_P 0 /* DMA Done Indicator */ +#define DMA_ERR_P 1 /* DMA Error Indicator */ +#define DFETCH_P 2 /* Descriptor Fetch Indicator */ +#define DMA_RUN_P 3 /* DMA Running Indicator */ + +/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ +#define CTYPE 0x00000040 /* DMA Channel Type Indicator */ +#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ +#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ +#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ +#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ +#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ +#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ +#define PMAP 0x00007000 /* DMA Peripheral Map Field */ + +/* + * GENERAL PURPOSE TIMER MASKS + */ + +/* PWM Timer bit definitions */ + +/* TIMER_ENABLE Register */ +#define TIMEN0 0x0001 +#define TIMEN1 0x0002 +#define TIMEN2 0x0004 + +#define TIMEN0_P 0x00 +#define TIMEN1_P 0x01 +#define TIMEN2_P 0x02 + +/* TIMER_DISABLE Register */ +#define TIMDIS0 0x0001 +#define TIMDIS1 0x0002 +#define TIMDIS2 0x0004 + +#define TIMDIS0_P 0x00 +#define TIMDIS1_P 0x01 +#define TIMDIS2_P 0x02 + +/* TIMER_STATUS Register */ +#define TIMIL0 0x0001 +#define TIMIL1 0x0002 +#define TIMIL2 0x0004 +#define TOVL_ERR0 0x0010 +#define TOVL_ERR1 0x0020 +#define TOVL_ERR2 0x0040 +#define TRUN0 0x1000 +#define TRUN1 0x2000 +#define TRUN2 0x4000 + +#define TIMIL0_P 0x00 +#define TIMIL1_P 0x01 +#define TIMIL2_P 0x02 +#define TOVL_ERR0_P 0x04 +#define TOVL_ERR1_P 0x05 +#define TOVL_ERR2_P 0x06 +#define TRUN0_P 0x0C +#define TRUN1_P 0x0D +#define TRUN2_P 0x0E + +/* TIMERx_CONFIG Registers */ +#define PWM_OUT 0x0001 +#define WDTH_CAP 0x0002 +#define EXT_CLK 0x0003 +#define PULSE_HI 0x0004 +#define PERIOD_CNT 0x0008 +#define IRQ_ENA 0x0010 +#define TIN_SEL 0x0020 +#define OUT_DIS 0x0040 +#define CLK_SEL 0x0080 +#define TOGGLE_HI 0x0100 +#define EMU_RUN 0x0200 +#define ERR_TYP(x) ((x & 0x03) << 14) + +#define TMODE_P0 0x00 +#define TMODE_P1 0x01 +#define PULSE_HI_P 0x02 +#define PERIOD_CNT_P 0x03 +#define IRQ_ENA_P 0x04 +#define TIN_SEL_P 0x05 +#define OUT_DIS_P 0x06 +#define CLK_SEL_P 0x07 +#define TOGGLE_HI_P 0x08 +#define EMU_RUN_P 0x09 +#define ERR_TYP_P0 0x0E +#define ERR_TYP_P1 0x0F + +/* + * PROGRAMMABLE FLAG MASKS + */ + +/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ +#define PF0 0x0001 +#define PF1 0x0002 +#define PF2 0x0004 +#define PF3 0x0008 +#define PF4 0x0010 +#define PF5 0x0020 +#define PF6 0x0040 +#define PF7 0x0080 +#define PF8 0x0100 +#define PF9 0x0200 +#define PF10 0x0400 +#define PF11 0x0800 +#define PF12 0x1000 +#define PF13 0x2000 +#define PF14 0x4000 +#define PF15 0x8000 + +/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ +#define PF0_P 0 +#define PF1_P 1 +#define PF2_P 2 +#define PF3_P 3 +#define PF4_P 4 +#define PF5_P 5 +#define PF6_P 6 +#define PF7_P 7 +#define PF8_P 8 +#define PF9_P 9 +#define PF10_P 10 +#define PF11_P 11 +#define PF12_P 12 +#define PF13_P 13 +#define PF14_P 14 +#define PF15_P 15 + +/* + * SERIAL PERIPHERAL INTERFACE (SPI) MASKS + */ + +/* SPI_CTL Masks */ +#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ +#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ +#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ +#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ +#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ +#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ +#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ +#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ +#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ +#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ +#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ +#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ + +/* SPI_FLG Masks */ +#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ +#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ + +/* SPI_FLG Bit Positions */ +#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ +#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ + +/* SPI_STAT Masks */ +#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ +#define MODF 0x00000002 /* Set(=1)in a master device when some other device tries to become master */ +#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ +#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ +#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ +#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ +#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ + +/* + * ASYNCHRONOUS MEMORY CONTROLLER MASKS + */ + +/* AMGCTL Masks */ +#define AMCKEN 0x00000001 /* Enable CLKOUT */ +#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */ +#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */ +#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ +#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ + +/* AMGCTL Bit Positions */ +#define AMCKEN_P 0x00000000 /* Enable CLKOUT */ +#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ +#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ +#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ + +/* AMBCTL0 Masks */ +#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ +#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ +#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ +#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ +#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ +#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ +#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ +#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ +#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ +#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ +#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ +#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ +#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ +#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ +#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ +#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ +#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ +#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ +#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ +#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ +#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ +#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ +#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ +#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ +#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ +#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ +#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ +#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ +#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ +#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ +#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ +#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ +#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ +#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ +#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ +#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ +#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ +#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ +#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ +#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ +#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ +#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ +#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ +#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ +#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ +#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ +#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ +#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ +#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ +#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ +#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ +#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ +#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ +#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ +#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ +#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ +#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ +#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ +#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ +#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ +#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ +#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ +#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ +#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ +#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ +#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ +#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ +#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ +#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ +#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ +#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ +#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ +#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ +#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ +#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ +#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ +#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ +#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ +#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ +#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ + +/* AMBCTL1 Masks */ +#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ +#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ +#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ +#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ +#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ +#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ +#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ +#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ +#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ +#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ +#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ +#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ +#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ +#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ +#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ +#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ +#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ +#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ +#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ +#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ +#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ +#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ +#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ +#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ +#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ +#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ +#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ +#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ +#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ +#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ +#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ +#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ +#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ +#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ +#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ +#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ +#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ +#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ +#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ +#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ +#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ +#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ +#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ +#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ +#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ +#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ +#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ +#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ +#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ +#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ +#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ +#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ +#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ +#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ +#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ +#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ +#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ +#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ +#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ +#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ +#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ +#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ +#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ +#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ +#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ +#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ +#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ +#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ +#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ +#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ +#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ +#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ + +/* + * SDRAM CONTROLLER MASKS + */ + +/* SDGCTL Masks */ +#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ +#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ +#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ +#define PFE 0x00000010 /* Enable SDRAM prefetch */ +#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ +#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ +#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ +#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ +#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ +#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ +#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ +#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ +#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ +#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ +#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ +#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ +#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ +#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ +#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ +#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ +#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ +#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ +#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ +#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ +#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ +#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ +#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ +#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ +#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ +#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ +#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ +#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ +#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ +#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ +#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ +#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ +#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ +#define PUPSD 0x00200000 /* Power-up start delay */ +#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ +#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ +#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ +#define EBUFE 0x02000000 /* Enable external buffering timing */ +#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ +#define EMREN 0x10000000 /* Extended mode register enable */ +#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ +#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ + +/* EBIU_SDBCTL Masks */ +#define EBE 0x00000001 /* Enable SDRAM external bank */ +#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ +#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ +#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ +#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ +#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ +#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ +#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ +#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ + +/* EBIU_SDSTAT Masks */ +#define SDCI 0x00000001 /* SDRAM controller is idle */ +#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ +#define SDPUA 0x00000004 /* SDRAM power up active */ +#define SDRS 0x00000008 /* SDRAM is in reset state */ +#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ +#define BGSTAT 0x00000020 /* Bus granted */ + +#endif /* _DEF_BF532_H */ diff --git a/include/asm-blackfin/arch-bf533/defBF533.h b/include/asm-blackfin/arch-bf533/defBF533.h new file mode 100644 index 0000000000..90e50afa7f --- /dev/null +++ b/include/asm-blackfin/arch-bf533/defBF533.h @@ -0,0 +1,24 @@ +/* + * defBF533.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _DEFBF533_H +#define _DEFBF533_H + +#include + +#endif /* _DEFBF533_H */ diff --git a/include/asm-blackfin/arch-bf533/defBF533_extn.h b/include/asm-blackfin/arch-bf533/defBF533_extn.h new file mode 100644 index 0000000000..045e8e49f8 --- /dev/null +++ b/include/asm-blackfin/arch-bf533/defBF533_extn.h @@ -0,0 +1,77 @@ +/* + * defBF533_extn.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _DEF_BF533_EXTN_H +#define _DEF_BF533_EXTN_H + +/* define macro for offset */ +#define OFFSET_( x ) ((x) & 0x0000FFFF) +/* Delay inserted for PLL transition */ +#define PLL_DELAY 0x1000 + +#define L1_ISRAM 0xFFA00000 +#define L1_ISRAM_END 0xFFA10000 +#define DATA_BANKA_SRAM 0xFF800000 +#define DATA_BANKA_SRAM_END 0xFF808000 +#define DATA_BANKB_SRAM 0xFF900000 +#define DATA_BANKB_SRAM_END 0xFF908000 +#define SYSMMR_BASE 0xFFC00000 +#define WDSIZE16 0x00000004 + +/* Event Vector Table Address */ +#define EVT_EMULATION_ADDR 0xffe02000 +#define EVT_RESET_ADDR 0xffe02004 +#define EVT_NMI_ADDR 0xffe02008 +#define EVT_EXCEPTION_ADDR 0xffe0200c +#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010 +#define EVT_HARDWARE_ERROR_ADDR 0xffe02014 +#define EVT_TIMER_ADDR 0xffe02018 +#define EVT_IVG7_ADDR 0xffe0201c +#define EVT_IVG8_ADDR 0xffe02020 +#define EVT_IVG9_ADDR 0xffe02024 +#define EVT_IVG10_ADDR 0xffe02028 +#define EVT_IVG11_ADDR 0xffe0202c +#define EVT_IVG12_ADDR 0xffe02030 +#define EVT_IVG13_ADDR 0xffe02034 +#define EVT_IVG14_ADDR 0xffe02038 +#define EVT_IVG15_ADDR 0xffe0203c +#define EVT_OVERRIDE_ADDR 0xffe02100 + +/* IMASK Bit values */ +#define IVG15_POS 0x00008000 +#define IVG14_POS 0x00004000 +#define IVG13_POS 0x00002000 +#define IVG12_POS 0x00001000 +#define IVG11_POS 0x00000800 +#define IVG10_POS 0x00000400 +#define IVG9_POS 0x00000200 +#define IVG8_POS 0x00000100 +#define IVG7_POS 0x00000080 +#define IVGTMR_POS 0x00000040 +#define IVGHW_POS 0x00000020 + +#define WDOG_TMR_DISABLE (0xAD << 4) +#define ICTL_RST 0x00000000 +#define ICTL_NMI 0x00000002 +#define ICTL_GP 0x00000004 +#define ICTL_DISABLE 0x00000003 + +/* Watch Dog timer values setup */ +#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE + +#endif /* _DEF_BF533_EXTN_H */ diff --git a/include/asm-blackfin/arch-bf533/irq.h b/include/asm-blackfin/arch-bf533/irq.h new file mode 100644 index 0000000000..9c5230db41 --- /dev/null +++ b/include/asm-blackfin/arch-bf533/irq.h @@ -0,0 +1,137 @@ +/* + * U-boot bf533_irq.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c + * Changed by HuTao Apr18, 2003 + * + * Copyright was missing when I got the code so took from MIPS arch ...MaTed--- + * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle + * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle + * + * Adapted for BlackFin (ADI) by Ted Ma + * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) + * Copyright (c) 2002 Lineo, Inc. + * + * Adapted for BlackFin BF533 by Bas Vermeulen + * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl) + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BF533_IRQ_H_ +#define _BF533_IRQ_H_ + +/* + * Interrupt source definitions + * Event Source Core Event Name Number + * EMU 0 + * Reset RST 1 + * NMI NMI 2 + * Exception EVX 3 + * Reserved -- 4 + * Hardware Error IVHW 5 + * Core Timer IVTMR 6 + * PLL Wakeup Interrupt IVG7 7 + * DMA Error (generic) IVG7 8 + * PPI Error Interrupt IVG7 9 + * SPORT0 Error Interrupt IVG7 10 + * SPORT1 Error Interrupt IVG7 11 + * SPI Error Interrupt IVG7 12 + * UART Error Interrupt IVG7 13 + * RTC Interrupt IVG8 14 + * DMA0 Interrupt (PPI) IVG8 15 + * DMA1 (SPORT0 RX) IVG9 16 + * DMA2 (SPORT0 TX) IVG9 17 + * DMA3 (SPORT1 RX) IVG9 18 + * DMA4 (SPORT1 TX) IVG9 19 + * DMA5 (PPI) IVG10 20 + * DMA6 (UART RX) IVG10 21 + * DMA7 (UART TX) IVG10 22 + * Timer0 IVG11 23 + * Timer1 IVG11 24 + * Timer2 IVG11 25 + * PF Interrupt A IVG12 26 + * PF Interrupt B IVG12 27 + * DMA8/9 Interrupt IVG13 28 + * DMA10/11 Interrupt IVG13 29 + * Watchdog Timer IVG13 30 + * Software Interrupt 1 IVG14 31 + * Software Interrupt 2 -- + * (lowest priority) IVG15 32 + */ + +/* The ABSTRACT IRQ definitions */ + +/* The first seven of the following are fixed, + * the rest you change if you need to + */ + +#define IRQ_EMU 0 /* Emulation */ +#define IRQ_RST 1 /* reset */ +#define IRQ_NMI 2 /* Non Maskable */ +#define IRQ_EVX 3 /* Exception */ +#define IRQ_UNUSED 4 /* - unused interrupt */ +#define IRQ_HWERR 5 /* Hardware Error */ +#define IRQ_CORETMR 6 /* Core timer */ +#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */ +#define IRQ_DMA_ERROR 8 /* DMA Error (general) */ +#define IRQ_PPI_ERROR 9 /* PPI Error Interrupt */ +#define IRQ_SPORT0_ERROR 10 /* SPORT0 Error Interrupt */ +#define IRQ_SPORT1_ERROR 11 /* SPORT1 Error Interrupt */ +#define IRQ_SPI_ERROR 12 /* SPI Error Interrupt */ +#define IRQ_UART_ERROR 13 /* UART Error Interrupt */ +#define IRQ_RTC 14 /* RTC Interrupt */ +#define IRQ_PPI 15 /* DMA0 Interrupt (PPI) */ +#define IRQ_SPORT0 16 /* DMA1 Interrupt (SPORT0 RX) */ +#define IRQ_SPARE1 17 /* DMA2 Interrupt (SPORT0 TX) */ +#define IRQ_SPORT1 18 /* DMA3 Interrupt (SPORT1 RX) */ +#define IRQ_SPARE2 19 /* DMA4 Interrupt (SPORT1 TX) */ +#define IRQ_SPI 20 /* DMA5 Interrupt (SPI) */ +#define IRQ_UART 21 /* DMA6 Interrupt (UART RX) */ +#define IRQ_SPARE3 22 /* DMA7 Interrupt (UART TX) */ +#define IRQ_TMR0 23 /* Timer 0 */ +#define IRQ_TMR1 24 /* Timer 1 */ +#define IRQ_TMR2 25 /* Timer 2 */ +#define IRQ_PROG_INTA 26 /* Programmable Flags A (8) */ +#define IRQ_PROG_INTB 27 /* Programmable Flags B (8) */ +#define IRQ_MEM_DMA0 28 /* DMA8/9 Interrupt (Memory DMA Stream 0) */ +#define IRQ_MEM_DMA1 29 /* DMA10/11 Interrupt (Memory DMA Stream 1) */ +#define IRQ_WATCH 30 /* Watch Dog Timer */ +#define IRQ_SW_INT1 31 /* Software Int 1 */ +#define IRQ_SW_INT2 32 /* Software Int 2 (reserved for SYSCALL) */ + +#define IRQ_UART_RX_BIT 0x4000 +#define IRQ_UART_TX_BIT 0x8000 +#define IRQ_UART_ERROR_BIT 0x40 + +#define IVG7 7 +#define IVG8 8 +#define IVG9 9 +#define IVG10 10 +#define IVG11 11 +#define IVG12 12 +#define IVG13 13 +#define IVG14 14 +#define IVG15 15 +#define SYS_IRQS 33 + +#endif diff --git a/include/asm-blackfin/arch-common/bf53x_rtc.h b/include/asm-blackfin/arch-common/bf53x_rtc.h new file mode 100644 index 0000000000..bc09922a5e --- /dev/null +++ b/include/asm-blackfin/arch-common/bf53x_rtc.h @@ -0,0 +1,46 @@ +/* + * U-boot - bf533_rtc.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BF533_RTC_H_ +#define _BF533_RTC_H_ + +void rtc_init(void); +void wait_for_complete(void); +void rtc_reset(void); + +#define MIN_TO_SECS(_x_) (60 * _x_) +#define HRS_TO_SECS(_x_) (60 * 60 * _x_) +#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_) + +#define NUM_SECS_IN_DAY (24 * 3600) +#define NUM_SECS_IN_HOUR (3600) +#define NUM_SECS_IN_MIN (60) + +/* Shift values for RTC_STAT register */ +#define DAY_BITS_OFF 17 +#define HOUR_BITS_OFF 12 +#define MIN_BITS_OFF 6 +#define SEC_BITS_OFF 0 + +#endif diff --git a/include/asm-blackfin/arch-common/cdefBF5xx.h b/include/asm-blackfin/arch-common/cdefBF5xx.h new file mode 100644 index 0000000000..aec70ce8b7 --- /dev/null +++ b/include/asm-blackfin/arch-common/cdefBF5xx.h @@ -0,0 +1,40 @@ +/************************************************************************ + * + * cdefBF53x.h + * + * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved. + * + ************************************************************************/ + +#ifndef _CDEFBF53x_H +#define _CDEFBF53x_H + +#if defined(__ADSPBF531__) + #include +#elif defined(__ADSPBF532__) + #include +#elif defined(__ADSPBF533__) + #include + #include + #include +#elif defined(__ADSPBF537__) + #include + #include + #include +#elif defined(__ADSPBF561__) + #include + #include + #include +#elif defined(__ADSPBF535__) + #include +#elif defined(__AD6532__) + #include +#else + #if defined(__ADSPLPBLACKFIN__) + #include + #else + #include + #endif +#endif + +#endif /* _CDEFBF53x_H */ diff --git a/include/asm-blackfin/arch-common/cdef_LPBlackfin.h b/include/asm-blackfin/arch-common/cdef_LPBlackfin.h new file mode 100644 index 0000000000..f82ccbe4ec --- /dev/null +++ b/include/asm-blackfin/arch-common/cdef_LPBlackfin.h @@ -0,0 +1,177 @@ +/************************************************************************ + * + * cdef_LPBlackfin.h + * + * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved. + * + ************************************************************************/ + +#ifndef _CDEF_LPBLACKFIN_H +#define _CDEF_LPBLACKFIN_H + +#if !defined(__ADSPLPBLACKFIN__) +#warning cdef_LPBlackfin.h should only be included for 532 compatible chips. +#endif +#include + +// Cache & SRAM Memory +#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS) +#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL) +#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS) +#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR) +/* +#define MMR_TIMEOUT 0xFFE00010 // Memory-Mapped Register Timeout Register +*/ +#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0) +#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1) +#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2) +#define pDCPLB_ADDR3 ((volatile void **)DCPLB_ADDR3) +#define pDCPLB_ADDR4 ((volatile void **)DCPLB_ADDR4) +#define pDCPLB_ADDR5 ((volatile void **)DCPLB_ADDR5) +#define pDCPLB_ADDR6 ((volatile void **)DCPLB_ADDR6) +#define pDCPLB_ADDR7 ((volatile void **)DCPLB_ADDR7) +#define pDCPLB_ADDR8 ((volatile void **)DCPLB_ADDR8) +#define pDCPLB_ADDR9 ((volatile void **)DCPLB_ADDR9) +#define pDCPLB_ADDR10 ((volatile void **)DCPLB_ADDR10) +#define pDCPLB_ADDR11 ((volatile void **)DCPLB_ADDR11) +#define pDCPLB_ADDR12 ((volatile void **)DCPLB_ADDR12) +#define pDCPLB_ADDR13 ((volatile void **)DCPLB_ADDR13) +#define pDCPLB_ADDR14 ((volatile void **)DCPLB_ADDR14) +#define pDCPLB_ADDR15 ((volatile void **)DCPLB_ADDR15) +#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0) +#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1) +#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2) +#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3) +#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4) +#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5) +#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6) +#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7) +#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8) +#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9) +#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10) +#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11) +#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12) +#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13) +#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14) +#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15) +#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND) +/* +#define DTEST_INDEX 0xFFE00304 // Data Test Index Register +*/ +#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0) +#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1) +/* +#define DTEST_DATA2 0xFFE00408 // Data Test Data Register +#define DTEST_DATA3 0xFFE0040C // Data Test Data Register +*/ +#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL) +#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS) +#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR) +#define pICPLB_ADDR0 ((volatile void **)ICPLB_ADDR0) +#define pICPLB_ADDR1 ((volatile void **)ICPLB_ADDR1) +#define pICPLB_ADDR2 ((volatile void **)ICPLB_ADDR2) +#define pICPLB_ADDR3 ((volatile void **)ICPLB_ADDR3) +#define pICPLB_ADDR4 ((volatile void **)ICPLB_ADDR4) +#define pICPLB_ADDR5 ((volatile void **)ICPLB_ADDR5) +#define pICPLB_ADDR6 ((volatile void **)ICPLB_ADDR6) +#define pICPLB_ADDR7 ((volatile void **)ICPLB_ADDR7) +#define pICPLB_ADDR8 ((volatile void **)ICPLB_ADDR8) +#define pICPLB_ADDR9 ((volatile void **)ICPLB_ADDR9) +#define pICPLB_ADDR10 ((volatile void **)ICPLB_ADDR10) +#define pICPLB_ADDR11 ((volatile void **)ICPLB_ADDR11) +#define pICPLB_ADDR12 ((volatile void **)ICPLB_ADDR12) +#define pICPLB_ADDR13 ((volatile void **)ICPLB_ADDR13) +#define pICPLB_ADDR14 ((volatile void **)ICPLB_ADDR14) +#define pICPLB_ADDR15 ((volatile void **)ICPLB_ADDR15) +#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0) +#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1) +#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2) +#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3) +#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4) +#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5) +#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6) +#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7) +#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8) +#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9) +#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10) +#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11) +#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12) +#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13) +#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14) +#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15) +#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND) +/* +#define ITEST_INDEX 0xFFE01304 // Instruction Test Index Register +*/ +#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0) +#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1) + +// Event/Interrupt Registers +#define pEVT0 ((volatile void **)EVT0) +#define pEVT1 ((volatile void **)EVT1) +#define pEVT2 ((volatile void **)EVT2) +#define pEVT3 ((volatile void **)EVT3) +#define pEVT4 ((volatile void **)EVT4) +#define pEVT5 ((volatile void **)EVT5) +#define pEVT6 ((volatile void **)EVT6) +#define pEVT7 ((volatile void **)EVT7) +#define pEVT8 ((volatile void **)EVT8) +#define pEVT9 ((volatile void **)EVT9) +#define pEVT10 ((volatile void **)EVT10) +#define pEVT11 ((volatile void **)EVT11) +#define pEVT12 ((volatile void **)EVT12) +#define pEVT13 ((volatile void **)EVT13) +#define pEVT14 ((volatile void **)EVT14) +#define pEVT15 ((volatile void **)EVT15) +#define pIMASK ((volatile unsigned long *)IMASK) +#define pIPEND ((volatile unsigned long *)IPEND) +#define pILAT ((volatile unsigned long *)ILAT) + +// Core Timer Registers +#define pTCNTL ((volatile unsigned long *)TCNTL) +#define pTPERIOD ((volatile unsigned long *)TPERIOD) +#define pTSCALE ((volatile unsigned long *)TSCALE) +#define pTCOUNT ((volatile unsigned long *)TCOUNT) + +// Debug/MP/Emulation Registers +#define pDSPID ((volatile unsigned long *)DSPID) +#define pDBGCTL ((volatile unsigned long *)DBGCTL) +#define pDBGSTAT ((volatile unsigned long *)DBGSTAT) +#define pEMUDAT ((volatile unsigned long *)EMUDAT) + +// Trace Buffer Registers +#define pTBUFCTL ((volatile unsigned long *)TBUFCTL) +#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT) +#define pTBUF ((volatile void **)TBUF) + +// Watch Point Control Registers +#define pWPIACTL ((volatile unsigned long *)WPIACTL) +#define pWPIA0 ((volatile void **)WPIA0) +#define pWPIA1 ((volatile void **)WPIA1) +#define pWPIA2 ((volatile void **)WPIA2) +#define pWPIA3 ((volatile void **)WPIA3) +#define pWPIA4 ((volatile void **)WPIA4) +#define pWPIA5 ((volatile void **)WPIA5) +#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0) +#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1) +#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2) +#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3) +#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4) +#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5) +#define pWPDACTL ((volatile unsigned long *)WPDACTL) +#define pWPDA0 ((volatile void **)WPDA0) +#define pWPDA1 ((volatile void **)WPDA1) +#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0) +#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1) +#define pWPSTAT ((volatile unsigned long *)WPSTAT) + +// Performance Monitor Registers +#define pPFCTL ((volatile unsigned long *)PFCTL) +#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0) +#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1) + +/* +#define IPRIO 0xFFE02110 // Core Interrupt Priority Register +*/ + +#endif /* _CDEF_LPBLACKFIN_H */ diff --git a/include/asm-blackfin/arch-common/def_LPBlackfin.h b/include/asm-blackfin/arch-common/def_LPBlackfin.h new file mode 100644 index 0000000000..ebeeea0321 --- /dev/null +++ b/include/asm-blackfin/arch-common/def_LPBlackfin.h @@ -0,0 +1,445 @@ +/* + * def_LPBlackfin.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */ + +#ifndef _DEF_LPBLACKFIN_H +#define _DEF_LPBLACKFIN_H + +/* + * #if !defined(__ADSPLPBLACKFIN__) + * #warning def_LPBlackfin.h should only be included for 532 compatible chips. + * #endif + */ + +#define MK_BMSK_( x ) (1<31 */ +#define TEST_WAY0 0x00000000 /* Access Way0 */ +#define TEST_WAY1 0x04000000 /* Access Way1 */ + +/* ** ITEST_COMMAND only */ +#define TEST_WAY2 0x08000000 /* Access Way2 */ +#define TEST_WAY3 0x0C000000 /* Access Way3 */ + +/* ** DTEST_COMMAND only */ +#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */ +#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */ + +#endif /* _DEF_LPBLACKFIN_H */ diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h index 65d2c25345..7766c4ab06 100644 --- a/include/asm-blackfin/bitops.h +++ b/include/asm-blackfin/bitops.h @@ -59,7 +59,7 @@ static __inline__ unsigned long ffz(unsigned long word) static __inline__ void set_bit(int nr, volatile void *addr) { - int *a = (int *) addr; + int *a = (int *)addr; int mask; unsigned long flags; @@ -72,7 +72,7 @@ static __inline__ void set_bit(int nr, volatile void *addr) static __inline__ void __set_bit(int nr, volatile void *addr) { - int *a = (int *) addr; + int *a = (int *)addr; int mask; a += nr >> 5; @@ -88,7 +88,7 @@ static __inline__ void __set_bit(int nr, volatile void *addr) static __inline__ void clear_bit(int nr, volatile void *addr) { - int *a = (int *) addr; + int *a = (int *)addr; int mask; unsigned long flags; @@ -102,7 +102,7 @@ static __inline__ void clear_bit(int nr, volatile void *addr) static __inline__ void change_bit(int nr, volatile void *addr) { int mask, flags; - unsigned long *ADDR = (unsigned long *) addr; + unsigned long *ADDR = (unsigned long *)addr; ADDR += nr >> 5; mask = 1 << (nr & 31); @@ -114,7 +114,7 @@ static __inline__ void change_bit(int nr, volatile void *addr) static __inline__ void __change_bit(int nr, volatile void *addr) { int mask; - unsigned long *ADDR = (unsigned long *) addr; + unsigned long *ADDR = (unsigned long *)addr; ADDR += nr >> 5; mask = 1 << (nr & 31); @@ -124,7 +124,7 @@ static __inline__ void __change_bit(int nr, volatile void *addr) static __inline__ int test_and_set_bit(int nr, volatile void *addr) { int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; + volatile unsigned int *a = (volatile unsigned int *)addr; unsigned long flags; a += nr >> 5; @@ -140,7 +140,7 @@ static __inline__ int test_and_set_bit(int nr, volatile void *addr) static __inline__ int __test_and_set_bit(int nr, volatile void *addr) { int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; + volatile unsigned int *a = (volatile unsigned int *)addr; a += nr >> 5; mask = 1 << (nr & 0x1f); @@ -152,7 +152,7 @@ static __inline__ int __test_and_set_bit(int nr, volatile void *addr) static __inline__ int test_and_clear_bit(int nr, volatile void *addr) { int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; + volatile unsigned int *a = (volatile unsigned int *)addr; unsigned long flags; a += nr >> 5; @@ -168,7 +168,7 @@ static __inline__ int test_and_clear_bit(int nr, volatile void *addr) static __inline__ int __test_and_clear_bit(int nr, volatile void *addr) { int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; + volatile unsigned int *a = (volatile unsigned int *)addr; a += nr >> 5; mask = 1 << (nr & 0x1f); @@ -180,7 +180,7 @@ static __inline__ int __test_and_clear_bit(int nr, volatile void *addr) static __inline__ int test_and_change_bit(int nr, volatile void *addr) { int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; + volatile unsigned int *a = (volatile unsigned int *)addr; unsigned long flags; a += nr >> 5; @@ -196,7 +196,7 @@ static __inline__ int test_and_change_bit(int nr, volatile void *addr) static __inline__ int __test_and_change_bit(int nr, volatile void *addr) { int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; + volatile unsigned int *a = (volatile unsigned int *)addr; a += nr >> 5; mask = 1 << (nr & 0x1f); @@ -208,16 +208,15 @@ static __inline__ int __test_and_change_bit(int nr, volatile void *addr) /* * This routine doesn't need to be atomic. */ -static __inline__ int __constant_test_bit(int nr, - const volatile void *addr) +static __inline__ int __constant_test_bit(int nr, const volatile void *addr) { return ((1UL << (nr & 31)) & - (((const volatile unsigned int *) addr)[nr >> 5])) != 0; + (((const volatile unsigned int *)addr)[nr >> 5])) != 0; } static __inline__ int __test_bit(int nr, volatile void *addr) { - int *a = (int *) addr; + int *a = (int *)addr; int mask; a += nr >> 5; @@ -235,7 +234,7 @@ static __inline__ int __test_bit(int nr, volatile void *addr) static __inline__ int find_next_zero_bit(void *addr, int size, int offset) { - unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long *p = ((unsigned long *)addr) + (offset >> 5); unsigned long result = offset & ~31UL; unsigned long tmp; @@ -290,7 +289,7 @@ static __inline__ int ext2_set_bit(int nr, volatile void *addr) { int mask, retval; unsigned long flags; - volatile unsigned char *ADDR = (unsigned char *) addr; + volatile unsigned char *ADDR = (unsigned char *)addr; ADDR += nr >> 3; mask = 1 << (nr & 0x07); @@ -305,7 +304,7 @@ static __inline__ int ext2_clear_bit(int nr, volatile void *addr) { int mask, retval; unsigned long flags; - volatile unsigned char *ADDR = (unsigned char *) addr; + volatile unsigned char *ADDR = (unsigned char *)addr; ADDR += nr >> 3; mask = 1 << (nr & 0x07); @@ -319,7 +318,7 @@ static __inline__ int ext2_clear_bit(int nr, volatile void *addr) static __inline__ int ext2_test_bit(int nr, const volatile void *addr) { int mask; - const volatile unsigned char *ADDR = (const unsigned char *) addr; + const volatile unsigned char *ADDR = (const unsigned char *)addr; ADDR += nr >> 3; mask = 1 << (nr & 0x07); @@ -331,10 +330,9 @@ static __inline__ int ext2_test_bit(int nr, const volatile void *addr) static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, - unsigned long - offset) + unsigned long offset) { - unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long *p = ((unsigned long *)addr) + (offset >> 5); unsigned long result = offset & ~31UL; unsigned long tmp; diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h index fbdbf30fa1..0ec92071b5 100644 --- a/include/asm-blackfin/blackfin.h +++ b/include/asm-blackfin/blackfin.h @@ -25,22 +25,16 @@ #ifndef _BLACKFIN_H_ #define _BLACKFIN_H_ -#include -#include +#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) +# ifdef SHARED_RESOURCES +# include +# endif -#ifndef __ASSEMBLY__ -#ifndef ASSEMBLY +# include -#ifdef SHARED_RESOURCES - #include +extern u_long get_sclk(void); #endif -#include -#endif -#endif - -#include -#include -#include +#include #endif diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h index 7715f645de..dd695e10ad 100644 --- a/include/asm-blackfin/cplb.h +++ b/include/asm-blackfin/cplb.h @@ -7,14 +7,15 @@ ************************************************************************/ /* Defines necessary for cplb initialisation routines. */ - #ifndef _CPLB_H #define _CPLB_H +#define CONFIG_BLKFIN_WT + #define CPLB_ENABLE_ICACHE_P 0 #define CPLB_ENABLE_DCACHE_P 1 #define CPLB_ENABLE_DCACHE2_P 2 -#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated!*/ +#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */ #define CPLB_ENABLE_ICPLBS_P 4 #define CPLB_ENABLE_DCPLBS_P 5 @@ -45,4 +46,35 @@ #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL -#endif /* _CPLB_H */ +/* Data Attibutes*/ + +#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) + +/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ + +#define ANOMALY_05000158 0x200 + +#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) +#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) + +#else /*Write Through */ +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) +#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) +#endif + +#if defined(CONFIG_BF561) +#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM +L1 + ASYNC_Memory */ +#else +#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 3) /* SDRAM + L1 + ASYNC_Memory */ +#endif +#endif /* _CPLB_H */ diff --git a/include/asm-blackfin/cplbtab.h b/include/asm-blackfin/cplbtab.h deleted file mode 100644 index ab7d989b1a..0000000000 --- a/include/asm-blackfin/cplbtab.h +++ /dev/null @@ -1,572 +0,0 @@ -/*This file is subject to the terms and conditions of the GNU General Public - * License. - * - * Blackfin BF533/2.6 support : LG Soft India - * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd - * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's - * shouldn't be victimized. cplbmgr.S search logic is corrected - * to findout the appropriate victim. - * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC - * : LG Soft India - */ -#include - -#ifndef __ARCH_BFINNOMMU_CPLBTAB_H -#define __ARCH_BFINNOMMU_CPLBTAB_H - -/************************************************************************* - * ICPLB TABLE - *************************************************************************/ - -.data - -/* This table is configurable */ - -.align 4; - -/* Data Attibutes*/ - -#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) -#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) - -/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ - -#define ANOMALY_05000158 0x200 -#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ - #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) - #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) - #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) - #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) - #define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) - -#else /*Write Through*/ - #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) - #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) - #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) - #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) - #define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) -#endif - -.global icplb_table -icplb_table: -.byte4 0xFFA00000; -.byte4 (L1_IMEMORY); -.byte4 0x00000000; -.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/ -.byte4 0x00400000; -.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/ -.byte4 0x07C00000; -.byte4 (SDRAM_IKERNEL); /*SDRAM_Page14*/ -.byte4 0x00800000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/ -.byte4 0x00C00000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/ -.byte4 0x01000000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/ -.byte4 0x01400000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/ -.byte4 0x01800000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/ -.byte4 0x01C00000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/ -#ifndef CONFIG_EZKIT /*STAMP Memory regions*/ -.byte4 0x02000000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/ -.byte4 0x02400000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/ -.byte4 0x02800000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/ -.byte4 0x02C00000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/ -.byte4 0x03000000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/ -.byte4 0x03400000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/ -#endif -.byte4 0xffffffff; /* end of section - termination*/ - -.align 4; -.global ipdt_table -ipdt_table: -#ifdef CONFIG_CPLB_INFO -.byte4 0x00000000; -.byte4 (SDRAM_IKERNEL); /*SDRAM_Page0*/ -.byte4 0x00400000; -.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/ -#endif -.byte4 0x00800000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/ -.byte4 0x00C00000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page3*/ -.byte4 0x01000000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/ -.byte4 0x01400000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/ -.byte4 0x01800000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/ -.byte4 0x01C00000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/ -#ifndef CONFIG_EZKIT /*STAMP Memory regions*/ -.byte4 0x02000000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/ -.byte4 0x02400000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/ -.byte4 0x02800000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/ -.byte4 0x02C00000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/ -.byte4 0x03000000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/ -.byte4 0x03400000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/ -.byte4 0x03800000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page14*/ -.byte4 0x03C00000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page15*/ -#endif -.byte4 0x20200000; -.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/ -.byte4 0x20100000; -.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/ -.byte4 0x20000000; -.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/ -.byte4 0x20300000; /*Fix for Network*/ -.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/ - -#ifdef CONFIG_STAMP -.byte4 0x04000000; -.byte4 (SDRAM_IGENERIC); -.byte4 0x04400000; -.byte4 (SDRAM_IGENERIC); -.byte4 0x04800000; -.byte4 (SDRAM_IGENERIC); -.byte4 0x04C00000; -.byte4 (SDRAM_IGENERIC); -.byte4 0x05000000; -.byte4 (SDRAM_IGENERIC); -.byte4 0x05400000; -.byte4 (SDRAM_IGENERIC); -.byte4 0x05800000; -.byte4 (SDRAM_IGENERIC); -.byte4 0x05C00000; -.byte4 (SDRAM_IGENERIC); -.byte4 0x06000000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page25*/ -.byte4 0x06400000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page26*/ -.byte4 0x06800000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page27*/ -.byte4 0x06C00000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page28*/ -.byte4 0x07000000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page29*/ -.byte4 0x07400000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page30*/ -.byte4 0x07800000; -.byte4 (SDRAM_IGENERIC); /*SDRAM_Page31*/ -#ifdef CONFIG_CPLB_INFO -.byte4 0x07C00000; -.byte4 (SDRAM_IKERNEL); /*SDRAM_Page32*/ -#endif -#endif -.byte4 0xffffffff; /* end of section - termination*/ - -/********************************************************************* - * DCPLB TABLE - ********************************************************************/ - -.global dcplb_table -dcplb_table: -.byte4 0x00000000; -.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ -.byte4 0x00400000; -.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ -.byte4 0x07C00000; -.byte4 (SDRAM_DKERNEL); /*SDRAM_Page15*/ -.byte4 0x00800000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/ -.byte4 0x00C00000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/ -.byte4 0x01000000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/ -.byte4 0x01400000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/ -.byte4 0x01800000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/ -.byte4 0x01C00000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/ -#ifndef CONFIG_EZKIT -.byte4 0x02000000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/ -.byte4 0x02400000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/ -.byte4 0x02800000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/ -.byte4 0x02C00000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/ -.byte4 0x03000000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/ -.byte4 0x03400000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/ -.byte4 0x03800000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/ -#endif -.byte4 0xffffffff; /*end of section - termination*/ - -/********************************************************************** - * PAGE DESCRIPTOR TABLE - * - **********************************************************************/ - -/* Till here we are discussing about the static memory management model. - * However, the operating envoronments commonly define more CPLB - * descriptors to cover the entire addressable memory than will fit into - * the available on-chip 16 CPLB MMRs. When this happens, the below table - * will be used which will hold all the potentially required CPLB descriptors - * - * This is how Page descriptor Table is implemented in uClinux/Blackfin. - */ -.global dpdt_table -dpdt_table: -#ifdef CONFIG_CPLB_INFO -.byte4 0x00000000; -.byte4 (SDRAM_DKERNEL); /*SDRAM_Page0*/ -.byte4 0x00400000; -.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ -#endif -.byte4 0x00800000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/ -.byte4 0x00C00000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/ -.byte4 0x01000000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/ -.byte4 0x01400000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/ -.byte4 0x01800000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/ -.byte4 0x01C00000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/ - -#ifndef CONFIG_EZKIT -.byte4 0x02000000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/ -.byte4 0x02400000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/ -.byte4 0x02800000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/ -.byte4 0x02C00000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/ -.byte4 0x03000000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/ -.byte4 0x03400000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/ -.byte4 0x03800000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/ -.byte4 0x03C00000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page15*/ -#endif -.byte4 0x20200000; -.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/ -.byte4 0x20100000; -.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/ -.byte4 0x20000000; -.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/ -.byte4 0x20300000; /*Fix for Network*/ -.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/ - -#ifdef CONFIG_STAMP -.byte4 0x04000000; -.byte4 (SDRAM_DGENERIC); -.byte4 0x04400000; -.byte4 (SDRAM_DGENERIC); -.byte4 0x04800000; -.byte4 (SDRAM_DGENERIC); -.byte4 0x04C00000; -.byte4 (SDRAM_DGENERIC); -.byte4 0x05000000; -.byte4 (SDRAM_DGENERIC); -.byte4 0x05400000; -.byte4 (SDRAM_DGENERIC); -.byte4 0x05800000; -.byte4 (SDRAM_DGENERIC); -.byte4 0x05C00000; -.byte4 (SDRAM_DGENERIC); -.byte4 0x06000000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page25*/ -.byte4 0x06400000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page26*/ -.byte4 0x06800000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page27*/ -.byte4 0x06C00000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page28*/ -.byte4 0x07000000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page29*/ -.byte4 0x07400000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page30*/ -.byte4 0x07800000; -.byte4 (SDRAM_DGENERIC); /*SDRAM_Page31*/ -#ifdef CONFIG_CPLB_INFO -.byte4 0x07C00000; -.byte4 (SDRAM_DKERNEL); /*SDRAM_Page32*/ -#endif -#endif - -.byte4 0xFF900000; -.byte4 (L1_DMEMORY); -.byte4 0xFF901000; -.byte4 (L1_DMEMORY); -.byte4 0xFF902000; -.byte4 (L1_DMEMORY); -.byte4 0xFF903000; -.byte4 (L1_DMEMORY); -.byte4 0xFF904000; -.byte4 (L1_DMEMORY); -.byte4 0xFF905000; -.byte4 (L1_DMEMORY); -.byte4 0xFF906000; -.byte4 (L1_DMEMORY); -.byte4 0xFF907000; -.byte4 (L1_DMEMORY); -.byte4 0xFF800000; -.byte4 (L1_DMEMORY); -.byte4 0xFF801000; -.byte4 (L1_DMEMORY); -.byte4 0xFF802000; -.byte4 (L1_DMEMORY); -.byte4 0xFF803000; -.byte4 (L1_DMEMORY); - -.byte4 0xffffffff; /*end of section - termination*/ - -#ifdef CONFIG_CPLB_INFO -.global ipdt_swapcount_table; /* swapin count first, then swapout count*/ -ipdt_swapcount_table: -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 10 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 20 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 30 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 40 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 50 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 60 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 70 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 80 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 90 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 100 */ - -.global dpdt_swapcount_table; /* swapin count first, then swapout count*/ -dpdt_swapcount_table: -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 10 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 20 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 30 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 40 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 50 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 60 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 70 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 80 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 80 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 100 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 110 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 120 */ - -#endif - -#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/ diff --git a/include/asm-blackfin/cpu/bf533_irq.h b/include/asm-blackfin/cpu/bf533_irq.h deleted file mode 100644 index 9c5230db41..0000000000 --- a/include/asm-blackfin/cpu/bf533_irq.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * U-boot bf533_irq.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * This file is based on - * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c - * Changed by HuTao Apr18, 2003 - * - * Copyright was missing when I got the code so took from MIPS arch ...MaTed--- - * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle - * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle - * - * Adapted for BlackFin (ADI) by Ted Ma - * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) - * Copyright (c) 2002 Lineo, Inc. - * - * Adapted for BlackFin BF533 by Bas Vermeulen - * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl) - - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BF533_IRQ_H_ -#define _BF533_IRQ_H_ - -/* - * Interrupt source definitions - * Event Source Core Event Name Number - * EMU 0 - * Reset RST 1 - * NMI NMI 2 - * Exception EVX 3 - * Reserved -- 4 - * Hardware Error IVHW 5 - * Core Timer IVTMR 6 - * PLL Wakeup Interrupt IVG7 7 - * DMA Error (generic) IVG7 8 - * PPI Error Interrupt IVG7 9 - * SPORT0 Error Interrupt IVG7 10 - * SPORT1 Error Interrupt IVG7 11 - * SPI Error Interrupt IVG7 12 - * UART Error Interrupt IVG7 13 - * RTC Interrupt IVG8 14 - * DMA0 Interrupt (PPI) IVG8 15 - * DMA1 (SPORT0 RX) IVG9 16 - * DMA2 (SPORT0 TX) IVG9 17 - * DMA3 (SPORT1 RX) IVG9 18 - * DMA4 (SPORT1 TX) IVG9 19 - * DMA5 (PPI) IVG10 20 - * DMA6 (UART RX) IVG10 21 - * DMA7 (UART TX) IVG10 22 - * Timer0 IVG11 23 - * Timer1 IVG11 24 - * Timer2 IVG11 25 - * PF Interrupt A IVG12 26 - * PF Interrupt B IVG12 27 - * DMA8/9 Interrupt IVG13 28 - * DMA10/11 Interrupt IVG13 29 - * Watchdog Timer IVG13 30 - * Software Interrupt 1 IVG14 31 - * Software Interrupt 2 -- - * (lowest priority) IVG15 32 - */ - -/* The ABSTRACT IRQ definitions */ - -/* The first seven of the following are fixed, - * the rest you change if you need to - */ - -#define IRQ_EMU 0 /* Emulation */ -#define IRQ_RST 1 /* reset */ -#define IRQ_NMI 2 /* Non Maskable */ -#define IRQ_EVX 3 /* Exception */ -#define IRQ_UNUSED 4 /* - unused interrupt */ -#define IRQ_HWERR 5 /* Hardware Error */ -#define IRQ_CORETMR 6 /* Core timer */ -#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */ -#define IRQ_DMA_ERROR 8 /* DMA Error (general) */ -#define IRQ_PPI_ERROR 9 /* PPI Error Interrupt */ -#define IRQ_SPORT0_ERROR 10 /* SPORT0 Error Interrupt */ -#define IRQ_SPORT1_ERROR 11 /* SPORT1 Error Interrupt */ -#define IRQ_SPI_ERROR 12 /* SPI Error Interrupt */ -#define IRQ_UART_ERROR 13 /* UART Error Interrupt */ -#define IRQ_RTC 14 /* RTC Interrupt */ -#define IRQ_PPI 15 /* DMA0 Interrupt (PPI) */ -#define IRQ_SPORT0 16 /* DMA1 Interrupt (SPORT0 RX) */ -#define IRQ_SPARE1 17 /* DMA2 Interrupt (SPORT0 TX) */ -#define IRQ_SPORT1 18 /* DMA3 Interrupt (SPORT1 RX) */ -#define IRQ_SPARE2 19 /* DMA4 Interrupt (SPORT1 TX) */ -#define IRQ_SPI 20 /* DMA5 Interrupt (SPI) */ -#define IRQ_UART 21 /* DMA6 Interrupt (UART RX) */ -#define IRQ_SPARE3 22 /* DMA7 Interrupt (UART TX) */ -#define IRQ_TMR0 23 /* Timer 0 */ -#define IRQ_TMR1 24 /* Timer 1 */ -#define IRQ_TMR2 25 /* Timer 2 */ -#define IRQ_PROG_INTA 26 /* Programmable Flags A (8) */ -#define IRQ_PROG_INTB 27 /* Programmable Flags B (8) */ -#define IRQ_MEM_DMA0 28 /* DMA8/9 Interrupt (Memory DMA Stream 0) */ -#define IRQ_MEM_DMA1 29 /* DMA10/11 Interrupt (Memory DMA Stream 1) */ -#define IRQ_WATCH 30 /* Watch Dog Timer */ -#define IRQ_SW_INT1 31 /* Software Int 1 */ -#define IRQ_SW_INT2 32 /* Software Int 2 (reserved for SYSCALL) */ - -#define IRQ_UART_RX_BIT 0x4000 -#define IRQ_UART_TX_BIT 0x8000 -#define IRQ_UART_ERROR_BIT 0x40 - -#define IVG7 7 -#define IVG8 8 -#define IVG9 9 -#define IVG10 10 -#define IVG11 11 -#define IVG12 12 -#define IVG13 13 -#define IVG14 14 -#define IVG15 15 -#define SYS_IRQS 33 - -#endif diff --git a/include/asm-blackfin/cpu/bf533_rtc.h b/include/asm-blackfin/cpu/bf533_rtc.h deleted file mode 100644 index bc09922a5e..0000000000 --- a/include/asm-blackfin/cpu/bf533_rtc.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * U-boot - bf533_rtc.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BF533_RTC_H_ -#define _BF533_RTC_H_ - -void rtc_init(void); -void wait_for_complete(void); -void rtc_reset(void); - -#define MIN_TO_SECS(_x_) (60 * _x_) -#define HRS_TO_SECS(_x_) (60 * 60 * _x_) -#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_) - -#define NUM_SECS_IN_DAY (24 * 3600) -#define NUM_SECS_IN_HOUR (3600) -#define NUM_SECS_IN_MIN (60) - -/* Shift values for RTC_STAT register */ -#define DAY_BITS_OFF 17 -#define HOUR_BITS_OFF 12 -#define MIN_BITS_OFF 6 -#define SEC_BITS_OFF 0 - -#endif diff --git a/include/asm-blackfin/cpu/bf533_serial.h b/include/asm-blackfin/cpu/bf533_serial.h deleted file mode 100644 index d5e162a8f9..0000000000 --- a/include/asm-blackfin/cpu/bf533_serial.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * U-boot bf533_serial.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#ifndef _BF533_SERIAL_H_ -#define _BF533_SERIAL_H_ - -#define BYTE_REF(addr) (*((volatile char*)addr)) -#define HALFWORD_REF(addr) (*((volatile short*)addr)) -#define WORD_REF(addr) (*((volatile long*)addr)) - -#define UART_THR_LO HALFWORD_REF(UART_THR) -#define UART_RBR_LO HALFWORD_REF(UART_RBR) -#define UART_DLL_LO HALFWORD_REF(UART_DLL) -#define UART_IER_LO HALFWORD_REF(UART_IER) -#define UART_IER_ERBFI 0x01 -#define UART_IER_ETBEI 0x02 -#define UART_IER_ELSI 0x04 -#define UART_IER_EDDSI 0x08 - -#define UART_DLH_LO HALFWORD_REF(UART_DLH) -#define UART_IIR_LO HALFWORD_REF(UART_IIR) -#define UART_IIR_NOINT 0x01 -#define UART_IIR_STATUS 0x06 -#define UART_IIR_LSR 0x06 -#define UART_IIR_RBR 0x04 -#define UART_IIR_THR 0x02 -#define UART_IIR_MSR 0x00 - -#define UART_LCR_LO HALFWORD_REF(UART_LCR) -#define UART_LCR_WLS5 0 -#define UART_LCR_WLS6 0x01 -#define UART_LCR_WLS7 0x02 -#define UART_LCR_WLS8 0x03 -#define UART_LCR_STB 0x04 -#define UART_LCR_PEN 0x08 -#define UART_LCR_EPS 0x10 -#define UART_LCR_SP 0x20 -#define UART_LCR_SB 0x40 -#define UART_LCR_DLAB 0x80 - -#define UART_MCR_LO HALFWORD_REF(UART_MCR) - -#define UART_LSR_LO HALFWORD_REF(UART_LSR) -#define UART_LSR_DR 0x01 -#define UART_LSR_OE 0x02 -#define UART_LSR_PE 0x04 -#define UART_LSR_FE 0x08 -#define UART_LSR_BI 0x10 -#define UART_LSR_THRE 0x20 -#define UART_LSR_TEMT 0x40 - -#define UART_MSR_LO HALFWORD_REF(UART_MSR) -#define UART_SCR_LO HALFWORD_REF(UART_SCR) -#define UART_GCTL_LO HALFWORD_REF(UART_GCTL) -#define UART_GCTL_UCEN 0x01 - -#endif diff --git a/include/asm-blackfin/cpu/cdefBF531.h b/include/asm-blackfin/cpu/cdefBF531.h deleted file mode 100644 index 68d841d185..0000000000 --- a/include/asm-blackfin/cpu/cdefBF531.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * cdefBF531.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _CDEFBF531_H -#define _CDEFBF531_H - -#include - -#endif /* _CDEFBF531_H */ diff --git a/include/asm-blackfin/cpu/cdefBF532.h b/include/asm-blackfin/cpu/cdefBF532.h deleted file mode 100644 index a4d422f765..0000000000 --- a/include/asm-blackfin/cpu/cdefBF532.h +++ /dev/null @@ -1,398 +0,0 @@ -/* - * cdefBF532.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _CDEF_BF532_H -#define _CDEF_BF532_H - -/* - * #if !defined(__ADSPLPBLACKFIN__) - * #warning cdefBF532.h should only be included for 532 compatible chips. - * #endif - */ - -/* include all Core registers and bit definitions */ -#include - -/* include core specific register pointer definitions */ -#include - -/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ -#define pPLL_CTL ((volatile unsigned short *)PLL_CTL) -#define pPLL_STAT ((volatile unsigned short *)PLL_STAT) -#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT) -#define pCHIPID ((volatile unsigned long *)CHIPID) -#define pSWRST ((volatile unsigned short *)SWRST) -#define pSYSCR ((volatile unsigned short *)SYSCR) -#define pPLL_DIV ((volatile unsigned short *)PLL_DIV) -#define pVR_CTL ((volatile unsigned short *)VR_CTL) - -/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ -#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0) -#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1) -#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2) -#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3) -#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK) -#define pSIC_ISR ((volatile unsigned long *)SIC_ISR) -#define pSIC_IWR ((volatile unsigned long *)SIC_IWR) - -/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */ -#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL) -#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT) -#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT) - -/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */ -#define pRTC_STAT ((volatile unsigned long *)RTC_STAT) -#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL) -#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT) -#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT) -#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM) -#define pRTC_FAST ((volatile unsigned short *)RTC_FAST) -#define pRTC_PREN ((volatile unsigned short *)RTC_PREN) - -/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ -#define pFIO_DIR ((volatile unsigned short *)FIO_DIR) -#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C) -#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S) -#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C) -#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S) -#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C) -#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S) -#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR) -#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE) -#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH) -#define pFIO_INEN ((volatile unsigned short *)FIO_INEN) -#define pFIO_FLAG_D ((volatile unsigned short *)FIO_FLAG_D) -#define pFIO_FLAG_T ((volatile unsigned short *)FIO_FLAG_T) -#define pFIO_MASKA_D ((volatile unsigned short *)FIO_MASKA_D) -#define pFIO_MASKA_T ((volatile unsigned short *)FIO_MASKA_T) -#define pFIO_MASKB_D ((volatile unsigned short *)FIO_MASKB_D) -#define pFIO_MASKB_T ((volatile unsigned short *)FIO_MASKB_T) - -/* DMA Test Registers */ -#define pDMA_CCOMP ((volatile unsigned long *)DMA_CCOMP) -#define pDMA_ACOMP ((volatile unsigned long *)DMA_ACOMP) -#define pDMA_MISR ((volatile unsigned long *)DMA_MISR) -#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER) -#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT) -#define pDMA_TMODE ((volatile unsigned short *)DMA_TMODE) -#define pDMA_TMCHAN ((volatile unsigned short *)DMA_TMCHAN) -#define pDMA_TMSTAT ((volatile unsigned short *)DMA_TMSTAT) -#define pDMA_TMBD ((volatile unsigned short *)DMA_TMBD) -#define pDMA_TMM0D ((volatile unsigned short *)DMA_TMM0D) -#define pDMA_TMM1D ((volatile unsigned short *)DMA_TMM1D) -#define pDMA_TMMA ((volatile void **)DMA_TMMA) - -/* DMA Controller */ -#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG) -#define pDMA0_NEXT_DESC_PTR ((volatile void **)DMA0_NEXT_DESC_PTR) -#define pDMA0_START_ADDR ((volatile void **)DMA0_START_ADDR) -#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT) -#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT) -#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY) -#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY) -#define pDMA0_CURR_DESC_PTR ((volatile void **)DMA0_CURR_DESC_PTR) -#define pDMA0_CURR_ADDR ((volatile void **)DMA0_CURR_ADDR) -#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT) -#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT) -#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS) -#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP) - -#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG) -#define pDMA1_NEXT_DESC_PTR ((volatile void **)DMA1_NEXT_DESC_PTR) -#define pDMA1_START_ADDR ((volatile void **)DMA1_START_ADDR) -#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT) -#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT) -#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY) -#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY) -#define pDMA1_CURR_DESC_PTR ((volatile void **)DMA1_CURR_DESC_PTR) -#define pDMA1_CURR_ADDR ((volatile void **)DMA1_CURR_ADDR) -#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT) -#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT) -#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS) -#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP) - -#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG) -#define pDMA2_NEXT_DESC_PTR ((volatile void **)DMA2_NEXT_DESC_PTR) -#define pDMA2_START_ADDR ((volatile void **)DMA2_START_ADDR) -#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT) -#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT) -#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY) -#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY) -#define pDMA2_CURR_DESC_PTR ((volatile void **)DMA2_CURR_DESC_PTR) -#define pDMA2_CURR_ADDR ((volatile void **)DMA2_CURR_ADDR) -#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT) -#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT) -#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS) -#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP) - -#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG) -#define pDMA3_NEXT_DESC_PTR ((volatile void **)DMA3_NEXT_DESC_PTR) -#define pDMA3_START_ADDR ((volatile void **)DMA3_START_ADDR) -#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT) -#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT) -#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY) -#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY) -#define pDMA3_CURR_DESC_PTR ((volatile void **)DMA3_CURR_DESC_PTR) -#define pDMA3_CURR_ADDR ((volatile void **)DMA3_CURR_ADDR) -#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT) -#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT) -#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS) -#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP) - -#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG) -#define pDMA4_NEXT_DESC_PTR ((volatile void **)DMA4_NEXT_DESC_PTR) -#define pDMA4_START_ADDR ((volatile void **)DMA4_START_ADDR) -#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT) -#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT) -#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY) -#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY) -#define pDMA4_CURR_DESC_PTR ((volatile void **)DMA4_CURR_DESC_PTR) -#define pDMA4_CURR_ADDR ((volatile void **)DMA4_CURR_ADDR) -#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT) -#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT) -#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS) -#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP) - -#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG) -#define pDMA5_NEXT_DESC_PTR ((volatile void **)DMA5_NEXT_DESC_PTR) -#define pDMA5_START_ADDR ((volatile void **)DMA5_START_ADDR) -#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT) -#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT) -#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY) -#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY) -#define pDMA5_CURR_DESC_PTR ((volatile void **)DMA5_CURR_DESC_PTR) -#define pDMA5_CURR_ADDR ((volatile void **)DMA5_CURR_ADDR) -#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT) -#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT) -#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS) -#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP) - -#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG) -#define pDMA6_NEXT_DESC_PTR ((volatile void **)DMA6_NEXT_DESC_PTR) -#define pDMA6_START_ADDR ((volatile void **)DMA6_START_ADDR) -#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT) -#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT) -#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY) -#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY) -#define pDMA6_CURR_DESC_PTR ((volatile void **)DMA6_CURR_DESC_PTR) -#define pDMA6_CURR_ADDR ((volatile void **)DMA6_CURR_ADDR) -#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT) -#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT) -#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS) -#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP) - -#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG) -#define pDMA7_NEXT_DESC_PTR ((volatile void **)DMA7_NEXT_DESC_PTR) -#define pDMA7_START_ADDR ((volatile void **)DMA7_START_ADDR) -#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT) -#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT) -#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY) -#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY) -#define pDMA7_CURR_DESC_PTR ((volatile void **)DMA7_CURR_DESC_PTR) -#define pDMA7_CURR_ADDR ((volatile void **)DMA7_CURR_ADDR) -#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT) -#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT) -#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS) -#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP) - -#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG) -#define pMDMA_D1_NEXT_DESC_PTR ((volatile void **)MDMA_D1_NEXT_DESC_PTR) -#define pMDMA_D1_START_ADDR ((volatile void **)MDMA_D1_START_ADDR) -#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT) -#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT) -#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY) -#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY) -#define pMDMA_D1_CURR_DESC_PTR ((volatile void **)MDMA_D1_CURR_DESC_PTR) -#define pMDMA_D1_CURR_ADDR ((volatile void **)MDMA_D1_CURR_ADDR) -#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT) -#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT) -#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS) -#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP) - -#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG) -#define pMDMA_S1_NEXT_DESC_PTR ((volatile void **)MDMA_S1_NEXT_DESC_PTR) -#define pMDMA_S1_START_ADDR ((volatile void **)MDMA_S1_START_ADDR) -#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT) -#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT) -#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY) -#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY) -#define pMDMA_S1_CURR_DESC_PTR ((volatile void **)MDMA_S1_CURR_DESC_PTR) -#define pMDMA_S1_CURR_ADDR ((volatile void **)MDMA_S1_CURR_ADDR) -#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT) -#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT) -#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS) -#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP) - -#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG) -#define pMDMA_D0_NEXT_DESC_PTR ((volatile void **)MDMA_D0_NEXT_DESC_PTR) -#define pMDMA_D0_START_ADDR ((volatile void **)MDMA_D0_START_ADDR) -#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT) -#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT) -#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY) -#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY) -#define pMDMA_D0_CURR_DESC_PTR ((volatile void **)MDMA_D0_CURR_DESC_PTR) -#define pMDMA_D0_CURR_ADDR ((volatile void **)MDMA_D0_CURR_ADDR) -#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT) -#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT) -#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS) -#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP) - -#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG) -#define pMDMA_S0_NEXT_DESC_PTR ((volatile void **)MDMA_S0_NEXT_DESC_PTR) -#define pMDMA_S0_START_ADDR ((volatile void **)MDMA_S0_START_ADDR) -#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT) -#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT) -#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY) -#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY) -#define pMDMA_S0_CURR_DESC_PTR ((volatile void **)MDMA_S0_CURR_DESC_PTR) -#define pMDMA_S0_CURR_ADDR ((volatile void **)MDMA_S0_CURR_ADDR) -#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT) -#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT) -#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS) -#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP) - -/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */ -#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL) -#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0) -#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1) - -/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */ -/* #define L1SBAR 0xFFC04840 */ /* L1 SRAM Base Address Register */ -/* #define L1CSR 0xFFC04844 */ /* L1 SRAM Control Initialization Register */ - -/* - * #define pDB_ACOMP ((volatile void **)DB_ACOMP) - * #define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP) - */ - -/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */ -#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL) -#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC) -#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT) -#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL) - -/* UART Controller */ -#define pUART_THR ((volatile unsigned short *)UART_THR) -#define pUART_RBR ((volatile unsigned short *)UART_RBR) -#define pUART_DLL ((volatile unsigned short *)UART_DLL) -#define pUART_IER ((volatile unsigned short *)UART_IER) -#define pUART_DLH ((volatile unsigned short *)UART_DLH) -#define pUART_IIR ((volatile unsigned short *)UART_IIR) -#define pUART_LCR ((volatile unsigned short *)UART_LCR) -#define pUART_MCR ((volatile unsigned short *)UART_MCR) -#define pUART_LSR ((volatile unsigned short *)UART_LSR) - -/* - * #define UART_MSR - */ -#define pUART_SCR ((volatile unsigned short *)UART_SCR) -#define pUART_GCTL ((volatile unsigned short *)UART_GCTL) - -/* SPI Controller */ -#define pSPI_CTL ((volatile unsigned short *)SPI_CTL) -#define pSPI_FLG ((volatile unsigned short *)SPI_FLG) -#define pSPI_STAT ((volatile unsigned short *)SPI_STAT) -#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR) -#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR) -#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD) -#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW) - -/* TIMER 0, 1, 2 Registers */ -#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG) -#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER) -#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD) -#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH) - -#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG) -#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER) -#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD) -#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH) - -#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG) -#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER) -#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD) -#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH) - -#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE) -#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE) -#define pTIMER_STATUS ((volatile unsigned short *)TIMER_STATUS) - -/* SPORT0 Controller */ -#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1) -#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2) -#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV) -#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV) -#define pSPORT0_TX ((volatile long *)SPORT0_TX) -#define pSPORT0_RX ((volatile long *)SPORT0_RX) -#define pSPORT0_TX32 ((volatile long *)SPORT0_TX) -#define pSPORT0_RX32 ((volatile long *)SPORT0_RX) -#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX) -#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX) -#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1) -#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2) -#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV) -#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV) -#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT) -#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL) -#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1) -#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2) -#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0) -#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1) -#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2) -#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3) -#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0) -#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1) -#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2) -#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3) - -/* SPORT1 Controller */ -#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1) -#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2) -#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV) -#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV) -#define pSPORT1_TX ((volatile long *)SPORT1_TX) -#define pSPORT1_RX ((volatile long *)SPORT1_RX) -#define pSPORT1_TX32 ((volatile long *)SPORT1_TX) -#define pSPORT1_RX32 ((volatile long *)SPORT1_RX) -#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX) -#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX) -#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1) -#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2) -#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV) -#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV) -#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT) -#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL) -#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1) -#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2) -#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0) -#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1) -#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2) -#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3) -#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0) -#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1) -#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2) -#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3) - -/* Parallel Peripheral Interface (PPI) */ -#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL) -#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS) -#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY) -#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT) -#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME) - -#endif /* _CDEF_BF532_H */ diff --git a/include/asm-blackfin/cpu/cdefBF533.h b/include/asm-blackfin/cpu/cdefBF533.h deleted file mode 100644 index 8c751e6073..0000000000 --- a/include/asm-blackfin/cpu/cdefBF533.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * cdefBF533.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _CDEFBF533_H -#define _CDEFBF533_H - -#include - -#endif /* _CDEFBF533_H */ diff --git a/include/asm-blackfin/cpu/cdefBF53x.h b/include/asm-blackfin/cpu/cdefBF53x.h deleted file mode 100644 index db4eaa9cf2..0000000000 --- a/include/asm-blackfin/cpu/cdefBF53x.h +++ /dev/null @@ -1,32 +0,0 @@ -/************************************************************************ - * - * cdefBF53x.h - * - * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved. - * - ************************************************************************/ - -#ifndef _CDEFBF53x_H -#define _CDEFBF53x_H - -#if defined(__ADSPBF531__) - #include -#elif defined(__ADSPBF532__) - #include -#elif defined(__ADSPBF533__) - #include -#elif defined(__ADSPBF561__) - #include -#elif defined(__ADSPBF535__) - #include -#elif defined(__AD6532__) - #include -#else - #if defined(__ADSPLPBLACKFIN__) - #include - #else - #include - #endif -#endif - -#endif /* _CDEFBF53x_H */ diff --git a/include/asm-blackfin/cpu/cdef_LPBlackfin.h b/include/asm-blackfin/cpu/cdef_LPBlackfin.h deleted file mode 100644 index e6471cbcb3..0000000000 --- a/include/asm-blackfin/cpu/cdef_LPBlackfin.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * cdef_LPBlackfin.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _CDEF_LPBLACKFIN_H -#define _CDEF_LPBLACKFIN_H - -/* - * #if !defined(__ADSPLPBLACKFIN__) - * #warning cdef_LPBlackfin.h should only be included for 532 compatible chips. - * #endif - */ -#include - -/* Cache & SRAM Memory */ -#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS) -#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL) -#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS) -#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR) - -/* #define MMR_TIMEOUT 0xFFE00010 */ /* Memory-Mapped Register Timeout Register */ -#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0) -#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1) -#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2) -#define pDCPLB_ADDR3 ((volatile void **)DCPLB_ADDR3) -#define pDCPLB_ADDR4 ((volatile void **)DCPLB_ADDR4) -#define pDCPLB_ADDR5 ((volatile void **)DCPLB_ADDR5) -#define pDCPLB_ADDR6 ((volatile void **)DCPLB_ADDR6) -#define pDCPLB_ADDR7 ((volatile void **)DCPLB_ADDR7) -#define pDCPLB_ADDR8 ((volatile void **)DCPLB_ADDR8) -#define pDCPLB_ADDR9 ((volatile void **)DCPLB_ADDR9) -#define pDCPLB_ADDR10 ((volatile void **)DCPLB_ADDR10) -#define pDCPLB_ADDR11 ((volatile void **)DCPLB_ADDR11) -#define pDCPLB_ADDR12 ((volatile void **)DCPLB_ADDR12) -#define pDCPLB_ADDR13 ((volatile void **)DCPLB_ADDR13) -#define pDCPLB_ADDR14 ((volatile void **)DCPLB_ADDR14) -#define pDCPLB_ADDR15 ((volatile void **)DCPLB_ADDR15) -#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0) -#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1) -#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2) -#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3) -#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4) -#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5) -#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6) -#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7) -#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8) -#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9) -#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10) -#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11) -#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12) -#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13) -#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14) -#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15) -#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND) - -/* #define DTEST_INDEX 0xFFE00304 */ /* Data Test Index Register */ -#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0) -#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1) - -/* - * # define DTEST_DATA2 0xFFE00408 Data Test Data Register - * #define DTEST_DATA3 0xFFE0040C Data Test Data Register - */ -#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL) -#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS) -#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR) -#define pICPLB_ADDR0 ((volatile void **)ICPLB_ADDR0) -#define pICPLB_ADDR1 ((volatile void **)ICPLB_ADDR1) -#define pICPLB_ADDR2 ((volatile void **)ICPLB_ADDR2) -#define pICPLB_ADDR3 ((volatile void **)ICPLB_ADDR3) -#define pICPLB_ADDR4 ((volatile void **)ICPLB_ADDR4) -#define pICPLB_ADDR5 ((volatile void **)ICPLB_ADDR5) -#define pICPLB_ADDR6 ((volatile void **)ICPLB_ADDR6) -#define pICPLB_ADDR7 ((volatile void **)ICPLB_ADDR7) -#define pICPLB_ADDR8 ((volatile void **)ICPLB_ADDR8) -#define pICPLB_ADDR9 ((volatile void **)ICPLB_ADDR9) -#define pICPLB_ADDR10 ((volatile void **)ICPLB_ADDR10) -#define pICPLB_ADDR11 ((volatile void **)ICPLB_ADDR11) -#define pICPLB_ADDR12 ((volatile void **)ICPLB_ADDR12) -#define pICPLB_ADDR13 ((volatile void **)ICPLB_ADDR13) -#define pICPLB_ADDR14 ((volatile void **)ICPLB_ADDR14) -#define pICPLB_ADDR15 ((volatile void **)ICPLB_ADDR15) -#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0) -#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1) -#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2) -#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3) -#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4) -#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5) -#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6) -#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7) -#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8) -#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9) -#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10) -#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11) -#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12) -#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13) -#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14) -#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15) -#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND) - -/* #define ITEST_INDEX 0xFFE01304 */ /* Instruction Test Index Register */ -#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0) -#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1) - -/* Event/Interrupt Registers */ -#define pEVT0 ((volatile void **)EVT0) -#define pEVT1 ((volatile void **)EVT1) -#define pEVT2 ((volatile void **)EVT2) -#define pEVT3 ((volatile void **)EVT3) -#define pEVT4 ((volatile void **)EVT4) -#define pEVT5 ((volatile void **)EVT5) -#define pEVT6 ((volatile void **)EVT6) -#define pEVT7 ((volatile void **)EVT7) -#define pEVT8 ((volatile void **)EVT8) -#define pEVT9 ((volatile void **)EVT9) -#define pEVT10 ((volatile void **)EVT10) -#define pEVT11 ((volatile void **)EVT11) -#define pEVT12 ((volatile void **)EVT12) -#define pEVT13 ((volatile void **)EVT13) -#define pEVT14 ((volatile void **)EVT14) -#define pEVT15 ((volatile void **)EVT15) -#define pIMASK ((volatile unsigned long *)IMASK) -#define pIPEND ((volatile unsigned long *)IPEND) -#define pILAT ((volatile unsigned long *)ILAT) - -/* Core Timer Registers */ -#define pTCNTL ((volatile unsigned long *)TCNTL) -#define pTPERIOD ((volatile unsigned long *)TPERIOD) -#define pTSCALE ((volatile unsigned long *)TSCALE) -#define pTCOUNT ((volatile unsigned long *)TCOUNT) - -/* Debug/MP/Emulation Registers */ -#define pDSPID ((volatile unsigned long *)DSPID) -#define pDBGCTL ((volatile unsigned long *)DBGCTL) -#define pDBGSTAT ((volatile unsigned long *)DBGSTAT) -#define pEMUDAT ((volatile unsigned long *)EMUDAT) - -/* Trace Buffer Registers */ -#define pTBUFCTL ((volatile unsigned long *)TBUFCTL) -#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT) -#define pTBUF ((volatile void **)TBUF) - -/* Watch Point Control Registers */ -#define pWPIACTL ((volatile unsigned long *)WPIACTL) -#define pWPIA0 ((volatile void **)WPIA0) -#define pWPIA1 ((volatile void **)WPIA1) -#define pWPIA2 ((volatile void **)WPIA2) -#define pWPIA3 ((volatile void **)WPIA3) -#define pWPIA4 ((volatile void **)WPIA4) -#define pWPIA5 ((volatile void **)WPIA5) -#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0) -#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1) -#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2) -#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3) -#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4) -#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5) -#define pWPDACTL ((volatile unsigned long *)WPDACTL) -#define pWPDA0 ((volatile void **)WPDA0) -#define pWPDA1 ((volatile void **)WPDA1) -#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0) -#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1) -#define pWPSTAT ((volatile unsigned long *)WPSTAT) - -/* Performance Monitor Registers */ -#define pPFCTL ((volatile unsigned long *)PFCTL) -#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0) -#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1) - -/* #define IPRIO 0xFFE02110 */ /* Core Interrupt Priority Register */ - -#endif /* _CDEF_LPBLACKFIN_H */ diff --git a/include/asm-blackfin/cpu/defBF531.h b/include/asm-blackfin/cpu/defBF531.h deleted file mode 100644 index 6c7cd5a6db..0000000000 --- a/include/asm-blackfin/cpu/defBF531.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * defBF531.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _DEFBF531_H -#define _DEFBF531_H - -#include - -#endif /* _DEFBF531_H */ diff --git a/include/asm-blackfin/cpu/defBF532.h b/include/asm-blackfin/cpu/defBF532.h deleted file mode 100644 index 26a5fe6442..0000000000 --- a/include/asm-blackfin/cpu/defBF532.h +++ /dev/null @@ -1,1159 +0,0 @@ -/* - * defBF532.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */ - -#ifndef _DEF_BF532_H -#define _DEF_BF532_H - -/* - * #if !defined(__ADSPLPBLACKFIN__) - * #warning defBF532.h should only be included for 532 compatible chips - * #endif - */ - -/* include all Core registers and bit definitions */ -#include - -/* Helper macros - * usage: - * P0.H = HI(UART_THR); - * P0.L = LO(UART_THR); - */ - -#define LO(con32) ((con32) & 0xFFFF) -#define lo(con32) ((con32) & 0xFFFF) -#define HI(con32) (((con32) >> 16) & 0xFFFF) -#define hi(con32) (((con32) >> 16) & 0xFFFF) - -/* - * System MMR Register Map - */ - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ -#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ -#define CHIPID 0xFFC00014 /* Chip ID register (32-bit) */ -#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ -#define SYSCR 0xFFC00104 /* System Configuration register */ - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ -#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ - -/* UART Controller (0xFFC00400 - 0xFFC004FF) */ -#define UART_THR 0xFFC00400 /* Transmit Holding register */ -#define UART_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART_LCR 0xFFC0040C /* Line Control Register */ -#define UART_MCR 0xFFC00410 /* Modem Control Register */ -#define UART_LSR 0xFFC00414 /* Line Status Register */ -/* #define UART_MSR 0xFFC00418 */ /* Modem Status Register (UNUSED in ADSP-BF532) */ -#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART_GCTL 0xFFC00424 /* Global Control Register */ - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define SPI_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI_STAT 0xFFC00508 /* SPI Status register */ -#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ - -/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ - -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ - -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ - -#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */ -#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ -#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ -#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ -#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ -#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ -#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ -#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ -#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ -#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ -#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ -#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ -#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ -#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ -#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ -#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ -#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ -#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ - -/* Asynchronous Memory Controller - External Bus Interface Unit */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ - -/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ - -/* DMA Test Registers */ -#define DMA_CCOMP 0xFFC00B04 /* DMA Cycle Count Register */ -#define DMA_ACOMP 0xFFC00B00 /* Debug Compare Address Register */ -#define DMA_MISR 0xFFC00B08 /* MISR Register */ -#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ -#define DMA_TMODE 0xFFC00B14 /* DMA Test Modes Register */ -#define DMA_TMCHAN 0xFFC00B18 /* DMA Testmode Selected Channel Register */ -#define DMA_TMSTAT 0xFFC00B1C /* DMA Testmode Channel Status Register */ -#define DMA_TMBD 0xFFC00B20 /* DMA Testmode DAB Bus Data Register */ -#define DMA_TMM0D 0xFFC00B24 /* DMA Testmode Mem0 Data Register */ -#define DMA_TMM1D 0xFFC00B28 /* DMA Testmode Mem1 Data Register */ -#define DMA_TMMA 0xFFC00B2C /* DMA Testmode Memory Address Register */ - -/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ - -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ - -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ - -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ - -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ - -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ - -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ - -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ - -#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */ -#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */ - -#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */ -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */ -#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */ -#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */ - -#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */ -#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */ - -#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */ -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */ -#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */ -#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */ - -/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ - -/* - * System MMR Register Bits - */ -/* - * PLL AND RESET MASKS - */ - -/* PLL_CTL Masks */ -#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ -#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ -#define PLL_OFF 0x00000002 /* Shut off PLL clocks */ -#define STOPCK_OFF 0x00000008 /* Core clock off */ -#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ -#define BYPASS 0x00000100 /* Bypass the PLL */ - -/* PLL_DIV Masks */ -#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ - -#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ -#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ -#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ -#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ - -/* SWRST Mask */ -#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ - -/* - * SYSTEM INTERRUPT CONTROLLER MASKS - */ - -/* SIC_IAR0 Masks */ -#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */ -#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ -#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ -#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */ -#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ -#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ -#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ -#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ - -/* SIC_IAR1 Masks */ -#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */ -#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ -#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ -#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */ -#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ -#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ -#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ -#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ - -/* SIC_IAR2 Masks */ -#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */ -#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ -#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ -#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */ -#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ -#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ -#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ -#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ - -/* SIC_IMASK Masks */ -#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ -#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ -#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ - -/* SIC_IWR Masks */ -#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ -#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ -#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ - -/* - * WATCHDOG TIMER MASKS - */ -/* Watchdog Timer WDOG_CTL Register */ -#define ICTL(x) ((x<<1) & 0x0006) -#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */ -#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */ -#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */ -#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */ - -#define TMR_EN 0x0000 -#define TMR_DIS 0x0AD0 -#define TRO 0x8000 - -#define ICTL_P0 0x01 -#define ICTL_P1 0x02 -#define TRO_P 0x0F - -/* RTC_STAT and RTC_ALARM register */ -#define RTSEC 0x0000003F /* Real-Time Clock Seconds */ -#define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */ -#define RTHR 0x0001F000 /* Real-Time Clock Hours */ -#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */ - -/* RTC_ICTL register */ -#define SWIE 0x0001 /* Stopwatch Interrupt Enable */ -#define AIE 0x0002 /* Alarm Interrupt Enable */ -#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */ -#define MIE 0x0008 /* Minutes Interrupt Enable */ -#define HIE 0x0010 /* Hours Interrupt Enable */ -#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */ -#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ -#define WCIE 0x8000 /* Write Complete Interrupt Enable */ - -/* RTC_ISTAT register */ -#define SWEF 0x0001 /* Stopwatch Event Flag */ -#define AEF 0x0002 /* Alarm Event Flag */ -#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */ -#define MEF 0x0008 /* Minutes Event Flag */ -#define HEF 0x0010 /* Hours Event Flag */ -#define DEF 0x0020 /* 24 Hours (Days) Event Flag */ -#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */ -#define WPS 0x4000 /* Write Pending Status (RO) */ -#define WCOM 0x8000 /* Write Complete */ - -/* RTC_FAST Mask (RTC_PREN Mask) */ -#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */ -#define PREN 0x00000001 /* ** Must be set after power-up for proper operation of RTC */ - -/* - * UART CONTROLLER MASKS - */ - -/* UART_LCR Register */ -#define DLAB 0x80 -#define SB 0x40 -#define STP 0x20 -#define EPS 0x10 -#define PEN 0x08 -#define STB 0x04 -#define WLS(x) ((x-5) & 0x03) - -#define DLAB_P 0x07 -#define SB_P 0x06 -#define STP_P 0x05 -#define EPS_P 0x04 -#define PEN_P 0x03 -#define STB_P 0x02 -#define WLS_P1 0x01 -#define WLS_P0 0x00 - -/* UART_MCR Register */ -#define LOOP_ENA 0x10 -#define LOOP_ENA_P 0x04 - -/* UART_LSR Register */ -#define TEMT 0x40 -#define THRE 0x20 -#define BI 0x10 -#define FE 0x08 -#define PE 0x04 -#define OE 0x02 -#define DR 0x01 - -#define TEMP_P 0x06 -#define THRE_P 0x05 -#define BI_P 0x04 -#define FE_P 0x03 -#define PE_P 0x02 -#define OE_P 0x01 -#define DR_P 0x00 - -/* UART_IER Register */ -#define ELSI 0x04 -#define ETBEI 0x02 -#define ERBFI 0x01 - -#define ELSI_P 0x02 -#define ETBEI_P 0x01 -#define ERBFI_P 0x00 - -/* UART_IIR Register */ -#define STATUS(x) ((x << 1) & 0x06) -#define NINT 0x01 -#define STATUS_P1 0x02 -#define STATUS_P0 0x01 -#define NINT_P 0x00 - -/* UART_GCTL Register */ -#define FFE 0x20 -#define FPE 0x10 -#define RPOLC 0x08 -#define TPOLC 0x04 -#define IREN 0x02 -#define UCEN 0x01 - -#define FFE_P 0x05 -#define FPE_P 0x04 -#define RPOLC_P 0x03 -#define TPOLC_P 0x02 -#define IREN_P 0x01 -#define UCEN_P 0x00 - -/* - * SERIAL PORT MASKS - */ -/* SPORTx_TCR1 Masks */ -#define TSPEN 0x0001 /* TX enable */ -#define ITCLK 0x0002 /* Internal TX Clock Select */ -#define TDTYPE 0x000C /* TX Data Formatting Select */ -#define TLSBIT 0x0010 /* TX Bit Order */ -#define ITFS 0x0200 /* Internal TX Frame Sync Select */ -#define TFSR 0x0400 /* TX Frame Sync Required Select */ -#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ -#define LTFS 0x1000 /* Low TX Frame Sync Select */ -#define LATFS 0x2000 /* Late TX Frame Sync Select */ -#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ - -/* SPORTx_TCR2 Masks */ -#define SLEN 0x001F /*TX Word Length */ -#define TXSE 0x0100 /*TX Secondary Enable */ -#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ -#define TRFST 0x0400 /*TX Right-First Data Order */ - -/* SPORTx_RCR1 Masks */ -#define RSPEN 0x0001 /* RX enable */ -#define IRCLK 0x0002 /* Internal RX Clock Select */ -#define RDTYPE 0x000C /* RX Data Formatting Select */ -#define RULAW 0x0008 /* u-Law enable */ -#define RALAW 0x000C /* A-Law enable */ -#define RLSBIT 0x0010 /* RX Bit Order */ -#define IRFS 0x0200 /* Internal RX Frame Sync Select */ -#define RFSR 0x0400 /* RX Frame Sync Required Select */ -#define LRFS 0x1000 /* Low RX Frame Sync Select */ -#define LARFS 0x2000 /* Late RX Frame Sync Select */ -#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ - -/* SPORTx_RCR2 Masks */ -#define SLEN 0x001F /* RX Word Length */ -#define RXSE 0x0100 /* RX Secondary Enable */ -#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ -#define RRFST 0x0400 /* Right-First Data Order */ - -/* SPORTx_STAT Masks */ -#define RXNE 0x0001 /* RX FIFO Not Empty Status */ -#define RUVF 0x0002 /* RX Underflow Status */ -#define ROVF 0x0004 /* RX Overflow Status */ -#define TXF 0x0008 /* TX FIFO Full Status */ -#define TUVF 0x0010 /* TX Underflow Status */ -#define TOVF 0x0020 /* TX Overflow Status */ -#define TXHRE 0x0040 /* TX Hold Register Empty */ - -/* SPORTx_MCMC1 Masks */ -#define WSIZE 0x0000F000 /* Multichannel Window Size Field */ -#define WOFF 0x000003FF /* /Multichannel Window Offset Field */ - -/* SPORTx_MCMC2 Masks */ -#define MCCRM 0x00000003 /* Multichannel Clock Recovery Mode */ -#define MCDTXPE 0x00000004 /* Multichannel DMA Transmit Packing */ -#define MCDRXPE 0x00000008 /* Multichannel DMA Receive Packing */ -#define MCMEN 0x00000010 /* Multichannel Frame Mode Enable */ -#define FSDR 0x00000080 /* Multichannel Frame Sync to Data Relationship */ -#define MFD 0x0000F000 /* Multichannel Frame Delay */ - -/* - * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS - */ - -/* PPI_CONTROL Masks */ -#define PORT_EN 0x00000001 /* PPI Port Enable */ -#define PORT_DIR 0x00000002 /* PPI Port Direction */ -#define XFR_TYPE 0x0000000C /* PPI Transfer Type */ -#define PORT_CFG 0x00000030 /* PPI Port Configuration */ -#define FLD_SEL 0x00000040 /* PPI Active Field Select */ -#define PACK_EN 0x00000080 /* PPI Packing Mode */ -#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ -#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ -#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ -#define DLENGTH 0x00003800 /* PPI Data Length */ -#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ -#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ -#define POL 0x0000C000 /* PPI Signal Polarities */ - -/* PPI_STATUS Masks */ -#define FLD 0x00000400 /* Field Indicator */ -#define FT_ERR 0x00000800 /* Frame Track Error */ -#define OVR 0x00001000 /* FIFO Overflow Error */ -#define UNDR 0x00002000 /* FIFO Underrun Error */ -#define ERR_DET 0x00004000 /* Error Detected Indicator */ -#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ - -/* - * DMA CONTROLLER MASKS - */ - -/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ -#define DMAEN 0x00000001 /* Channel Enable */ -#define WNR 0x00000002 /* Channel Direction (W/R*) */ -#define WDSIZE_8 0x00000000 /* Word Size 8 bits */ -#define WDSIZE_16 0x00000004 /* Word Size 16 bits */ -#define WDSIZE_32 0x00000008 /* Word Size 32 bits */ -#define DMA2D 0x00000010 /* 2D/1D* Mode */ -#define RESTART 0x00000020 /* Restart */ -#define DI_SEL 0x00000040 /* Data Interrupt Select */ -#define DI_EN 0x00000080 /* Data Interrupt Enable */ -#define NDSIZE 0x00000900 /* Next Descriptor Size */ -#define FLOW 0x00007000 /* Flow Control */ - -#define DMAEN_P 0 /* Channel Enable */ -#define WNR_P 1 /* Channel Direction (W/R*) */ -#define DMA2D_P 4 /* 2D/1D* Mode */ -#define RESTART_P 5 /* Restart */ -#define DI_SEL_P 6 /* Data Interrupt Select */ -#define DI_EN_P 7 /* Data Interrupt Enable */ - -/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ -#define DMA_DONE 0x00000001 /* DMA Done Indicator */ -#define DMA_ERR 0x00000002 /* DMA Error Indicator */ -#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ -#define DMA_RUN 0x00000008 /* DMA Running Indicator */ - -#define DMA_DONE_P 0 /* DMA Done Indicator */ -#define DMA_ERR_P 1 /* DMA Error Indicator */ -#define DFETCH_P 2 /* Descriptor Fetch Indicator */ -#define DMA_RUN_P 3 /* DMA Running Indicator */ - -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ -#define CTYPE 0x00000040 /* DMA Channel Type Indicator */ -#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ -#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ -#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ -#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ -#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ -#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ -#define PMAP 0x00007000 /* DMA Peripheral Map Field */ - -/* - * GENERAL PURPOSE TIMER MASKS - */ - -/* PWM Timer bit definitions */ - -/* TIMER_ENABLE Register */ -#define TIMEN0 0x0001 -#define TIMEN1 0x0002 -#define TIMEN2 0x0004 - -#define TIMEN0_P 0x00 -#define TIMEN1_P 0x01 -#define TIMEN2_P 0x02 - -/* TIMER_DISABLE Register */ -#define TIMDIS0 0x0001 -#define TIMDIS1 0x0002 -#define TIMDIS2 0x0004 - -#define TIMDIS0_P 0x00 -#define TIMDIS1_P 0x01 -#define TIMDIS2_P 0x02 - -/* TIMER_STATUS Register */ -#define TIMIL0 0x0001 -#define TIMIL1 0x0002 -#define TIMIL2 0x0004 -#define TOVL_ERR0 0x0010 -#define TOVL_ERR1 0x0020 -#define TOVL_ERR2 0x0040 -#define TRUN0 0x1000 -#define TRUN1 0x2000 -#define TRUN2 0x4000 - -#define TIMIL0_P 0x00 -#define TIMIL1_P 0x01 -#define TIMIL2_P 0x02 -#define TOVL_ERR0_P 0x04 -#define TOVL_ERR1_P 0x05 -#define TOVL_ERR2_P 0x06 -#define TRUN0_P 0x0C -#define TRUN1_P 0x0D -#define TRUN2_P 0x0E - -/* TIMERx_CONFIG Registers */ -#define PWM_OUT 0x0001 -#define WDTH_CAP 0x0002 -#define EXT_CLK 0x0003 -#define PULSE_HI 0x0004 -#define PERIOD_CNT 0x0008 -#define IRQ_ENA 0x0010 -#define TIN_SEL 0x0020 -#define OUT_DIS 0x0040 -#define CLK_SEL 0x0080 -#define TOGGLE_HI 0x0100 -#define EMU_RUN 0x0200 -#define ERR_TYP(x) ((x & 0x03) << 14) - -#define TMODE_P0 0x00 -#define TMODE_P1 0x01 -#define PULSE_HI_P 0x02 -#define PERIOD_CNT_P 0x03 -#define IRQ_ENA_P 0x04 -#define TIN_SEL_P 0x05 -#define OUT_DIS_P 0x06 -#define CLK_SEL_P 0x07 -#define TOGGLE_HI_P 0x08 -#define EMU_RUN_P 0x09 -#define ERR_TYP_P0 0x0E -#define ERR_TYP_P1 0x0F - -/* - * PROGRAMMABLE FLAG MASKS - */ - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ -#define PF0_P 0 -#define PF1_P 1 -#define PF2_P 2 -#define PF3_P 3 -#define PF4_P 4 -#define PF5_P 5 -#define PF6_P 6 -#define PF7_P 7 -#define PF8_P 8 -#define PF9_P 9 -#define PF10_P 10 -#define PF11_P 11 -#define PF12_P 12 -#define PF13_P 13 -#define PF14_P 14 -#define PF15_P 15 - -/* - * SERIAL PERIPHERAL INTERFACE (SPI) MASKS - */ - -/* SPI_CTL Masks */ -#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ -#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ -#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ -#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ -#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ -#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ -#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ -#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ -#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ -#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ -#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ -#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ - -/* SPI_FLG Masks */ -#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_FLG Bit Positions */ -#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_STAT Masks */ -#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ -#define MODF 0x00000002 /* Set(=1)in a master device when some other device tries to become master */ -#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ -#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ -#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ -#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ -#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ - -/* - * ASYNCHRONOUS MEMORY CONTROLLER MASKS - */ - -/* AMGCTL Masks */ -#define AMCKEN 0x00000001 /* Enable CLKOUT */ -#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */ -#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ -#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ - -/* AMGCTL Bit Positions */ -#define AMCKEN_P 0x00000000 /* Enable CLKOUT */ -#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ -#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ -#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ - -/* AMBCTL0 Masks */ -#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ -#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ -#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ -#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ -#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ -#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ -#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ -#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ -#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ -#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ -#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ -#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ -#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ -#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ -#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ -#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ -#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ -#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ -#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ -#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ -#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ -#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ -#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ -#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ -#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ -#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ -#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ -#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ -#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ -#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ -#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ -#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ -#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ -#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ -#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ -#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ -#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ -#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ -#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ -#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ -#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ -#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ -#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ -#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ -#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ -#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ -#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ -#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ -#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ -#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ -#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ -#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ -#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ -#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ -#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ -#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ -#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ -#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ -#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ -#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ -#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ -#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ -#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ -#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ -#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ -#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ -#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ -#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ -#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ -#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ -#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ -#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ -#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ -#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ -#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ -#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ -#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ -#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ -#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ -#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ - -/* AMBCTL1 Masks */ -#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ -#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ -#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ -#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ -#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ -#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ -#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ -#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ -#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ -#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ -#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ -#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ -#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ -#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ -#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ -#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ -#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ -#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ -#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ -#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ -#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ -#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ -#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ -#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ -#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ -#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ -#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ -#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ -#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ -#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ -#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ -#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ -#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ -#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ -#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ -#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ -#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ -#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ -#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ -#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ -#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ -#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ -#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ -#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ -#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ -#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ -#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ -#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ -#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ -#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ -#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ -#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ -#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ -#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ -#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ -#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ -#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ -#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ -#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ -#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ -#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ -#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ -#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ -#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ -#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ -#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ -#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ -#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ -#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ -#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ -#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ -#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ - -/* - * SDRAM CONTROLLER MASKS - */ - -/* SDGCTL Masks */ -#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ -#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ -#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ -#define PFE 0x00000010 /* Enable SDRAM prefetch */ -#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ -#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ -#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ -#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ -#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ -#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ -#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ -#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ -#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ -#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ -#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ -#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ -#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ -#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ -#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ -#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ -#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ -#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ -#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ -#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ -#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ -#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ -#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ -#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ -#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ -#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ -#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ -#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ -#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ -#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ -#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ -#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ -#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ -#define PUPSD 0x00200000 /* Power-up start delay */ -#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ -#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ -#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ -#define EBUFE 0x02000000 /* Enable external buffering timing */ -#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ -#define EMREN 0x10000000 /* Extended mode register enable */ -#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ -#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ - -/* EBIU_SDBCTL Masks */ -#define EBE 0x00000001 /* Enable SDRAM external bank */ -#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ -#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ -#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ -#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ -#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ -#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ -#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ -#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ - -/* EBIU_SDSTAT Masks */ -#define SDCI 0x00000001 /* SDRAM controller is idle */ -#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ -#define SDPUA 0x00000004 /* SDRAM power up active */ -#define SDRS 0x00000008 /* SDRAM is in reset state */ -#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ -#define BGSTAT 0x00000020 /* Bus granted */ - -#endif /* _DEF_BF532_H */ diff --git a/include/asm-blackfin/cpu/defBF533.h b/include/asm-blackfin/cpu/defBF533.h deleted file mode 100644 index 90e50afa7f..0000000000 --- a/include/asm-blackfin/cpu/defBF533.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * defBF533.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _DEFBF533_H -#define _DEFBF533_H - -#include - -#endif /* _DEFBF533_H */ diff --git a/include/asm-blackfin/cpu/defBF533_extn.h b/include/asm-blackfin/cpu/defBF533_extn.h deleted file mode 100644 index a9a1c7ccbd..0000000000 --- a/include/asm-blackfin/cpu/defBF533_extn.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * defBF533_extn.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _DEF_BF533_EXTN_H -#define _DEF_BF533_EXTN_H - -#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */ -/* Delay inserted for PLL transition */ -#define DELAY 0x1000 - -#define L1_ISRAM 0xFFA00000 -#define L1_ISRAM_END 0xFFA10000 -#define DATA_BANKA_SRAM 0xFF800000 -#define DATA_BANKA_SRAM_END 0xFF808000 -#define DATA_BANKB_SRAM 0xFF900000 -#define DATA_BANKB_SRAM_END 0xFF908000 -#define SYSMMR_BASE 0xFFC00000 -#define WDSIZE16 0x00000004 - -/* Event Vector Table Address */ -#define EVT_EMULATION_ADDR 0xffe02000 -#define EVT_RESET_ADDR 0xffe02004 -#define EVT_NMI_ADDR 0xffe02008 -#define EVT_EXCEPTION_ADDR 0xffe0200c -#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010 -#define EVT_HARDWARE_ERROR_ADDR 0xffe02014 -#define EVT_TIMER_ADDR 0xffe02018 -#define EVT_IVG7_ADDR 0xffe0201c -#define EVT_IVG8_ADDR 0xffe02020 -#define EVT_IVG9_ADDR 0xffe02024 -#define EVT_IVG10_ADDR 0xffe02028 -#define EVT_IVG11_ADDR 0xffe0202c -#define EVT_IVG12_ADDR 0xffe02030 -#define EVT_IVG13_ADDR 0xffe02034 -#define EVT_IVG14_ADDR 0xffe02038 -#define EVT_IVG15_ADDR 0xffe0203c -#define EVT_OVERRIDE_ADDR 0xffe02100 - -/* IMASK Bit values */ -#define IVG15_POS 0x00008000 -#define IVG14_POS 0x00004000 -#define IVG13_POS 0x00002000 -#define IVG12_POS 0x00001000 -#define IVG11_POS 0x00000800 -#define IVG10_POS 0x00000400 -#define IVG9_POS 0x00000200 -#define IVG8_POS 0x00000100 -#define IVG7_POS 0x00000080 -#define IVGTMR_POS 0x00000040 -#define IVGHW_POS 0x00000020 - -#define WDOG_TMR_DISABLE (0xAD << 4) -#define ICTL_RST 0x00000000 -#define ICTL_NMI 0x00000002 -#define ICTL_GP 0x00000004 -#define ICTL_DISABLE 0x00000003 - -/* Watch Dog timer values setup */ -#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE - -#endif /* _DEF_BF533_EXTN_H */ diff --git a/include/asm-blackfin/cpu/def_LPBlackfin.h b/include/asm-blackfin/cpu/def_LPBlackfin.h deleted file mode 100644 index 9ac78c836a..0000000000 --- a/include/asm-blackfin/cpu/def_LPBlackfin.h +++ /dev/null @@ -1,445 +0,0 @@ -/* - * def_LPBlackfin.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */ - -#ifndef _DEF_LPBLACKFIN_H -#define _DEF_LPBLACKFIN_H - -/* - * #if !defined(__ADSPLPBLACKFIN__) - * #warning def_LPBlackfin.h should only be included for 532 compatible chips. - * #endif - */ - -#define MK_BMSK_( x ) (1<31 */ -#define TEST_WAY0 0x00000000 /* Access Way0 */ -#define TEST_WAY1 0x04000000 /* Access Way1 */ - -/* ** ITEST_COMMAND only */ -#define TEST_WAY2 0x08000000 /* Access Way2 */ -#define TEST_WAY3 0x0C000000 /* Access Way3 */ - -/* ** DTEST_COMMAND only */ -#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */ -#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */ - -#endif /* _DEF_LPBLACKFIN_H */ diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h index dbb73887ef..0c01e9fb7d 100644 --- a/include/asm-blackfin/delay.h +++ b/include/asm-blackfin/delay.h @@ -35,9 +35,9 @@ extern __inline__ void __delay(unsigned long loops) { __asm__ __volatile__("1:\t%0 += -1;\n\t" - "cc = %0 == 0;\n\t" - "if ! cc jump 1b;\n":"=d"(loops) - :"0"(loops)); + "cc = %0 == 0;\n\t" + "if ! cc jump 1b;\n":"=d"(loops) + :"0"(loops)); } /* diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h index 607a5b8e98..b64d406992 100644 --- a/include/asm-blackfin/entry.h +++ b/include/asm-blackfin/entry.h @@ -370,16 +370,12 @@ #define STR1(X) #X #if defined(NEW_PT_REGS) - #define PT_OFF_ORIG_R0 208 #define PT_OFF_SR 8 - #else - #define PT_OFF_ORIG_R0 0x54 #define PT_OFF_SR 0x38 /* seqstat in pt_regs */ - -#endif #endif #endif +#endif diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h index 56a12f07b3..1c738533c8 100644 --- a/include/asm-blackfin/global_data.h +++ b/include/asm-blackfin/global_data.h @@ -45,11 +45,16 @@ typedef struct global_data { unsigned long board_type; unsigned long baudrate; unsigned long have_console; /* serial_init() was called */ - unsigned long ram_size; /* RAM size */ + unsigned long ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ - unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ - void **jt; /* jump table */ +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) + unsigned long post_log_word; /* Record POST activities */ + unsigned long post_init_f_time; /* When post_init_f started */ +#endif + + void **jt; /* jump table */ } gd_t; /* @@ -59,6 +64,6 @@ typedef struct global_data { #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("P5") +#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P5") #endif diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h index 1ee050ec14..baa3e0c5c3 100644 --- a/include/asm-blackfin/hw_irq.h +++ b/include/asm-blackfin/hw_irq.h @@ -30,8 +30,14 @@ #include #ifdef CONFIG_EZKIT533 -#include +#include +#endif +#ifdef CONFIG_EZKIT561 +#include #endif #ifdef CONFIG_STAMP -#include +#include +#endif +#ifdef CONFIG_BF537 +#include #endif diff --git a/include/asm-blackfin/io-kernel.h b/include/asm-blackfin/io-kernel.h index 0b0572ffa4..3c087c33ee 100644 --- a/include/asm-blackfin/io-kernel.h +++ b/include/asm-blackfin/io-kernel.h @@ -87,7 +87,8 @@ #define IOMAP_WRITETHROUGH 3 #ifndef __ASSEMBLY__ -extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag); +extern void *__ioremap(unsigned long physaddr, unsigned long size, + int cacheflag); extern void __iounmap(void *addr, unsigned long size); extern inline void *ioremap(unsigned long physaddr, unsigned long size) { @@ -97,11 +98,13 @@ extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size) { return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); } -extern inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size) +extern inline void *ioremap_writethrough(unsigned long physaddr, + unsigned long size) { return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); } -extern inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size) +extern inline void *ioremap_fullcache(unsigned long physaddr, + unsigned long size) { return __ioremap(physaddr, size, IOMAP_FULL_CACHING); } diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index fc27194a42..6bab6e766a 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -25,11 +25,6 @@ #ifndef _BLACKFIN_IO_H #define _BLACKFIN_IO_H -static inline void sync(void) -{ - __asm__ __volatile__ asm("ssync" : : : "memory"); -} - #ifdef __KERNEL__ #include @@ -38,7 +33,11 @@ static inline void sync(void) extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words); extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words); extern unsigned char cf_inb(volatile unsigned char *addr); -extern void cf_outb(unsigned char val, volatile unsigned char* addr); +extern void cf_outb(unsigned char val, volatile unsigned char *addr); + +static inline void sync(void) +{ +} /* * These are for ISA/PCI shared memory _only_ and should never be used @@ -51,7 +50,6 @@ extern void cf_outb(unsigned char val, volatile unsigned char* addr); * memory location directly. */ - #define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; }) #define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; }) #define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; }) @@ -100,8 +98,7 @@ extern inline void *ioremap(unsigned long physaddr, unsigned long size) { return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); } -extern inline void *ioremap_nocache(unsigned long physaddr, - unsigned long size) +extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size) { return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); } diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h index 5fbc5a363b..aede742120 100644 --- a/include/asm-blackfin/irq.h +++ b/include/asm-blackfin/irq.h @@ -39,7 +39,7 @@ #define _BLACKFIN_IRQ_H_ #include -#include +#include /* * On the Blackfin, the interrupt structure allows remmapping of the hardware @@ -85,8 +85,8 @@ static __inline__ int irq_cannonicalize(int irq) extern void (*mach_enable_irq) (unsigned int); extern void (*mach_disable_irq) (unsigned int); extern int sys_request_irq(unsigned int, - void (*)(int, void *, struct pt_regs *), - unsigned long, const char *, void *); + void (*)(int, void *, struct pt_regs *), + unsigned long, const char *, void *); extern void sys_free_irq(unsigned int, void *); /* diff --git a/include/asm-blackfin/machdep.h b/include/asm-blackfin/machdep.h index 0a43ba1c5a..4fea74c6c9 100644 --- a/include/asm-blackfin/machdep.h +++ b/include/asm-blackfin/machdep.h @@ -39,7 +39,8 @@ struct hwclk_time; struct gendisk; struct buffer_head; -extern void (*mach_sched_init) (void (*handler) (int, void *, struct pt_regs *)); +extern + void (*mach_sched_init) (void (*handler) (int, void *, struct pt_regs *)); /* machine dependent keyboard functions */ extern int (*mach_keyb_init) (void); diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h index 1a13d908e0..a9baacdfb8 100644 --- a/include/asm-blackfin/mem_init.h +++ b/include/asm-blackfin/mem_init.h @@ -22,7 +22,13 @@ * MA 02111-1307 USA */ -#if ( CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E ) +#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \ + CONFIG_MEM_MT48LC64M4A2FB_7E || \ + CONFIG_MEM_MT48LC16M8A2TG_75 || \ + CONFIG_MEM_MT48LC8M16A2TG_7E || \ + CONFIG_MEM_MT48LC8M32B2B5_7 || \ + CONFIG_MEM_MT48LC32M8A2_75) + #if ( CONFIG_SCLK_HZ > 119402985 ) #define SDRAM_tRP TRP_2 #define SDRAM_tRP_num 2 @@ -66,7 +72,7 @@ #if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 ) #define SDRAM_tRP TRP_1 #define SDRAM_tRP_num 1 - #define SDRAM_tRAS TRAS_4 + #define SDRAM_tRAS TRAS_3 #define SDRAM_tRAS_num 3 #define SDRAM_tRCD TRCD_1 #define SDRAM_tWR TWR_2 @@ -111,6 +117,34 @@ #define SDRAM_CL CL_2 #endif +#if (CONFIG_MEM_MT48LC16M8A2TG_75) + /*SDRAM INFORMATION: */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ + #define SDRAM_CL CL_3 +#endif + +#if (CONFIG_MEM_MT48LC32M8A2_75) + /*SDRAM INFORMATION: */ +#define SDRAM_Tref 64 /* Refresh period in milliseconds */ +#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ +#define SDRAM_CL CL_3 +#endif + +#if (CONFIG_MEM_MT48LC8M16A2TG_7E) + /*SDRAM INFORMATION: */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ + #define SDRAM_CL CL_2 +#endif + +#if (CONFIG_MEM_MT48LC8M32B2B5_7) + /*SDRAM INFORMATION: */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ + #define SDRAM_CL CL_3 +#endif + #if ( CONFIG_MEM_SIZE == 128 ) #define SDRAM_SIZE EBSZ_128 #endif diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h index 406ece5377..d59828cdac 100644 --- a/include/asm-blackfin/page.h +++ b/include/asm-blackfin/page.h @@ -112,11 +112,6 @@ extern __inline__ int get_order(unsigned long size) #define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)) #define VALID_PAGE(page) ((page - mem_map) < max_mapnr) -#define BUG() do { \ - \ - while (1); /* dead-loop */ \ -} while (0) - #define PAGE_BUG(page) do { \ BUG(); \ } while (0) diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h index 19bd720106..df49bedc0a 100644 --- a/include/asm-blackfin/processor.h +++ b/include/asm-blackfin/processor.h @@ -126,8 +126,7 @@ static inline void release_thread(struct task_struct *dead_task) { } -extern int kernel_thread(int (*fn) (void *), void *arg, - unsigned long flags); +extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags); #define copy_segments(tsk, mm) do { } while (0) #define release_segments(mm) do { } while (0) diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h index 6ce96880ac..a3c1715b4a 100644 --- a/include/asm-blackfin/setup.h +++ b/include/asm-blackfin/setup.h @@ -75,12 +75,13 @@ extern unsigned long vme_brdtype; extern int blackfin_num_memory; /* # of memory blocks found (and used) */ extern int blackfin_realnum_memory; /* real # of memory blocks found */ -extern struct mem_info blackfin_memory[NUM_MEMINFO]; /* memory description */ struct mem_info { unsigned long addr; /* physical address of memory chunk */ unsigned long size; /* length of memory chunk (in bytes) */ }; + +extern struct mem_info blackfin_memory[NUM_MEMINFO]; /* memory description */ #endif #endif diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h index ffd81d61a8..aac6bc99f5 100644 --- a/include/asm-blackfin/string.h +++ b/include/asm-blackfin/string.h @@ -31,21 +31,26 @@ #include #include -#include +#include +#include #define __HAVE_ARCH_STRCPY #define __HAVE_ARCH_STRNCPY #define __HAVE_ARCH_STRCMP #define __HAVE_ARCH_STRNCMP #define __HAVE_ARCH_MEMCPY +#define __HAVE_ARCH_MEMCMP +#define __HAVE_ARCH_MEMSET +#define __HAVE_ARCH_MEMMOVE extern char *strcpy(char *dest, const char *src); extern char *strncpy(char *dest, const char *src, size_t n); extern int strcmp(const char *cs, const char *ct); extern int strncmp(const char *cs, const char *ct, size_t count); -extern void * memcpy(void * dest,const void *src,size_t count); +extern void *memcpy(void *dest, const void *src, size_t count); extern void *memset(void *s, int c, size_t count); extern int memcmp(const void *, const void *, __kernel_size_t); +extern void *memmove(void *dest, const void *src, size_t count); #else /* KERNEL */ diff --git a/include/asm-blackfin/u-boot.h b/include/asm-blackfin/u-boot.h index ec39338039..e1a435a137 100644 --- a/include/asm-blackfin/u-boot.h +++ b/include/asm-blackfin/u-boot.h @@ -29,7 +29,7 @@ #define _U_BOOT_H_ 1 typedef struct bd_info { - int bi_baudrate; /* serial console baudrate */ + int bi_baudrate; /* serial console baudrate */ unsigned long bi_ip_addr; /* IP Address */ unsigned char bi_enetaddr[6]; /* Ethernet adress */ unsigned long bi_arch_number; /* unique id for this board */ diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h index 8578166a37..61e2bfea7c 100644 --- a/include/asm-blackfin/uaccess.h +++ b/include/asm-blackfin/uaccess.h @@ -41,11 +41,10 @@ /* We let the MMU do all checking */ static inline int access_ok(int type, const void *addr, unsigned long size) { - return ((unsigned long) addr < 0x10f00000); /* need final decision - Tony */ + return ((unsigned long)addr < 0x10f00000); /* need final decision - Tony */ } -static inline int verify_area(int type, const void *addr, - unsigned long size) +static inline int verify_area(int type, const void *addr, unsigned long size) { return access_ok(type, addr, size) ? 0 : -EFAULT; } @@ -173,12 +172,11 @@ static inline int bad_user_access_length(void) * Copy a null terminated string from userspace. */ -static inline long strncpy_from_user(char *dst, const char *src, - long count) +static inline long strncpy_from_user(char *dst, const char *src, long count) { char *tmp; strncpy(dst, src, count); - for (tmp = dst; *tmp && count > 0; tmp++, count--); + for (tmp = dst; *tmp && count > 0; tmp++, count--) ; return (tmp - dst); /* DAVIDM should we count a NUL ? check getname */ } diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h new file mode 100644 index 0000000000..7afc1a17fe --- /dev/null +++ b/include/configs/bf533-ezkit.h @@ -0,0 +1,228 @@ +/* + * U-boot - Configuration file for BF533 EZKIT board + */ + +#ifndef __CONFIG_EZKIT533_H__ +#define __CONFIG_EZKIT533_H__ + +#define CONFIG_BAUDRATE 57600 +#define CONFIG_STAMP 1 + +#define CONFIG_BOOTDELAY 5 +#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */ + +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_LOADADDR 0x01000000 /* default load address */ +#define CONFIG_BOOTCOMMAND "tftp $(loadaddr) linux" +//#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" + +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20310300 + +#if 0 +#define CONFIG_MII +#define CFG_DISCOVER_PHY +#endif + +#define CONFIG_RTC_BFIN 1 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ + +/* + * Boot Mode Set + * Blackfin can support several boot modes + */ +#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */ +#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */ +#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */ +/* Define the boot mode */ +#define BFIN_BOOT_MODE BF533_BYPASS_BOOT +//#define BFIN_BOOT_MODE BF533_SPI_BOOT + +#define CONFIG_PANIC_HANG 1 + +#define ADSP_BF531 0x31 +#define ADSP_BF532 0x32 +#define ADSP_BF533 0x33 +#define BFIN_CPU ADSP_BF533 + +/* This sets the default state of the cache on U-Boot's boot */ +#define CONFIG_ICACHE_ON +#define CONFIG_DCACHE_ON + +/* Define where the uboot will be loaded by on-chip boot rom */ +#define APP_ENTRY 0x00001000 + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 27000000 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 22 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 +/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ +/* Values can range from 2-65535 */ +/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ +#define CONFIG_SPI_BAUD 2 +#define CONFIG_SPI_BAUD_INITBLOCK 4 + +#if ( CONFIG_CLKIN_HALF == 0 ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#else +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#endif + +#if (CONFIG_PLL_BYPASS == 0) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC16M16A2TG_75 1 + +#define CONFIG_LOADS_ECHO 1 + + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DATE) +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600" + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024 * 1024) /* 1 ... 31 MB in DRAM */ +#define CFG_LOAD_ADDR 0x01000000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024) +#define CFG_FLASH_BASE 0x20000000 + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_SIZE 0x4000 +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) + +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_FLASH0_BASE 0x20000000 +#define CFG_FLASH1_BASE 0x20200000 +#define CFG_FLASH2_BASE 0x20280000 +#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x20020000 +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ + +/* JFFS Partition offset set */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CFG_JFFS2_FIRST_SECTOR 11 + + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#define POLL_MODE 1 +#define FLASH_TOT_SECT 40 +#define FLASH_SIZE 0x220000 +#define CFG_FLASH_SIZE 0x220000 + +/* + * Initialize PSD4256 registers for using I2C + */ +#define CONFIG_MISC_INIT_R + +/* + * I2C settings + * By default PF1 is used as SDA and PF0 as SCL on the Stamp board + */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +/* + * Software (bit-bang) I2C driver configuration + */ +#define PF_SCL PF0 +#define PF_SDA PF1 + +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE + +#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ + +/* 0xFF, 0x7BB07BB0, 0x22547BB0 */ +/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ + ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) +#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ + B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) +*/ +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0x7BB07BB0 +#define AMBCTL1VAL 0xFFC27BB0 + +#define CONFIG_VDSP 1 + +#ifdef CONFIG_VDSP +#define ET_EXEC_VDSP 0x8 +#define SHT_STRTAB_VDSP 0x1 +#define ELFSHDRSIZE_VDSP 0x2C +#define VDSP_ENTRY_ADDR 0xFFA00000 +#endif + +#endif diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h new file mode 100644 index 0000000000..353a43c286 --- /dev/null +++ b/include/configs/bf533-stamp.h @@ -0,0 +1,475 @@ +/* + * U-boot - Configuration file for BF533 STAMP board + */ + +#ifndef __CONFIG_STAMP_H__ +#define __CONFIG_STAMP_H__ + +#define CONFIG_STAMP 1 +#define CONFIG_RTC_BFIN 1 +#define CONFIG_BF533 1 +/* + * Boot Mode Set + * Blackfin can support several boot modes + */ +#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */ +#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */ +#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */ +/* Define the boot mode */ +#define BFIN_BOOT_MODE BF533_BYPASS_BOOT +//#define BFIN_BOOT_MODE BF533_SPI_BOOT + +#define CONFIG_PANIC_HANG 1 + +#define ADSP_BF531 0x31 +#define ADSP_BF532 0x32 +#define ADSP_BF533 0x33 +#define BFIN_CPU ADSP_BF533 + +/* This sets the default state of the cache on U-Boot's boot */ +#define CONFIG_ICACHE_ON +#define CONFIG_DCACHE_ON + +/* Define where the uboot will be loaded by on-chip boot rom */ +#define APP_ENTRY 0x00001000 + +/* + * Stringize definitions - needed for environmental settings + */ +#define STRINGIZE2(x) #x +#define STRINGIZE(x) STRINGIZE2(x) + +/* + * Board settings + * + */ +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20300300 + +/* FLASH/ETHERNET uses the same address range */ +#define SHARED_RESOURCES 1 + +/* Is I2C bit-banged? */ +#define CONFIG_SOFT_I2C 1 + +/* + * Software (bit-bang) I2C driver configuration + */ +#define PF_SCL PF3 +#define PF_SDA PF2 + +/* + * Video splash screen support + */ +#define CONFIG_VIDEO 0 + +#define CONFIG_VDSP 1 + +/* + * Clock settings + * + */ + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 11059200 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 36 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 +/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ +/* Values can range from 2-65535 */ +/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ +#define CONFIG_SPI_BAUD 2 + +#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#define CONFIG_SPI_BAUD_INITBLOCK 4 +#endif + + +/* + * Network settings + * + */ + +#if (CONFIG_DRIVER_SMC91111) +#if 0 +#define CONFIG_MII +#endif + +/* network support */ +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME STAMP +#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs + +/* To remove hardcoding and enable MAC storage in EEPROM */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ +#endif /* CONFIG_DRIVER_SMC91111 */ + +/* + * Flash settings + * + */ + +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET + +#define CFG_FLASH_BASE 0x20000000 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x20004000 +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) +#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */ +#endif + +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */ +#define ENV_IS_EMBEDDED + +#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ +#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ + +/* JFFS Partition offset set */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CFG_JFFS2_FIRST_SECTOR 11 + +/* + * following timeouts shall be used once the + * Flash real protection is enabled + */ +#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ + +/* + * SDRAM settings & memory map + * + */ + +#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC64M4A2FB_7E 1 + +#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#endif + +#define CFG_SDRAM_BASE 0x00000000 + +#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 *1024) +#define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1) +#define CONFIG_LOADADDR 0x01000000 + +#define CFG_LOAD_ADDR CONFIG_LOADADDR +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - 0x40000) +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) + +/* Check to make sure everything fits in SDRAM */ +#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE) + #error Memory Map does not fit into configuration +#endif + +#if ( CONFIG_CLKIN_HALF == 0 ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#else +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#endif + +#if (CONFIG_PLL_BYPASS == 0) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000) +#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */ +#else +#undef CONFIG_SPI_FLASH_FAST_READ +#endif +#endif +/* + * Command settings + * + */ + +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) +#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */ +#endif + /* configuration lookup from the BOOTP/DHCP server, */ + /* but not try to load any image using TFTP */ + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ +#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) +#define CONFIG_BOOTCOMMAND "run ramboot" +#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#define CONFIG_BOOTCOMMAND "eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000" +#endif + +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600" + +#if (CONFIG_DRIVER_SMC91111) +#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DATE) + +#else +#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ + CFG_CMD_ELF | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DATE) + +#endif + +#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) +#if (CONFIG_DRIVER_SMC91111) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \ + "$(rootpath) console=ttyBF0,57600\0" \ + "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ + "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \ + "ramboot=tftpboot $(loadaddr) linux; " \ + "run ramargs;run addip;bootelf\0" \ + "nfsboot=tftpboot $(loadaddr) linux; " \ + "run nfsargs;run addip;bootelf\0" \ + "flashboot=bootm 0x20100000\0" \ + "update=tftpboot $(loadaddr) u-boot.bin; " \ + "protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \ + "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \ + "" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "flashboot=bootm 0x20100000\0" \ + "" +#endif + +#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \ + "$(rootpath) console=ttyBF0,57600\0" \ + "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ + "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \ + "ramboot=tftpboot $(loadaddr) linux; " \ + "run ramargs;run addip;bootelf\0" \ + "nfsboot=tftpboot $(loadaddr) linux; " \ + "run nfsargs;run addip;bootelf\0" \ + "flashboot=bootm 0x20100000\0" \ + "update=tftpboot $(loadaddr) u-boot.ldr;" \ + "eeprom write $(loadaddr) 0x0 $(filesize);\0"\ + "" +#endif + +#ifdef CONFIG_SOFT_I2C +#if (!CONFIG_SOFT_I2C) +#undef CONFIG_SOFT_I2C +#endif +#endif + +#if (CONFIG_SOFT_I2C) +#define CONFIG_COMMANDS2 CFG_CMD_I2C +#else +#define CONFIG_COMMANDS2 0 +#endif /* CONFIG_SOFT_I2C */ + +#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) +#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2 | CFG_CMD_DHCP) +#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2) +#endif + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Console settings + * + */ + +#define CONFIG_BAUDRATE 57600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#if (BFIN_CPU == ADSP_BF531) +#define CFG_PROMPT "serial_bf531> " /* Monitor Command Prompt */ +#elif (BFIN_CPU == ADSP_BF532) +#define CFG_PROMPT "serial_bf532> " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "serial_bf533> " /* Monitor Command Prompt */ +#endif +#else +#if (BFIN_CPU == ADSP_BF531) +#define CFG_PROMPT "bf531> " /* Monitor Command Prompt */ +#elif (BFIN_CPU == ADSP_BF532) +#define CFG_PROMPT "bf532> " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "bf533> " /* Monitor Command Prompt */ +#endif +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_LOADS_ECHO 1 + +/* + * I2C settings + * By default PF2 is used as SDA and PF3 as SCL on the Stamp board + */ +#if (CONFIG_SOFT_I2C) + +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE +#endif /* CONFIG_SOFT_I2C */ + +/* + * Compact Flash settings + */ + +/* Enabled below option for CF support */ +/* #define CONFIG_STAMP_CF 1 */ + +#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE) + +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_DOS_PARTITION 1 +/* + * IDE/ATA stuff + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0x20200000 +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ + +#define CFG_ATA_STRIDE 2 +#endif + +/* + * Miscellaneous configurable options + */ + +#define CFG_HZ 1000 /* 1ms time tick */ + +#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ + +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ + +#define CONFIG_SPI + +#ifdef CONFIG_VIDEO +#if (CONFIG_VIDEO) +#define CONFIG_SPLASH_SCREEN 1 +#define CONFIG_SILENT_CONSOLE 1 +#else +#undef CONFIG_VIDEO +#endif +#endif + +/* + * FLASH organization and environment definitions + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* 0xFF, 0xBBC3BBc3, 0x99B39983 */ +/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ + B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) +#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ + B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) +*/ +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0xBBC3BBC3 +#define AMBCTL1VAL 0x99B39983 +#define CF_AMBCTL1VAL 0x99B3ffc2 + +#ifdef CONFIG_VDSP +#define ET_EXEC_VDSP 0x8 +#define SHT_STRTAB_VDSP 0x1 +#define ELFSHDRSIZE_VDSP 0x2C +#define VDSP_ENTRY_ADDR 0xFFA00000 +#endif + + +#endif diff --git a/include/configs/ezkit533.h b/include/configs/ezkit533.h deleted file mode 100644 index 5eda6732ca..0000000000 --- a/include/configs/ezkit533.h +++ /dev/null @@ -1,188 +0,0 @@ -#ifndef __CONFIG_EZKIT533_H__ -#define __CONFIG_EZKIT533_H__ - -#define CFG_LONGHELP 1 -#define CONFIG_BAUDRATE 57600 -#define CONFIG_STAMP 1 -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_DRIVER_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20310300 -#if 0 -#define CONFIG_MII -#define CFG_DISCOVER_PHY -#endif - -#define CONFIG_RTC_BF533 1 -#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ - -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 27000000 -/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ -/* 1=CLKIN/2 */ -#define CONFIG_CLKIN_HALF 0 -/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ -/* 1=bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ -/* Values can range from 1-64 */ -#define CONFIG_VCO_MULT 22 -/* CONFIG_CCLK_DIV controls what the core clock divider is */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -#if ( CONFIG_CLKIN_HALF == 0 ) -#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) -#else -#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) -#endif - -#if (CONFIG_PLL_BYPASS == 0) -#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) -#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) -#else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ -#endif - -#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ -#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ -#define CONFIG_MEM_MT48LC16M16A2TG_75 1 - -#define CONFIG_LOADS_ECHO 1 - - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PING | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_DATE) -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off" - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01F00000 /* 1 ... 31 MB in DRAM */ -#define CFG_LOAD_ADDR 0x01000000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x02000000 -#define CFG_FLASH_BASE 0x20000000 - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_SIZE 0x4000 -#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) - -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -#define CFG_FLASH0_BASE 0x20000000 -#define CFG_FLASH1_BASE 0x20200000 -#define CFG_FLASH2_BASE 0x20280000 -#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0x20020000 -#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ - -/* JFFS Partition offset set */ -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_NUM_BANKS 1 -/* 512k reserved for u-boot */ -#define CFG_JFFS2_FIRST_SECTOR 11 - - -/* - * Stack sizes - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - -#define POLL_MODE 1 -#define FLASH_TOT_SECT 40 -#define FLASH_SIZE 0x220000 -#define CFG_FLASH_SIZE 0x220000 - -/* - * Initialize PSD4256 registers for using I2C - */ -#define CONFIG_MISC_INIT_R - -/* - * I2C settings - * By default PF1 is used as SDA and PF0 as SCL on the Stamp board - */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -/* - * Software (bit-bang) I2C driver configuration - */ -#define PF_SCL PF0 -#define PF_SDA PF1 - -#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") -#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") -#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") -#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") -#define I2C_SDA(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SDA; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SDA; \ - asm("ssync;"); \ - } -#define I2C_SCL(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SCL; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SCL; \ - asm("ssync;"); \ - } -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0xFE - - -#define __ADSPLPBLACKFIN__ 1 -#define __ADSPBF533__ 1 - -/* 0xFF, 0x7BB07BB0, 0x22547BB0 */ -/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) -#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ - ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) -#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ - B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) -*/ -#define AMGCTLVAL 0xFF -#define AMBCTL0VAL 0x7BB07BB0 -#define AMBCTL1VAL 0xFFC27BB0 - -#define CONFIG_VDSP 1 - -#ifdef CONFIG_VDSP -#define ET_EXEC_VDSP 0x8 -#define SHT_STRTAB_VDSP 0x1 -#define ELFSHDRSIZE_VDSP 0x2C -#define VDSP_ENTRY_ADDR 0xFFA00000 -#endif - -#endif diff --git a/include/configs/stamp.h b/include/configs/stamp.h deleted file mode 100644 index 248ca70de0..0000000000 --- a/include/configs/stamp.h +++ /dev/null @@ -1,333 +0,0 @@ -/* - * U-boot - stamp.h Configuration file for STAMP board - * having BF533 processor - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_STAMP_H__ -#define __CONFIG_STAMP_H__ - -/* - * Board settings - * - */ - -#define __ADSPLPBLACKFIN__ 1 -#define __ADSPBF533__ 1 -#define CONFIG_STAMP 1 -#define CONFIG_RTC_BF533 1 - -/* FLASH/ETHERNET uses the same address range */ -#define SHARED_RESOURCES 1 - -#define CONFIG_VDSP 1 - -/* - * Clock settings - * - */ - -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 11059200 -/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ -/* 1=CLKIN/2 */ -#define CONFIG_CLKIN_HALF 0 -/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ -/* 1=bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ -/* Values can range from 1-64 */ -#define CONFIG_VCO_MULT 45 -/* CONFIG_CCLK_DIV controls what the core clock divider is */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 6 - -/* - * Network Settings - */ -/* network support */ -#define CONFIG_IPADDR 192.168.0.15 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_HOSTNAME STAMP -#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs - -/* To remove hardcoding and enable MAC storage in EEPROM */ -/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ - -/* - * Command settings - * - */ - -#define CFG_LONGHELP 1 - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ -#define CONFIG_BOOTCOMMAND "run ramboot" -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PING | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_CACHE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_DATE) -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):eth0:off\0" \ - "ramboot=tftpboot 0x1000000 linux;" \ - "run ramargs;run addip;bootelf\0" \ - "nfsboot=tftpboot 0x1000000 linux;" \ - "run nfsargs;run addip;bootelf\0" \ - "flashboot=bootm 0x20100000\0" \ - "" - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Console settings - * - */ - -#define CONFIG_BAUDRATE 57600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_PROMPT "stamp>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_LOADS_ECHO 1 - -/* - * Network settings - * - */ - -#define CONFIG_DRIVER_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20300300 -/* To remove hardcoding and enable MAC storage in EEPROM */ -/* #define HARDCODE_MAC 1 */ - -/* - * Flash settings - * - */ - -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_CFI_AMD_RESET - -#define CFG_ENV_IS_IN_FLASH 1 - -#define CFG_FLASH_BASE 0x20000000 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_ENV_ADDR 0x20020000 -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ - -#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ -#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ - -/* JFFS Partition offset set */ -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_NUM_BANKS 1 -/* 512k reserved for u-boot */ -#define CFG_JFFS2_FIRST_SECTOR 11 - -/* - * following timeouts shall be used once the - * Flash real protection is enabled - */ -#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ - -/* - * I2C settings - * By default PF2 is used as SDA and PF3 as SCL on the Stamp board - */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -/* - * Software (bit-bang) I2C driver configuration - */ -#define PF_SCL PF3 -#define PF_SDA PF2 - -#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") -#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") -#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") -#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") -#define I2C_SDA(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SDA; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SDA; \ - asm("ssync;"); \ - } -#define I2C_SCL(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SCL; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SCL; \ - asm("ssync;"); \ - } -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0xFE - -/* - * Compact Flash settings - */ - -/* Enabled below option for CF support */ -/* #define CONFIG_STAMP_CF 1 */ - -#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE) - -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_DOS_PARTITION 1 - -/* - * IDE/ATA stuff - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0x20200000 -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ - -#define CFG_ATA_STRIDE 2 -#endif - -/* - * SDRAM settings - * - */ - -#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ -#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ -#define CONFIG_MEM_MT48LC64M4A2FB_7E 1 - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x07EFFFFF /* 1 ... 127 MB in DRAM */ -#define CFG_LOAD_ADDR 0x01000000 /* default load address */ - -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x08000000 - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) - -#if ( CONFIG_CLKIN_HALF == 0 ) -#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) -#else -#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) -#endif - -#if (CONFIG_PLL_BYPASS == 0) -#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) -#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) -#else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_HZ 1000 /* 1ms time tick */ - -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_SIZE 0x4000 -#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) - -#define CFG_LARGE_IMAGE_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ - -/* - * Stack sizes - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - -/* - * FLASH organization and environment definitions - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* 0xFF, 0xBBC3BBc3, 0x99B39983 */ -/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) -#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ - B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) -#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ - B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) -*/ -#define AMGCTLVAL 0xFF -#define AMBCTL0VAL 0xBBC3BBC3 -#define AMBCTL1VAL 0x99B39983 -#define CF_AMBCTL1VAL 0x99B3ffc2 - -#ifdef CONFIG_VDSP -#define ET_EXEC_VDSP 0x8 -#define SHT_STRTAB_VDSP 0x1 -#define ELFSHDRSIZE_VDSP 0x2C -#define VDSP_ENTRY_ADDR 0xFFA00000 -#endif - -#endif -- cgit v1.2.1 From ef26a08fef928b7bc11ae2c109e638dc3a016d91 Mon Sep 17 00:00:00 2001 From: "Aubrey.Li" Date: Fri, 9 Mar 2007 13:40:56 +0800 Subject: [Blackfin][PATCH-2/2] Common files changed to support bf533 platform --- include/linux/stat.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/stat.h b/include/linux/stat.h index f9422cb1fa..4d05aa92d9 100644 --- a/include/linux/stat.h +++ b/include/linux/stat.h @@ -67,7 +67,7 @@ struct stat { #endif /* __PPC__ */ -#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__blackfin__) +#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) struct stat { unsigned short st_dev; -- cgit v1.2.1 From 8db13d63157811c839d15a313d9f2d2f5fd10af3 Mon Sep 17 00:00:00 2001 From: Aubrey Li Date: Sat, 10 Mar 2007 23:49:29 +0800 Subject: [Blackfin][PATCH] code cleanup --- include/asm-blackfin/arch-bf533/anomaly.h | 100 +++--- include/asm-blackfin/arch-bf533/defBF532.h | 2 +- include/asm-blackfin/arch-common/cdef_LPBlackfin.h | 31 +- include/asm-blackfin/mem_init.h | 32 +- include/configs/bf533-ezkit.h | 156 ++++----- include/configs/bf533-stamp.h | 378 ++++++++++----------- 6 files changed, 337 insertions(+), 362 deletions(-) (limited to 'include') diff --git a/include/asm-blackfin/arch-bf533/anomaly.h b/include/asm-blackfin/arch-bf533/anomaly.h index 0e5f919438..4fe425c9c1 100644 --- a/include/asm-blackfin/arch-bf533/anomaly.h +++ b/include/asm-blackfin/arch-bf533/anomaly.h @@ -46,126 +46,126 @@ /* Issues that are common to 0.5, 0.4, and 0.3 silicon */ #if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in - slot1 and store of a P register in slot 2 is not - supported */ + slot1 and store of a P register in slot 2 is not + supported */ #define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on - every corresponding match */ + every corresponding match */ #define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive - Channel DMA stops */ + Channel DMA stops */ #define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR - registers. */ + registers. */ #define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out - upper bits*/ + upper bits*/ #define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ #define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame - syncs */ + syncs */ #define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not - functional */ + functional */ #define ANOMALY_05000219 /* NMI event at boot time results in unpredictable - state */ + state */ #define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */ #define ANOMALY_05000272 /* Certain data cache write through modes fail for - VDDint <=0.9V */ + VDDint <=0.9V */ #define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */ #define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after - an edge is detected may clear interrupt */ + an edge is detected may clear interrupt */ #define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause - DMA system instability */ + DMA system instability */ #define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is - not restored */ + not restored */ #define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic - control */ + control */ #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when - killed in a particular stage*/ + killed in a particular stage*/ #endif /* These issues only occur on 0.3 or 0.4 BF533 */ #if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) #define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not - updated at the same time. */ + updated at the same time. */ #define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data - Cache Fill can be corrupted after or during - Instruction DMA if certain core stalls exist */ + Cache Fill can be corrupted after or during + Instruction DMA if certain core stalls exist */ #define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General - Purpose TX or RX modes */ + Purpose TX or RX modes */ #define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by - preceding memory read */ + preceding memory read */ #define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during - inactive channels in certain conditions */ + inactive channels in certain conditions */ #define ANOMALY_05000202 /* Possible infinite stall with specific dual dag - situation */ + situation */ #define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */ #define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */ #define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect - data*/ + data*/ #define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate - Differences in certain Conditions */ + Differences in certain Conditions */ #define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */ #define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to - hardware reset */ + hardware reset */ #define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or - IDLE around a Change of Control causes - unpredictable results */ + IDLE around a Change of Control causes + unpredictable results */ #define ANOMALY_05000245 /* Spurious Hardware Error from an access in the - shadow of a conditional branch */ + shadow of a conditional branch */ #define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware - errors */ + errors */ #define ANOMALY_05000253 /* Maximum external clock speed for Timers */ #define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event - interrupt not functional */ + interrupt not functional */ #define ANOMALY_05000257 /* An interrupt or exception during short Hardware - loops may cause the instruction fetch unit to - malfunction */ + loops may cause the instruction fetch unit to + malfunction */ #define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of - the ICPLB Data registers differ */ + the ICPLB Data registers differ */ #define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ #define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ #define ANOMALY_05000262 /* Stores to data cache may be lost */ #define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */ #define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE - instruction will cause an infinite stall in the - second to last instruction in a hardware loop */ + instruction will cause an infinite stall in the + second to last instruction in a hardware loop */ #define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on - SPORT external receive and transmit clocks. */ + SPORT external receive and transmit clocks. */ #define ANOMALY_05000269 /* High I/O activity causes the output voltage of the - internal voltage regulator (VDDint) to increase. */ + internal voltage regulator (VDDint) to increase. */ #define ANOMALY_05000270 /* High I/O activity causes the output voltage of the - internal voltage regulator (VDDint) to decrease */ + internal voltage regulator (VDDint) to decrease */ #endif /* These issues are only on 0.4 silicon */ #if (defined(CONFIG_BF_REV_0_4)) #define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */ #define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel - (TDM) */ + (TDM) */ #endif /* These issues are only on 0.3 silicon */ #if defined(CONFIG_BF_REV_0_3) #define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with - External Frame Syncs */ + External Frame Syncs */ #define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative - Instruction or Data Fetches, or by Fetches at the - boundary of reserved memory space */ + Instruction or Data Fetches, or by Fetches at the + boundary of reserved memory space */ #define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs - when polarity setting is changed */ + when polarity setting is changed */ #define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data - corruption */ + corruption */ #define ANOMALY_05000199 /* DMA current address shows wrong value during carry - fix */ + fix */ #define ANOMALY_05000201 /* Receive frame sync not ignored during active - frames in sport MCM */ + frames in sport MCM */ #define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA - stopping */ + stopping */ #if defined(CONFIG_BF533) #define ANOMALY_05000204 /* Incorrect data read with write-through cache and - allocate cache lines on reads only mode */ + allocate cache lines on reads only mode */ #endif /* CONFIG_BF533 */ #define ANOMALY_05000207 /* Recovery from "brown-out" condition */ #define ANOMALY_05000209 /* Speed-Path in computational unit affects certain - instructions */ + instructions */ #define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame - Sync Transmit Mode */ + Sync Transmit Mode */ #define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */ #endif diff --git a/include/asm-blackfin/arch-bf533/defBF532.h b/include/asm-blackfin/arch-bf533/defBF532.h index 312ff2bf5c..25a74e6846 100644 --- a/include/asm-blackfin/arch-bf533/defBF532.h +++ b/include/asm-blackfin/arch-bf533/defBF532.h @@ -88,7 +88,7 @@ #define UART_LCR 0xFFC0040C /* Line Control Register */ #define UART_MCR 0xFFC00410 /* Modem Control Register */ #define UART_LSR 0xFFC00414 /* Line Status Register */ -/* #define UART_MSR 0xFFC00418 *//* Modem Status Register (UNUSED in ADSP-BF532) */ +/* #define UART_MSR 0xFFC00418 */ /* Modem Status Register (UNUSED in ADSP-BF532) */ #define UART_SCR 0xFFC0041C /* SCR Scratch Register */ #define UART_GCTL 0xFFC00424 /* Global Control Register */ diff --git a/include/asm-blackfin/arch-common/cdef_LPBlackfin.h b/include/asm-blackfin/arch-common/cdef_LPBlackfin.h index f82ccbe4ec..90b21e525b 100644 --- a/include/asm-blackfin/arch-common/cdef_LPBlackfin.h +++ b/include/asm-blackfin/arch-common/cdef_LPBlackfin.h @@ -14,14 +14,11 @@ #endif #include -// Cache & SRAM Memory +/* Cache & SRAM Memory */ #define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS) #define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL) #define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS) #define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR) -/* -#define MMR_TIMEOUT 0xFFE00010 // Memory-Mapped Register Timeout Register -*/ #define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0) #define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1) #define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2) @@ -55,15 +52,8 @@ #define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14) #define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15) #define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND) -/* -#define DTEST_INDEX 0xFFE00304 // Data Test Index Register -*/ #define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0) #define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1) -/* -#define DTEST_DATA2 0xFFE00408 // Data Test Data Register -#define DTEST_DATA3 0xFFE0040C // Data Test Data Register -*/ #define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL) #define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS) #define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR) @@ -100,13 +90,10 @@ #define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14) #define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15) #define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND) -/* -#define ITEST_INDEX 0xFFE01304 // Instruction Test Index Register -*/ #define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0) #define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1) -// Event/Interrupt Registers +/* Event/Interrupt Registers */ #define pEVT0 ((volatile void **)EVT0) #define pEVT1 ((volatile void **)EVT1) #define pEVT2 ((volatile void **)EVT2) @@ -127,24 +114,24 @@ #define pIPEND ((volatile unsigned long *)IPEND) #define pILAT ((volatile unsigned long *)ILAT) -// Core Timer Registers +/* Core Timer Registers */ #define pTCNTL ((volatile unsigned long *)TCNTL) #define pTPERIOD ((volatile unsigned long *)TPERIOD) #define pTSCALE ((volatile unsigned long *)TSCALE) #define pTCOUNT ((volatile unsigned long *)TCOUNT) -// Debug/MP/Emulation Registers +/* Debug/MP/Emulation Registers */ #define pDSPID ((volatile unsigned long *)DSPID) #define pDBGCTL ((volatile unsigned long *)DBGCTL) #define pDBGSTAT ((volatile unsigned long *)DBGSTAT) #define pEMUDAT ((volatile unsigned long *)EMUDAT) -// Trace Buffer Registers +/* Trace Buffer Registers */ #define pTBUFCTL ((volatile unsigned long *)TBUFCTL) #define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT) #define pTBUF ((volatile void **)TBUF) -// Watch Point Control Registers +/* Watch Point Control Registers */ #define pWPIACTL ((volatile unsigned long *)WPIACTL) #define pWPIA0 ((volatile void **)WPIA0) #define pWPIA1 ((volatile void **)WPIA1) @@ -165,13 +152,9 @@ #define pWPDACNT1 ((volatile unsigned long *)WPDACNT1) #define pWPSTAT ((volatile unsigned long *)WPSTAT) -// Performance Monitor Registers +/* Performance Monitor Registers */ #define pPFCTL ((volatile unsigned long *)PFCTL) #define pPFCNTR0 ((volatile unsigned long *)PFCNTR0) #define pPFCNTR1 ((volatile unsigned long *)PFCNTR1) -/* -#define IPRIO 0xFFE02110 // Core Interrupt Priority Register -*/ - #endif /* _CDEF_LPBLACKFIN_H */ diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h index a9baacdfb8..d9d8bf9ba2 100644 --- a/include/asm-blackfin/mem_init.h +++ b/include/asm-blackfin/mem_init.h @@ -26,7 +26,7 @@ CONFIG_MEM_MT48LC64M4A2FB_7E || \ CONFIG_MEM_MT48LC16M8A2TG_75 || \ CONFIG_MEM_MT48LC8M16A2TG_7E || \ - CONFIG_MEM_MT48LC8M32B2B5_7 || \ + CONFIG_MEM_MT48LC8M32B2B5_7 || \ CONFIG_MEM_MT48LC32M8A2_75) #if ( CONFIG_SCLK_HZ > 119402985 ) @@ -105,43 +105,43 @@ #if (CONFIG_MEM_MT48LC16M16A2TG_75) /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ #define SDRAM_CL CL_3 #endif #if (CONFIG_MEM_MT48LC64M4A2FB_7E) /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ #define SDRAM_CL CL_2 #endif #if (CONFIG_MEM_MT48LC16M8A2TG_75) - /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ - #define SDRAM_CL CL_3 + /*SDRAM INFORMATION: */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ + #define SDRAM_CL CL_3 #endif #if (CONFIG_MEM_MT48LC32M8A2_75) - /*SDRAM INFORMATION: */ -#define SDRAM_Tref 64 /* Refresh period in milliseconds */ -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ +/*SDRAM INFORMATION: */ +#define SDRAM_Tref 64 /* Refresh period in milliseconds */ +#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ #define SDRAM_CL CL_3 #endif #if (CONFIG_MEM_MT48LC8M16A2TG_7E) /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ #define SDRAM_CL CL_2 #endif #if (CONFIG_MEM_MT48LC8M32B2B5_7) /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ #define SDRAM_CL CL_3 #endif diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index 7afc1a17fe..3e165f2495 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -9,13 +9,13 @@ #define CONFIG_STAMP 1 #define CONFIG_BOOTDELAY 5 -#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */ +#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */ -#define CFG_LONGHELP 1 +#define CFG_LONGHELP 1 #define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_LOADADDR 0x01000000 /* default load address */ +#define CONFIG_LOADADDR 0x01000000 /* default load address */ #define CONFIG_BOOTCOMMAND "tftp $(loadaddr) linux" -//#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" +/* #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" */ #define CONFIG_DRIVER_SMC91111 1 #define CONFIG_SMC91111_BASE 0x20310300 @@ -32,12 +32,12 @@ * Boot Mode Set * Blackfin can support several boot modes */ -#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */ -#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */ -#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */ +#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */ +#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */ +#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */ /* Define the boot mode */ #define BFIN_BOOT_MODE BF533_BYPASS_BOOT -//#define BFIN_BOOT_MODE BF533_SPI_BOOT +/* #define BFIN_BOOT_MODE BF533_SPI_BOOT */ #define CONFIG_PANIC_HANG 1 @@ -53,46 +53,46 @@ /* Define where the uboot will be loaded by on-chip boot rom */ #define APP_ENTRY 0x00001000 -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 27000000 -/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ -/* 1=CLKIN/2 */ -#define CONFIG_CLKIN_HALF 0 -/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ -/* 1=bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ -/* Values can range from 1-64 */ -#define CONFIG_VCO_MULT 22 -/* CONFIG_CCLK_DIV controls what the core clock divider is */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 27000000 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 22 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 /* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 -/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ -/* Values can range from 2-65535 */ -/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ -#define CONFIG_SPI_BAUD 2 -#define CONFIG_SPI_BAUD_INITBLOCK 4 +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 +/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ +/* Values can range from 2-65535 */ +/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ +#define CONFIG_SPI_BAUD 2 +#define CONFIG_SPI_BAUD_INITBLOCK 4 #if ( CONFIG_CLKIN_HALF == 0 ) -#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) #else -#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) #endif #if (CONFIG_PLL_BYPASS == 0) -#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) -#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) #else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ #endif -#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ -#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ -#define CONFIG_MEM_MT48LC16M16A2TG_75 1 +#define CONFIG_MEM_SIZ 32 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC16M16A2TG_75 1 #define CONFIG_LOADS_ECHO 1 @@ -146,16 +146,16 @@ #define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ /* JFFS Partition offset set */ -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_NUM_BANKS 1 +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 /* 512k reserved for u-boot */ -#define CFG_JFFS2_FIRST_SECTOR 11 +#define CFG_JFFS2_FIRST_SECTOR 11 /* * Stack sizes */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ #define POLL_MODE 1 #define FLASH_TOT_SECT 40 @@ -171,50 +171,50 @@ * I2C settings * By default PF1 is used as SDA and PF0 as SCL on the Stamp board */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ /* * Software (bit-bang) I2C driver configuration */ -#define PF_SCL PF0 -#define PF_SDA PF1 - -#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") -#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") -#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") -#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") -#define I2C_SDA(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SDA; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SDA; \ - asm("ssync;"); \ - } -#define I2C_SCL(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SCL; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SCL; \ - asm("ssync;"); \ - } -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0xFE +#define PF_SCL PF0 +#define PF_SDA PF1 + +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE #define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ /* 0xFF, 0x7BB07BB0, 0x22547BB0 */ -/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) -#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ - ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) -#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ - B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) +/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ + ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) +#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ + B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) */ -#define AMGCTLVAL 0xFF -#define AMBCTL0VAL 0x7BB07BB0 -#define AMBCTL1VAL 0xFFC27BB0 +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0x7BB07BB0 +#define AMBCTL1VAL 0xFFC27BB0 #define CONFIG_VDSP 1 diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 353a43c286..cde2c245c8 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -12,12 +12,12 @@ * Boot Mode Set * Blackfin can support several boot modes */ -#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */ -#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */ -#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */ +#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */ +#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */ +#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */ /* Define the boot mode */ #define BFIN_BOOT_MODE BF533_BYPASS_BOOT -//#define BFIN_BOOT_MODE BF533_SPI_BOOT +/* #define BFIN_BOOT_MODE BF533_SPI_BOOT */ #define CONFIG_PANIC_HANG 1 @@ -41,65 +41,61 @@ /* * Board settings - * */ -#define CONFIG_DRIVER_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20300300 +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20300300 /* FLASH/ETHERNET uses the same address range */ -#define SHARED_RESOURCES 1 +#define SHARED_RESOURCES 1 /* Is I2C bit-banged? */ -#define CONFIG_SOFT_I2C 1 +#define CONFIG_SOFT_I2C 1 /* * Software (bit-bang) I2C driver configuration */ -#define PF_SCL PF3 -#define PF_SDA PF2 +#define PF_SCL PF3 +#define PF_SDA PF2 /* * Video splash screen support */ -#define CONFIG_VIDEO 0 +#define CONFIG_VIDEO 0 -#define CONFIG_VDSP 1 +#define CONFIG_VDSP 1 /* * Clock settings - * */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 11059200 -/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ -/* 1=CLKIN/2 */ -#define CONFIG_CLKIN_HALF 0 -/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ -/* 1=bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ -/* Values can range from 1-64 */ -#define CONFIG_VCO_MULT 36 -/* CONFIG_CCLK_DIV controls what the core clock divider is */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 -/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ -/* Values can range from 2-65535 */ -/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ -#define CONFIG_SPI_BAUD 2 +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 11059200 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 36 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 +/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ +/* Values can range from 2-65535 */ +/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ +#define CONFIG_SPI_BAUD 2 #if (BFIN_BOOT_MODE == BF533_SPI_BOOT) -#define CONFIG_SPI_BAUD_INITBLOCK 4 +#define CONFIG_SPI_BAUD_INITBLOCK 4 #endif - /* * Network settings - * */ #if (CONFIG_DRIVER_SMC91111) @@ -108,92 +104,90 @@ #endif /* network support */ -#define CONFIG_IPADDR 192.168.0.15 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_HOSTNAME STAMP -#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME STAMP +#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs /* To remove hardcoding and enable MAC storage in EEPROM */ -/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ #endif /* CONFIG_DRIVER_SMC91111 */ /* * Flash settings - * */ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_CFI_AMD_RESET -#define CFG_FLASH_BASE 0x20000000 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ +#define CFG_FLASH_BASE 0x20000000 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0x20004000 -#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x20004000 +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) #elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) -#define CFG_ENV_IS_IN_EEPROM 1 -#define CFG_ENV_OFFSET 0x4000 -#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */ +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */ #endif -#define CFG_ENV_SIZE 0x2000 -#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */ #define ENV_IS_EMBEDDED -#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ +#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ #define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ /* JFFS Partition offset set */ #define CFG_JFFS2_FIRST_BANK 0 #define CFG_JFFS2_NUM_BANKS 1 /* 512k reserved for u-boot */ -#define CFG_JFFS2_FIRST_SECTOR 11 +#define CFG_JFFS2_FIRST_SECTOR 11 /* * following timeouts shall be used once the * Flash real protection is enabled */ -#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ +#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ /* * SDRAM settings & memory map - * */ -#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ -#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ #define CONFIG_MEM_MT48LC64M4A2FB_7E 1 #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ #elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ #endif -#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE 0x00000000 #define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 *1024) #define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1) #define CONFIG_LOADADDR 0x01000000 -#define CFG_LOAD_ADDR CONFIG_LOADADDR -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#define CFG_LOAD_ADDR CONFIG_LOADADDR +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ #define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - 0x40000) -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) /* Check to make sure everything fits in SDRAM */ #if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE) @@ -201,17 +195,17 @@ #endif #if ( CONFIG_CLKIN_HALF == 0 ) -#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) #else -#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) #endif #if (CONFIG_PLL_BYPASS == 0) -#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) -#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) #else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ #endif #if (BFIN_BOOT_MODE == BF533_SPI_BOOT) @@ -221,71 +215,71 @@ #undef CONFIG_SPI_FLASH_FAST_READ #endif #endif + /* * Command settings - * */ -#define CFG_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) -#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */ +#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */ #endif - /* configuration lookup from the BOOTP/DHCP server, */ - /* but not try to load any image using TFTP */ -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ +/* configuration lookup from the BOOTP/DHCP server, */ +/* but not try to load any image using TFTP */ + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) -#define CONFIG_BOOTCOMMAND "run ramboot" +#define CONFIG_BOOTCOMMAND "run ramboot" #elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) -#define CONFIG_BOOTCOMMAND "eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000" +#define CONFIG_BOOTCOMMAND "eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000" #endif -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600" +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600" #if (CONFIG_DRIVER_SMC91111) -#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ - CFG_CMD_PING | \ - CFG_CMD_ELF | \ - CFG_CMD_CACHE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DATE) +#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DATE) #else -#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ - CFG_CMD_ELF | \ - CFG_CMD_CACHE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DATE) - +#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ + CFG_CMD_ELF | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DATE) #endif #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) #if (CONFIG_DRIVER_SMC91111) #define CONFIG_EXTRA_ENV_SETTINGS \ - "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \ - "$(rootpath) console=ttyBF0,57600\0" \ - "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ - "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \ - "ramboot=tftpboot $(loadaddr) linux; " \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \ + "$(rootpath) console=ttyBF0,57600\0" \ + "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ + "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \ + "ramboot=tftpboot $(loadaddr) linux; " \ "run ramargs;run addip;bootelf\0" \ - "nfsboot=tftpboot $(loadaddr) linux; " \ + "nfsboot=tftpboot $(loadaddr) linux; " \ "run nfsargs;run addip;bootelf\0" \ - "flashboot=bootm 0x20100000\0" \ - "update=tftpboot $(loadaddr) u-boot.bin; " \ - "protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \ - "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \ - "" + "flashboot=bootm 0x20100000\0" \ + "update=tftpboot $(loadaddr) u-boot.bin; " \ + "protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \ + "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \ + "" #else #define CONFIG_EXTRA_ENV_SETTINGS \ - "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ - "flashboot=bootm 0x20100000\0" \ - "" + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "flashboot=bootm 0x20100000\0" \ + " #endif #elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) @@ -328,40 +322,39 @@ /* * Console settings - * */ -#define CONFIG_BAUDRATE 57600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_BAUDRATE 57600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #if (BFIN_BOOT_MODE == BF533_SPI_BOOT) #if (BFIN_CPU == ADSP_BF531) -#define CFG_PROMPT "serial_bf531> " /* Monitor Command Prompt */ +#define CFG_PROMPT "serial_bf531> " /* Monitor Command Prompt */ #elif (BFIN_CPU == ADSP_BF532) -#define CFG_PROMPT "serial_bf532> " /* Monitor Command Prompt */ +#define CFG_PROMPT "serial_bf532> " /* Monitor Command Prompt */ #else -#define CFG_PROMPT "serial_bf533> " /* Monitor Command Prompt */ +#define CFG_PROMPT "serial_bf533> " /* Monitor Command Prompt */ #endif #else #if (BFIN_CPU == ADSP_BF531) -#define CFG_PROMPT "bf531> " /* Monitor Command Prompt */ +#define CFG_PROMPT "bf531> " /* Monitor Command Prompt */ #elif (BFIN_CPU == ADSP_BF532) -#define CFG_PROMPT "bf532> " /* Monitor Command Prompt */ +#define CFG_PROMPT "bf532> " /* Monitor Command Prompt */ #else -#define CFG_PROMPT "bf533> " /* Monitor Command Prompt */ +#define CFG_PROMPT "bf533> " /* Monitor Command Prompt */ #endif #endif #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_LOADS_ECHO 1 +#define CONFIG_LOADS_ECHO 1 /* * I2C settings @@ -369,30 +362,30 @@ */ #if (CONFIG_SOFT_I2C) -#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") -#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") -#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") -#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") -#define I2C_SDA(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SDA; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SDA; \ - asm("ssync;"); \ - } -#define I2C_SCL(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SCL; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SCL; \ - asm("ssync;"); \ - } -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0xFE +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE #endif /* CONFIG_SOFT_I2C */ /* @@ -400,48 +393,48 @@ */ /* Enabled below option for CF support */ -/* #define CONFIG_STAMP_CF 1 */ +/* #define CONFIG_STAMP_CF 1 */ #if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE) -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_DOS_PARTITION 1 /* * IDE/ATA stuff */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ -#define CFG_ATA_BASE_ADDR 0x20200000 -#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_BASE_ADDR 0x20200000 +#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ -#define CFG_ATA_STRIDE 2 +#define CFG_ATA_STRIDE 2 #endif /* * Miscellaneous configurable options */ -#define CFG_HZ 1000 /* 1ms time tick */ +#define CFG_HZ 1000 /* 1ms time tick */ -#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ +#define CFG_BOOTM_LEN 0x4000000/* Large Image Length, set to 64 Meg */ -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ #define CONFIG_SPI #ifdef CONFIG_VIDEO #if (CONFIG_VIDEO) -#define CONFIG_SPLASH_SCREEN 1 -#define CONFIG_SILENT_CONSOLE 1 +#define CONFIG_SPLASH_SCREEN 1 +#define CONFIG_SILENT_CONSOLE 1 #else #undef CONFIG_VIDEO #endif @@ -450,19 +443,19 @@ /* * FLASH organization and environment definitions */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */ /* 0xFF, 0xBBC3BBc3, 0x99B39983 */ -/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) -#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ - B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) -#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ - B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) +/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ + B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) +#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ + B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) */ -#define AMGCTLVAL 0xFF -#define AMBCTL0VAL 0xBBC3BBC3 -#define AMBCTL1VAL 0x99B39983 -#define CF_AMBCTL1VAL 0x99B3ffc2 +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0xBBC3BBC3 +#define AMBCTL1VAL 0x99B39983 +#define CF_AMBCTL1VAL 0x99B3ffc2 #ifdef CONFIG_VDSP #define ET_EXEC_VDSP 0x8 @@ -471,5 +464,4 @@ #define VDSP_ENTRY_ADDR 0xFFA00000 #endif - #endif -- cgit v1.2.1 From 8440bb14581a294375c34b91b42512f9753d1130 Mon Sep 17 00:00:00 2001 From: Aubrey Li Date: Mon, 12 Mar 2007 00:25:14 +0800 Subject: [Blackfin][PATCH] code cleanup --- include/configs/bf533-ezkit.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index 3e165f2495..65dfc81554 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -90,7 +90,7 @@ #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ #endif -#define CONFIG_MEM_SIZ 32 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ #define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ #define CONFIG_MEM_MT48LC16M16A2TG_75 1 -- cgit v1.2.1 From 0d93de11449390a5984b0236c3612e50f6dbb7e8 Mon Sep 17 00:00:00 2001 From: Aubrey Li Date: Mon, 12 Mar 2007 12:11:55 +0800 Subject: [Blackfin][PATCH] minor cleanup --- include/configs/bf533-stamp.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index cde2c245c8..79a1404a40 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -120,7 +120,7 @@ */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_CFI_AMD_RESET #define CFG_FLASH_BASE 0x20000000 @@ -228,7 +228,7 @@ #endif /* configuration lookup from the BOOTP/DHCP server, */ -/* but not try to load any image using TFTP */ +/* but not try to load any image using TFTP */ #define CONFIG_BOOTDELAY 5 #define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ @@ -289,7 +289,7 @@ "$(rootpath) console=ttyBF0,57600\0" \ "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \ - "ramboot=tftpboot $(loadaddr) linux; " \ + "ramboot=tftpboot $(loadaddr) linux; " \ "run ramargs;run addip;bootelf\0" \ "nfsboot=tftpboot $(loadaddr) linux; " \ "run nfsargs;run addip;bootelf\0" \ -- cgit v1.2.1 From 8502e30a28e492c756ea2d7df0ace026388fce4b Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 13 Mar 2007 09:40:59 +0100 Subject: [PATCH] update board config for jupiter Board: added Hush Shell, CONFIG_CMDLINE_EDITING, CFG_ENV_ADDR_REDUND activated Signed-off-by: Heiko Schocher --- include/configs/jupiter.h | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 0a6dba6721..f21550dc36 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -116,12 +116,16 @@ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ + "flash_nfs=run nfsargs addip addcon;" \ "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ + "addcon=setenv bootargs ${bootargs} console=${contyp}," \ + "${baudrate}\0" \ + "contyp=ttyS0\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcon;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ "bootfile=/tftpboot/jupiter/uImage\0" \ "" @@ -195,6 +199,10 @@ #define CFG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_OVERWRITE 1 +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + /* * Memory map */ @@ -240,6 +248,12 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -- cgit v1.2.1 From a7090b993d3d4d2221ac3f33e6cb1d1b2ccc6bf0 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 13 Mar 2007 16:05:55 +0100 Subject: Make SC3 board build with 'make O='; use 'addcons' consistently (SC3 and Jupiter used to use 'addcon' instead). Signed-off-by: Wolfgang Denk wd@denx.de --- include/configs/jupiter.h | 6 +++--- include/configs/sc3.h | 9 ++++++--- 2 files changed, 9 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 64dbd9b9f9..5b97526fc4 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -116,14 +116,14 @@ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip addcon;" \ + "flash_nfs=run nfsargs addip addcons;" \ "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "addcon=setenv bootargs ${bootargs} console=${contyp}," \ + "addcons=setenv bootargs ${bootargs} console=${contyp}," \ "${baudrate}\0" \ "contyp=ttyS0\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcon;" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ "bootm\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ "bootfile=/tftpboot/jupiter/uImage\0" \ diff --git a/include/configs/sc3.h b/include/configs/sc3.h index f2f059863d..8298084f1e 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -113,10 +113,13 @@ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ + "addcons=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate}\0" \ + "flash_nfs=run nfsargs addip addcons;" \ "bootm ${kernel_addr}\0" \ - "flash_nand=run nand_args addip addcon;bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "flash_nand=run nand_args addip addcons;bootm ${kernel_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ + "bootm\0" \ "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=/tftpboot/sc3/uImage\0" \ "u-boot=/tftpboot/sc3/u-boot.bin\0" \ -- cgit v1.2.1 From 76d1466f918b881cda2d259254761e73885093c2 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Tue, 13 Mar 2007 13:38:05 +0100 Subject: [PATCH] renamed environment variable 'addcon' to 'addcons' for PCI405 boards in terms of unification. Signed-off-by: Matthias Fuchs --- include/configs/PCI405.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 9d5c4f4d04..027dd22bf4 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -1,6 +1,9 @@ /* + * (C) Copyright 2007 + * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com + * * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this * project. @@ -32,8 +35,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_IDENT_STRING " $Name: esd_PCI405_05_07_28 $" - #define CONFIG_405GP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PCI405 1 /* ...on a PCI405 board */ @@ -53,9 +54,9 @@ "mem_linux=14336k\0" \ "optargs=panic=0\0" \ "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \ - "addcon=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \ + "addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \ "" -#define CONFIG_BOOTCOMMAND "run ramargs;run addcon;loadpci" +#define CONFIG_BOOTCOMMAND "run ramargs;run addcons;loadpci" #define CONFIG_PREBOOT /* enable preboot variable */ -- cgit v1.2.1 From 8423e5e31a7235d05a482627315fb11d49c17bd7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 16 Mar 2007 21:11:42 +0100 Subject: [PATCH] Use dynamic SDRAM TLB setup on AMCC Ebony eval board Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the DDR memory are dynamically programmed matching the total size of the equipped memory (DIMM modules). Signed-off-by: Stefan Roese --- include/configs/ebony.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 6c4d7cc4fe..a42319b097 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -133,8 +133,9 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ +#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/ /*----------------------------------------------------------------------- * I2C -- cgit v1.2.1 From 26bf7deca364a5b33f39e8f14ddd3f4081345015 Mon Sep 17 00:00:00 2001 From: Aubrey Li Date: Mon, 19 Mar 2007 01:24:52 +0800 Subject: [Blackfin][PATCH] Add BF537 stamp board support --- include/asm-blackfin/arch-bf537/anomaly.h | 116 + include/asm-blackfin/arch-bf537/bf537_serial.h | 78 + include/asm-blackfin/arch-bf537/bf5xx_rtc.h | 46 + include/asm-blackfin/arch-bf537/cdefBF534.h | 1009 +++++++++ include/asm-blackfin/arch-bf537/cdefBF537.h | 186 ++ include/asm-blackfin/arch-bf537/cplbtab.h | 408 ++++ include/asm-blackfin/arch-bf537/defBF534.h | 2627 +++++++++++++++++++++++ include/asm-blackfin/arch-bf537/defBF537.h | 488 +++++ include/asm-blackfin/arch-bf537/defBF537_extn.h | 76 + include/asm-blackfin/arch-bf537/irq.h | 94 + include/configs/bf537-stamp.h | 502 +++++ 11 files changed, 5630 insertions(+) create mode 100644 include/asm-blackfin/arch-bf537/anomaly.h create mode 100644 include/asm-blackfin/arch-bf537/bf537_serial.h create mode 100644 include/asm-blackfin/arch-bf537/bf5xx_rtc.h create mode 100644 include/asm-blackfin/arch-bf537/cdefBF534.h create mode 100644 include/asm-blackfin/arch-bf537/cdefBF537.h create mode 100644 include/asm-blackfin/arch-bf537/cplbtab.h create mode 100644 include/asm-blackfin/arch-bf537/defBF534.h create mode 100644 include/asm-blackfin/arch-bf537/defBF537.h create mode 100644 include/asm-blackfin/arch-bf537/defBF537_extn.h create mode 100644 include/asm-blackfin/arch-bf537/irq.h create mode 100644 include/configs/bf537-stamp.h (limited to 'include') diff --git a/include/asm-blackfin/arch-bf537/anomaly.h b/include/asm-blackfin/arch-bf537/anomaly.h new file mode 100644 index 0000000000..50b44da986 --- /dev/null +++ b/include/asm-blackfin/arch-bf537/anomaly.h @@ -0,0 +1,116 @@ +/* + * File: include/asm-blackfin/arch-bf537/anomaly.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* This file shoule be up to date with: + * - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List + * - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List + * - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List + */ + +#ifndef _MACH_ANOMALY_H_ +#define _MACH_ANOMALY_H_ + +/* We do not support 0.1 silicon - sorry */ +#if (defined(CONFIG_BF_REV_0_1)) +#error Kernel will not work on BF537/6/4 Version 0.1 +#endif + +#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2)) +#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in + slot1 and store of a P register in slot 2 is not + supported */ +#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive + Channel DMA stops */ +#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR + registers. */ +#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out + upper bits */ +#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame + syncs */ +#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) +#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is + Changed */ +#endif +#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on + SPORT external receive and transmit clocks. */ +#define ANOMALY_05000272 /* Certain data cache write through modes fail for + VDDint <=0.9V */ +#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */ +#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after + an edge is detected may clear interrupt */ +#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is + not restored */ +#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic + control */ +#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when + killed in a particular stage */ +#endif + +#if defined(CONFIG_BF_REV_0_2) +#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or + IDLE around a Change of Control causes + unpredictable results */ +#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel + (TDM) */ +#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) +#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */ +#endif +#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ +#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event + interrupt not functional */ +#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) +#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */ +#endif +#define ANOMALY_05000257 /* An interrupt or exception during short Hardware + loops may cause the instruction fetch unit to + malfunction */ +#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of + the ICPLB Data registers differ */ +#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ +#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ +#define ANOMALY_05000262 /* Stores to data cache may be lost */ +#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */ +#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE + instruction will cause an infinite stall in the + second to last instruction in a hardware loop */ +#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running + and non-zero DEB_TRAFFIC_PERIOD value */ +#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the + internal voltage regulator (VDDint) to decrease */ +#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after + an edge is detected may clear interrupt */ +#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause + DMA system instability */ +#define ANOMALY_05000280 /* SPI Master boot mode does not work well with + Atmel Dataflash devices */ + +#endif /* CONFIG_BF_REV_0_2 */ + +#endif /* _MACH_ANOMALY_H_ */ diff --git a/include/asm-blackfin/arch-bf537/bf537_serial.h b/include/asm-blackfin/arch-bf537/bf537_serial.h new file mode 100644 index 0000000000..1610411ee9 --- /dev/null +++ b/include/asm-blackfin/arch-bf537/bf537_serial.h @@ -0,0 +1,78 @@ +/* + * U-boot bf537_serial.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BF537_SERIAL_H_ +#define _BF537_SERIAL_H_ + +#define BYTE_REF(addr) (*((volatile char*)addr)) +#define HALFWORD_REF(addr) (*((volatile short*)addr)) +#define WORD_REF(addr) (*((volatile long*)addr)) + +#define UART_THR_LO HALFWORD_REF(UART_THR) +#define UART_RBR_LO HALFWORD_REF(UART_RBR) +#define UART_DLL_LO HALFWORD_REF(UART_DLL) +#define UART_IER_LO HALFWORD_REF(UART_IER) +#define UART_IER_ERBFI 0x01 +#define UART_IER_ETBEI 0x02 +#define UART_IER_ELSI 0x04 +#define UART_IER_EDDSI 0x08 + +#define UART_DLH_LO HALFWORD_REF(UART_DLH) +#define UART_IIR_LO HALFWORD_REF(UART_IIR) +#define UART_IIR_NOINT 0x01 +#define UART_IIR_STATUS 0x06 +#define UART_IIR_LSR 0x06 +#define UART_IIR_RBR 0x04 +#define UART_IIR_THR 0x02 +#define UART_IIR_MSR 0x00 + +#define UART_LCR_LO HALFWORD_REF(UART_LCR) +#define UART_LCR_WLS5 0 +#define UART_LCR_WLS6 0x01 +#define UART_LCR_WLS7 0x02 +#define UART_LCR_WLS8 0x03 +#define UART_LCR_STB 0x04 +#define UART_LCR_PEN 0x08 +#define UART_LCR_EPS 0x10 +#define UART_LCR_SP 0x20 +#define UART_LCR_SB 0x40 +#define UART_LCR_DLAB 0x80 + +#define UART_MCR_LO HALFWORD_REF(UART_MCR) + +#define UART_LSR_LO HALFWORD_REF(UART_LSR) +#define UART_LSR_DR 0x01 +#define UART_LSR_OE 0x02 +#define UART_LSR_PE 0x04 +#define UART_LSR_FE 0x08 +#define UART_LSR_BI 0x10 +#define UART_LSR_THRE 0x20 +#define UART_LSR_TEMT 0x40 + +#define UART_MSR_LO HALFWORD_REF(UART_MSR) +#define UART_SCR_LO HALFWORD_REF(UART_SCR) +#define UART_GCTL_LO HALFWORD_REF(UART_GCTL) +#define UART_GCTL_UCEN 0x01 + +#endif diff --git a/include/asm-blackfin/arch-bf537/bf5xx_rtc.h b/include/asm-blackfin/arch-bf537/bf5xx_rtc.h new file mode 100644 index 0000000000..0043e42bf2 --- /dev/null +++ b/include/asm-blackfin/arch-bf537/bf5xx_rtc.h @@ -0,0 +1,46 @@ +/* + * U-boot - bf537_rtc.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BF537_RTC_H_ +#define _BF537_RTC_H_ + +void rtc_init(void); +void wait_for_complete(void); +void rtc_reset(void); + +#define MIN_TO_SECS(_x_) (60 * _x_) +#define HRS_TO_SECS(_x_) (60 * 60 * _x_) +#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_) + +#define NUM_SECS_IN_DAY (24 * 3600) +#define NUM_SECS_IN_HOUR (3600) +#define NUM_SECS_IN_MIN (60) + +/* Shift values for RTC_STAT register */ +#define DAY_BITS_OFF 17 +#define HOUR_BITS_OFF 12 +#define MIN_BITS_OFF 6 +#define SEC_BITS_OFF 0 + +#endif diff --git a/include/asm-blackfin/arch-bf537/cdefBF534.h b/include/asm-blackfin/arch-bf537/cdefBF534.h new file mode 100644 index 0000000000..5a89e92536 --- /dev/null +++ b/include/asm-blackfin/arch-bf537/cdefBF534.h @@ -0,0 +1,1009 @@ +/* + * Copyright (C) 2005 Analog Devices Inc., All Rights Reserved. + * + *********************************************************************************** + * + * This include file contains a list of macro "defines" to enable the programmer + * to use symbolic names for register-access. + * + * ---------------------------- + * revision 0.1 + * date: 2005/01/27 14:31:01; author: joeb + * Initial revision + */ + +/* + * System MMR Register Map + */ + +#ifndef _CDEF_BF534_H +#define _CDEF_BF534_H + +/* Include all Core registers and bit definitions */ +#include + +/* Include core specific register pointer definitions */ +#include + +#define pCHIPID ((volatile unsigned long *)CHIPID) + +/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ +#define pPLL_CTL ((volatile unsigned short *)PLL_CTL) +#define pPLL_DIV ((volatile unsigned short *)PLL_DIV) +#define pVR_CTL ((volatile unsigned short *)VR_CTL) +#define pPLL_STAT ((volatile unsigned short *)PLL_STAT) +#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT) + +/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ +#define pSWRST ((volatile unsigned short *)SWRST) +#define pSYSCR ((volatile unsigned short *)SYSCR) +#define pSIC_RVECT ((void * volatile *)SIC_RVECT) +#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK) +#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0) +#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1) +#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2) +#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3) +#define pSIC_ISR ((volatile unsigned long *)SIC_ISR) +#define pSIC_IWR ((volatile unsigned long *)SIC_IWR) + +/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ +#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL) +#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT) +#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT) + +/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ +#define pRTC_STAT ((volatile unsigned long *)RTC_STAT) +#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL) +#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT) +#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT) +#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM) +#define pRTC_FAST ((volatile unsigned short *)RTC_FAST) +#define pRTC_PREN ((volatile unsigned short *)RTC_PREN) + +/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ +#define pUART0_THR ((volatile unsigned short *)UART0_THR) +#define pUART0_RBR ((volatile unsigned short *)UART0_RBR) +#define pUART0_DLL ((volatile unsigned short *)UART0_DLL) +#define pUART0_IER ((volatile unsigned short *)UART0_IER) +#define pUART0_DLH ((volatile unsigned short *)UART0_DLH) +#define pUART0_IIR ((volatile unsigned short *)UART0_IIR) +#define pUART0_LCR ((volatile unsigned short *)UART0_LCR) +#define pUART0_MCR ((volatile unsigned short *)UART0_MCR) +#define pUART0_LSR ((volatile unsigned short *)UART0_LSR) +#define pUART0_MSR ((volatile unsigned short *)UART0_LSR) +#define pUART0_SCR ((volatile unsigned short *)UART0_SCR) +#define pUART0_GCTL ((volatile unsigned short *)UART0_GCTL) + +/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define pSPI_CTL ((volatile unsigned short *)SPI_CTL) +#define pSPI_FLG ((volatile unsigned short *)SPI_FLG) +#define pSPI_STAT ((volatile unsigned short *)SPI_STAT) +#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR) +#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR) +#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD) +#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW) + +/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ +#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG) +#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER) +#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD) +#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH) + +#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG) +#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER) +#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD) +#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH) + +#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG) +#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER) +#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD) +#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH) + +#define pTIMER3_CONFIG ((volatile unsigned short *)TIMER3_CONFIG) +#define pTIMER3_COUNTER ((volatile unsigned long *)TIMER3_COUNTER) +#define pTIMER3_PERIOD ((volatile unsigned long *)TIMER3_PERIOD) +#define pTIMER3_WIDTH ((volatile unsigned long *)TIMER3_WIDTH) + +#define pTIMER4_CONFIG ((volatile unsigned short *)TIMER4_CONFIG) +#define pTIMER4_COUNTER ((volatile unsigned long *)TIMER4_COUNTER) +#define pTIMER4_PERIOD ((volatile unsigned long *)TIMER4_PERIOD) +#define pTIMER4_WIDTH ((volatile unsigned long *)TIMER4_WIDTH) + +#define pTIMER5_CONFIG ((volatile unsigned short *)TIMER5_CONFIG) +#define pTIMER5_COUNTER ((volatile unsigned long *)TIMER5_COUNTER) +#define pTIMER5_PERIOD ((volatile unsigned long *)TIMER5_PERIOD) +#define pTIMER5_WIDTH ((volatile unsigned long *)TIMER5_WIDTH) + +#define pTIMER6_CONFIG ((volatile unsigned short *)TIMER6_CONFIG) +#define pTIMER6_COUNTER ((volatile unsigned long *)TIMER6_COUNTER) +#define pTIMER6_PERIOD ((volatile unsigned long *)TIMER6_PERIOD) +#define pTIMER6_WIDTH ((volatile unsigned long *)TIMER6_WIDTH) + +#define pTIMER7_CONFIG ((volatile unsigned short *)TIMER7_CONFIG) +#define pTIMER7_COUNTER ((volatile unsigned long *)TIMER7_COUNTER) +#define pTIMER7_PERIOD ((volatile unsigned long *)TIMER7_PERIOD) +#define pTIMER7_WIDTH ((volatile unsigned long *)TIMER7_WIDTH) + +#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE) +#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE) +#define pTIMER_STATUS ((volatile unsigned long *)TIMER_STATUS) + +/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ +#define pPORTFIO ((volatile unsigned short *)PORTFIO) +#define pPORTFIO_CLEAR ((volatile unsigned short *)PORTFIO_CLEAR) +#define pPORTFIO_SET ((volatile unsigned short *)PORTFIO_SET) +#define pPORTFIO_TOGGLE ((volatile unsigned short *)PORTFIO_TOGGLE) +#define pPORTFIO_MASKA ((volatile unsigned short *)PORTFIO_MASKA) +#define pPORTFIO_MASKA_CLEAR ((volatile unsigned short *)PORTFIO_MASKA_CLEAR) +#define pPORTFIO_MASKA_SET ((volatile unsigned short *)PORTFIO_MASKA_SET) +#define pPORTFIO_MASKA_TOGGLE ((volatile unsigned short *)PORTFIO_MASKA_TOGGLE) +#define pPORTFIO_MASKB ((volatile unsigned short *)PORTFIO_MASKB) +#define pPORTFIO_MASKB_CLEAR ((volatile unsigned short *)PORTFIO_MASKB_CLEAR) +#define pPORTFIO_MASKB_SET ((volatile unsigned short *)PORTFIO_MASKB_SET) +#define pPORTFIO_MASKB_TOGGLE ((volatile unsigned short *)PORTFIO_MASKB_TOGGLE) +#define pPORTFIO_DIR ((volatile unsigned short *)PORTFIO_DIR) +#define pPORTFIO_POLAR ((volatile unsigned short *)PORTFIO_POLAR) +#define pPORTFIO_EDGE ((volatile unsigned short *)PORTFIO_EDGE) +#define pPORTFIO_BOTH ((volatile unsigned short *)PORTFIO_BOTH) +#define pPORTFIO_INEN ((volatile unsigned short *)PORTFIO_INEN) + +#define pFIO_DIR pPORTFIO_DIR +#define pFIO_FLAG_C pPORTFIO_CLEAR +#define pFIO_FLAG_S pPORTFIO_SET +#define pFIO_INEN pPORTFIO_INEN +#define pFIO_FLAG_D pPORTFIO + +/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ +#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1) +#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2) +#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV) +#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV) +#define pSPORT0_TX ((volatile unsigned long *)SPORT0_TX) +#define pSPORT0_RX ((volatile unsigned long *)SPORT0_RX) +#define pSPORT0_TX32 ((volatile unsigned long *)SPORT0_TX) +#define pSPORT0_RX32 ((volatile unsigned long *)SPORT0_RX) +#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX) +#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX) +#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1) +#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2) +#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV) +#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV) +#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT) +#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL) +#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1) +#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2) +#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0) +#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1) +#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2) +#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3) +#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0) +#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1) +#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2) +#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3) + +/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ +#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1) +#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2) +#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV) +#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV) +#define pSPORT1_TX ((volatile unsigned long *)SPORT1_TX) +#define pSPORT1_RX ((volatile unsigned long *)SPORT1_RX) +#define pSPORT1_TX32 ((volatile unsigned long *)SPORT1_TX) +#define pSPORT1_RX32 ((volatile unsigned long *)SPORT1_RX) +#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX) +#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX) +#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1) +#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2) +#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV) +#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV) +#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT) +#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL) +#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1) +#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2) +#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0) +#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1) +#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2) +#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3) +#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0) +#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1) +#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2) +#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3) + +/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ +#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL) +#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0) +#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1) +#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL) +#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL) +#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC) +#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT) + +/* DMA Traffic Control Registers */ +#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER) +#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT) + +/* DMA Controller */ +#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG) +#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) +#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) +#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT) +#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT) +#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY) +#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY) +#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) +#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) +#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT) +#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT) +#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS) +#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP) + +#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG) +#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) +#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) +#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT) +#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT) +#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY) +#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY) +#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) +#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) +#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT) +#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT) +#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS) +#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP) + +#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG) +#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) +#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) +#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT) +#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT) +#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY) +#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY) +#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) +#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) +#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT) +#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT) +#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS) +#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP) + +#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG) +#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) +#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) +#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT) +#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT) +#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY) +#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY) +#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) +#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) +#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT) +#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT) +#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS) +#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP) + +#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG) +#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) +#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) +#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT) +#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT) +#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY) +#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY) +#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) +#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) +#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT) +#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT) +#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS) +#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP) + +#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG) +#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) +#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) +#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT) +#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT) +#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY) +#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY) +#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) +#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) +#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT) +#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT) +#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS) +#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP) + +#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG) +#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) +#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) +#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT) +#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT) +#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY) +#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY) +#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) +#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) +#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT) +#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT) +#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS) +#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP) + +#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG) +#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) +#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) +#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT) +#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT) +#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY) +#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY) +#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) +#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) +#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT) +#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT) +#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS) +#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP) + +#define pDMA8_CONFIG ((volatile unsigned short *)DMA8_CONFIG) +#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) +#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) +#define pDMA8_X_COUNT ((volatile unsigned short *)DMA8_X_COUNT) +#define pDMA8_Y_COUNT ((volatile unsigned short *)DMA8_Y_COUNT) +#define pDMA8_X_MODIFY ((volatile signed short *)DMA8_X_MODIFY) +#define pDMA8_Y_MODIFY ((volatile signed short *)DMA8_Y_MODIFY) +#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) +#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) +#define pDMA8_CURR_X_COUNT ((volatile unsigned short *)DMA8_CURR_X_COUNT) +#define pDMA8_CURR_Y_COUNT ((volatile unsigned short *)DMA8_CURR_Y_COUNT) +#define pDMA8_IRQ_STATUS ((volatile unsigned short *)DMA8_IRQ_STATUS) +#define pDMA8_PERIPHERAL_MAP ((volatile unsigned short *)DMA8_PERIPHERAL_MAP) + +#define pDMA9_CONFIG ((volatile unsigned short *)DMA9_CONFIG) +#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) +#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) +#define pDMA9_X_COUNT ((volatile unsigned short *)DMA9_X_COUNT) +#define pDMA9_Y_COUNT ((volatile unsigned short *)DMA9_Y_COUNT) +#define pDMA9_X_MODIFY ((volatile signed short *)DMA9_X_MODIFY) +#define pDMA9_Y_MODIFY ((volatile signed short *)DMA9_Y_MODIFY) +#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) +#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) +#define pDMA9_CURR_X_COUNT ((volatile unsigned short *)DMA9_CURR_X_COUNT) +#define pDMA9_CURR_Y_COUNT ((volatile unsigned short *)DMA9_CURR_Y_COUNT) +#define pDMA9_IRQ_STATUS ((volatile unsigned short *)DMA9_IRQ_STATUS) +#define pDMA9_PERIPHERAL_MAP ((volatile unsigned short *)DMA9_PERIPHERAL_MAP) + +#define pDMA10_CONFIG ((volatile unsigned short *)DMA10_CONFIG) +#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) +#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) +#define pDMA10_X_COUNT ((volatile unsigned short *)DMA10_X_COUNT) +#define pDMA10_Y_COUNT ((volatile unsigned short *)DMA10_Y_COUNT) +#define pDMA10_X_MODIFY ((volatile signed short *)DMA10_X_MODIFY) +#define pDMA10_Y_MODIFY ((volatile signed short *)DMA10_Y_MODIFY) +#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) +#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) +#define pDMA10_CURR_X_COUNT ((volatile unsigned short *)DMA10_CURR_X_COUNT) +#define pDMA10_CURR_Y_COUNT ((volatile unsigned short *)DMA10_CURR_Y_COUNT) +#define pDMA10_IRQ_STATUS ((volatile unsigned short *)DMA10_IRQ_STATUS) +#define pDMA10_PERIPHERAL_MAP ((volatile unsigned short *)DMA10_PERIPHERAL_MAP) + +#define pDMA11_CONFIG ((volatile unsigned short *)DMA11_CONFIG) +#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) +#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) +#define pDMA11_X_COUNT ((volatile unsigned short *)DMA11_X_COUNT) +#define pDMA11_Y_COUNT ((volatile unsigned short *)DMA11_Y_COUNT) +#define pDMA11_X_MODIFY ((volatile signed short *)DMA11_X_MODIFY) +#define pDMA11_Y_MODIFY ((volatile signed short *)DMA11_Y_MODIFY) +#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) +#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) +#define pDMA11_CURR_X_COUNT ((volatile unsigned short *)DMA11_CURR_X_COUNT) +#define pDMA11_CURR_Y_COUNT ((volatile unsigned short *)DMA11_CURR_Y_COUNT) +#define pDMA11_IRQ_STATUS ((volatile unsigned short *)DMA11_IRQ_STATUS) +#define pDMA11_PERIPHERAL_MAP ((volatile unsigned short *)DMA11_PERIPHERAL_MAP) + +#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG) +#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) +#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) +#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT) +#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT) +#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY) +#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY) +#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) +#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) +#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT) +#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT) +#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS) +#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP) + +#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG) +#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) +#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) +#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT) +#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT) +#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY) +#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY) +#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) +#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) +#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT) +#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT) +#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS) +#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP) + +#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG) +#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) +#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) +#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT) +#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT) +#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY) +#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY) +#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) +#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) +#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT) +#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT) +#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS) +#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP) + +#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG) +#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) +#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) +#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT) +#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT) +#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY) +#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY) +#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) +#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) +#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT) +#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT) +#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS) +#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP) + +/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ +#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL) +#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS) +#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY) +#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT) +#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME) + +/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ +#define pTWI_CLKDIV ((volatile unsigned short *)TWI_CLKDIV) +#define pTWI_CONTROL ((volatile unsigned short *)TWI_CONTROL) +#define pTWI_SLAVE_CTL ((volatile unsigned short *)TWI_SLAVE_CTL) +#define pTWI_SLAVE_STAT ((volatile unsigned short *)TWI_SLAVE_STAT) +#define pTWI_SLAVE_ADDR ((volatile unsigned short *)TWI_SLAVE_ADDR) +#define pTWI_MASTER_CTL ((volatile unsigned short *)TWI_MASTER_CTL) +#define pTWI_MASTER_STAT ((volatile unsigned short *)TWI_MASTER_STAT) +#define pTWI_MASTER_ADDR ((volatile unsigned short *)TWI_MASTER_ADDR) +#define pTWI_INT_STAT ((volatile unsigned short *)TWI_INT_STAT) +#define pTWI_INT_MASK ((volatile unsigned short *)TWI_INT_MASK) +#define pTWI_FIFO_CTL ((volatile unsigned short *)TWI_FIFO_CTL) +#define pTWI_FIFO_STAT ((volatile unsigned short *)TWI_FIFO_STAT) +#define pTWI_XMT_DATA8 ((volatile unsigned short *)TWI_XMT_DATA8) +#define pTWI_XMT_DATA16 ((volatile unsigned short *)TWI_XMT_DATA16) +#define pTWI_RCV_DATA8 ((volatile unsigned short *)TWI_RCV_DATA8) +#define pTWI_RCV_DATA16 ((volatile unsigned short *)TWI_RCV_DATA16) + +/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ +#define pPORTGIO ((volatile unsigned short *)PORTGIO) +#define pPORTGIO_CLEAR ((volatile unsigned short *)PORTGIO_CLEAR) +#define pPORTGIO_SET ((volatile unsigned short *)PORTGIO_SET) +#define pPORTGIO_TOGGLE ((volatile unsigned short *)PORTGIO_TOGGLE) +#define pPORTGIO_MASKA ((volatile unsigned short *)PORTGIO_MASKA) +#define pPORTGIO_MASKA_CLEAR ((volatile unsigned short *)PORTGIO_MASKA_CLEAR) +#define pPORTGIO_MASKA_SET ((volatile unsigned short *)PORTGIO_MASKA_SET) +#define pPORTGIO_MASKA_TOGGLE ((volatile unsigned short *)PORTGIO_MASKA_TOGGLE) +#define pPORTGIO_MASKB ((volatile unsigned short *)PORTGIO_MASKB) +#define pPORTGIO_MASKB_CLEAR ((volatile unsigned short *)PORTGIO_MASKB_CLEAR) +#define pPORTGIO_MASKB_SET ((volatile unsigned short *)PORTGIO_MASKB_SET) +#define pPORTGIO_MASKB_TOGGLE ((volatile unsigned short *)PORTGIO_MASKB_TOGGLE) +#define pPORTGIO_DIR ((volatile unsigned short *)PORTGIO_DIR) +#define pPORTGIO_POLAR ((volatile unsigned short *)PORTGIO_POLAR) +#define pPORTGIO_EDGE ((volatile unsigned short *)PORTGIO_EDGE) +#define pPORTGIO_BOTH ((volatile unsigned short *)PORTGIO_BOTH) +#define pPORTGIO_INEN ((volatile unsigned short *)PORTGIO_INEN) + +/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ +#define pPORTHIO ((volatile unsigned short *)PORTHIO) +#define pPORTHIO_CLEAR ((volatile unsigned short *)PORTHIO_CLEAR) +#define pPORTHIO_SET ((volatile unsigned short *)PORTHIO_SET) +#define pPORTHIO_TOGGLE ((volatile unsigned short *)PORTHIO_TOGGLE) +#define pPORTHIO_MASKA ((volatile unsigned short *)PORTHIO_MASKA) +#define pPORTHIO_MASKA_CLEAR ((volatile unsigned short *)PORTHIO_MASKA_CLEAR) +#define pPORTHIO_MASKA_SET ((volatile unsigned short *)PORTHIO_MASKA_SET) +#define pPORTHIO_MASKA_TOGGLE ((volatile unsigned short *)PORTHIO_MASKA_TOGGLE) +#define pPORTHIO_MASKB ((volatile unsigned short *)PORTHIO_MASKB) +#define pPORTHIO_MASKB_CLEAR ((volatile unsigned short *)PORTHIO_MASKB_CLEAR) +#define pPORTHIO_MASKB_SET ((volatile unsigned short *)PORTHIO_MASKB_SET) +#define pPORTHIO_MASKB_TOGGLE ((volatile unsigned short *)PORTHIO_MASKB_TOGGLE) +#define pPORTHIO_DIR ((volatile unsigned short *)PORTHIO_DIR) +#define pPORTHIO_POLAR ((volatile unsigned short *)PORTHIO_POLAR) +#define pPORTHIO_EDGE ((volatile unsigned short *)PORTHIO_EDGE) +#define pPORTHIO_BOTH ((volatile unsigned short *)PORTHIO_BOTH) +#define pPORTHIO_INEN ((volatile unsigned short *)PORTHIO_INEN) + +/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ +#define pUART1_THR ((volatile unsigned short *)UART1_THR) +#define pUART1_RBR ((volatile unsigned short *)UART1_RBR) +#define pUART1_DLL ((volatile unsigned short *)UART1_DLL) +#define pUART1_IER ((volatile unsigned short *)UART1_IER) +#define pUART1_DLH ((volatile unsigned short *)UART1_DLH) +#define pUART1_IIR ((volatile unsigned short *)UART1_IIR) +#define pUART1_LCR ((volatile unsigned short *)UART1_LCR) +#define pUART1_MCR ((volatile unsigned short *)UART1_MCR) +#define pUART1_LSR ((volatile unsigned short *)UART1_LSR) +#define pUART1_MSR ((volatile unsigned short *)UART1_LSR) +#define pUART1_SCR ((volatile unsigned short *)UART1_SCR) +#define pUART1_GCTL ((volatile unsigned short *)UART1_GCTL) + +/* default UART controller */ +#if (CONFIG_UART_CONSOLE==1) + +#define pUART_THR pUART1_THR +#define pUART_RBR pUART1_RBR +#define pUART_DLL pUART1_DLL +#define pUART_IER pUART1_IER +#define pUART_DLH pUART1_DLH +#define pUART_IIR pUART1_IIR +#define pUART_LCR pUART1_LCR +#define pUART_MCR pUART1_MCR +#define pUART_LSR pUART1_LSR +#define pUART_MSR pUART1_MSR +#define pUART_SCR pUART1_SCR +#define pUART_GCTL pUART1_GCTL + +#else + +#define pUART_THR pUART0_THR +#define pUART_RBR pUART0_RBR +#define pUART_DLL pUART0_DLL +#define pUART_IER pUART0_IER +#define pUART_DLH pUART0_DLH +#define pUART_IIR pUART0_IIR +#define pUART_LCR pUART0_LCR +#define pUART_MCR pUART0_MCR +#define pUART_LSR pUART0_LSR +#define pUART_MSR pUART0_MSR +#define pUART_SCR pUART0_SCR +#define pUART_GCTL pUART0_GCTL + +#endif + +/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */ +/* For Mailboxes 0-15 */ +#define pCAN_MC1 ((volatile unsigned short *)CAN_MC1) +#define pCAN_MD1 ((volatile unsigned short *)CAN_MD1) +#define pCAN_TRS1 ((volatile unsigned short *)CAN_TRS1) +#define pCAN_TRR1 ((volatile unsigned short *)CAN_TRR1) +#define pCAN_TA1 ((volatile unsigned short *)CAN_TA1) +#define pCAN_AA1 ((volatile unsigned short *)CAN_AA1) +#define pCAN_RMP1 ((volatile unsigned short *)CAN_RMP1) +#define pCAN_RML1 ((volatile unsigned short *)CAN_RML1) +#define pCAN_MBTIF1 ((volatile unsigned short *)CAN_MBTIF1) +#define pCAN_MBRIF1 ((volatile unsigned short *)CAN_MBRIF1) +#define pCAN_MBIM1 ((volatile unsigned short *)CAN_MBIM1) +#define pCAN_RFH1 ((volatile unsigned short *)CAN_RFH1) +#define pCAN_OPSS1 ((volatile unsigned short *)CAN_OPSS1) + +/* For Mailboxes 16-31 */ +#define pCAN_MC2 ((volatile unsigned short *)CAN_MC2) +#define pCAN_MD2 ((volatile unsigned short *)CAN_MD2) +#define pCAN_TRS2 ((volatile unsigned short *)CAN_TRS2) +#define pCAN_TRR2 ((volatile unsigned short *)CAN_TRR2) +#define pCAN_TA2 ((volatile unsigned short *)CAN_TA2) +#define pCAN_AA2 ((volatile unsigned short *)CAN_AA2) +#define pCAN_RMP2 ((volatile unsigned short *)CAN_RMP2) +#define pCAN_RML2 ((volatile unsigned short *)CAN_RML2) +#define pCAN_MBTIF2 ((volatile unsigned short *)CAN_MBTIF2) +#define pCAN_MBRIF2 ((volatile unsigned short *)CAN_MBRIF2) +#define pCAN_MBIM2 ((volatile unsigned short *)CAN_MBIM2) +#define pCAN_RFH2 ((volatile unsigned short *)CAN_RFH2) +#define pCAN_OPSS2 ((volatile unsigned short *)CAN_OPSS2) + +#define pCAN_CLOCK ((volatile unsigned short *)CAN_CLOCK) +#define pCAN_TIMING ((volatile unsigned short *)CAN_TIMING) +#define pCAN_DEBUG ((volatile unsigned short *)CAN_DEBUG) +#define pCAN_STATUS ((volatile unsigned short *)CAN_STATUS) +#define pCAN_CEC ((volatile unsigned short *)CAN_CEC) +#define pCAN_GIS ((volatile unsigned short *)CAN_GIS) +#define pCAN_GIM ((volatile unsigned short *)CAN_GIM) +#define pCAN_GIF ((volatile unsigned short *)CAN_GIF) +#define pCAN_CONTROL ((volatile unsigned short *)CAN_CONTROL) +#define pCAN_INTR ((volatile unsigned short *)CAN_INTR) +#define pCAN_SFCMVER ((volatile unsigned short *)CAN_SFCMVER) +#define pCAN_MBTD ((volatile unsigned short *)CAN_MBTD) +#define pCAN_EWR ((volatile unsigned short *)CAN_EWR) +#define pCAN_ESR ((volatile unsigned short *)CAN_ESR) +#define pCAN_UCREG ((volatile unsigned short *)CAN_UCREG) +#define pCAN_UCCNT ((volatile unsigned short *)CAN_UCCNT) +#define pCAN_UCRC ((volatile unsigned short *)CAN_UCRC) +#define pCAN_UCCNF ((volatile unsigned short *)CAN_UCCNF) +#define pCAN_SFCMVER2 ((volatile unsigned short *)CAN_SFCMVER2) + +/* Mailbox Acceptance Masks */ +#define pCAN_AM00L ((volatile unsigned short *)CAN_AM00L) +#define pCAN_AM00H ((volatile unsigned short *)CAN_AM00H) +#define pCAN_AM01L ((volatile unsigned short *)CAN_AM01L) +#define pCAN_AM01H ((volatile unsigned short *)CAN_AM01H) +#define pCAN_AM02L ((volatile unsigned short *)CAN_AM02L) +#define pCAN_AM02H ((volatile unsigned short *)CAN_AM02H) +#define pCAN_AM03L ((volatile unsigned short *)CAN_AM03L) +#define pCAN_AM03H ((volatile unsigned short *)CAN_AM03H) +#define pCAN_AM04L ((volatile unsigned short *)CAN_AM04L) +#define pCAN_AM04H ((volatile unsigned short *)CAN_AM04H) +#define pCAN_AM05L ((volatile unsigned short *)CAN_AM05L) +#define pCAN_AM05H ((volatile unsigned short *)CAN_AM05H) +#define pCAN_AM06L ((volatile unsigned short *)CAN_AM06L) +#define pCAN_AM06H ((volatile unsigned short *)CAN_AM06H) +#define pCAN_AM07L ((volatile unsigned short *)CAN_AM07L) +#define pCAN_AM07H ((volatile unsigned short *)CAN_AM07H) +#define pCAN_AM08L ((volatile unsigned short *)CAN_AM08L) +#define pCAN_AM08H ((volatile unsigned short *)CAN_AM08H) +#define pCAN_AM09L ((volatile unsigned short *)CAN_AM09L) +#define pCAN_AM09H ((volatile unsigned short *)CAN_AM09H) +#define pCAN_AM10L ((volatile unsigned short *)CAN_AM10L) +#define pCAN_AM10H ((volatile unsigned short *)CAN_AM10H) +#define pCAN_AM11L ((volatile unsigned short *)CAN_AM11L) +#define pCAN_AM11H ((volatile unsigned short *)CAN_AM11H) +#define pCAN_AM12L ((volatile unsigned short *)CAN_AM12L) +#define pCAN_AM12H ((volatile unsigned short *)CAN_AM12H) +#define pCAN_AM13L ((volatile unsigned short *)CAN_AM13L) +#define pCAN_AM13H ((volatile unsigned short *)CAN_AM13H) +#define pCAN_AM14L ((volatile unsigned short *)CAN_AM14L) +#define pCAN_AM14H ((volatile unsigned short *)CAN_AM14H) +#define pCAN_AM15L ((volatile unsigned short *)CAN_AM15L) +#define pCAN_AM15H ((volatile unsigned short *)CAN_AM15H) + +#define pCAN_AM16L ((volatile unsigned short *)CAN_AM16L) +#define pCAN_AM16H ((volatile unsigned short *)CAN_AM16H) +#define pCAN_AM17L ((volatile unsigned short *)CAN_AM17L) +#define pCAN_AM17H ((volatile unsigned short *)CAN_AM17H) +#define pCAN_AM18L ((volatile unsigned short *)CAN_AM18L) +#define pCAN_AM18H ((volatile unsigned short *)CAN_AM18H) +#define pCAN_AM19L ((volatile unsigned short *)CAN_AM19L) +#define pCAN_AM19H ((volatile unsigned short *)CAN_AM19H) +#define pCAN_AM20L ((volatile unsigned short *)CAN_AM20L) +#define pCAN_AM20H ((volatile unsigned short *)CAN_AM20H) +#define pCAN_AM21L ((volatile unsigned short *)CAN_AM21L) +#define pCAN_AM21H ((volatile unsigned short *)CAN_AM21H) +#define pCAN_AM22L ((volatile unsigned short *)CAN_AM22L) +#define pCAN_AM22H ((volatile unsigned short *)CAN_AM22H) +#define pCAN_AM23L ((volatile unsigned short *)CAN_AM23L) +#define pCAN_AM23H ((volatile unsigned short *)CAN_AM23H) +#define pCAN_AM24L ((volatile unsigned short *)CAN_AM24L) +#define pCAN_AM24H ((volatile unsigned short *)CAN_AM24H) +#define pCAN_AM25L ((volatile unsigned short *)CAN_AM25L) +#define pCAN_AM25H ((volatile unsigned short *)CAN_AM25H) +#define pCAN_AM26L ((volatile unsigned short *)CAN_AM26L) +#define pCAN_AM26H ((volatile unsigned short *)CAN_AM26H) +#define pCAN_AM27L ((volatile unsigned short *)CAN_AM27L) +#define pCAN_AM27H ((volatile unsigned short *)CAN_AM27H) +#define pCAN_AM28L ((volatile unsigned short *)CAN_AM28L) +#define pCAN_AM28H ((volatile unsigned short *)CAN_AM28H) +#define pCAN_AM29L ((volatile unsigned short *)CAN_AM29L) +#define pCAN_AM29H ((volatile unsigned short *)CAN_AM29H) +#define pCAN_AM30L ((volatile unsigned short *)CAN_AM30L) +#define pCAN_AM30H ((volatile unsigned short *)CAN_AM30H) +#define pCAN_AM31L ((volatile unsigned short *)CAN_AM31L) +#define pCAN_AM31H ((volatile unsigned short *)CAN_AM31H) + +/* CAN Acceptance Mask Area Macros */ +#define pCAN_AM_L(x) ((volatile unsigned short *)CAN_AM_L(x)) +#define pCAN_AM_H(x) ((volatile unsigned short *)CAN_AM_H(x)) + +/* Mailbox Registers */ +#define pCAN_MB00_ID1 ((volatile unsigned short *)CAN_MB00_ID1) +#define pCAN_MB00_ID0 ((volatile unsigned short *)CAN_MB00_ID0) +#define pCAN_MB00_TIMESTAMP ((volatile unsigned short *)CAN_MB00_TIMESTAMP) +#define pCAN_MB00_LENGTH ((volatile unsigned short *)CAN_MB00_LENGTH) +#define pCAN_MB00_DATA3 ((volatile unsigned short *)CAN_MB00_DATA3) +#define pCAN_MB00_DATA2 ((volatile unsigned short *)CAN_MB00_DATA2) +#define pCAN_MB00_DATA1 ((volatile unsigned short *)CAN_MB00_DATA1) +#define pCAN_MB00_DATA0 ((volatile unsigned short *)CAN_MB00_DATA0) + +#define pCAN_MB01_ID1 ((volatile unsigned short *)CAN_MB01_ID1) +#define pCAN_MB01_ID0 ((volatile unsigned short *)CAN_MB01_ID0) +#define pCAN_MB01_TIMESTAMP ((volatile unsigned short *)CAN_MB01_TIMESTAMP) +#define pCAN_MB01_LENGTH ((volatile unsigned short *)CAN_MB01_LENGTH) +#define pCAN_MB01_DATA3 ((volatile unsigned short *)CAN_MB01_DATA3) +#define pCAN_MB01_DATA2 ((volatile unsigned short *)CAN_MB01_DATA2) +#define pCAN_MB01_DATA1 ((volatile unsigned short *)CAN_MB01_DATA1) +#define pCAN_MB01_DATA0 ((volatile unsigned short *)CAN_MB01_DATA0) + +#define pCAN_MB02_ID1 ((volatile unsigned short *)CAN_MB02_ID1) +#define pCAN_MB02_ID0 ((volatile unsigned short *)CAN_MB02_ID0) +#define pCAN_MB02_TIMESTAMP ((volatile unsigned short *)CAN_MB02_TIMESTAMP) +#define pCAN_MB02_LENGTH ((volatile unsigned short *)CAN_MB02_LENGTH) +#define pCAN_MB02_DATA3 ((volatile unsigned short *)CAN_MB02_DATA3) +#define pCAN_MB02_DATA2 ((volatile unsigned short *)CAN_MB02_DATA2) +#define pCAN_MB02_DATA1 ((volatile unsigned short *)CAN_MB02_DATA1) +#define pCAN_MB02_DATA0 ((volatile unsigned short *)CAN_MB02_DATA0) + +#define pCAN_MB03_ID1 ((volatile unsigned short *)CAN_MB03_ID1) +#define pCAN_MB03_ID0 ((volatile unsigned short *)CAN_MB03_ID0) +#define pCAN_MB03_TIMESTAMP ((volatile unsigned short *)CAN_MB03_TIMESTAMP) +#define pCAN_MB03_LENGTH ((volatile unsigned short *)CAN_MB03_LENGTH) +#define pCAN_MB03_DATA3 ((volatile unsigned short *)CAN_MB03_DATA3) +#define pCAN_MB03_DATA2 ((volatile unsigned short *)CAN_MB03_DATA2) +#define pCAN_MB03_DATA1 ((volatile unsigned short *)CAN_MB03_DATA1) +#define pCAN_MB03_DATA0 ((volatile unsigned short *)CAN_MB03_DATA0) + +#define pCAN_MB04_ID1 ((volatile unsigned short *)CAN_MB04_ID1) +#define pCAN_MB04_ID0 ((volatile unsigned short *)CAN_MB04_ID0) +#define pCAN_MB04_TIMESTAMP ((volatile unsigned short *)CAN_MB04_TIMESTAMP) +#define pCAN_MB04_LENGTH ((volatile unsigned short *)CAN_MB04_LENGTH) +#define pCAN_MB04_DATA3 ((volatile unsigned short *)CAN_MB04_DATA3) +#define pCAN_MB04_DATA2 ((volatile unsigned short *)CAN_MB04_DATA2) +#define pCAN_MB04_DATA1 ((volatile unsigned short *)CAN_MB04_DATA1) +#define pCAN_MB04_DATA0 ((volatile unsigned short *)CAN_MB04_DATA0) + +#define pCAN_MB05_ID1 ((volatile unsigned short *)CAN_MB05_ID1) +#define pCAN_MB05_ID0 ((volatile unsigned short *)CAN_MB05_ID0) +#define pCAN_MB05_TIMESTAMP ((volatile unsigned short *)CAN_MB05_TIMESTAMP) +#define pCAN_MB05_LENGTH ((volatile unsigned short *)CAN_MB05_LENGTH) +#define pCAN_MB05_DATA3 ((volatile unsigned short *)CAN_MB05_DATA3) +#define pCAN_MB05_DATA2 ((volatile unsigned short *)CAN_MB05_DATA2) +#define pCAN_MB05_DATA1 ((volatile unsigned short *)CAN_MB05_DATA1) +#define pCAN_MB05_DATA0 ((volatile unsigned short *)CAN_MB05_DATA0) + +#define pCAN_MB06_ID1 ((volatile unsigned short *)CAN_MB06_ID1) +#define pCAN_MB06_ID0 ((volatile unsigned short *)CAN_MB06_ID0) +#define pCAN_MB06_TIMESTAMP ((volatile unsigned short *)CAN_MB06_TIMESTAMP) +#define pCAN_MB06_LENGTH ((volatile unsigned short *)CAN_MB06_LENGTH) +#define pCAN_MB06_DATA3 ((volatile unsigned short *)CAN_MB06_DATA3) +#define pCAN_MB06_DATA2 ((volatile unsigned short *)CAN_MB06_DATA2) +#define pCAN_MB06_DATA1 ((volatile unsigned short *)CAN_MB06_DATA1) +#define pCAN_MB06_DATA0 ((volatile unsigned short *)CAN_MB06_DATA0) + +#define pCAN_MB07_ID1 ((volatile unsigned short *)CAN_MB07_ID1) +#define pCAN_MB07_ID0 ((volatile unsigned short *)CAN_MB07_ID0) +#define pCAN_MB07_TIMESTAMP ((volatile unsigned short *)CAN_MB07_TIMESTAMP) +#define pCAN_MB07_LENGTH ((volatile unsigned short *)CAN_MB07_LENGTH) +#define pCAN_MB07_DATA3 ((volatile unsigned short *)CAN_MB07_DATA3) +#define pCAN_MB07_DATA2 ((volatile unsigned short *)CAN_MB07_DATA2) +#define pCAN_MB07_DATA1 ((volatile unsigned short *)CAN_MB07_DATA1) +#define pCAN_MB07_DATA0 ((volatile unsigned short *)CAN_MB07_DATA0) + +#define pCAN_MB08_ID1 ((volatile unsigned short *)CAN_MB08_ID1) +#define pCAN_MB08_ID0 ((volatile unsigned short *)CAN_MB08_ID0) +#define pCAN_MB08_TIMESTAMP ((volatile unsigned short *)CAN_MB08_TIMESTAMP) +#define pCAN_MB08_LENGTH ((volatile unsigned short *)CAN_MB08_LENGTH) +#define pCAN_MB08_DATA3 ((volatile unsigned short *)CAN_MB08_DATA3) +#define pCAN_MB08_DATA2 ((volatile unsigned short *)CAN_MB08_DATA2) +#define pCAN_MB08_DATA1 ((volatile unsigned short *)CAN_MB08_DATA1) +#define pCAN_MB08_DATA0 ((volatile unsigned short *)CAN_MB08_DATA0) + +#define pCAN_MB09_ID1 ((volatile unsigned short *)CAN_MB09_ID1) +#define pCAN_MB09_ID0 ((volatile unsigned short *)CAN_MB09_ID0) +#define pCAN_MB09_TIMESTAMP ((volatile unsigned short *)CAN_MB09_TIMESTAMP) +#define pCAN_MB09_LENGTH ((volatile unsigned short *)CAN_MB09_LENGTH) +#define pCAN_MB09_DATA3 ((volatile unsigned short *)CAN_MB09_DATA3) +#define pCAN_MB09_DATA2 ((volatile unsigned short *)CAN_MB09_DATA2) +#define pCAN_MB09_DATA1 ((volatile unsigned short *)CAN_MB09_DATA1) +#define pCAN_MB09_DATA0 ((volatile unsigned short *)CAN_MB09_DATA0) + +#define pCAN_MB10_ID1 ((volatile unsigned short *)CAN_MB10_ID1) +#define pCAN_MB10_ID0 ((volatile unsigned short *)CAN_MB10_ID0) +#define pCAN_MB10_TIMESTAMP ((volatile unsigned short *)CAN_MB10_TIMESTAMP) +#define pCAN_MB10_LENGTH ((volatile unsigned short *)CAN_MB10_LENGTH) +#define pCAN_MB10_DATA3 ((volatile unsigned short *)CAN_MB10_DATA3) +#define pCAN_MB10_DATA2 ((volatile unsigned short *)CAN_MB10_DATA2) +#define pCAN_MB10_DATA1 ((volatile unsigned short *)CAN_MB10_DATA1) +#define pCAN_MB10_DATA0 ((volatile unsigned short *)CAN_MB10_DATA0) + +#define pCAN_MB11_ID1 ((volatile unsigned short *)CAN_MB11_ID1) +#define pCAN_MB11_ID0 ((volatile unsigned short *)CAN_MB11_ID0) +#define pCAN_MB11_TIMESTAMP ((volatile unsigned short *)CAN_MB11_TIMESTAMP) +#define pCAN_MB11_LENGTH ((volatile unsigned short *)CAN_MB11_LENGTH) +#define pCAN_MB11_DATA3 ((volatile unsigned short *)CAN_MB11_DATA3) +#define pCAN_MB11_DATA2 ((volatile unsigned short *)CAN_MB11_DATA2) +#define pCAN_MB11_DATA1 ((volatile unsigned short *)CAN_MB11_DATA1) +#define pCAN_MB11_DATA0 ((volatile unsigned short *)CAN_MB11_DATA0) + +#define pCAN_MB12_ID1 ((volatile unsigned short *)CAN_MB12_ID1) +#define pCAN_MB12_ID0 ((volatile unsigned short *)CAN_MB12_ID0) +#define pCAN_MB12_TIMESTAMP ((volatile unsigned short *)CAN_MB12_TIMESTAMP) +#define pCAN_MB12_LENGTH ((volatile unsigned short *)CAN_MB12_LENGTH) +#define pCAN_MB12_DATA3 ((volatile unsigned short *)CAN_MB12_DATA3) +#define pCAN_MB12_DATA2 ((volatile unsigned short *)CAN_MB12_DATA2) +#define pCAN_MB12_DATA1 ((volatile unsigned short *)CAN_MB12_DATA1) +#define pCAN_MB12_DATA0 ((volatile unsigned short *)CAN_MB12_DATA0) + +#define pCAN_MB13_ID1 ((volatile unsigned short *)CAN_MB13_ID1) +#define pCAN_MB13_ID0 ((volatile unsigned short *)CAN_MB13_ID0) +#define pCAN_MB13_TIMESTAMP ((volatile unsigned short *)CAN_MB13_TIMESTAMP) +#define pCAN_MB13_LENGTH ((volatile unsigned short *)CAN_MB13_LENGTH) +#define pCAN_MB13_DATA3 ((volatile unsigned short *)CAN_MB13_DATA3) +#define pCAN_MB13_DATA2 ((volatile unsigned short *)CAN_MB13_DATA2) +#define pCAN_MB13_DATA1 ((volatile unsigned short *)CAN_MB13_DATA1) +#define pCAN_MB13_DATA0 ((volatile unsigned short *)CAN_MB13_DATA0) + +#define pCAN_MB14_ID1 ((volatile unsigned short *)CAN_MB14_ID1) +#define pCAN_MB14_ID0 ((volatile unsigned short *)CAN_MB14_ID0) +#define pCAN_MB14_TIMESTAMP ((volatile unsigned short *)CAN_MB14_TIMESTAMP) +#define pCAN_MB14_LENGTH ((volatile unsigned short *)CAN_MB14_LENGTH) +#define pCAN_MB14_DATA3 ((volatile unsigned short *)CAN_MB14_DATA3) +#define pCAN_MB14_DATA2 ((volatile unsigned short *)CAN_MB14_DATA2) +#define pCAN_MB14_DATA1 ((volatile unsigned short *)CAN_MB14_DATA1) +#define pCAN_MB14_DATA0 ((volatile unsigned short *)CAN_MB14_DATA0) + +#define pCAN_MB15_ID1 ((volatile unsigned short *)CAN_MB15_ID1) +#define pCAN_MB15_ID0 ((volatile unsigned short *)CAN_MB15_ID0) +#define pCAN_MB15_TIMESTAMP ((volatile unsigned short *)CAN_MB15_TIMESTAMP) +#define pCAN_MB15_LENGTH ((volatile unsigned short *)CAN_MB15_LENGTH) +#define pCAN_MB15_DATA3 ((volatile unsigned short *)CAN_MB15_DATA3) +#define pCAN_MB15_DATA2 ((volatile unsigned short *)CAN_MB15_DATA2) +#define pCAN_MB15_DATA1 ((volatile unsigned short *)CAN_MB15_DATA1) +#define pCAN_MB15_DATA0 ((volatile unsigned short *)CAN_MB15_DATA0) + +#define pCAN_MB16_ID1 ((volatile unsigned short *)CAN_MB16_ID1) +#define pCAN_MB16_ID0 ((volatile unsigned short *)CAN_MB16_ID0) +#define pCAN_MB16_TIMESTAMP ((volatile unsigned short *)CAN_MB16_TIMESTAMP) +#define pCAN_MB16_LENGTH ((volatile unsigned short *)CAN_MB16_LENGTH) +#define pCAN_MB16_DATA3 ((volatile unsigned short *)CAN_MB16_DATA3) +#define pCAN_MB16_DATA2 ((volatile unsigned short *)CAN_MB16_DATA2) +#define pCAN_MB16_DATA1 ((volatile unsigned short *)CAN_MB16_DATA1) +#define pCAN_MB16_DATA0 ((volatile unsigned short *)CAN_MB16_DATA0) + +#define pCAN_MB17_ID1 ((volatile unsigned short *)CAN_MB17_ID1) +#define pCAN_MB17_ID0 ((volatile unsigned short *)CAN_MB17_ID0) +#define pCAN_MB17_TIMESTAMP ((volatile unsigned short *)CAN_MB17_TIMESTAMP) +#define pCAN_MB17_LENGTH ((volatile unsigned short *)CAN_MB17_LENGTH) +#define pCAN_MB17_DATA3 ((volatile unsigned short *)CAN_MB17_DATA3) +#define pCAN_MB17_DATA2 ((volatile unsigned short *)CAN_MB17_DATA2) +#define pCAN_MB17_DATA1 ((volatile unsigned short *)CAN_MB17_DATA1) +#define pCAN_MB17_DATA0 ((volatile unsigned short *)CAN_MB17_DATA0) + +#define pCAN_MB18_ID1 ((volatile unsigned short *)CAN_MB18_ID1) +#define pCAN_MB18_ID0 ((volatile unsigned short *)CAN_MB18_ID0) +#define pCAN_MB18_TIMESTAMP ((volatile unsigned short *)CAN_MB18_TIMESTAMP) +#define pCAN_MB18_LENGTH ((volatile unsigned short *)CAN_MB18_LENGTH) +#define pCAN_MB18_DATA3 ((volatile unsigned short *)CAN_MB18_DATA3) +#define pCAN_MB18_DATA2 ((volatile unsigned short *)CAN_MB18_DATA2) +#define pCAN_MB18_DATA1 ((volatile unsigned short *)CAN_MB18_DATA1) +#define pCAN_MB18_DATA0 ((volatile unsigned short *)CAN_MB18_DATA0) + +#define pCAN_MB19_ID1 ((volatile unsigned short *)CAN_MB19_ID1) +#define pCAN_MB19_ID0 ((volatile unsigned short *)CAN_MB19_ID0) +#define pCAN_MB19_TIMESTAMP ((volatile unsigned short *)CAN_MB19_TIMESTAMP) +#define pCAN_MB19_LENGTH ((volatile unsigned short *)CAN_MB19_LENGTH) +#define pCAN_MB19_DATA3 ((volatile unsigned short *)CAN_MB19_DATA3) +#define pCAN_MB19_DATA2 ((volatile unsigned short *)CAN_MB19_DATA2) +#define pCAN_MB19_DATA1 ((volatile unsigned short *)CAN_MB19_DATA1) +#define pCAN_MB19_DATA0 ((volatile unsigned short *)CAN_MB19_DATA0) + +#define pCAN_MB20_ID1 ((volatile unsigned short *)CAN_MB20_ID1) +#define pCAN_MB20_ID0 ((volatile unsigned short *)CAN_MB20_ID0) +#define pCAN_MB20_TIMESTAMP ((volatile unsigned short *)CAN_MB20_TIMESTAMP) +#define pCAN_MB20_LENGTH ((volatile unsigned short *)CAN_MB20_LENGTH) +#define pCAN_MB20_DATA3 ((volatile unsigned short *)CAN_MB20_DATA3) +#define pCAN_MB20_DATA2 ((volatile unsigned short *)CAN_MB20_DATA2) +#define pCAN_MB20_DATA1 ((volatile unsigned short *)CAN_MB20_DATA1) +#define pCAN_MB20_DATA0 ((volatile unsigned short *)CAN_MB20_DATA0) + +#define pCAN_MB21_ID1 ((volatile unsigned short *)CAN_MB21_ID1) +#define pCAN_MB21_ID0 ((volatile unsigned short *)CAN_MB21_ID0) +#define pCAN_MB21_TIMESTAMP ((volatile unsigned short *)CAN_MB21_TIMESTAMP) +#define pCAN_MB21_LENGTH ((volatile unsigned short *)CAN_MB21_LENGTH) +#define pCAN_MB21_DATA3 ((volatile unsigned short *)CAN_MB21_DATA3) +#define pCAN_MB21_DATA2 ((volatile unsigned short *)CAN_MB21_DATA2) +#define pCAN_MB21_DATA1 ((volatile unsigned short *)CAN_MB21_DATA1) +#define pCAN_MB21_DATA0 ((volatile unsigned short *)CAN_MB21_DATA0) + +#define pCAN_MB22_ID1 ((volatile unsigned short *)CAN_MB22_ID1) +#define pCAN_MB22_ID0 ((volatile unsigned short *)CAN_MB22_ID0) +#define pCAN_MB22_TIMESTAMP ((volatile unsigned short *)CAN_MB22_TIMESTAMP) +#define pCAN_MB22_LENGTH ((volatile unsigned short *)CAN_MB22_LENGTH) +#define pCAN_MB22_DATA3 ((volatile unsigned short *)CAN_MB22_DATA3) +#define pCAN_MB22_DATA2 ((volatile unsigned short *)CAN_MB22_DATA2) +#define pCAN_MB22_DATA1 ((volatile unsigned short *)CAN_MB22_DATA1) +#define pCAN_MB22_DATA0 ((volatile unsigned short *)CAN_MB22_DATA0) + +#define pCAN_MB23_ID1 ((volatile unsigned short *)CAN_MB23_ID1) +#define pCAN_MB23_ID0 ((volatile unsigned short *)CAN_MB23_ID0) +#define pCAN_MB23_TIMESTAMP ((volatile unsigned short *)CAN_MB23_TIMESTAMP) +#define pCAN_MB23_LENGTH ((volatile unsigned short *)CAN_MB23_LENGTH) +#define pCAN_MB23_DATA3 ((volatile unsigned short *)CAN_MB23_DATA3) +#define pCAN_MB23_DATA2 ((volatile unsigned short *)CAN_MB23_DATA2) +#define pCAN_MB23_DATA1 ((volatile unsigned short *)CAN_MB23_DATA1) +#define pCAN_MB23_DATA0 ((volatile unsigned short *)CAN_MB23_DATA0) + +#define pCAN_MB24_ID1 ((volatile unsigned short *)CAN_MB24_ID1) +#define pCAN_MB24_ID0 ((volatile unsigned short *)CAN_MB24_ID0) +#define pCAN_MB24_TIMESTAMP ((volatile unsigned short *)CAN_MB24_TIMESTAMP) +#define pCAN_MB24_LENGTH ((volatile unsigned short *)CAN_MB24_LENGTH) +#define pCAN_MB24_DATA3 ((volatile unsigned short *)CAN_MB24_DATA3) +#define pCAN_MB24_DATA2 ((volatile unsigned short *)CAN_MB24_DATA2) +#define pCAN_MB24_DATA1 ((volatile unsigned short *)CAN_MB24_DATA1) +#define pCAN_MB24_DATA0 ((volatile unsigned short *)CAN_MB24_DATA0) + +#define pCAN_MB25_ID1 ((volatile unsigned short *)CAN_MB25_ID1) +#define pCAN_MB25_ID0 ((volatile unsigned short *)CAN_MB25_ID0) +#define pCAN_MB25_TIMESTAMP ((volatile unsigned short *)CAN_MB25_TIMESTAMP) +#define pCAN_MB25_LENGTH ((volatile unsigned short *)CAN_MB25_LENGTH) +#define pCAN_MB25_DATA3 ((volatile unsigned short *)CAN_MB25_DATA3) +#define pCAN_MB25_DATA2 ((volatile unsigned short *)CAN_MB25_DATA2) +#define pCAN_MB25_DATA1 ((volatile unsigned short *)CAN_MB25_DATA1) +#define pCAN_MB25_DATA0 ((volatile unsigned short *)CAN_MB25_DATA0) + +#define pCAN_MB26_ID1 ((volatile unsigned short *)CAN_MB26_ID1) +#define pCAN_MB26_ID0 ((volatile unsigned short *)CAN_MB26_ID0) +#define pCAN_MB26_TIMESTAMP ((volatile unsigned short *)CAN_MB26_TIMESTAMP) +#define pCAN_MB26_LENGTH ((volatile unsigned short *)CAN_MB26_LENGTH) +#define pCAN_MB26_DATA3 ((volatile unsigned short *)CAN_MB26_DATA3) +#define pCAN_MB26_DATA2 ((volatile unsigned short *)CAN_MB26_DATA2) +#define pCAN_MB26_DATA1 ((volatile unsigned short *)CAN_MB26_DATA1) +#define pCAN_MB26_DATA0 ((volatile unsigned short *)CAN_MB26_DATA0) + +#define pCAN_MB27_ID1 ((volatile unsigned short *)CAN_MB27_ID1) +#define pCAN_MB27_ID0 ((volatile unsigned short *)CAN_MB27_ID0) +#define pCAN_MB27_TIMESTAMP ((volatile unsigned short *)CAN_MB27_TIMESTAMP) +#define pCAN_MB27_LENGTH ((volatile unsigned short *)CAN_MB27_LENGTH) +#define pCAN_MB27_DATA3 ((volatile unsigned short *)CAN_MB27_DATA3) +#define pCAN_MB27_DATA2 ((volatile unsigned short *)CAN_MB27_DATA2) +#define pCAN_MB27_DATA1 ((volatile unsigned short *)CAN_MB27_DATA1) +#define pCAN_MB27_DATA0 ((volatile unsigned short *)CAN_MB27_DATA0) + +#define pCAN_MB28_ID1 ((volatile unsigned short *)CAN_MB28_ID1) +#define pCAN_MB28_ID0 ((volatile unsigned short *)CAN_MB28_ID0) +#define pCAN_MB28_TIMESTAMP ((volatile unsigned short *)CAN_MB28_TIMESTAMP) +#define pCAN_MB28_LENGTH ((volatile unsigned short *)CAN_MB28_LENGTH) +#define pCAN_MB28_DATA3 ((volatile unsigned short *)CAN_MB28_DATA3) +#define pCAN_MB28_DATA2 ((volatile unsigned short *)CAN_MB28_DATA2) +#define pCAN_MB28_DATA1 ((volatile unsigned short *)CAN_MB28_DATA1) +#define pCAN_MB28_DATA0 ((volatile unsigned short *)CAN_MB28_DATA0) + +#define pCAN_MB29_ID1 ((volatile unsigned short *)CAN_MB29_ID1) +#define pCAN_MB29_ID0 ((volatile unsigned short *)CAN_MB29_ID0) +#define pCAN_MB29_TIMESTAMP ((volatile unsigned short *)CAN_MB29_TIMESTAMP) +#define pCAN_MB29_LENGTH ((volatile unsigned short *)CAN_MB29_LENGTH) +#define pCAN_MB29_DATA3 ((volatile unsigned short *)CAN_MB29_DATA3) +#define pCAN_MB29_DATA2 ((volatile unsigned short *)CAN_MB29_DATA2) +#define pCAN_MB29_DATA1 ((volatile unsigned short *)CAN_MB29_DATA1) +#define pCAN_MB29_DATA0 ((volatile unsigned short *)CAN_MB29_DATA0) + +#define pCAN_MB30_ID1 ((volatile unsigned short *)CAN_MB30_ID1) +#define pCAN_MB30_ID0 ((volatile unsigned short *)CAN_MB30_ID0) +#define pCAN_MB30_TIMESTAMP ((volatile unsigned short *)CAN_MB30_TIMESTAMP) +#define pCAN_MB30_LENGTH ((volatile unsigned short *)CAN_MB30_LENGTH) +#define pCAN_MB30_DATA3 ((volatile unsigned short *)CAN_MB30_DATA3) +#define pCAN_MB30_DATA2 ((volatile unsigned short *)CAN_MB30_DATA2) +#define pCAN_MB30_DATA1 ((volatile unsigned short *)CAN_MB30_DATA1) +#define pCAN_MB30_DATA0 ((volatile unsigned short *)CAN_MB30_DATA0) + +#define pCAN_MB31_ID1 ((volatile unsigned short *)CAN_MB31_ID1) +#define pCAN_MB31_ID0 ((volatile unsigned short *)CAN_MB31_ID0) +#define pCAN_MB31_TIMESTAMP ((volatile unsigned short *)CAN_MB31_TIMESTAMP) +#define pCAN_MB31_LENGTH ((volatile unsigned short *)CAN_MB31_LENGTH) +#define pCAN_MB31_DATA3 ((volatile unsigned short *)CAN_MB31_DATA3) +#define pCAN_MB31_DATA2 ((volatile unsigned short *)CAN_MB31_DATA2) +#define pCAN_MB31_DATA1 ((volatile unsigned short *)CAN_MB31_DATA1) +#define pCAN_MB31_DATA0 ((volatile unsigned short *)CAN_MB31_DATA0) + +/* CAN Mailbox Area Macros */ +#define pCAN_MB_ID1(x) ((volatile unsigned short *)CAN_MB_ID1(x)) +#define pCAN_MB_ID0(x) ((volatile unsigned short *)CAN_MB_ID0(x)) +#define pCAN_MB_TIMESTAMP(x) ((volatile unsigned short *)CAN_MB_TIMESTAMP(x)) +#define pCAN_MB_LENGTH(x) ((volatile unsigned short *)CAN_MB_LENGTH(x)) +#define pCAN_MB_DATA3(x) ((volatile unsigned short *)CAN_MB_DATA3(x)) +#define pCAN_MB_DATA2(x) ((volatile unsigned short *)CAN_MB_DATA2(x)) +#define pCAN_MB_DATA1(x) ((volatile unsigned short *)CAN_MB_DATA1(x)) +#define pCAN_MB_DATA0(x) ((volatile unsigned short *)CAN_MB_DATA0(x)) + +/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ +#define pPORTF_FER ((volatile unsigned short *)PORTF_FER) +#define pPORTG_FER ((volatile unsigned short *)PORTG_FER) +#define pPORTH_FER ((volatile unsigned short *)PORTH_FER) +#define pPORT_MUX ((volatile unsigned short *)PORT_MUX) + +#define PORTF_UART0_TX 0x0001 +#define PORTF_UART0_RX 0x0002 + +#define PORT_MUX_PFDE 0x0040 /* 0: Enable UART0 RX, UART0 TX; 1: Enable DMAR0, DMAr1 */ + +/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ +#define pHMDMA0_CONTROL ((volatile unsigned short *)HMDMA0_CONTROL) +#define pHMDMA0_ECINIT ((volatile unsigned short *)HMDMA0_ECINIT) +#define pHMDMA0_BCINIT ((volatile unsigned short *)HMDMA0_BCINIT) +#define pHMDMA0_ECURGENT ((volatile unsigned short *)HMDMA0_ECURGENT) +#define pHMDMA0_ECOVERFLOW ((volatile unsigned short *)HMDMA0_ECOVERFLOW) +#define pHMDMA0_ECOUNT ((volatile unsigned short *)HMDMA0_ECOUNT) +#define pHMDMA0_BCOUNT ((volatile unsigned short *)HMDMA0_BCOUNT) + +#define pHMDMA1_CONTROL ((volatile unsigned short *)HMDMA1_CONTROL) +#define pHMDMA1_ECINIT ((volatile unsigned short *)HMDMA1_ECINIT) +#define pHMDMA1_BCINIT ((volatile unsigned short *)HMDMA1_BCINIT) +#define pHMDMA1_ECURGENT ((volatile unsigned short *)HMDMA1_ECURGENT) +#define pHMDMA1_ECOVERFLOW ((volatile unsigned short *)HMDMA1_ECOVERFLOW) +#define pHMDMA1_ECOUNT ((volatile unsigned short *)HMDMA1_ECOUNT) +#define pHMDMA1_BCOUNT ((volatile unsigned short *)HMDMA1_BCOUNT) + +#endif /* _CDEF_BF534_H */ diff --git a/include/asm-blackfin/arch-bf537/cdefBF537.h b/include/asm-blackfin/arch-bf537/cdefBF537.h new file mode 100644 index 0000000000..3de1d936d0 --- /dev/null +++ b/include/asm-blackfin/arch-bf537/cdefBF537.h @@ -0,0 +1,186 @@ +/* + * Copyright (C) 2004 Analog Devices Inc., All Rights Reserved. + * + *********************************************************************************** + * + * This include file contains a list of macro "defines" to enable the programmer + * to use symbolic names for register-access. + * + * ---------------------------- + * revision 0.1 + * date: 2004/03/01 21:23:01; author: joeb + * Initial revision + * + * ---------------------------- + * revision 0.2 + * date: 2004/05/15 16:30:00; author: joeb + * comments: removed I2C/IIC references to TWI, changed GPIO sections + * + * ---------------------------- + * revision 0.3 + * date: 2004/06/08 12:25:00; author: joeb + * comments: renamed some TWI and GPIO registers + * + * ---------------------------- + * revision 0.4 + * date: 2004/06/09 14:25:00; author: joeb + * comments: changed Timer status register to 32-bit, renamed EMAC count registers + * + * ---------------------------- + * revision 0.5 + * date: 2004/08/10 10:25:00; author: joeb + * comments: Renamed EMAC wake-up registers, changed bit-names in EMAC registers + * + * ---------------------------- + * revision 0.6 + * date: 2004/08/17 16:25:00; author: joeb + * comments: Renamed TWI_INT_ENABLE to TWI_INT_MASK + * + * ---------------------------- + * revision 0.7 + * date: 2004/08/18 13:21:00; author: joeb + * comments: Renamed GPIO registers to remove _D, _S, _C, _T suffixes + * + * ---------------------------- + * revision 0.8 + * date: 2004/08/20 10:27:00; author: joeb + * comments: Renamed External DMA to Handshake DMA + * + * ---------------------------- + * revision 0.9 + * date: 2004/08/23 13:42:00; author: joeb + * comments: Renamed Handshake DMA Register Set + * + * ---------------------------- + * revision 0.10 + * date: 2004/10/28 15:40:00; author: joeb + * comments: Shortened EMAC Count Register Names + * + * ---------------------------- + * revision 0.11 + * date: 2004/12/13 11:05:00; author: joeb + * comments: Fixed address pointers - (volatile void **) to (void * volatile *) + * + * ---------------------------- + * revision 0.12 + * date: 2004/12/17 14:25:00; author: joeb + * comments: Replaced C++ Single-Line Comments w/C-standard Comments + * Changed EMAC EQ1024 TX/RX References to GE1024 + * + * ---------------------------- + * revision 0.13 + * date: 2005/01/05 10:50:00; author: joeb + * comments: Removed excess white space in CAN_AM section + * Added support for CAN Macros to Index AM and Mailbox Areas + * + * ---------------------------- + * revision 0.14 + * date: 2005/01/26 14:10:00; author: joeb + * comments: Fixed Typo In EMAC_RXC_PAUSE register + * + * ---------------------------- + * revision 0.15 + * date: 2005/01/27 14:41:00; author: joeb + * comments: Moved Common MMRs to cdefBF534.h + */ + +/* + * System MMR Register Map + */ + +#ifndef _CDEF_BF537_H +#define _CDEF_BF537_H + +/* Include MMRs Common to BF534 */ +#include + +/* Include all Core registers and bit definitions */ +#include + +/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */ +/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ +#define pEMAC_OPMODE ((volatile unsigned long *)EMAC_OPMODE) +#define pEMAC_ADDRLO ((volatile unsigned long *)EMAC_ADDRLO) +#define pEMAC_ADDRHI ((volatile unsigned long *)EMAC_ADDRHI) +#define pEMAC_HASHLO ((volatile unsigned long *)EMAC_HASHLO) +#define pEMAC_HASHHI ((volatile unsigned long *)EMAC_HASHHI) +#define pEMAC_STAADD ((volatile unsigned long *)EMAC_STAADD) +#define pEMAC_STADAT ((volatile unsigned long *)EMAC_STADAT) +#define pEMAC_FLC ((volatile unsigned long *)EMAC_FLC) +#define pEMAC_VLAN1 ((volatile unsigned long *)EMAC_VLAN1) +#define pEMAC_VLAN2 ((volatile unsigned long *)EMAC_VLAN2) +#define pEMAC_WKUP_CTL ((volatile unsigned long *)EMAC_WKUP_CTL) +#define pEMAC_WKUP_FFMSK0 ((volatile unsigned long *)EMAC_WKUP_FFMSK0) +#define pEMAC_WKUP_FFMSK1 ((volatile unsigned long *)EMAC_WKUP_FFMSK1) +#define pEMAC_WKUP_FFMSK2 ((volatile unsigned long *)EMAC_WKUP_FFMSK2) +#define pEMAC_WKUP_FFMSK3 ((volatile unsigned long *)EMAC_WKUP_FFMSK3) +#define pEMAC_WKUP_FFCMD ((volatile unsigned long *)EMAC_WKUP_FFCMD) +#define pEMAC_WKUP_FFOFF ((volatile unsigned long *)EMAC_WKUP_FFOFF) +#define pEMAC_WKUP_FFCRC0 ((volatile unsigned long *)EMAC_WKUP_FFCRC0) +#define pEMAC_WKUP_FFCRC1 ((volatile unsigned long *)EMAC_WKUP_FFCRC1) + +#define pEMAC_SYSCTL ((volatile unsigned long *)EMAC_SYSCTL) +#define pEMAC_SYSTAT ((volatile unsigned long *)EMAC_SYSTAT) +#define pEMAC_RX_STAT ((volatile unsigned long *)EMAC_RX_STAT) +#define pEMAC_RX_STKY ((volatile unsigned long *)EMAC_RX_STKY) +#define pEMAC_RX_IRQE ((volatile unsigned long *)EMAC_RX_IRQE) +#define pEMAC_TX_STAT ((volatile unsigned long *)EMAC_TX_STAT) +#define pEMAC_TX_STKY ((volatile unsigned long *)EMAC_TX_STKY) +#define pEMAC_TX_IRQE ((volatile unsigned long *)EMAC_TX_IRQE) + +#define pEMAC_MMC_CTL ((volatile unsigned long *)EMAC_MMC_CTL) +#define pEMAC_MMC_RIRQS ((volatile unsigned long *)EMAC_MMC_RIRQS) +#define pEMAC_MMC_RIRQE ((volatile unsigned long *)EMAC_MMC_RIRQE) +#define pEMAC_MMC_TIRQS ((volatile unsigned long *)EMAC_MMC_TIRQS) +#define pEMAC_MMC_TIRQE ((volatile unsigned long *)EMAC_MMC_TIRQE) + +#define pEMAC_RXC_OK ((volatile unsigned long *)EMAC_RXC_OK) +#define pEMAC_RXC_FCS ((volatile unsigned long *)EMAC_RXC_FCS) +#define pEMAC_RXC_ALIGN ((volatile unsigned long *)EMAC_RXC_ALIGN) +#define pEMAC_RXC_OCTET ((volatile unsigned long *)EMAC_RXC_OCTET) +#define pEMAC_RXC_DMAOVF ((volatile unsigned long *)EMAC_RXC_DMAOVF) +#define pEMAC_RXC_UNICST ((volatile unsigned long *)EMAC_RXC_UNICST) +#define pEMAC_RXC_MULTI ((volatile unsigned long *)EMAC_RXC_MULTI) +#define pEMAC_RXC_BROAD ((volatile unsigned long *)EMAC_RXC_BROAD) +#define pEMAC_RXC_LNERRI ((volatile unsigned long *)EMAC_RXC_LNERRI) +#define pEMAC_RXC_LNERRO ((volatile unsigned long *)EMAC_RXC_LNERRO) +#define pEMAC_RXC_LONG ((volatile unsigned long *)EMAC_RXC_LONG) +#define pEMAC_RXC_MACCTL ((volatile unsigned long *)EMAC_RXC_MACCTL) +#define pEMAC_RXC_OPCODE ((volatile unsigned long *)EMAC_RXC_OPCODE) +#define pEMAC_RXC_PAUSE ((volatile unsigned long *)EMAC_RXC_PAUSE) +#define pEMAC_RXC_ALLFRM ((volatile unsigned long *)EMAC_RXC_ALLFRM) +#define pEMAC_RXC_ALLOCT ((volatile unsigned long *)EMAC_RXC_ALLOCT) +#define pEMAC_RXC_TYPED ((volatile unsigned long *)EMAC_RXC_TYPED) +#define pEMAC_RXC_SHORT ((volatile unsigned long *)EMAC_RXC_SHORT) +#define pEMAC_RXC_EQ64 ((volatile unsigned long *)EMAC_RXC_EQ64) +#define pEMAC_RXC_LT128 ((volatile unsigned long *)EMAC_RXC_LT128) +#define pEMAC_RXC_LT256 ((volatile unsigned long *)EMAC_RXC_LT256) +#define pEMAC_RXC_LT512 ((volatile unsigned long *)EMAC_RXC_LT512) +#define pEMAC_RXC_LT1024 ((volatile unsigned long *)EMAC_RXC_LT1024) +#define pEMAC_RXC_GE1024 ((volatile unsigned long *)EMAC_RXC_GE1024) + +#define pEMAC_TXC_OK ((volatile unsigned long *)EMAC_TXC_OK) +#define pEMAC_TXC_1COL ((volatile unsigned long *)EMAC_TXC_1COL) +#define pEMAC_TXC_GT1COL ((volatile unsigned long *)EMAC_TXC_GT1COL) +#define pEMAC_TXC_OCTET ((volatile unsigned long *)EMAC_TXC_OCTET) +#define pEMAC_TXC_DEFER ((volatile unsigned long *)EMAC_TXC_DEFER) +#define pEMAC_TXC_LATECL ((volatile unsigned long *)EMAC_TXC_LATECL) +#define pEMAC_TXC_XS_COL ((volatile unsigned long *)EMAC_TXC_XS_COL) +#define pEMAC_TXC_DMAUND ((volatile unsigned long *)EMAC_TXC_DMAUND) +#define pEMAC_TXC_CRSERR ((volatile unsigned long *)EMAC_TXC_CRSERR) +#define pEMAC_TXC_UNICST ((volatile unsigned long *)EMAC_TXC_UNICST) +#define pEMAC_TXC_MULTI ((volatile unsigned long *)EMAC_TXC_MULTI) +#define pEMAC_TXC_BROAD ((volatile unsigned long *)EMAC_TXC_BROAD) +#define pEMAC_TXC_XS_DFR ((volatile unsigned long *)EMAC_TXC_XS_DFR) +#define pEMAC_TXC_MACCTL ((volatile unsigned long *)EMAC_TXC_MACCTL) +#define pEMAC_TXC_ALLFRM ((volatile unsigned long *)EMAC_TXC_ALLFRM) +#define pEMAC_TXC_ALLOCT ((volatile unsigned long *)EMAC_TXC_ALLOCT) +#define pEMAC_TXC_EQ64 ((volatile unsigned long *)EMAC_TXC_EQ64) +#define pEMAC_TXC_LT128 ((volatile unsigned long *)EMAC_TXC_LT128) +#define pEMAC_TXC_LT256 ((volatile unsigned long *)EMAC_TXC_LT256) +#define pEMAC_TXC_LT512 ((volatile unsigned long *)EMAC_TXC_LT512) +#define pEMAC_TXC_LT1024 ((volatile unsigned long *)EMAC_TXC_LT1024) +#define pEMAC_TXC_GE1024 ((volatile unsigned long *)EMAC_TXC_GE1024) +#define pEMAC_TXC_ABORT ((volatile unsigned long *)EMAC_TXC_ABORT) + +#endif /* _CDEF_BF537_H */ diff --git a/include/asm-blackfin/arch-bf537/cplbtab.h b/include/asm-blackfin/arch-bf537/cplbtab.h new file mode 100644 index 0000000000..c5151bb4ab --- /dev/null +++ b/include/asm-blackfin/arch-bf537/cplbtab.h @@ -0,0 +1,408 @@ +/*This file is subject to the terms and conditions of the GNU General Public + * License. + * + * Blackfin BF533/2.6 support : LG Soft India + * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd + * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's + * shouldn't be victimized. cplbmgr.S search logic is corrected + * to findout the appropriate victim. + * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC + * : LG Soft India + */ +#include + +#ifndef __ARCH_BFINNOMMU_CPLBTAB_H +#define __ARCH_BFINNOMMU_CPLBTAB_H + +/* + * ICPLB TABLE + */ + +.data +/* This table is configurable */ + .align 4; + +/* Data Attibutes*/ + +#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) + +/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ + +#define ANOMALY_05000158 0x200 +#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) +#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) + +#else /*Write Through */ +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) +#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) +#endif + +.align 4; +.global _ipdt_table _ipdt_table:.byte4 0x00000000; +.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */ +.byte4 0x00400000; +.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */ +.byte4 0x00800000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */ +.byte4 0x00C00000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */ +.byte4 0x01000000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */ +.byte4 0x01400000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */ +.byte4 0x01800000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */ +.byte4 0x01C00000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */ +.byte4 0x02000000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */ +.byte4 0x02400000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */ +.byte4 0x02800000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */ +.byte4 0x02C00000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */ +.byte4 0x03000000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */ +.byte4 0x03400000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */ +.byte4 0x03800000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */ +.byte4 0x03C00000; +.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */ +.byte4 0x20000000; +.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */ + +.byte4 0xffffffff; /* end of section - termination */ + +/* + * PAGE DESCRIPTOR TABLE + * + */ + +/* + * Till here we are discussing about the static memory management model. + * However, the operating envoronments commonly define more CPLB + * descriptors to cover the entire addressable memory than will fit into + * the available on-chip 16 CPLB MMRs. When this happens, the below table + * will be used which will hold all the potentially required CPLB descriptors + * + * This is how Page descriptor Table is implemented in uClinux/Blackfin. + */ +.global _dpdt_table _dpdt_table:.byte4 0x00000000; +.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */ +.byte4 0x00400000; +.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */ +.byte4 0x00800000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */ +.byte4 0x00C00000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */ +.byte4 0x01000000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */ +.byte4 0x01400000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */ +.byte4 0x01800000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */ +.byte4 0x01C00000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */ +.byte4 0x02000000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */ +.byte4 0x02400000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */ +.byte4 0x02800000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */ +.byte4 0x02C00000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */ +.byte4 0x03000000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */ +.byte4 0x03400000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */ +.byte4 0x03800000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */ +.byte4 0x03C00000; +.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */ +.byte4 0x20000000; +.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */ + +#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537)) +.byte4 0xFF800000; +.byte4(L1_DMEMORY); +.byte4 0xFF801000; +.byte4(L1_DMEMORY); +.byte4 0xFF802000; +.byte4(L1_DMEMORY); +.byte4 0xFF803000; +.byte4(L1_DMEMORY); +#endif +.byte4 0xFF804000; +.byte4(L1_DMEMORY); +.byte4 0xFF805000; +.byte4(L1_DMEMORY); +.byte4 0xFF806000; +.byte4(L1_DMEMORY); +.byte4 0xFF807000; +.byte4(L1_DMEMORY); +#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537)) +.byte4 0xFF900000; +.byte4(L1_DMEMORY); +.byte4 0xFF901000; +.byte4(L1_DMEMORY); +.byte4 0xFF902000; +.byte4(L1_DMEMORY); +.byte4 0xFF903000; +.byte4(L1_DMEMORY); +#endif +.byte4 0xFF904000; +.byte4(L1_DMEMORY); +.byte4 0xFF905000; +.byte4(L1_DMEMORY); +.byte4 0xFF906000; +.byte4(L1_DMEMORY); +.byte4 0xFF907000; +.byte4(L1_DMEMORY); + +.byte4 0xFFB00000; +.byte4(L1_DMEMORY); + +.byte4 0xffffffff; /*end of section - termination */ + +#ifdef CONFIG_CPLB_INFO +.global _ipdt_swapcount_table; /* swapin count first, then swapout count */ +_ipdt_swapcount_table: +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 10 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 20 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 30 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 40 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 50 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 60 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 70 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 80 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 90 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 100 */ + +.global _dpdt_swapcount_table; /* swapin count first, then swapout count */ +_dpdt_swapcount_table: +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 10 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 20 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 30 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 40 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 50 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 60 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 70 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 80 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 80 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 100 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 110 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 120 */ + +#endif + +#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/ diff --git a/include/asm-blackfin/arch-bf537/defBF534.h b/include/asm-blackfin/arch-bf537/defBF534.h new file mode 100644 index 0000000000..c603d448ec --- /dev/null +++ b/include/asm-blackfin/arch-bf537/defBF534.h @@ -0,0 +1,2627 @@ +/* + * Copyright (C) 2004 Analog Devices Inc., All Rights Reserved. + * + *********************************************************************************** + * + * This include file contains a list of macro "defines" to enable the programmer + * to use symbolic names for register-access and bit-manipulation. + * + * ---------------------------- + * revision 0.1 + * date: 2004/03/01 21:23:01; author: joeb + * Initial revision + * + */ +#ifndef _DEF_BF534_H +#define _DEF_BF534_H + +/* Include all Core registers and bit definitions */ +#include + +#define LO(con32) ((con32) & 0xFFFF) +#define lo(con32) ((con32) & 0xFFFF) +#define HI(con32) (((con32) >> 16) & 0xFFFF) +#define hi(con32) (((con32) >> 16) & 0xFFFF) + +/* + * System MMR Register Map + */ +/* Clock and System Control (0xFFC00000 - 0xFFC000FF)*/ +#define PLL_CTL 0xFFC00000 /* PLL Control Register */ +#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ +#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ +#define CHIPID 0xFFC00014 /* Chip ID register (32-bit) */ +#define PLL_STAT 0xFFC0000C /* PLL Status Register */ +#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ + +/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ +#define SWRST 0xFFC00100 /* Software Reset Register */ +#define SYSCR 0xFFC00104 /* System Configuration Register */ +#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ +#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ +#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ +#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ +#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ +#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ + +/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ +#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ +#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ +#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ + +/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ +#define RTC_STAT 0xFFC00300 /* RTC Status Register */ +#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ +#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ +#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ +#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ +#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ +#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ + +/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ +#define UART0_THR 0xFFC00400 /* Transmit Holding register */ +#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ +#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ +#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ +#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ +#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ +#define UART0_LCR 0xFFC0040C /* Line Control Register */ +#define UART0_MCR 0xFFC00410 /* Modem Control Register */ +#define UART0_LSR 0xFFC00414 /* Line Status Register */ +#define UART0_MSR 0xFFC00418 /* Modem Status Register */ +#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ +#define UART0_GCTL 0xFFC00424 /* Global Control Register */ + +/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define SPI_CTL 0xFFC00500 /* SPI Control Register */ +#define SPI_FLG 0xFFC00504 /* SPI Flag register */ +#define SPI_STAT 0xFFC00508 /* SPI Status register */ +#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ +#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ +#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ +#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ + +/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ +#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ +#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ +#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ +#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ + +#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ +#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ +#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ +#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ + +#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ +#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ +#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ +#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ + +#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ +#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ +#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ +#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ + +#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ +#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ +#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ +#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ + +#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ +#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ +#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ +#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ + +#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ +#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ +#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ +#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ + +#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ +#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ +#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ +#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ + +#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ +#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ +#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ + +/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ +#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ +#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ +#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ +#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ +#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ +#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ +#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ +#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ +#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ +#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ +#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ +#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ +#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ +#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ +#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ +#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ +#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ + +/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ +#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ +#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ +#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ +#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ +#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ +#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ +#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ + +/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ +#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ +#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ +#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ +#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ +#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ +#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ +#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ +#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ +#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ +#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ +#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ +#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ +#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ +#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ +#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ +#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ +#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ +#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ + +/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ +#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ +#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ +#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ +#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ +#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ +#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ +#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ + +/* DMA Traffic Control Registers */ +#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ +#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ + +/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ +#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ +#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ +#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ +#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ +#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ +#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ +#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ +#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ +#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ +#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ +#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ +#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ +#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ + +#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ +#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ +#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ +#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ +#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ +#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ +#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ +#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ +#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ +#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ +#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ +#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ +#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ + +#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ +#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ +#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ +#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ +#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ +#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ +#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ +#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ +#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ +#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ +#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ +#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ +#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ + +#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ +#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ +#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ +#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ +#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ +#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ +#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ +#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ +#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ +#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ +#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ +#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ +#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ + +#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ +#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ +#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ +#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ +#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ +#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ +#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ +#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ +#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ +#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ +#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ +#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ +#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ + +#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ +#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ +#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ +#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ +#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ +#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ +#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ +#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ +#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ +#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ +#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ +#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ +#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ + +#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ +#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ +#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ +#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ +#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ +#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ +#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ +#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ +#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ +#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ +#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ +#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ +#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ + +#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ +#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ +#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ +#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ +#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ +#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ +#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ +#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ +#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ +#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ +#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ +#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ +#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ + +#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ +#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ +#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ +#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ +#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ +#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ +#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ +#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ +#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ +#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ +#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ +#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ +#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ + +#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ +#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ +#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ +#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ +#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ +#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ +#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ +#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ +#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ +#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ +#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ +#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ +#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ + +#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ +#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ +#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ +#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ +#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ +#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ +#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ +#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ +#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ +#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ +#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ +#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ +#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ + +#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ +#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ +#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ +#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ +#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ +#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ +#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ +#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ +#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ +#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ +#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ +#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ +#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ + +#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ +#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ +#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ +#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ +#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ +#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ +#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ +#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ +#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ +#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ +#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ +#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ +#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ + +#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ +#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ +#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ +#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ +#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ +#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ +#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ +#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ +#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ +#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ +#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ +#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ +#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ + +#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ +#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ +#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ +#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ +#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ +#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ +#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ +#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ +#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ +#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ +#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ +#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ +#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ + +#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ +#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ +#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ +#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ +#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ +#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ +#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ +#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ +#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ +#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ +#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ +#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ +#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ + +/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ +#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ +#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ +#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ +#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ +#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ + +/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ +#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ +#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ +#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ +#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ +#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ +#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ +#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ +#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ +#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ +#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ +#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ +#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ +#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ +#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ +#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ +#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ + +/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ +#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ +#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ +#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ +#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ +#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ +#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ +#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ +#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ +#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ +#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ +#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ +#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ +#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ +#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ +#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ +#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ +#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ + +/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ +#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ +#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ +#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ +#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ +#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ +#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ +#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ +#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ +#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ +#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ +#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ +#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ +#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ +#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ +#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ +#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ +#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ + +/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ +#define UART1_THR 0xFFC02000 /* Transmit Holding register */ +#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ +#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ +#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ +#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ +#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ +#define UART1_LCR 0xFFC0200C /* Line Control Register */ +#define UART1_MCR 0xFFC02010 /* Modem Control Register */ +#define UART1_LSR 0xFFC02014 /* Line Status Register */ +#define UART1_MSR 0xFFC02018 /* Modem Status Register */ +#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ +#define UART1_GCTL 0xFFC02024 /* Global Control Register */ + +/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */ +/* For Mailboxes 0-15 */ +#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ +#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ +#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ +#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ +#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ +#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ +#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ +#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ +#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ +#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ +#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ +#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ +#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */ + +/* For Mailboxes 16-31 */ +#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ +#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ +#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ +#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ +#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ +#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ +#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ +#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ +#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ +#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ +#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ +#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ +#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */ + +/* CAN Configuration, Control, and Status Registers */ +#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ +#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ +#define CAN_DEBUG 0xFFC02A88 /* Debug Register */ +#define CAN_STATUS 0xFFC02A8C /* Global Status Register */ +#define CAN_CEC 0xFFC02A90 /* Error Counter Register */ +#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ +#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ +#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ +#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ +#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ +#define CAN_SFCMVER 0xFFC02AA8 /* Version Code Register */ +#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ +#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ +#define CAN_ESR 0xFFC02AB4 /* Error Status Register */ +#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */ +#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ +#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */ +#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ + +/* Mailbox Acceptance Masks */ +#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ +#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ +#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ +#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ +#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ +#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ +#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ +#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ +#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ +#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ +#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ +#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ +#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ +#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ +#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ +#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ +#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ +#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ +#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ +#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ +#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ +#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ +#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ +#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ +#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ +#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ +#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ +#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ +#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ +#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ +#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ +#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ + +#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ +#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ +#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ +#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ +#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ +#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ +#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ +#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ +#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ +#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ +#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ +#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ +#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ +#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ +#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ +#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ +#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ +#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ +#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ +#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ +#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ +#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ +#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ +#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ +#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ +#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ +#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ +#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ +#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ +#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ +#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ +#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ + +/* CAN Acceptance Mask Macros */ +#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8)) +#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8)) + +/* Mailbox Registers */ +#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ +#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ +#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ +#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ +#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ +#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ +#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ +#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ + +#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ +#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ +#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ +#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ +#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ +#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ +#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ +#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ + +#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ +#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ +#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ +#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ +#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ +#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ +#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ +#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ + +#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ +#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ +#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ +#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ +#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ +#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ +#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ +#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ + +#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ +#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ +#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ +#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ +#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ +#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ +#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ +#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ + +#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ +#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ +#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ +#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ +#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ +#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ +#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ +#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ + +#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ +#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ +#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ +#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ +#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ +#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ +#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ +#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ + +#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ +#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ +#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ +#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ +#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ +#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ +#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ +#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ + +#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ +#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ +#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ +#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ +#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ +#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ +#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ +#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ + +#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ +#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ +#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ +#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ +#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ +#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ +#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ +#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ + +#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ +#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ +#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ +#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ +#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ +#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ +#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ +#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ + +#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ +#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ +#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ +#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ +#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ +#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ +#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ +#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ + +#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ +#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ +#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ +#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ +#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ +#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ +#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ +#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ + +#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ +#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ +#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ +#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ +#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ +#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ +#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ +#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ + +#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ +#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ +#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ +#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ +#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ +#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ +#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ +#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ + +#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ +#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ +#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ +#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ +#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ +#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ +#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ +#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ + +#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ +#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ +#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ +#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ +#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ +#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ +#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ +#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ + +#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ +#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ +#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ +#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ +#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ +#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ +#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ +#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ + +#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ +#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ +#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ +#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ +#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ +#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ +#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ +#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ + +#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ +#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ +#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ +#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ +#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ +#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ +#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ +#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ + +#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ +#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ +#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ +#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ +#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ +#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ +#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ +#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ + +#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ +#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ +#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ +#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ +#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ +#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ +#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ +#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ + +#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ +#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ +#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ +#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ +#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ +#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ +#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ +#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ + +#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ +#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ +#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ +#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ +#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ +#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ +#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ +#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ + +#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ +#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ +#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ +#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ +#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ +#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ +#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ +#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ + +#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ +#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ +#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ +#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ +#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ +#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ +#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ +#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ + +#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ +#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ +#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ +#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ +#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ +#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ +#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ +#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ + +#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ +#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ +#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ +#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ +#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ +#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ +#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ +#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ + +#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ +#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ +#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ +#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ +#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ +#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ +#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ +#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ + +#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ +#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ +#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ +#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ +#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ +#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ +#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ +#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ + +#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ +#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ +#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ +#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ +#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ +#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ +#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ +#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ + +#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ +#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ +#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ +#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ +#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ +#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ +#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ +#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ + +/* CAN Mailbox Area Macros */ +#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20)) +#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20)) +#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20)) +#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20)) +#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20)) +#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20)) +#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20)) +#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20)) + +/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ +#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ +#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ +#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ +#define PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ + +/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ +#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ +#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ +#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ +#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ +#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ +#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ +#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ + +#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ +#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ +#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ +#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ +#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ +#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ +#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ + +/* + * System MMR Register Bits And Macros + * + * Disclaimer: All macros are intended to make C and Assembly code more readable. + * Use these macros carefully, as any that do left shifts for field + * depositing will result in the lower order bits being destroyed. Any + * macro that shifts left to properly position the bit-field should be + * used as part of an OR to initialize a register and NOT as a dynamic + * modifier UNLESS the lower order bits are saved and ORed back in when + * the macro is used. + */ +/* + * PLL AND RESET MASKS + * PLL_CTL Masks + */ +#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ +#define PLL_OFF 0x0002 /* PLL Not Powered */ +#define STOPCK 0x0008 /* Core Clock Off */ +#define PDWN 0x0020 /* Enter Deep Sleep Mode */ +#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ +#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ +#define BYPASS 0x0100 /* Bypass the PLL */ +#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ +/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ +#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ + +/* PLL_DIV Masks */ +#define SSEL 0x000F /* System Select */ +#define CSEL 0x0030 /* Core Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ + +#define CCLK_DIV1 CSEL_DIV1 +#define CCLK_DIV2 CSEL_DIV2 +#define CCLK_DIV4 CSEL_DIV4 +#define CCLK_DIV8 CSEL_DIV8 +/* PLL_DIV Macros */ +#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ + +/* VR_CTL Masks */ +#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ +#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ + +#define GAIN 0x000C /* Voltage Level Gain */ +#define GAIN_5 0x0000 /* GAIN = 5 */ +#define GAIN_10 0x0004 /* GAIN = 10 */ +#define GAIN_20 0x0008 /* GAIN = 20 */ +#define GAIN_50 0x000C /* GAIN = 50 */ + +#define VLEV 0x00F0 /* Internal Voltage Level */ +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + +#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ +#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ +#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ +#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ +#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ +#define CKELOW 0x8000 /* Enable Drive CKE Low During Reset */ + +/* PLL_STAT Masks */ +#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ +#define FULL_ON 0x0002 /* Processor In Full On Mode */ +#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ +#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ + +/* SWRST Masks */ +#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ +#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ +#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ +#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ +#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ + +/* SYSCR Masks */ +#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ +#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ + +/* + * SYSTEM INTERRUPT CONTROLLER MASKS + */ +/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ +#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ +#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ +#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ +#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ +#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ +#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ +#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ +#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ + +#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ +#define IRQ_TWI 0x00000200 /* TWI Interrupt */ +#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ +#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ +#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ +#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ +#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ +#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */ + +#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */ +#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */ +#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */ +#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */ +#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */ +#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */ +#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */ +#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */ +#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */ +#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */ + +#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */ +#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */ +#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */ +#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */ +#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */ +#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */ +#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */ +#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */ +#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ +#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ +#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ + +/* SIC_IAR0 Macros */ +#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ +#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ +#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ +#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */ +#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ +#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ +#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ +#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ + +/* SIC_IAR1 Macros */ +#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */ +#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ +#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ +#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */ +#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ +#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ +#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ +#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ + +/* SIC_IAR2 Macros */ +#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */ +#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ +#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ +#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */ +#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ +#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ +#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ +#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ + +/* SIC_IAR3 Macros */ +#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */ +#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */ +#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */ +#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */ +#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */ +#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */ +#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */ +#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */ + +/* SIC_IMASK Masks */ +#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ +#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ +#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ +#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ + +/* SIC_IWR Masks */ +#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ +#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ +#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ +#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ + +/* ********* WATCHDOG TIMER MASKS ******************** */ + +/* Watchdog Timer WDOG_CTL Register Masks */ + +#define WDEV(x) ((x<<1) & 0x0006) /* event generated on roll over */ +#define WDEV_RESET 0x0000 /* generate reset event on roll over */ +#define WDEV_NMI 0x0002 /* generate NMI event on roll over */ +#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */ +#define WDEV_NONE 0x0006 /* no event on roll over */ +#define WDEN 0x0FF0 /* enable watchdog */ +#define WDDIS 0x0AD0 /* disable watchdog */ +#define WDRO 0x8000 /* watchdog rolled over latch */ + +/* depreciated WDOG_CTL Register Masks for legacy code */ + +#define ICTL WDEV +#define ENABLE_RESET WDEV_RESET +#define WDOG_RESET WDEV_RESET +#define ENABLE_NMI WDEV_NMI +#define WDOG_NMI WDEV_NMI +#define ENABLE_GPI WDEV_GPI +#define WDOG_GPI WDEV_GPI +#define DISABLE_EVT WDEV_NONE +#define WDOG_NONE WDEV_NONE + +#define TMR_EN WDEN +#define TMR_DIS WDDIS +#define TRO WDRO +#define ICTL_P0 0x01 +#define ICTL_P1 0x02 +#define TRO_P 0x0F + +/* + * REAL TIME CLOCK MASKS + */ +/* RTC_STAT and RTC_ALARM Masks */ +#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */ +#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */ +#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */ +#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */ + +/* + * RTC_ALARM Macro + * z=day y=hr x=min w=sec + */ +#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F)) + +/* RTC_ICTL and RTC_ISTAT Masks */ +#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */ +#define ALARM 0x0002 /* Alarm Interrupt Enable */ +#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */ +#define MINUTE 0x0008 /* Minutes Interrupt Enable */ +#define HOUR 0x0010 /* Hours Interrupt Enable */ +#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */ +#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ +#define WRITE_PENDING 0x4000 /* Write Pending Status */ +#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */ + +/* RTC_FAST / RTC_PREN Mask */ +#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */ + +/* + * UART CONTROLLER MASKS + */ +/* UARTx_LCR Masks */ +#define WLS(x) ((((x)&0x3)-5) & 0x03) /* Word Length Select */ +#define STB 0x04 /* Stop Bits */ +#define PEN 0x08 /* Parity Enable */ +#define EPS 0x10 /* Even Parity Select */ +#define STP 0x20 /* Stick Parity */ +#define SB 0x40 /* Set Break */ +#define DLAB 0x80 /* Divisor Latch Access */ + +/* UARTx_MCR Mask */ +#define LOOP 0x10 /* Loopback Mode Enable */ + +/* UARTx_LSR Masks */ +#define DR 0x01 /* Data Ready */ +#define OE 0x02 /* Overrun Error */ +#define PE 0x04 /* Parity Error */ +#define FE 0x08 /* Framing Error */ +#define BI 0x10 /* Break Interrupt */ +#define THRE 0x20 /* THR Empty */ +#define TEMT 0x40 /* TSR and UART_THR Empty */ + +/* UARTx_IER Masks */ +#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ +#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ +#define ELSI 0x04 /* Enable RX Status Interrupt */ + +/* UARTx_IIR Masks */ +#define NINT 0x01 /* Pending Interrupt */ +#define STATUS 0x06 /* Highest Priority Pending Interrupt */ + +/* UARTx_GCTL Masks */ +#define UCEN 0x01 /* Enable UARTx Clocks */ +#define IREN 0x02 /* Enable IrDA Mode */ +#define TPOLC 0x04 /* IrDA TX Polarity Change */ +#define RPOLC 0x08 /* IrDA RX Polarity Change */ +#define FPE 0x10 /* Force Parity Error On Transmit */ +#define FFE 0x20 /* Force Framing Error On Transmit */ + +/* + * SERIAL PERIPHERAL INTERFACE (SPI) MASKS + */ +/* SPI_CTL Masks */ +#define TIMOD 0x0003 /* Transfer Initiate Mode */ +#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ +#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ +#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ +#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ +#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ +#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ +#define PSSE 0x0010 /* Slave-Select Input Enable */ +#define EMISO 0x0020 /* Enable MISO As Output */ +#define SIZE 0x0100 /* Size of Words (16/8* Bits) */ +#define LSBF 0x0200 /* LSB First */ +#define CPHA 0x0400 /* Clock Phase */ +#define CPOL 0x0800 /* Clock Polarity */ +#define MSTR 0x1000 /* Master/Slave* */ +#define WOM 0x2000 /* Write Open Drain Master */ +#define SPE 0x4000 /* SPI Enable */ + +/* SPI_FLG Masks */ +#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */ +#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */ +#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */ +#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */ +#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */ +#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */ +#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */ +#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */ +#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */ +#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */ +#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */ +#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */ +#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */ +#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */ + +/* SPI_STAT Masks */ +#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */ +#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */ +#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */ +#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */ +#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */ +#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ +#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ + +/* + * GENERAL PURPOSE TIMER MASKS + */ +/* TIMER_ENABLE Masks */ +#define TIMEN0 0x0001 /* Enable Timer 0 */ +#define TIMEN1 0x0002 /* Enable Timer 1 */ +#define TIMEN2 0x0004 /* Enable Timer 2 */ +#define TIMEN3 0x0008 /* Enable Timer 3 */ +#define TIMEN4 0x0010 /* Enable Timer 4 */ +#define TIMEN5 0x0020 /* Enable Timer 5 */ +#define TIMEN6 0x0040 /* Enable Timer 6 */ +#define TIMEN7 0x0080 /* Enable Timer 7 */ + +/* TIMER_DISABLE Masks */ +#define TIMDIS0 TIMEN0 /* Disable Timer 0 */ +#define TIMDIS1 TIMEN1 /* Disable Timer 1 */ +#define TIMDIS2 TIMEN2 /* Disable Timer 2 */ +#define TIMDIS3 TIMEN3 /* Disable Timer 3 */ +#define TIMDIS4 TIMEN4 /* Disable Timer 4 */ +#define TIMDIS5 TIMEN5 /* Disable Timer 5 */ +#define TIMDIS6 TIMEN6 /* Disable Timer 6 */ +#define TIMDIS7 TIMEN7 /* Disable Timer 7 */ + +/* TIMER_STATUS Masks */ +#define TIMIL0 0x00000001 /* Timer 0 Interrupt */ +#define TIMIL1 0x00000002 /* Timer 1 Interrupt */ +#define TIMIL2 0x00000004 /* Timer 2 Interrupt */ +#define TIMIL3 0x00000008 /* Timer 3 Interrupt */ +#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ +#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ +#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ +#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ +#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ +#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ +#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ +#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ +#define TIMIL4 0x00010000 /* Timer 4 Interrupt */ +#define TIMIL5 0x00020000 /* Timer 5 Interrupt */ +#define TIMIL6 0x00040000 /* Timer 6 Interrupt */ +#define TIMIL7 0x00080000 /* Timer 7 Interrupt */ +#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ +#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ +#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ +#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ +#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ +#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ +#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ +#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ + +/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ +#define TOVL_ERR0 TOVF_ERR0 +#define TOVL_ERR1 TOVF_ERR1 +#define TOVL_ERR2 TOVF_ERR2 +#define TOVL_ERR3 TOVF_ERR3 +#define TOVL_ERR4 TOVF_ERR4 +#define TOVL_ERR5 TOVF_ERR5 +#define TOVL_ERR6 TOVF_ERR6 +#define TOVL_ERR7 TOVF_ERR7 + +/* TIMERx_CONFIG Masks */ +#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ +#define WDTH_CAP 0x0002 /* Width Capture Input Mode */ +#define EXT_CLK 0x0003 /* External Clock Mode */ +#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ +#define PERIOD_CNT 0x0008 /* Period Count */ +#define IRQ_ENA 0x0010 /* Interrupt Request Enable */ +#define TIN_SEL 0x0020 /* Timer Input Select */ +#define OUT_DIS 0x0040 /* Output Pad Disable */ +#define CLK_SEL 0x0080 /* Timer Clock Select */ +#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ +#define EMU_RUN 0x0200 /* Emulation Behavior Select */ +#define ERR_TYP 0xC000 /* Error Type */ + +/* + * GPIO PORTS F, G, H MASKS + * General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks + */ +/* Port F Masks */ +#define PF0 0x0001 +#define PF1 0x0002 +#define PF2 0x0004 +#define PF3 0x0008 +#define PF4 0x0010 +#define PF5 0x0020 +#define PF6 0x0040 +#define PF7 0x0080 +#define PF8 0x0100 +#define PF9 0x0200 +#define PF10 0x0400 +#define PF11 0x0800 +#define PF12 0x1000 +#define PF13 0x2000 +#define PF14 0x4000 +#define PF15 0x8000 + +/* Port G Masks */ +#define PG0 0x0001 +#define PG1 0x0002 +#define PG2 0x0004 +#define PG3 0x0008 +#define PG4 0x0010 +#define PG5 0x0020 +#define PG6 0x0040 +#define PG7 0x0080 +#define PG8 0x0100 +#define PG9 0x0200 +#define PG10 0x0400 +#define PG11 0x0800 +#define PG12 0x1000 +#define PG13 0x2000 +#define PG14 0x4000 +#define PG15 0x8000 + +/* Port H Masks */ +#define PH0 0x0001 +#define PH1 0x0002 +#define PH2 0x0004 +#define PH3 0x0008 +#define PH4 0x0010 +#define PH5 0x0020 +#define PH6 0x0040 +#define PH7 0x0080 +#define PH8 0x0100 +#define PH9 0x0200 +#define PH10 0x0400 +#define PH11 0x0800 +#define PH12 0x1000 +#define PH13 0x2000 +#define PH14 0x4000 +#define PH15 0x8000 + +/* + * SERIAL PORT MASKS + */ +/* SPORTx_TCR1 Masks */ +#define TSPEN 0x0001 /* Transmit Enable */ +#define ITCLK 0x0002 /* Internal Transmit Clock Select */ +#define DTYPE_NORM 0x0004 /* Data Format Normal */ +#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ +#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ +#define TLSBIT 0x0010 /* Transmit Bit Order */ +#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */ +#define TFSR 0x0400 /* Transmit Frame Sync Required Select */ +#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */ +#define LTFS 0x1000 /* Low Transmit Frame Sync Select */ +#define LATFS 0x2000 /* Late Transmit Frame Sync Select */ +#define TCKFE 0x4000 /* Clock Falling Edge Select */ + +/* SPORTx_TCR2 Masks and Macro */ +#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */ +#define TXSE 0x0100 /* TX Secondary Enable */ +#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */ +#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */ + +/* SPORTx_RCR1 Masks */ +#define RSPEN 0x0001 /* Receive Enable */ +#define IRCLK 0x0002 /* Internal Receive Clock Select */ +#define DTYPE_NORM 0x0004 /* Data Format Normal */ +#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ +#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ +#define RLSBIT 0x0010 /* Receive Bit Order */ +#define IRFS 0x0200 /* Internal Receive Frame Sync Select */ +#define RFSR 0x0400 /* Receive Frame Sync Required Select */ +#define LRFS 0x1000 /* Low Receive Frame Sync Select */ +#define LARFS 0x2000 /* Late Receive Frame Sync Select */ +#define RCKFE 0x4000 /* Clock Falling Edge Select */ + +/* SPORTx_RCR2 Masks */ +#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */ +#define RXSE 0x0100 /* RX Secondary Enable */ +#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ +#define RRFST 0x0400 /* Right-First Data Order */ + +/* SPORTx_STAT Masks */ +#define RXNE 0x0001 /* Receive FIFO Not Empty Status */ +#define RUVF 0x0002 /* Sticky Receive Underflow Status */ +#define ROVF 0x0004 /* Sticky Receive Overflow Status */ +#define TXF 0x0008 /* Transmit FIFO Full Status */ +#define TUVF 0x0010 /* Sticky Transmit Underflow Status */ +#define TOVF 0x0020 /* Sticky Transmit Overflow Status */ +#define TXHRE 0x0040 /* Transmit Hold Register Empty */ + +/* SPORTx_MCMC1 Macros */ +#define WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */ + +/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */ +#define WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */ + +/* SPORTx_MCMC2 Masks */ +#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ +#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ +#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ +#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ +#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ +#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ +#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ +#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ +#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ +#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ +#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ +#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ +#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ +#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ +#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ +#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ +#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ +#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ +#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ +#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ +#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ +#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ +#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ + +/* + * ASYNCHRONOUS MEMORY CONTROLLER MASKS + */ +/* EBIU_AMGCTL Masks */ +#define AMCKEN 0x0001 /* Enable CLKOUT */ +#define AMBEN_NONE 0x0000 /* All Banks Disabled */ +#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ +#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ +#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ +#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ + +/* EBIU_AMBCTL0 Masks */ +#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ +#define B0RDYPOL 0x00000002 /* B0 RDY Active High */ +#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ +#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ +#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ +#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ +#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ +#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ +#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ +#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ +#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ +#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ +#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ +#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ +#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ +#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ +#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ +#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ +#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ +#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ +#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ +#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ +#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ +#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ +#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ +#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ +#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ +#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ +#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ +#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ +#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ +#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ +#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ +#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ +#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ +#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ +#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ +#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ +#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ +#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ +#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ +#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ +#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ +#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ + +#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ +#define B1RDYPOL 0x00020000 /* B1 RDY Active High */ +#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ +#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ +#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ +#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ +#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ +#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ +#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ +#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ +#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ +#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ +#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ +#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ +#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ +#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ +#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ +#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ +#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ +#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ +#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ +#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ +#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ +#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ +#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ +#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ +#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ +#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ +#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ +#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ +#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ +#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ +#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ +#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ +#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ +#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ +#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ +#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ +#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ +#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ +#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ +#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ +#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ +#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ + +/* EBIU_AMBCTL1 Masks */ +#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ +#define B2RDYPOL 0x00000002 /* B2 RDY Active High */ +#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ +#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ +#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ +#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ +#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ +#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ +#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ +#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ +#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ +#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ +#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ +#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ +#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ +#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ +#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ +#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ +#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ +#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ +#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ +#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ +#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ +#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ +#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ +#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ +#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ +#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ +#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ +#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ +#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ +#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ +#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ +#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ +#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ +#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ +#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ +#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ +#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ +#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ +#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ +#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ +#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ +#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ + +#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ +#define B3RDYPOL 0x00020000 /* B3 RDY Active High */ +#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ +#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ +#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ +#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ +#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ +#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ +#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ +#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ +#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ +#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ +#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ +#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ +#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ +#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ +#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ +#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ +#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ +#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ +#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ +#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ +#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ +#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ +#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ +#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ +#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ +#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ +#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ +#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ +#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ +#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ +#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ +#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ +#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ +#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ +#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ +#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ +#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ +#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ +#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ +#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ +#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ +#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ + +/* + * SDRAM CONTROLLER MASKS + */ +/* EBIU_SDGCTL Masks */ +#define SCTLE 0x00000001 /* Enable SDRAM Signals */ +#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ +#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ +#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ +#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ +#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ +#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ +#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ +#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ +#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ +#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ +#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ +#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ +#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ +#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ +#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ +#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ +#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ +#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ +#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ +#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ +#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ +#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ +#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ +#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ +#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ +#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ +#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ +#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ +#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ +#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ +#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ +#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ +#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ +#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ +#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ +#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ +#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ +#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ +#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ +#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ +#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ +#define EBUFE 0x02000000 /* Enable External Buffering Timing */ +#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ +#define EMREN 0x10000000 /* Extended Mode Register Enable */ +#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ +#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ + +/* EBIU_SDBCTL Masks */ +#define EBE 0x0001 /* Enable SDRAM External Bank */ +#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ +#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ +#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ +#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ +#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ +#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ +#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ +#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ + +/* EBIU_SDSTAT Masks */ +#define SDCI 0x0001 /* SDRAM Controller Idle */ +#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */ +#define SDPUA 0x0004 /* SDRAM Power-Up Active */ +#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ +#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ +#define BGSTAT 0x0020 /* Bus Grant Status */ + +/* + * DMA CONTROLLER MASKS + */ +/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ +#define DMAEN 0x0001 /* DMA Channel Enable */ +#define WNR 0x0002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ +#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ +#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ +#define RESTART 0x0020 /* DMA Buffer Clear */ +#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ +#define DI_EN 0x0080 /* Data Interrupt Enable */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ +#define FLOW_STOP 0x0000 /* Stop Mode */ +#define FLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ + +/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ +#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ +#define PMAP 0xF000 /* Peripheral Mapped To This Channel */ +#define PMAP_PPI 0x0000 /* PPI Port DMA */ +#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ +#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ +#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ +#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ +#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ +#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ +#define PMAP_SPI 0x7000 /* SPI Port DMA */ +#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ +#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ +#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ +#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ + +/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ +#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ +#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ +#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ +#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ + +/* + * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS + */ +/* PPI_CONTROL Masks */ +#define PORT_EN 0x0001 /* PPI Port Enable */ +#define PORT_DIR 0x0002 /* PPI Port Direction */ +#define XFR_TYPE 0x000C /* PPI Transfer Type */ +#define PORT_CFG 0x0030 /* PPI Port Configuration */ +#define FLD_SEL 0x0040 /* PPI Active Field Select */ +#define PACK_EN 0x0080 /* PPI Packing Mode */ +#define DMA32 0x0100 /* PPI 32-bit DMA Enable */ +#define SKIP_EN 0x0200 /* PPI Skip Element Enable */ +#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ +#define DLEN_8 0x0000 /* Data Length = 8 Bits */ +#define DLEN_10 0x0800 /* Data Length = 10 Bits */ +#define DLEN_11 0x1000 /* Data Length = 11 Bits */ +#define DLEN_12 0x1800 /* Data Length = 12 Bits */ +#define DLEN_13 0x2000 /* Data Length = 13 Bits */ +#define DLEN_14 0x2800 /* Data Length = 14 Bits */ +#define DLEN_15 0x3000 /* Data Length = 15 Bits */ +#define DLEN_16 0x3800 /* Data Length = 16 Bits */ +#define POLC 0x4000 /* PPI Clock Polarity */ +#define POLS 0x8000 /* PPI Frame Sync Polarity */ + +/* PPI_STATUS Masks */ +#define FLD 0x0400 /* Field Indicator */ +#define FT_ERR 0x0800 /* Frame Track Error */ +#define OVR 0x1000 /* FIFO Overflow Error */ +#define UNDR 0x2000 /* FIFO Underrun Error */ +#define ERR_DET 0x4000 /* Error Detected Indicator */ +#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ + +/* + * TWO-WIRE INTERFACE (TWI) MASKS + */ +/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ +#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ +#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ + +/* TWI_PRESCALE Masks */ +#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ +#define TWI_ENA 0x0080 /* TWI Enable */ +#define SCCB 0x0200 /* SCCB Compatibility Enable */ + +/* TWI_SLAVE_CTRL Masks */ +#define SEN 0x0001 /* Slave Enable */ +#define SADD_LEN 0x0002 /* Slave Address Length */ +#define STDVAL 0x0004 /* Slave Transmit Data Valid */ +#define TSC_NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ +#define GEN 0x0010 /* General Call Adrress Matching Enabled */ + +/* TWI_SLAVE_STAT Masks */ +#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ +#define GCALL 0x0002 /* General Call Indicator */ + +/* TWI_MASTER_CTRL Masks */ +#define MEN 0x0001 /* Master Mode Enable */ +#define MADD_LEN 0x0002 /* Master Address Length */ +#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ +#define FAST 0x0008 /* Use Fast Mode Timing Specs */ +#define STOP 0x0010 /* Issue Stop Condition */ +#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ +#define DCNT 0x3FC0 /* Data Bytes To Transfer */ +#define SDAOVR 0x4000 /* Serial Data Override */ +#define SCLOVR 0x8000 /* Serial Clock Override */ + +/* TWI_MASTER_STAT Masks */ +#define MPROG 0x0001 /* Master Transfer In Progress */ +#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ +#define ANAK 0x0004 /* Address Not Acknowledged */ +#define DNAK 0x0008 /* Data Not Acknowledged */ +#define BUFRDERR 0x0010 /* Buffer Read Error */ +#define BUFWRERR 0x0020 /* Buffer Write Error */ +#define SDASEN 0x0040 /* Serial Data Sense */ +#define SCLSEN 0x0080 /* Serial Clock Sense */ +#define BUSBUSY 0x0100 /* Bus Busy Indicator */ + +/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ +#define SINIT 0x0001 /* Slave Transfer Initiated */ +#define SCOMP 0x0002 /* Slave Transfer Complete */ +#define SERR 0x0004 /* Slave Transfer Error */ +#define SOVF 0x0008 /* Slave Overflow */ +#define MCOMP 0x0010 /* Master Transfer Complete */ +#define MERR 0x0020 /* Master Transfer Error */ +#define XMTSERV 0x0040 /* Transmit FIFO Service */ +#define RCVSERV 0x0080 /* Receive FIFO Service */ + +/* TWI_FIFO_CTRL Masks */ +#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ +#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ +#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ +#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ + +/* TWI_FIFO_STAT Masks */ +#define XMTSTAT 0x0003 /* Transmit FIFO Status */ +#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ +#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ +#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ + +#define RCVSTAT 0x000C /* Receive FIFO Status */ +#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ +#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ +#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ + +/* + * CONTROLLER AREA NETWORK (CAN) MASKS + */ +/* CAN_CONTROL Masks */ +#define SRS 0x0001 /* Software Reset */ +#define DNM 0x0002 /* Device Net Mode */ +#define ABO 0x0004 /* Auto-Bus On Enable */ +#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */ +#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */ +#define SMR 0x0020 /* Sleep Mode Request */ +#define CSR 0x0040 /* CAN Suspend Mode Request */ +#define CCR 0x0080 /* CAN Configuration Mode Request */ + +/* CAN_STATUS Masks */ +#define WT 0x0001 /* TX Warning Flag */ +#define WR 0x0002 /* RX Warning Flag */ +#define EP 0x0004 /* Error Passive Mode */ +#define EBO 0x0008 /* Error Bus Off Mode */ +#define SMA 0x0020 /* Sleep Mode Acknowledge */ +#define CSA 0x0040 /* Suspend Mode Acknowledge */ +#define CCA 0x0080 /* Configuration Mode Acknowledge */ +#define MBPTR 0x1F00 /* Mailbox Pointer */ +#define TRM 0x4000 /* Transmit Mode */ +#define REC 0x8000 /* Receive Mode */ + +/* CAN_CLOCK Masks */ +#define BRP 0x03FF /* Bit-Rate Pre-Scaler */ + +/* CAN_TIMING Masks */ +#define TSEG1 0x000F /* Time Segment 1 */ +#define TSEG2 0x0070 /* Time Segment 2 */ +#define SAM 0x0080 /* Sampling */ +#define SJW 0x0300 /* Synchronization Jump Width */ + +/* CAN_DEBUG Masks */ +#define DEC 0x0001 /* Disable CAN Error Counters */ +#define DRI 0x0002 /* Disable CAN RX Input */ +#define DTO 0x0004 /* Disable CAN TX Output */ +#define DIL 0x0008 /* Disable CAN Internal Loop */ +#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */ +#define MRB 0x0020 /* Mode Read Back Enable */ +#define CDE 0x8000 /* CAN Debug Enable */ + +/* CAN_CEC Masks */ +#define RXECNT 0x00FF /* Receive Error Counter */ +#define TXECNT 0xFF00 /* Transmit Error Counter */ + +/* CAN_INTR Masks */ +#define MBRIF 0x0001 /* Mailbox Receive Interrupt */ +#define MBTIF 0x0002 /* Mailbox Transmit Interrupt */ +#define GIRQ 0x0004 /* Global Interrupt */ +#define SMACK 0x0008 /* Sleep Mode Acknowledge */ +#define CANTX 0x0040 /* CAN TX Bus Value */ +#define CANRX 0x0080 /* CAN RX Bus Value */ + +/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */ +#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */ +#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */ +#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */ +#define BASEID 0x1FFC /* Base Identifier */ +#define IDE 0x2000 /* Identifier Extension */ +#define RTR 0x4000 /* Remote Frame Transmission Request */ +#define AME 0x8000 /* Acceptance Mask Enable */ + +/* CAN_MBxx_TIMESTAMP Masks */ +#define TSV 0xFFFF /* Timestamp */ + +/* CAN_MBxx_LENGTH Masks */ +#define DLC 0x000F /* Data Length Code */ + +/* CAN_AMxxH and CAN_AMxxL Masks */ +#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */ +#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */ +#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */ +#define BASEID 0x1FFC /* Base Identifier */ +#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */ +#define FMD 0x4000 /* Full Mask Data Field Enable */ +#define FDF 0x8000 /* Filter On Data Field Enable */ + +/* CAN_MC1 Masks */ +#define MC0 0x0001 /* Enable Mailbox 0 */ +#define MC1 0x0002 /* Enable Mailbox 1 */ +#define MC2 0x0004 /* Enable Mailbox 2 */ +#define MC3 0x0008 /* Enable Mailbox 3 */ +#define MC4 0x0010 /* Enable Mailbox 4 */ +#define MC5 0x0020 /* Enable Mailbox 5 */ +#define MC6 0x0040 /* Enable Mailbox 6 */ +#define MC7 0x0080 /* Enable Mailbox 7 */ +#define MC8 0x0100 /* Enable Mailbox 8 */ +#define MC9 0x0200 /* Enable Mailbox 9 */ +#define MC10 0x0400 /* Enable Mailbox 10 */ +#define MC11 0x0800 /* Enable Mailbox 11 */ +#define MC12 0x1000 /* Enable Mailbox 12 */ +#define MC13 0x2000 /* Enable Mailbox 13 */ +#define MC14 0x4000 /* Enable Mailbox 14 */ +#define MC15 0x8000 /* Enable Mailbox 15 */ + +/* CAN_MC2 Masks */ +#define MC16 0x0001 /* Enable Mailbox 16 */ +#define MC17 0x0002 /* Enable Mailbox 17 */ +#define MC18 0x0004 /* Enable Mailbox 18 */ +#define MC19 0x0008 /* Enable Mailbox 19 */ +#define MC20 0x0010 /* Enable Mailbox 20 */ +#define MC21 0x0020 /* Enable Mailbox 21 */ +#define MC22 0x0040 /* Enable Mailbox 22 */ +#define MC23 0x0080 /* Enable Mailbox 23 */ +#define MC24 0x0100 /* Enable Mailbox 24 */ +#define MC25 0x0200 /* Enable Mailbox 25 */ +#define MC26 0x0400 /* Enable Mailbox 26 */ +#define MC27 0x0800 /* Enable Mailbox 27 */ +#define MC28 0x1000 /* Enable Mailbox 28 */ +#define MC29 0x2000 /* Enable Mailbox 29 */ +#define MC30 0x4000 /* Enable Mailbox 30 */ +#define MC31 0x8000 /* Enable Mailbox 31 */ + +/* CAN_MD1 Masks */ +#define MD0 0x0001 /* Enable Mailbox 0 For Receive */ +#define MD1 0x0002 /* Enable Mailbox 1 For Receive */ +#define MD2 0x0004 /* Enable Mailbox 2 For Receive */ +#define MD3 0x0008 /* Enable Mailbox 3 For Receive */ +#define MD4 0x0010 /* Enable Mailbox 4 For Receive */ +#define MD5 0x0020 /* Enable Mailbox 5 For Receive */ +#define MD6 0x0040 /* Enable Mailbox 6 For Receive */ +#define MD7 0x0080 /* Enable Mailbox 7 For Receive */ +#define MD8 0x0100 /* Enable Mailbox 8 For Receive */ +#define MD9 0x0200 /* Enable Mailbox 9 For Receive */ +#define MD10 0x0400 /* Enable Mailbox 10 For Receive */ +#define MD11 0x0800 /* Enable Mailbox 11 For Receive */ +#define MD12 0x1000 /* Enable Mailbox 12 For Receive */ +#define MD13 0x2000 /* Enable Mailbox 13 For Receive */ +#define MD14 0x4000 /* Enable Mailbox 14 For Receive */ +#define MD15 0x8000 /* Enable Mailbox 15 For Receive */ + +/* CAN_MD2 Masks */ +#define MD16 0x0001 /* Enable Mailbox 16 For Receive */ +#define MD17 0x0002 /* Enable Mailbox 17 For Receive */ +#define MD18 0x0004 /* Enable Mailbox 18 For Receive */ +#define MD19 0x0008 /* Enable Mailbox 19 For Receive */ +#define MD20 0x0010 /* Enable Mailbox 20 For Receive */ +#define MD21 0x0020 /* Enable Mailbox 21 For Receive */ +#define MD22 0x0040 /* Enable Mailbox 22 For Receive */ +#define MD23 0x0080 /* Enable Mailbox 23 For Receive */ +#define MD24 0x0100 /* Enable Mailbox 24 For Receive */ +#define MD25 0x0200 /* Enable Mailbox 25 For Receive */ +#define MD26 0x0400 /* Enable Mailbox 26 For Receive */ +#define MD27 0x0800 /* Enable Mailbox 27 For Receive */ +#define MD28 0x1000 /* Enable Mailbox 28 For Receive */ +#define MD29 0x2000 /* Enable Mailbox 29 For Receive */ +#define MD30 0x4000 /* Enable Mailbox 30 For Receive */ +#define MD31 0x8000 /* Enable Mailbox 31 For Receive */ + +/* CAN_RMP1 Masks */ +#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */ +#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */ +#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */ +#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */ +#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */ +#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */ +#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */ +#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */ +#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */ +#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */ +#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */ +#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */ +#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */ +#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */ +#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */ +#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */ + +/* CAN_RMP2 Masks */ +#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */ +#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */ +#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */ +#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */ +#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */ +#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */ +#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */ +#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */ +#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */ +#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */ +#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */ +#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */ +#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */ +#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */ +#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */ +#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */ + +/* CAN_RML1 Masks */ +#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */ +#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */ +#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */ +#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */ +#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */ +#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */ +#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */ +#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */ +#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */ +#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */ +#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */ +#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */ +#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */ +#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */ +#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */ +#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */ + +/* CAN_RML2 Masks */ +#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */ +#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */ +#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */ +#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */ +#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */ +#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */ +#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */ +#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */ +#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */ +#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */ +#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */ +#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */ +#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */ +#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */ +#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */ +#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */ + +/* CAN_OPSS1 Masks */ +#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */ +#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */ +#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */ +#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */ +#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */ +#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */ +#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */ +#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */ +#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */ +#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */ +#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */ +#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */ +#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */ +#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */ +#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */ +#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */ + +/* CAN_OPSS2 Masks */ +#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */ +#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */ +#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */ +#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */ +#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */ +#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */ +#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */ +#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */ +#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */ +#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */ +#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */ +#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */ +#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */ +#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */ +#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */ +#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */ + +/* CAN_TRR1 Masks */ +#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */ +#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */ +#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */ +#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */ +#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */ +#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */ +#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */ +#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */ +#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */ +#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */ +#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */ +#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */ +#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */ +#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */ +#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */ +#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */ + +/* CAN_TRR2 Masks */ +#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */ +#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */ +#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */ +#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */ +#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */ +#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */ +#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */ +#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */ +#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */ +#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */ +#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */ +#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */ +#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */ +#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */ +#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */ +#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */ + +/* CAN_TRS1 Masks */ +#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */ +#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */ +#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */ +#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */ +#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */ +#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */ +#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */ +#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */ +#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */ +#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */ +#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */ +#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */ +#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */ +#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */ +#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */ +#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */ + +/* CAN_TRS2 Masks */ +#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */ +#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */ +#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */ +#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */ +#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */ +#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */ +#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */ +#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */ +#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */ +#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */ +#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */ +#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */ +#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */ +#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */ +#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */ +#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */ + +/* CAN_AA1 Masks */ +#define AA0 0x0001 /* Aborted Message In Mailbox 0 */ +#define AA1 0x0002 /* Aborted Message In Mailbox 1 */ +#define AA2 0x0004 /* Aborted Message In Mailbox 2 */ +#define AA3 0x0008 /* Aborted Message In Mailbox 3 */ +#define AA4 0x0010 /* Aborted Message In Mailbox 4 */ +#define AA5 0x0020 /* Aborted Message In Mailbox 5 */ +#define AA6 0x0040 /* Aborted Message In Mailbox 6 */ +#define AA7 0x0080 /* Aborted Message In Mailbox 7 */ +#define AA8 0x0100 /* Aborted Message In Mailbox 8 */ +#define AA9 0x0200 /* Aborted Message In Mailbox 9 */ +#define AA10 0x0400 /* Aborted Message In Mailbox 10 */ +#define AA11 0x0800 /* Aborted Message In Mailbox 11 */ +#define AA12 0x1000 /* Aborted Message In Mailbox 12 */ +#define AA13 0x2000 /* Aborted Message In Mailbox 13 */ +#define AA14 0x4000 /* Aborted Message In Mailbox 14 */ +#define AA15 0x8000 /* Aborted Message In Mailbox 15 */ + +/* CAN_AA2 Masks */ +#define AA16 0x0001 /* Aborted Message In Mailbox 16 */ +#define AA17 0x0002 /* Aborted Message In Mailbox 17 */ +#define AA18 0x0004 /* Aborted Message In Mailbox 18 */ +#define AA19 0x0008 /* Aborted Message In Mailbox 19 */ +#define AA20 0x0010 /* Aborted Message In Mailbox 20 */ +#define AA21 0x0020 /* Aborted Message In Mailbox 21 */ +#define AA22 0x0040 /* Aborted Message In Mailbox 22 */ +#define AA23 0x0080 /* Aborted Message In Mailbox 23 */ +#define AA24 0x0100 /* Aborted Message In Mailbox 24 */ +#define AA25 0x0200 /* Aborted Message In Mailbox 25 */ +#define AA26 0x0400 /* Aborted Message In Mailbox 26 */ +#define AA27 0x0800 /* Aborted Message In Mailbox 27 */ +#define AA28 0x1000 /* Aborted Message In Mailbox 28 */ +#define AA29 0x2000 /* Aborted Message In Mailbox 29 */ +#define AA30 0x4000 /* Aborted Message In Mailbox 30 */ +#define AA31 0x8000 /* Aborted Message In Mailbox 31 */ + +/* CAN_TA1 Masks */ +#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */ +#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */ +#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */ +#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */ +#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */ +#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */ +#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */ +#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */ +#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */ +#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */ +#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */ +#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */ +#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */ +#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */ +#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */ +#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */ + +/* CAN_TA2 Masks */ +#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */ +#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */ +#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */ +#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */ +#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */ +#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */ +#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */ +#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */ +#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */ +#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */ +#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */ +#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */ +#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */ +#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */ +#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */ +#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */ + +/* CAN_MBTD Masks */ +#define TDPTR 0x001F /* Mailbox To Temporarily Disable */ +#define TDA 0x0040 /* Temporary Disable Acknowledge */ +#define TDR 0x0080 /* Temporary Disable Request */ + +/* CAN_RFH1 Masks */ +#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */ +#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */ +#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */ +#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */ +#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */ +#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */ +#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */ +#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */ +#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */ +#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */ +#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */ +#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */ +#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */ +#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */ +#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */ +#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */ + +/* CAN_RFH2 Masks */ +#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */ +#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */ +#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */ +#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */ +#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */ +#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */ +#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */ +#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */ +#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */ +#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */ +#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */ +#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */ +#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */ +#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */ +#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */ +#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */ + +/* CAN_MBTIF1 Masks */ +#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */ +#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */ +#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */ +#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */ +#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */ +#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */ +#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */ +#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */ +#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */ +#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */ +#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */ +#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */ +#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */ +#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */ +#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */ +#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */ + +/* CAN_MBTIF2 Masks */ +#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */ +#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */ +#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */ +#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */ +#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */ +#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */ +#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */ +#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */ +#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */ +#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */ +#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */ +#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */ +#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */ +#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */ +#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */ +#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */ + +/* CAN_MBRIF1 Masks */ +#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */ +#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */ +#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */ +#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */ +#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */ +#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */ +#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */ +#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */ +#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */ +#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */ +#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */ +#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */ +#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */ +#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */ +#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */ +#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */ + +/* CAN_MBRIF2 Masks */ +#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */ +#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */ +#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */ +#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */ +#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */ +#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */ +#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */ +#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */ +#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */ +#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */ +#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */ +#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */ +#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */ +#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */ +#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */ +#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */ + +/* CAN_MBIM1 Masks */ +#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */ +#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */ +#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */ +#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */ +#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */ +#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */ +#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */ +#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */ +#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */ +#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */ +#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */ +#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */ +#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */ +#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */ +#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */ +#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */ + +/* CAN_MBIM2 Masks */ +#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */ +#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */ +#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */ +#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */ +#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */ +#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */ +#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */ +#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */ +#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */ +#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */ +#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */ +#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */ +#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */ +#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */ +#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */ +#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */ + +/* CAN_GIM Masks */ +#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */ +#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */ +#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */ +#define BOIM 0x0008 /* Enable Bus Off Interrupt */ +#define WUIM 0x0010 /* Enable Wake-Up Interrupt */ +#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */ +#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */ +#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */ +#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */ +#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */ +#define ADIM 0x0400 /* Enable Access Denied Interrupt */ + +/* CAN_GIS Masks */ +#define EWTIS 0x0001 /* TX Error Count IRQ Status */ +#define EWRIS 0x0002 /* RX Error Count IRQ Status */ +#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */ +#define BOIS 0x0008 /* Bus Off IRQ Status */ +#define WUIS 0x0010 /* Wake-Up IRQ Status */ +#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */ +#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */ +#define RMLIS 0x0080 /* RX Message Lost IRQ Status */ +#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */ +#define EXTIS 0x0200 /* External Trigger Output IRQ Status */ +#define ADIS 0x0400 /* Access Denied IRQ Status */ + +/* CAN_GIF Masks */ +#define EWTIF 0x0001 /* TX Error Count IRQ Flag */ +#define EWRIF 0x0002 /* RX Error Count IRQ Flag */ +#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */ +#define BOIF 0x0008 /* Bus Off IRQ Flag */ +#define WUIF 0x0010 /* Wake-Up IRQ Flag */ +#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */ +#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */ +#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */ +#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */ +#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */ +#define ADIF 0x0400 /* Access Denied IRQ Flag */ + +/* CAN_UCCNF Masks */ +#define UCCNF 0x000F /* Universal Counter Mode */ +#define UC_STAMP 0x0001 /* Timestamp Mode */ +#define UC_WDOG 0x0002 /* Watchdog Mode */ +#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */ +#define UC_ERROR 0x0006 /* CAN Error Frame Count */ +#define UC_OVER 0x0007 /* CAN Overload Frame Count */ +#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */ +#define UC_AA 0x0009 /* TX Abort Count */ +#define UC_TA 0x000A /* TX Successful Count */ +#define UC_REJECT 0x000B /* RX Message Rejected Count */ +#define UC_RML 0x000C /* RX Message Lost Count */ +#define UC_RX 0x000D /* Total Successful RX Messages Count */ +#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */ +#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */ +#define UCRC 0x0020 /* Universal Counter Reload/Clear */ +#define UCCT 0x0040 /* Universal Counter CAN Trigger */ +#define UCE 0x0080 /* Universal Counter Enable */ + +/* CAN_ESR Masks */ +#define ACKE 0x0004 /* Acknowledge Error */ +#define SER 0x0008 /* Stuff Error */ +#define CRCE 0x0010 /* CRC Error */ +#define SA0 0x0020 /* Stuck At Dominant Error */ +#define BEF 0x0040 /* Bit Error Flag */ +#define FER 0x0080 /* Form Error Flag */ + +/* CAN_EWR Masks */ +#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */ +#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */ + +/* + * PIN CONTROL REGISTER MASKS + */ +/* PORT_MUX Masks */ +#define PJSE 0x0001 /* Port J SPI/SPORT Enable */ +#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ +#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ + +#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */ +#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ +#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */ +#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ + +#define PFDE 0x0008 /* Port F DMA Request Enable */ +#define PGDE_UART 0x0000 /* Enable UART0 RX/TX */ +#define PGDE_DMA 0x0008 /* Enable DMAR1:0 */ + +#define PFTE 0x0010 /* Port F Timer Enable */ +#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ +#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */ + +#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ +#define PFS6E_TIMER 0x0000 /* Enable TMR5 */ +#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ + +#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ +#define PFS5E_TIMER 0x0000 /* Enable TMR4 */ +#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ + +#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ +#define PFS4E_TIMER 0x0000 /* Enable TMR3 */ +#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ + +#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */ +#define PFFE_TIMER 0x0000 /* Enable TMR2 */ +#define PFFE_PPI 0x0100 /* Enable PPI FS3 */ + +#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ +#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */ +#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ + +#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */ +#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */ +#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ + +#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ +#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ +#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ + +/* + * HANDSHAKE DMA (HDMA) MASKS + */ +/* HDMAx_CTL Masks */ +#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */ +#define REP 0x0002 /* HDMA Request Polarity */ +#define UTE 0x0004 /* Urgency Threshold Enable */ +#define OIE 0x0010 /* Overflow Interrupt Enable */ +#define BDIE 0x0020 /* Block Done Interrupt Enable */ +#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */ +#define DRQ 0x0300 /* HDMA Request Type */ +#define DRQ_NONE 0x0000 /* No Request */ +#define DRQ_SINGLE 0x0100 /* Channels Request Single */ +#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */ +#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */ +#define RBC 0x1000 /* Reload BCNT With IBCNT */ +#define PS 0x2000 /* HDMA Pin Status */ +#define OI 0x4000 /* Overflow Interrupt Generated */ +#define BDI 0x8000 /* Block Done Interrupt Generated */ + +/* entry addresses of the user-callable Boot ROM functions */ + +#define _BOOTROM_RESET 0xEF000000 +#define _BOOTROM_FINAL_INIT 0xEF000002 +#define _BOOTROM_DO_MEMORY_DMA 0xEF000006 +#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 +#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A +#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C +#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 +#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 +#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 + +#endif /* _DEF_BF534_H */ diff --git a/include/asm-blackfin/arch-bf537/defBF537.h b/include/asm-blackfin/arch-bf537/defBF537.h new file mode 100644 index 0000000000..8d16c374a0 --- /dev/null +++ b/include/asm-blackfin/arch-bf537/defBF537.h @@ -0,0 +1,488 @@ +/* + * Copyright (C) 2004-2005 Analog Devices Inc., All Rights Reserved. + * + *********************************************************************************** + * + * This include file contains a list of macro "defines" to enable the programmer + * to use symbolic names for register-access and bit-manipulation. + * + * ---------------------------- + * revision 0.1 + * date: 2004/03/01 21:23:01; author: joeb + * Initial revision + * + * ---------------------------- + * revision 0.2 + * date: 2004/05/15 16:30:00; author: joeb + * comments: removed I2C/IIC references, changed GPIO sections + * + * ---------------------------- + * revision 0.3 + * date: 2004/06/08 12:25:00; author: joeb + * comments: fixed mis-mapped TIMER registers, changed TWI register names, fixed + * FLAG references in GPIO register names + * + * ---------------------------- + * revision 0.4 + * date: 2004/06/09 2:25:00; author: joeb + * comments: fixed bit-defines for EMAC section, renamed EMAC count registers, + * combined 2 Timer status registers into one + * + * ---------------------------- + * revision 0.5 + * date: 2004/08/10 10:25:00; author: joeb + * comments: Renamed EMAC wake-up registers, changed bit-names in EMAC registers + * + * ---------------------------- + * revision 0.6 + * date: 2004/08/17 16:25:00; author: joeb + * comments: Renamed TWI_INT_ENABLE to TWI_INT_MASK + * + * ---------------------------- + * revision 0.7 + * date: 2004/08/18 13:21:00; author: joeb + * comments: Renamed GPIO registers to remove _D, _S, _C, _T suffixes + * + * ---------------------------- + * revision 0.8 + * date: 2004/08/20 10:24:00; author: joeb + * comments: Renamed External DMA to Handshake MDMA + * + * ---------------------------- + * revision 0.9 + * date: 2004/08/23 13:42:00; author: joeb + * comments: Renamed Handshake DMA Register Set + * + * ---------------------------- + * revision 0.10 + * date: 2004/09/07 11:21:00; author: joeb + * comments: Fixed EMAC TX/RX DMA Priority (DMA and SIC Bit Names) + * + * ---------------------------- + * revision 0.11 + * date: 2004/09/28 15:14:00; author: joeb + * comments: Fixed CAN Mailbox Area + * + * ---------------------------- + * revision 0.12 + * date: 2004/10/27 13:18:00; author: joeb + * comments: Added IEEE EMAC Register Support + * + * ---------------------------- + * revision 0.13 + * date: 2004/10/28 15:40:00; author: joeb + * comments: Shortened EMAC Count Register Names + * + * ---------------------------- + * revision 0.14 + * date: 2004/11/09 10:45:00; author: joeb + * comments: Fixed WDSIZE macros + * + * ---------------------------- + * revision 0.15 + * date: 2004/11/18 07:45:00; author: joeb + * comments: Fixed TIMER_STATUS register, added EMAC macros + * + * ---------------------------- + * revision 0.16 + * date: 2004/12/13 11:05:00; author: joeb + * comments: Removed HI/LO macros (now Assembler mnemonics) + * Renamed enable bit for HMDMA from EN to HMDMAEN + * + * ---------------------------- + * revision 0.17 + * date: 2004/12/17 14:25:00; author: joeb + * comments: Replaced C++ Single-Line Comments w/C-standard Comments + * Changed EMAC EQ1024 TX/RX References to GE1024 + * + * ---------------------------- + * revision 0.18 + * date: 2005/01/05 10:50:00; author: joeb + * comments: Added CAN Macros To Index Mailbox Area and Acceptance Masks + * Added mask values for field deposit protection + * + * ---------------------------- + * revision 0.19 + * date: 2005/01/10 10:30:00; author: joeb + * comments: Made all Macro argument syntax compliant to MISRA-C 2004 rule 19.10. + * + * ---------------------------- + * revision 0.20 + * date: 2005/01/27 14:25:15; author: joeb + * comments: Moved MMRs common to BF534 to BF534 header. + */ +#ifndef _DEF_BF537_H +#define _DEF_BF537_H + +/* Include all Core registers and bit definitions */ +#include + +/* Include all MMR and bit defines common to BF534 */ +#include + +/* + * Define EMAC Section Unique to BF536/BF537 + */ + +/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ +#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ +#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ +#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ +#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ +#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ +#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ +#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ +#define EMAC_FLC 0xFFC0301C /* Flow Control Register */ +#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ +#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ +#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ +#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ +#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ +#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ +#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ +#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ +#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ +#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ +#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ + +#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ +#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ +#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ +#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ +#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ +#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ +#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ +#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ + +#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ +#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ +#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ +#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ +#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ + +#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ +#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ +#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ +#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ +#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ +#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ +#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ +#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ +#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ +#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ +#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ +#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ +#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ +#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ +#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ +#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ +#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ +#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ +#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ +#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */ +#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ +#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ +#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ +#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ + +#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ +#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ +#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ +#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ +#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ +#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ +#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ +#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ +#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ +#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ +#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ +#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ +#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ +#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ +#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ +#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ +#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ +#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ +#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ +#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ +#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ +#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ +#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ + +/* Listing for IEEE-Supported Count Registers */ +#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */ +#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */ +#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */ +#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */ +#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */ +#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */ +#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */ +#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */ +#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */ +#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */ +#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */ +#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */ +#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */ +#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */ +#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */ +#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */ +#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */ +#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */ +#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */ +#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */ +#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ +#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ +#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ +#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */ + +#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */ +#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */ +#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */ +#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */ +#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */ +#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */ +#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */ +#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */ +#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */ +#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */ +#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */ +#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */ +#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */ +#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */ +#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */ +#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */ +#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */ +#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ +#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ +#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */ +#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ +#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */ +#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */ + +/* + * System MMR Register Bits And Macros + * + * Disclaimer: All macros are intended to make C and Assembly code more readable. + * Use these macros carefully, as any that do left shifts for field + * depositing will result in the lower order bits being destroyed. Any + * macro that shifts left to properly position the bit-field should be + * used as part of an OR to initialize a register and NOT as a dynamic + * modifier UNLESS the lower order bits are saved and ORed back in when + * the macro is used. + */ +/* + * ETHERNET 10/100 CONTROLLER MASKS + */ +/* EMAC_OPMODE Masks */ +#define RE 0x00000001 /* Receiver Enable */ +#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ +#define HU 0x00000010 /* Hash Filter Unicast Address */ +#define HM 0x00000020 /* Hash Filter Multicast Address */ +#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ +#define PR 0x00000080 /* Promiscuous Mode Enable */ +#define IFE 0x00000100 /* Inverse Filtering Enable */ +#define DBF 0x00000200 /* Disable Broadcast Frame Reception */ +#define PBF 0x00000400 /* Pass Bad Frames Enable */ +#define PSF 0x00000800 /* Pass Short Frames Enable */ +#define RAF 0x00001000 /* Receive-All Mode */ +#define TE 0x00010000 /* Transmitter Enable */ +#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ +#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ +#define DC 0x00080000 /* Deferral Check */ +#define BOLMT 0x00300000 /* Back-Off Limit */ +#define BOLMT_10 0x00000000 /* 10-bit range */ +#define BOLMT_8 0x00100000 /* 8-bit range */ +#define BOLMT_4 0x00200000 /* 4-bit range */ +#define BOLMT_1 0x00300000 /* 1-bit range */ +#define DRTY 0x00400000 /* Disable TX Retry On Collision */ +#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ +#define RMII 0x01000000 /* RMII/MII* Mode */ +#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ +#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ +#define LB 0x08000000 /* Internal Loopback Enable */ +#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ + +/* EMAC_STAADD Masks */ +#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ +#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ +#define STADISPRE 0x00000004 /* Disable Preamble Generation */ +#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ +#define REGAD 0x000007C0 /* STA Register Address */ +#define PHYAD 0x0000F800 /* PHY Device Address */ + +#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */ +#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */ + +/* EMAC_STADAT Mask */ +#define STADATA 0x0000FFFF /* Station Management Data */ + +/* EMAC_FLC Masks */ +#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ +#define FLCE 0x00000002 /* Flow Control Enable */ +#define PCF 0x00000004 /* Pass Control Frames */ +#define BKPRSEN 0x00000008 /* Enable Backpressure */ +#define FLCPAUSE 0xFFFF0000 /* Pause Time */ + +#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */ + +/* EMAC_WKUP_CTL Masks */ +#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ +#define MPKE 0x00000002 /* Magic Packet Enable */ +#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ +#define GUWKE 0x00000008 /* Global Unicast Wake Enable */ +#define MPKS 0x00000020 /* Magic Packet Received Status */ +#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ + +/* EMAC_WKUP_FFCMD Masks */ +#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ +#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ +#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ +#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ +#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ +#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ +#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ +#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ + +/* EMAC_WKUP_FFOFF Masks */ +#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ +#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ +#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ +#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ + +#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ +#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ +#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ +#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ +/* Set ALL Offsets */ +#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) + +/* EMAC_WKUP_FFCRC0 Masks */ +#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ +#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ + +#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0) /* Set Wake-Up Filter 0 Target CRC */ +#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16) /* Set Wake-Up Filter 1 Target CRC */ + +/* EMAC_WKUP_FFCRC1 Masks */ +#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ +#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ + +#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0) /* Set Wake-Up Filter 2 Target CRC */ +#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16) /* Set Wake-Up Filter 3 Target CRC */ + +/* EMAC_SYSCTL Masks */ +#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ +#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ +#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ +#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ + +#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ + +/* EMAC_SYSTAT Masks */ +#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ +#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ +#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ +#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ +#define WAKEDET 0x00000010 /* Wake-Up Detected Status */ +#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ +#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ +#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ + +/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ +#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ +#define RX_COMP 0x00001000 /* RX Frame Complete */ +#define RX_OK 0x00002000 /* RX Frame Received With No Errors */ +#define RX_LONG 0x00004000 /* RX Frame Too Long Error */ +#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ +#define RX_CRC 0x00010000 /* RX Frame CRC Error */ +#define RX_LEN 0x00020000 /* RX Frame Length Error */ +#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ +#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ +#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ +#define RX_PHY 0x00200000 /* RX Frame PHY Error */ +#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ +#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ +#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ +#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ +#define RX_CTL 0x04000000 /* RX Control Frame Indicator */ +#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ +#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ +#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ +#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ +#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ + +/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ +#define TX_COMP 0x00000001 /* TX Frame Complete */ +#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ +#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ +#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ +#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ +#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ +#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ +#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ +#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ +#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ +#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ +#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ +#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ +#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ +#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ + +/* EMAC_MMC_CTL Masks */ +#define RSTC 0x00000001 /* Reset All Counters */ +#define CROLL 0x00000002 /* Counter Roll-Over Enable */ +#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ +#define MMCE 0x00000008 /* Enable MMC Counter Operation */ + +/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ +#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ +#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ +#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ +#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ +#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ +#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ +#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ +#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ +#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ +#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ +#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ +#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ +#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ +#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ +#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ +#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ +#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ +#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ +#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ +#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ +#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ +#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ +#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ +#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ + +/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ +#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ +#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ +#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ +#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ +#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ +#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ +#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ +#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ +#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ +#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ +#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ +#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ +#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ +#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ +#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ +#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ +#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ +#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ +#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ +#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ +#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ +#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ +#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ + +#endif /* _DEF_BF537_H */ diff --git a/include/asm-blackfin/arch-bf537/defBF537_extn.h b/include/asm-blackfin/arch-bf537/defBF537_extn.h new file mode 100644 index 0000000000..8090da66b6 --- /dev/null +++ b/include/asm-blackfin/arch-bf537/defBF537_extn.h @@ -0,0 +1,76 @@ +/* + * defBF537_extn.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _DEF_BF537_EXTN_H +#define _DEF_BF537_EXTN_H + +#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */ +/* Delay inserted for PLL transition */ +#define PLL_DELAY 0x1000 + +#define L1_ISRAM 0xFFA00000 +#define L1_ISRAM_END 0xFFA10000 +#define DATA_BANKA_SRAM 0xFF800000 +#define DATA_BANKA_SRAM_END 0xFF808000 +#define DATA_BANKB_SRAM 0xFF900000 +#define DATA_BANKB_SRAM_END 0xFF908000 +#define SYSMMR_BASE 0xFFC00000 +#define WDSIZE16 0x00000004 + +/* Event Vector Table Address */ +#define EVT_EMULATION_ADDR 0xffe02000 +#define EVT_RESET_ADDR 0xffe02004 +#define EVT_NMI_ADDR 0xffe02008 +#define EVT_EXCEPTION_ADDR 0xffe0200c +#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010 +#define EVT_HARDWARE_ERROR_ADDR 0xffe02014 +#define EVT_TIMER_ADDR 0xffe02018 +#define EVT_IVG7_ADDR 0xffe0201c +#define EVT_IVG8_ADDR 0xffe02020 +#define EVT_IVG9_ADDR 0xffe02024 +#define EVT_IVG10_ADDR 0xffe02028 +#define EVT_IVG11_ADDR 0xffe0202c +#define EVT_IVG12_ADDR 0xffe02030 +#define EVT_IVG13_ADDR 0xffe02034 +#define EVT_IVG14_ADDR 0xffe02038 +#define EVT_IVG15_ADDR 0xffe0203c +#define EVT_OVERRIDE_ADDR 0xffe02100 + +/* IMASK Bit values */ +#define IVG15_POS 0x00008000 +#define IVG14_POS 0x00004000 +#define IVG13_POS 0x00002000 +#define IVG12_POS 0x00001000 +#define IVG11_POS 0x00000800 +#define IVG10_POS 0x00000400 +#define IVG9_POS 0x00000200 +#define IVG8_POS 0x00000100 +#define IVG7_POS 0x00000080 +#define IVGTMR_POS 0x00000040 +#define IVGHW_POS 0x00000020 + +#define WDOG_TMR_DISABLE (0xAD << 4) +#define ICTL_RST 0x00000000 +#define ICTL_NMI 0x00000002 +#define ICTL_GP 0x00000004 +#define ICTL_DISABLE 0x00000003 + +/* Watch Dog timer values setup */ +#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE + +#endif /* _DEF_BF537_EXTN_H */ diff --git a/include/asm-blackfin/arch-bf537/irq.h b/include/asm-blackfin/arch-bf537/irq.h new file mode 100644 index 0000000000..4cb4c1502f --- /dev/null +++ b/include/asm-blackfin/arch-bf537/irq.h @@ -0,0 +1,94 @@ +/* + * U-boot bf537_irq.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c + * Changed by HuTao Apr18, 2003 + * + * Copyright was missing when I got the code so took from MIPS arch ...MaTed--- + * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle + * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle + * + * Adapted for BlackFin (ADI) by Ted Ma + * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) + * Copyright (c) 2002 Lineo, Inc. + * + * Adapted for BlackFin BF537 by Bas Vermeulen + * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl) + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BF537_IRQ_H_ +#define _BF537_IRQ_H_ + +/* + * Interrupt source definitions + * Event Source Core Event Name Number + * EMU 0 + * Reset RST 1 + * NMI NMI 2 + * Exception EVX 3 + * Reserved -- 4 + * Hardware Error IVHW 5 + * Core Timer IVTMR 6 + * PLL Wakeup Interrupt IVG7 7 + * DMA Error (generic) IVG7 8 + * PPI Error Interrupt IVG7 9 + * SPORT0 Error Interrupt IVG7 10 + * SPORT1 Error Interrupt IVG7 11 + * SPI Error Interrupt IVG7 12 + * UART Error Interrupt IVG7 13 + * RTC Interrupt IVG8 14 + * DMA0 Interrupt (PPI) IVG8 15 + * DMA1 (SPORT0 RX) IVG9 16 + * DMA2 (SPORT0 TX) IVG9 17 + * DMA3 (SPORT1 RX) IVG9 18 + * DMA4 (SPORT1 TX) IVG9 19 + * DMA5 (PPI) IVG10 20 + * DMA6 (UART RX) IVG10 21 + * DMA7 (UART TX) IVG10 22 + * Timer0 IVG11 23 + * Timer1 IVG11 24 + * Timer2 IVG11 25 + * PF Interrupt A IVG12 26 + * PF Interrupt B IVG12 27 + * DMA8/9 Interrupt IVG13 28 + * DMA10/11 Interrupt IVG13 29 + * Watchdog Timer IVG13 30 + * Software Interrupt 1 IVG14 31 + * Software Interrupt 2 -- + * (lowest priority) IVG15 32 + */ + +#define IRQ_EMU 0 /* Emulation */ +#define IRQ_RST 1 /* reset */ +#define IRQ_NMI 2 /* Non Maskable */ +#define IRQ_EVX 3 /* Exception */ +#define IRQ_UNUSED 4 /* - unused interrupt */ +#define IRQ_HWERR 5 /* Hardware Error */ +#define IRQ_CORETMR 6 /* Core timer */ + +#define IRQ_UART_RX_BIT 0x0800 +#define IRQ_UART_TX_BIT 0x1000 +#define IRQ_UART_ERROR_BIT 0x40 + +#endif diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h new file mode 100644 index 0000000000..f6755acf69 --- /dev/null +++ b/include/configs/bf537-stamp.h @@ -0,0 +1,502 @@ +/* + * U-boot - Configuration file for BF537 STAMP board + */ + +#ifndef __CONFIG_BF537_H__ +#define __CONFIG_BF537_H__ + +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_BAUDRATE 57600 +/* Set default serial console for bf537 */ +#define CONFIG_UART_CONSOLE 0 +#define CONFIG_BF537 1 +#define CONFIG_BOOTDELAY 5 +/* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/ +/*#define CONFIG_BF537_STAMP_LEDCMD 1*/ + +/* + * Boot Mode Set + * Blackfin can support several boot modes + */ +#define BF537_BYPASS_BOOT 0x0011 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */ +#define BF537_PARA_BOOT 0x0012 /* Bootmode 1: Boot from 8-bit or 16-bit flash */ +#define BF537_SPI_MASTER_BOOT 0x0014 /* Bootmode 3: SPI master mode boot from SPI flash */ +#define BF537_SPI_SLAVE_BOOT 0x0015 /* Bootmode 4: SPI slave mode boot from SPI flash */ +#define BF537_TWI_MASTER_BOOT 0x0016 /* Bootmode 5: TWI master mode boot from EEPROM */ +#define BF537_TWI_SLAVE_BOOT 0x0017 /* Bootmode 6: TWI slave mode boot from EEPROM */ +#define BF537_UART_BOOT 0x0018 /* Bootmode 7: UART slave mdoe boot via UART host */ +/* Define the boot mode */ +#define BFIN_BOOT_MODE BF537_BYPASS_BOOT + +#define CONFIG_PANIC_HANG 1 + +#define ADSP_BF534 0x34 +#define ADSP_BF536 0x36 +#define ADSP_BF537 0x37 +#define BFIN_CPU ADSP_BF537 + +/* This sets the default state of the cache on U-Boot's boot */ +#define CONFIG_ICACHE_ON +#define CONFIG_DCACHE_ON + +/* Define if want to do post memory test */ +#undef CONFIG_POST_TEST + +/* Define where the uboot will be loaded by on-chip boot rom */ +#define APP_ENTRY 0x00001000 + +#define CONFIG_RTC_BFIN 1 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL*/ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 20 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 +/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ +/* Values can range from 2-65535 */ +/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ +#define CONFIG_SPI_BAUD 2 +#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) +#define CONFIG_SPI_BAUD_INITBLOCK 4 +#endif + +#if ( CONFIG_CLKIN_HALF == 0 ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#else +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#endif + +#if (CONFIG_PLL_BYPASS == 0) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) +#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000) +#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */ +#else +#undef CONFIG_SPI_FLASH_FAST_READ +#endif +#endif + +#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC32M8A2_75 1 + +#define CONFIG_LOADS_ECHO 1 + +/* + * rarpb, bootp or dhcp commands will perform only a + * configuration lookup from the BOOTP/DHCP server + * but not try to load any image using TFTP + */ +#define CFG_AUTOLOAD "no" + +/* + * Network Settings + */ +/* network support */ +#if (BFIN_CPU != ADSP_BF534) +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME BF537 +#endif + +#define CONFIG_ROOTPATH /romfs +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ +/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */ + +#define CFG_LONGHELP 1 +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ +#define CONFIG_BOOTCOMMAND "run ramboot" + +#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) && defined(CONFIG_POST_TEST) +/* POST support */ +#define CONFIG_POST ( CFG_POST_MEMORY | \ + CFG_POST_UART | \ + CFG_POST_FLASH | \ + CFG_POST_ETHER | \ + CFG_POST_LED | \ + CFG_POST_BUTTON) +#else +#undef CONFIG_POST +#endif + +#ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */ +#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ +#else +#define CFG_CMD_POST_DIAG 0 +#endif + +/* CF-CARD IDE-HDD Support */ + +/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */ +/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */ +/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */ + +#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE) +# define CONFIG_BFIN_IDE 1 +# define ADD_IDE_CMD CFG_CMD_IDE +#else +# define ADD_IDE_CMD 0 +#endif + +/*#define CONFIG_BF537_NAND */ /* Add nand flash support */ + +#ifdef CONFIG_BF537_NAND +# define ADD_NAND_CMD CFG_CMD_NAND +#else +# define ADD_NAND_CMD 0 +#endif + +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NET_MULTI 1 + +#if (BFIN_CPU == ADSP_BF534) +#define CONFIG_BFIN_CMD (CONFIG_CMD_DFL & ~CFG_CMD_NET) +#else +#define CONFIG_BFIN_CMD (CONFIG_CMD_DFL | CFG_CMD_PING) +#endif + +#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) +#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DHCP | \ + ADD_IDE_CMD | \ + ADD_NAND_CMD | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_DATE) +#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) +#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_EEPROM | \ + ADD_IDE_CMD | \ + CFG_CMD_DATE) +#endif + +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600" +#define CONFIG_LOADADDR 0x1000000 + +#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) +#if (BFIN_CPU != ADSP_BF534) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot $(loadaddr) linux;" \ + "run ramargs;run addip;bootelf\0" \ + "nfsboot=tftpboot $(loadaddr) linux;" \ + "run nfsargs;run addip;bootelf\0" \ + "flashboot=bootm 0x20100000\0" \ + "update=tftpboot $(loadaddr) u-boot.bin;" \ + "protect off 0x20000000 0x2007FFFF;" \ + "erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0" \ + "" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "flashboot=bootm 0x20100000\0" \ + "" +#endif +#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) +#if (BFIN_CPU != ADSP_BF534) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot $(loadaddr) linux;" \ + "run ramargs;run addip;bootelf\0" \ + "nfsboot=tftpboot $(loadaddr) linux;" \ + "run nfsargs;run addip;bootelf\0" \ + "flashboot=bootm 0x20100000\0" \ + "update=tftpboot $(loadaddr) u-boot.ldr;" \ + "eeprom write $(loadaddr) 0x0 $(filesize);\0" \ + "" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "flashboot=bootm 0x20100000\0" \ + "" +#endif +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) +#if (BFIN_CPU == ADSP_BF534) +#define CFG_PROMPT "serial_bf534> " /* Monitor Command Prompt */ +#elif (BFIN_CPU == ADSP_BF536) +#define CFG_PROMPT "serial_bf536> " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "serial_bf537> " /* Monitor Command Prompt */ +#endif +#else +#if (BFIN_CPU == ADSP_BF534) +#define CFG_PROMPT "bf534> " /* Monitor Command Prompt */ +#elif (BFIN_CPU == ADSP_BF536) +#define CFG_PROMPT "bf536> " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "bf537> " /* Monitor Command Prompt */ +#endif +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024) +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MEMTEST_START 0x0 /* memtest works on */ +#define CFG_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024*1024) /* 1 ... 63 MB in DRAM */ +#define CFG_LOAD_ADDR CONFIG_LOADADDR /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_SDRAM_BASE 0x00000000 + +#define CFG_FLASH_BASE 0x20000000 + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_SIZE 0x4000 +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) + +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_UART_BOOT) +/* for bf537-stamp, usrt boot mode still store env in flash */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x20004000 +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) +#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */ +#endif +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */ +/* #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) */ +#define ENV_IS_EMBEDDED +/* #endif */ + +/* JFFS Partition offset set */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CFG_JFFS2_FIRST_SECTOR 15 + +#define CONFIG_SPI + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#define POLL_MODE 1 +#define FLASH_TOT_SECT 71 +#define FLASH_SIZE 0x400000 +#define CFG_FLASH_SIZE 0x400000 + +/* + * Board NAND Infomation + */ + +#define CFG_NAND_ADDR 0x20212000 +#define CFG_NAND_BASE CFG_NAND_ADDR +#define CFG_MAX_NAND_DEVICE 1 +#define SECTORSIZE 512 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define BFIN_NAND_READY PF3 + +#define NAND_WAIT_READY(nand) \ + do { \ + int timeout = 0; \ + while(!(*pPORTFIO & PF3)) \ + if (timeout++ > 100000) \ + break; \ + } while (0) + +#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */ +#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */ + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +/* + * Initialize PSD4256 registers for using I2C + */ +#define CONFIG_MISC_INIT_R + +#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ + +/* + * I2C settings + * By default PF1 is used as SDA and PF0 as SCL on the Stamp board + */ +/* #define CONFIG_SOFT_I2C 1*/ /* I2C bit-banged */ +#define CONFIG_HARD_I2C 1 /* I2C TWI */ +#if defined CONFIG_HARD_I2C +#define CONFIG_TWICLK_KHZ 50 +#endif + +#if defined CONFIG_SOFT_I2C +/* + * Software (bit-bang) I2C driver configuration + */ +#define PF_SCL PF0 +#define PF_SDA PF1 + +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#endif + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE + +/* 0xFF, 0x7BB07BB0, 0x22547BB0 */ +/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ + ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) +#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ + B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) +*/ + +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0x7BB07BB0 +#define AMBCTL1VAL 0xFFC27BB0 + +#define CONFIG_VDSP 1 + +#ifdef CONFIG_VDSP +#define ET_EXEC_VDSP 0x8 +#define SHT_STRTAB_VDSP 0x1 +#define ELFSHDRSIZE_VDSP 0x2C +#define VDSP_ENTRY_ADDR 0xFFA00000 +#endif + +#if defined(CONFIG_BFIN_IDE) + +#define CONFIG_DOS_PARTITION 1 +/* + * IDE/ATA stuff + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#undef AMBCTL1VAL +#define AMBCTL1VAL 0xFFC3FFC3 + +#define CONFIG_CF_ATASEL_DIS 0x20311800 +#define CONFIG_CF_ATASEL_ENA 0x20311802 + +#if defined(CONFIG_BFIN_TRUE_IDE) +/* + * Note that these settings aren't for the most part used in include/ata.h + * when all of the ATA registers are setup + */ +#define CFG_ATA_BASE_ADDR 0x2031C000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */ +#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */ +#endif /* CONFIG_BFIN_TRUE_IDE */ + +#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */ +#define CFG_ATA_BASE_ADDR 0x20211800 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */ +#define CFG_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */ +#endif /* CONFIG_BFIN_CF_IDE */ + +#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */ +#define CFG_ATA_BASE_ADDR 0x20314000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */ +#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */ + +#undef CONFIG_SCLK_DIV +#define CONFIG_SCLK_DIV 8 +#endif /* CONFIG_BFIN_HDD_IDE */ + +#endif /*CONFIG_BFIN_IDE */ + +#endif -- cgit v1.2.1 From 8e709bbb2636b5670a8f2b575e138eb1f55773f6 Mon Sep 17 00:00:00 2001 From: Aubrey Li Date: Mon, 19 Mar 2007 01:26:11 +0800 Subject: [PATCH] Add flash chip M29W320ET/B support --- include/flash.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/flash.h b/include/flash.h index 55b6d8f388..43b9c6bdca 100644 --- a/include/flash.h +++ b/include/flash.h @@ -252,6 +252,8 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */ #define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */ #define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */ +#define STM_ID_29W320ET 0x22562256 /* M29W320ET ID (32 M, top boot sector) */ +#define STM_ID_29W320EB 0x22572257 /* M29W320EB ID (32 M, bottom boot sect)*/ #define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */ #define FLASH_PSD4256GV 0x00E9 /* PSD4256 Flash and CPLD combination */ -- cgit v1.2.1 From 654589873dbafcf104dff133ce0d03a4506e9cc3 Mon Sep 17 00:00:00 2001 From: Aubrey Li Date: Tue, 20 Mar 2007 18:16:24 +0800 Subject: [Blackfin][PATCH] Add BF561 EZKIT board support --- include/asm-blackfin/arch-bf561/anomaly.h | 181 +++ include/asm-blackfin/arch-bf561/bf561_serial.h | 78 + include/asm-blackfin/arch-bf561/cdefBF561.h | 998 ++++++++++++ include/asm-blackfin/arch-bf561/defBF561.h | 1941 +++++++++++++++++++++++ include/asm-blackfin/arch-bf561/defBF561_extn.h | 76 + include/asm-blackfin/arch-bf561/irq.h | 137 ++ include/configs/bf561-ezkit.h | 244 +++ 7 files changed, 3655 insertions(+) create mode 100644 include/asm-blackfin/arch-bf561/anomaly.h create mode 100644 include/asm-blackfin/arch-bf561/bf561_serial.h create mode 100644 include/asm-blackfin/arch-bf561/cdefBF561.h create mode 100644 include/asm-blackfin/arch-bf561/defBF561.h create mode 100644 include/asm-blackfin/arch-bf561/defBF561_extn.h create mode 100644 include/asm-blackfin/arch-bf561/irq.h create mode 100644 include/configs/bf561-ezkit.h (limited to 'include') diff --git a/include/asm-blackfin/arch-bf561/anomaly.h b/include/asm-blackfin/arch-bf561/anomaly.h new file mode 100644 index 0000000000..467649b5a7 --- /dev/null +++ b/include/asm-blackfin/arch-bf561/anomaly.h @@ -0,0 +1,181 @@ +/* + * File: include/asm-blackfin/arch-bf561/anomaly.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * This file shoule be up to date with: + * - Revision L, 10Aug2006; ADSP-BF561 Silicon Anomaly List + */ + +#ifndef _MACH_ANOMALY_H_ +#define _MACH_ANOMALY_H_ + +/* We do not support 0.1 or 0.4 silicon - sorry */ +#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2) || defined(CONFIG_BF_REV_0_4)) +#error Kernel will not work on BF561 Version 0.1, 0.2, or 0.4 +#endif + +/* Issues that are common to 0.5 and 0.3 silicon */ +#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) +#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in + slot1 and store of a P register in slot 2 is not + supported */ +#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not + updated at the same time. */ +#define ANOMALY_05000120 /* Testset instructions restricted to 32-bit aligned + memory locations */ +#define ANOMALY_05000122 /* Rx.H cannot be used to access 16-bit System MMR + registers */ +#define ANOMALY_05000127 /* Signbits instruction not functional under certain + conditions */ +#define ANOMALY_05000149 /* IMDMA S1/D1 channel may stall */ +#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out + upper bits */ +#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ +#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame + syncs */ +#define ANOMALY_05000182 /* IMDMA does not operate to full speed for 600MHz + and higher devices */ +#define ANOMALY_05000187 /* IMDMA Corrupted Data after a Halt */ +#define ANOMALY_05000190 /* PPI not functional at core voltage < 1Volt */ +#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not + functional */ +#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the + shadow of a conditional branch */ +#define ANOMALY_05000257 /* Interrupt/Exception during short hardware loop + may cause bad instruction fetches */ +#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on + external SPORT TX and RX clocks */ +#define ANOMALY_05000267 /* IMDMA may corrupt data under certain conditions */ +#define ANOMALY_05000269 /* High I/O activity causes output voltage of internal + voltage regulator (VDDint) to increase */ +#define ANOMALY_05000270 /* High I/O activity causes output voltage of internal + voltage regulator (VDDint) to decrease */ +#define ANOMALY_05000272 /* Certain data cache write through modes fail for + VDDint <=0.9V */ +#define ANOMALY_05000274 /* Data cache write back to external synchronous memory + may be lost */ +#define ANOMALY_05000275 /* PPI Timing and sampling informaton updates */ +#endif /* (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */ + +#if (defined(CONFIG_BF_REV_0_5)) +#define ANOMALY_05000254 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT + mode with external clock */ +#define ANOMALY_05000266 /* IMDMA destination IRQ status must be read prior to + using IMDMA */ +#endif + +#if (defined(CONFIG_BF_REV_0_3)) +#define ANOMALY_05000156 /* Timers in PWM-Out Mode with PPI GP Receive (Input) + Mode with 0 Frame Syncs */ +#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */ +#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost write-through + cache data writes */ +#define ANOMALY_05000171 /* Boot-ROM code modifies SICA_IWRx wakeup registers */ +#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */ +#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */ +#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an + accumulator saturation */ +#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General + Purpose TX or RX modes */ +#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration + registers */ +#define ANOMALY_05000184 /* Timer Pin limitations for PPI TX Modes with + External Frame Syncs */ +#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */ +#define ANOMALY_05000186 /* PPI packing with Data Length greater than 8 bits + (not a meaningful mode) */ +#define ANOMALY_05000188 /* IMDMA Restrictions on Descriptor and Buffer + Placement in Memory */ +#define ANOMALY_05000189 /* False Protection Exception */ +#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs + when polarity setting is changed */ +#define ANOMALY_05000194 /* Restarting SPORT in specific modes may cause data + corruption */ +#define ANOMALY_05000198 /* Failing MMR accesses when stalled by preceding + memory read */ +#define ANOMALY_05000199 /* DMA current address shows wrong value during carry + fix */ +#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during + inactive channels in certain conditions */ +#define ANOMALY_05000202 /* Possible infinite stall with specific dual-DAG + situation */ +#define ANOMALY_05000204 /* Incorrect data read with write-through cache and + allocate cache lines on reads only mode */ +#define ANOMALY_05000205 /* Specific sequence that can cause DMA error or DMA + stopping */ +#define ANOMALY_05000207 /* Recovery from "brown-out" condition */ +#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain + instructions */ +#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */ +#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable + state */ +#define ANOMALY_05000220 /* Data Corruption with Cached External Memory and + Non-Cached On-Chip L2 Memory */ +#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */ +#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect + data */ +#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate + Differences in certain Conditions */ +#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */ +#define ANOMALY_05000232 /* SPORT data transmit lines are incorrectly driven in + multichannel mode */ +#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to + hardware reset */ +#define ANOMALY_05000244 /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of + Control causes failures */ +#define ANOMALY_05000248 /* TESTSET operation forces stall on the other core */ +#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel + (TDM) mode in certain conditions */ +#define ANOMALY_05000251 /* Exception not generated for MMR accesses in + reserved region */ +#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ +#define ANOMALY_05000258 /* Instruction Cache is corrupted when bits 9 and 12 + of the ICPLB Data registers differ */ +#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ +#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ +#define ANOMALY_05000262 /* Stores to data cache may be lost */ +#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB + exception */ +#define ANOMALY_05000264 /* CSYNC/SSYNC/IDLE causes infinite stall in second + to last instruction in hardware loop */ +#define ANOMALY_05000276 /* Timing requirements change for External Frame + Sync PPI Modes with non-zero PPI_DELAY */ +#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause + DMA system instability */ +#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is + not restored */ +#define ANOMALY_05000283 /* An MMR write is stalled indefinitely when killed + in a particular stage */ +#define ANOMALY_05000287 /* A read will receive incorrect data under certain + conditions */ +#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */ +#endif + +#endif /* _MACH_ANOMALY_H_ */ diff --git a/include/asm-blackfin/arch-bf561/bf561_serial.h b/include/asm-blackfin/arch-bf561/bf561_serial.h new file mode 100644 index 0000000000..0810228397 --- /dev/null +++ b/include/asm-blackfin/arch-bf561/bf561_serial.h @@ -0,0 +1,78 @@ +/* + * U-boot bf561_serial.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BF561_SERIAL_H_ +#define _BF561_SERIAL_H_ + +#define BYTE_REF(addr) (*((volatile char*)addr)) +#define HALFWORD_REF(addr) (*((volatile short*)addr)) +#define WORD_REF(addr) (*((volatile long*)addr)) + +#define UART_THR_LO HALFWORD_REF(UART_THR) +#define UART_RBR_LO HALFWORD_REF(UART_RBR) +#define UART_DLL_LO HALFWORD_REF(UART_DLL) +#define UART_IER_LO HALFWORD_REF(UART_IER) +#define UART_IER_ERBFI 0x01 +#define UART_IER_ETBEI 0x02 +#define UART_IER_ELSI 0x04 +#define UART_IER_EDDSI 0x08 + +#define UART_DLH_LO HALFWORD_REF(UART_DLH) +#define UART_IIR_LO HALFWORD_REF(UART_IIR) +#define UART_IIR_NOINT 0x01 +#define UART_IIR_STATUS 0x06 +#define UART_IIR_LSR 0x06 +#define UART_IIR_RBR 0x04 +#define UART_IIR_THR 0x02 +#define UART_IIR_MSR 0x00 + +#define UART_LCR_LO HALFWORD_REF(UART_LCR) +#define UART_LCR_WLS5 0 +#define UART_LCR_WLS6 0x01 +#define UART_LCR_WLS7 0x02 +#define UART_LCR_WLS8 0x03 +#define UART_LCR_STB 0x04 +#define UART_LCR_PEN 0x08 +#define UART_LCR_EPS 0x10 +#define UART_LCR_SP 0x20 +#define UART_LCR_SB 0x40 +#define UART_LCR_DLAB 0x80 + +#define UART_MCR_LO HALFWORD_REF(UART_MCR) + +#define UART_LSR_LO HALFWORD_REF(UART_LSR) +#define UART_LSR_DR 0x01 +#define UART_LSR_OE 0x02 +#define UART_LSR_PE 0x04 +#define UART_LSR_FE 0x08 +#define UART_LSR_BI 0x10 +#define UART_LSR_THRE 0x20 +#define UART_LSR_TEMT 0x40 + +#define UART_MSR_LO HALFWORD_REF(UART_MSR) +#define UART_SCR_LO HALFWORD_REF(UART_SCR) +#define UART_GCTL_LO HALFWORD_REF(UART_GCTL) +#define UART_GCTL_UCEN 0x01 + +#endif diff --git a/include/asm-blackfin/arch-bf561/cdefBF561.h b/include/asm-blackfin/arch-bf561/cdefBF561.h new file mode 100644 index 0000000000..f217ba720a --- /dev/null +++ b/include/asm-blackfin/arch-bf561/cdefBF561.h @@ -0,0 +1,998 @@ +/* + * cdefBF561.h + * + * (c) Copyright 2001-2004 Analog Devices, Inc. All rights reserved. + * + */ + +/* C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */ + +#ifndef _CDEF_BF561_H +#define _CDEF_BF561_H + +/* + * #if !defined(__ADSPBF561__) + * #warning cdefBF561.h should only be included for BF561 chip. + * #endif + */ + +/* include all Core registers and bit definitions */ +#include +#include + +/* + * System MMR Register Map + */ + +/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ +#define pPLL_CTL (volatile unsigned short *)PLL_CTL +#define pPLL_DIV (volatile unsigned short *)PLL_DIV +#define pVR_CTL (volatile unsigned short *)VR_CTL +#define pPLL_STAT (volatile unsigned short *)PLL_STAT +#define pPLL_LOCKCNT (volatile unsigned short *)PLL_LOCKCNT + +/* + * System Reset and Interrupt Controller registers for + * core A (0xFFC0 0100-0xFFC0 01FF) + */ +#define pSICA_SWRST (volatile unsigned short *)SICA_SWRST +#define pSICA_SYSCR (volatile unsigned short *)SICA_SYSCR +#define pSICA_RVECT (volatile unsigned short *)SICA_RVECT +#define pSICA_IMASK (volatile unsigned long *)SICA_IMASK +#define pSICA_IMASK0 (volatile unsigned long *)SICA_IMASK0 +#define pSICA_IMASK1 (volatile unsigned long *)SICA_IMASK1 +#define pSICA_IAR0 (volatile unsigned long *)SICA_IAR0 +#define pSICA_IAR1 (volatile unsigned long *)SICA_IAR1 +#define pSICA_IAR2 (volatile unsigned long *)SICA_IAR2 +#define pSICA_IAR3 (volatile unsigned long *)SICA_IAR3 +#define pSICA_IAR4 (volatile unsigned long *)SICA_IAR4 +#define pSICA_IAR5 (volatile unsigned long *)SICA_IAR5 +#define pSICA_IAR6 (volatile unsigned long *)SICA_IAR6 +#define pSICA_IAR7 (volatile unsigned long *)SICA_IAR7 +#define pSICA_ISR0 (volatile unsigned long *)SICA_ISR0 +#define pSICA_ISR1 (volatile unsigned long *)SICA_ISR1 +#define pSICA_IWR0 (volatile unsigned long *)SICA_IWR0 +#define pSICA_IWR1 (volatile unsigned long *)SICA_IWR1 + +/* + * System Reset and Interrupt Controller registers for + * Core B (0xFFC0 1100-0xFFC0 11FF) + */ +#define pSICB_SWRST (volatile unsigned short *)SICB_SWRST +#define pSICB_SYSCR (volatile unsigned short *)SICB_SYSCR +#define pSICB_RVECT (volatile unsigned short *)SICB_RVECT +#define pSICB_IMASK0 (volatile unsigned long *)SICB_IMASK0 +#define pSICB_IMASK1 (volatile unsigned long *)SICB_IMASK1 +#define pSICB_IAR0 (volatile unsigned long *)SICB_IAR0 +#define pSICB_IAR1 (volatile unsigned long *)SICB_IAR1 +#define pSICB_IAR2 (volatile unsigned long *)SICB_IAR2 +#define pSICB_IAR3 (volatile unsigned long *)SICB_IAR3 +#define pSICB_IAR4 (volatile unsigned long *)SICB_IAR4 +#define pSICB_IAR5 (volatile unsigned long *)SICB_IAR5 +#define pSICB_IAR6 (volatile unsigned long *)SICB_IAR6 +#define pSICB_IAR7 (volatile unsigned long *)SICB_IAR7 +#define pSICB_ISR0 (volatile unsigned long *)SICB_ISR0 +#define pSICB_ISR1 (volatile unsigned long *)SICB_ISR1 +#define pSICB_IWR0 (volatile unsigned long *)SICB_IWR0 +#define pSICB_IWR1 (volatile unsigned long *)SICB_IWR1 + +/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ +#define pWDOGA_CTL (volatile unsigned short *)WDOGA_CTL +#define pWDOGA_CNT (volatile unsigned long *)WDOGA_CNT +#define pWDOGA_STAT (volatile unsigned long *)WDOGA_STAT + +/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */ +#define pWDOGB_CTL (volatile unsigned short *)WDOGB_CTL +#define pWDOGB_CNT (volatile unsigned long *)WDOGB_CNT +#define pWDOGB_STAT (volatile unsigned long *)WDOGB_STAT + +/* UART Controller (0xFFC00400 - 0xFFC004FF) */ +#define pUART_THR (volatile unsigned short *)UART_THR +#define pUART_RBR (volatile unsigned short *)UART_RBR +#define pUART_DLL (volatile unsigned short *)UART_DLL +#define pUART_IER (volatile unsigned short *)UART_IER +#define pUART_DLH (volatile unsigned short *)UART_DLH +#define pUART_IIR (volatile unsigned short *)UART_IIR +#define pUART_LCR (volatile unsigned short *)UART_LCR +#define pUART_MCR (volatile unsigned short *)UART_MCR +#define pUART_LSR (volatile unsigned short *)UART_LSR +#define pUART_MSR (volatile unsigned short *)UART_MSR +#define pUART_SCR (volatile unsigned short *)UART_SCR +#define pUART_GCTL (volatile unsigned short *)UART_GCTL + +/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define pSPI_CTL (volatile unsigned short *)SPI_CTL +#define pSPI_FLG (volatile unsigned short *)SPI_FLG +#define pSPI_STAT (volatile unsigned short *)SPI_STAT +#define pSPI_TDBR (volatile unsigned short *)SPI_TDBR +#define pSPI_RDBR (volatile unsigned short *)SPI_RDBR +#define pSPI_BAUD (volatile unsigned short *)SPI_BAUD +#define pSPI_SHADOW (volatile unsigned short *)SPI_SHADOW + +/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */ +#define pTIMER0_CONFIG (volatile unsigned short *)TIMER0_CONFIG +#define pTIMER0_COUNTER (volatile unsigned long *)TIMER0_COUNTER +#define pTIMER0_PERIOD (volatile unsigned long *)TIMER0_PERIOD +#define pTIMER0_WIDTH (volatile unsigned long *)TIMER0_WIDTH +#define pTIMER1_CONFIG (volatile unsigned short *)TIMER1_CONFIG +#define pTIMER1_COUNTER (volatile unsigned long *)TIMER1_COUNTER +#define pTIMER1_PERIOD (volatile unsigned long *)TIMER1_PERIOD +#define pTIMER1_WIDTH (volatile unsigned long *)TIMER1_WIDTH +#define pTIMER2_CONFIG (volatile unsigned short *)TIMER2_CONFIG +#define pTIMER2_COUNTER (volatile unsigned long *)TIMER2_COUNTER +#define pTIMER2_PERIOD (volatile unsigned long *)TIMER2_PERIOD +#define pTIMER2_WIDTH (volatile unsigned long *)TIMER2_WIDTH +#define pTIMER3_CONFIG (volatile unsigned short *)TIMER3_CONFIG +#define pTIMER3_COUNTER (volatile unsigned long *)TIMER3_COUNTER +#define pTIMER3_PERIOD (volatile unsigned long *)TIMER3_PERIOD +#define pTIMER3_WIDTH (volatile unsigned long *)TIMER3_WIDTH +#define pTIMER4_CONFIG (volatile unsigned short *)TIMER4_CONFIG +#define pTIMER4_COUNTER (volatile unsigned long *)TIMER4_COUNTER +#define pTIMER4_PERIOD (volatile unsigned long *)TIMER4_PERIOD +#define pTIMER4_WIDTH (volatile unsigned long *)TIMER4_WIDTH +#define pTIMER5_CONFIG (volatile unsigned short *)TIMER5_CONFIG +#define pTIMER5_COUNTER (volatile unsigned long *)TIMER5_COUNTER +#define pTIMER5_PERIOD (volatile unsigned long *)TIMER5_PERIOD +#define pTIMER5_WIDTH (volatile unsigned long *)TIMER5_WIDTH +#define pTIMER6_CONFIG (volatile unsigned short *)TIMER6_CONFIG +#define pTIMER6_COUNTER (volatile unsigned long *)TIMER6_COUNTER +#define pTIMER6_PERIOD (volatile unsigned long *)TIMER6_PERIOD +#define pTIMER6_WIDTH (volatile unsigned long *)TIMER6_WIDTH +#define pTIMER7_CONFIG (volatile unsigned short *)TIMER7_CONFIG +#define pTIMER7_COUNTER (volatile unsigned long *)TIMER7_COUNTER +#define pTIMER7_PERIOD (volatile unsigned long *)TIMER7_PERIOD +#define pTIMER7_WIDTH (volatile unsigned long *)TIMER7_WIDTH + +/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */ +#define pTMRS8_ENABLE (volatile unsigned short *)TMRS8_ENABLE +#define pTMRS8_DISABLE (volatile unsigned short *)TMRS8_DISABLE +#define pTMRS8_STATUS (volatile unsigned long *)TMRS8_STATUS +#define pTIMER8_CONFIG (volatile unsigned short *)TIMER8_CONFIG +#define pTIMER8_COUNTER (volatile unsigned long *)TIMER8_COUNTER +#define pTIMER8_PERIOD (volatile unsigned long *)TIMER8_PERIOD +#define pTIMER8_WIDTH (volatile unsigned long *)TIMER8_WIDTH +#define pTIMER9_CONFIG (volatile unsigned short *)TIMER9_CONFIG +#define pTIMER9_COUNTER (volatile unsigned long *)TIMER9_COUNTER +#define pTIMER9_PERIOD (volatile unsigned long *)TIMER9_PERIOD +#define pTIMER9_WIDTH (volatile unsigned long *)TIMER9_WIDTH +#define pTIMER10_CONFIG (volatile unsigned short *)TIMER10_CONFIG +#define pTIMER10_COUNTER (volatile unsigned long *)TIMER10_COUNTER +#define pTIMER10_PERIOD (volatile unsigned long *)TIMER10_PERIOD +#define pTIMER10_WIDTH (volatile unsigned long *)TIMER10_WIDTH +#define pTIMER11_CONFIG (volatile unsigned short *)TIMER11_CONFIG +#define pTIMER11_COUNTER (volatile unsigned long *)TIMER11_COUNTER +#define pTIMER11_PERIOD (volatile unsigned long *)TIMER11_PERIOD +#define pTIMER11_WIDTH (volatile unsigned long *)TIMER11_WIDTH +#define pTMRS4_ENABLE (volatile unsigned short *)TMRS4_ENABLE +#define pTMRS4_DISABLE (volatile unsigned short *)TMRS4_DISABLE +#define pTMRS4_STATUS (volatile unsigned long *)TMRS4_STATUS + +/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ +#define pFIO0_FLAG_D (volatile unsigned short *)FIO0_FLAG_D +#define pFIO0_FLAG_C (volatile unsigned short *)FIO0_FLAG_C +#define pFIO0_FLAG_S (volatile unsigned short *)FIO0_FLAG_S +#define pFIO0_FLAG_T (volatile unsigned short *)FIO0_FLAG_T +#define pFIO0_MASKA_D (volatile unsigned short *)FIO0_MASKA_D +#define pFIO0_MASKA_C (volatile unsigned short *)FIO0_MASKA_C +#define pFIO0_MASKA_S (volatile unsigned short *)FIO0_MASKA_S +#define pFIO0_MASKA_T (volatile unsigned short *)FIO0_MASKA_T +#define pFIO0_MASKB_D (volatile unsigned short *)FIO0_MASKB_D +#define pFIO0_MASKB_C (volatile unsigned short *)FIO0_MASKB_C +#define pFIO0_MASKB_S (volatile unsigned short *)FIO0_MASKB_S +#define pFIO0_MASKB_T (volatile unsigned short *)FIO0_MASKB_T +#define pFIO0_DIR (volatile unsigned short *)FIO0_DIR +#define pFIO0_POLAR (volatile unsigned short *)FIO0_POLAR +#define pFIO0_EDGE (volatile unsigned short *)FIO0_EDGE +#define pFIO0_BOTH (volatile unsigned short *)FIO0_BOTH +#define pFIO0_INEN (volatile unsigned short *)FIO0_INEN + +/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */ +#define pFIO1_FLAG_D (volatile unsigned short *)FIO1_FLAG_D +#define pFIO1_FLAG_C (volatile unsigned short *)FIO1_FLAG_C +#define pFIO1_FLAG_S (volatile unsigned short *)FIO1_FLAG_S +#define pFIO1_FLAG_T (volatile unsigned short *)FIO1_FLAG_T +#define pFIO1_MASKA_D (volatile unsigned short *)FIO1_MASKA_D +#define pFIO1_MASKA_C (volatile unsigned short *)FIO1_MASKA_C +#define pFIO1_MASKA_S (volatile unsigned short *)FIO1_MASKA_S +#define pFIO1_MASKA_T (volatile unsigned short *)FIO1_MASKA_T +#define pFIO1_MASKB_D (volatile unsigned short *)FIO1_MASKB_D +#define pFIO1_MASKB_C (volatile unsigned short *)FIO1_MASKB_C +#define pFIO1_MASKB_S (volatile unsigned short *)FIO1_MASKB_S +#define pFIO1_MASKB_T (volatile unsigned short *)FIO1_MASKB_T +#define pFIO1_DIR (volatile unsigned short *)FIO1_DIR +#define pFIO1_POLAR (volatile unsigned short *)FIO1_POLAR +#define pFIO1_EDGE (volatile unsigned short *)FIO1_EDGE +#define pFIO1_BOTH (volatile unsigned short *)FIO1_BOTH +#define pFIO1_INEN (volatile unsigned short *)FIO1_INEN + +/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */ +#define pFIO2_FLAG_D (volatile unsigned short *)FIO2_FLAG_D +#define pFIO2_FLAG_C (volatile unsigned short *)FIO2_FLAG_C +#define pFIO2_FLAG_S (volatile unsigned short *)FIO2_FLAG_S +#define pFIO2_FLAG_T (volatile unsigned short *)FIO2_FLAG_T +#define pFIO2_MASKA_D (volatile unsigned short *)FIO2_MASKA_D +#define pFIO2_MASKA_C (volatile unsigned short *)FIO2_MASKA_C +#define pFIO2_MASKA_S (volatile unsigned short *)FIO2_MASKA_S +#define pFIO2_MASKA_T (volatile unsigned short *)FIO2_MASKA_T +#define pFIO2_MASKB_D (volatile unsigned short *)FIO2_MASKB_D +#define pFIO2_MASKB_C (volatile unsigned short *)FIO2_MASKB_C +#define pFIO2_MASKB_S (volatile unsigned short *)FIO2_MASKB_S +#define pFIO2_MASKB_T (volatile unsigned short *)FIO2_MASKB_T +#define pFIO2_DIR (volatile unsigned short *)FIO2_DIR +#define pFIO2_POLAR (volatile unsigned short *)FIO2_POLAR +#define pFIO2_EDGE (volatile unsigned short *)FIO2_EDGE +#define pFIO2_BOTH (volatile unsigned short *)FIO2_BOTH +#define pFIO2_INEN (volatile unsigned short *)FIO2_INEN + +/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ +#define pSPORT0_TCR1 (volatile unsigned short *)SPORT0_TCR1 +#define pSPORT0_TCR2 (volatile unsigned short *)SPORT0_TCR2 +#define pSPORT0_TCLKDIV (volatile unsigned short *)SPORT0_TCLKDIV +#define pSPORT0_TFSDIV (volatile unsigned short *)SPORT0_TFSDIV +#define pSPORT0_TX (volatile unsigned long *)SPORT0_TX +#define pSPORT0_RX (volatile unsigned long *)SPORT0_RX +#define pSPORT0_TX32 ((volatile long *)SPORT0_TX) +#define pSPORT0_RX32 ((volatile long *)SPORT0_RX) +#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX) +#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX) +#define pSPORT0_RCR1 (volatile unsigned short *)SPORT0_RCR1 +#define pSPORT0_RCR2 (volatile unsigned short *)SPORT0_RCR2 +#define pSPORT0_RCLKDIV (volatile unsigned short *)SPORT0_RCLKDIV +#define pSPORT0_RFSDIV (volatile unsigned short *)SPORT0_RFSDIV +#define pSPORT0_STAT (volatile unsigned short *)SPORT0_STAT +#define pSPORT0_CHNL (volatile unsigned short *)SPORT0_CHNL +#define pSPORT0_MCMC1 (volatile unsigned short *)SPORT0_MCMC1 +#define pSPORT0_MCMC2 (volatile unsigned short *)SPORT0_MCMC2 +#define pSPORT0_MTCS0 (volatile unsigned long *)SPORT0_MTCS0 +#define pSPORT0_MTCS1 (volatile unsigned long *)SPORT0_MTCS1 +#define pSPORT0_MTCS2 (volatile unsigned long *)SPORT0_MTCS2 +#define pSPORT0_MTCS3 (volatile unsigned long *)SPORT0_MTCS3 +#define pSPORT0_MRCS0 (volatile unsigned long *)SPORT0_MRCS0 +#define pSPORT0_MRCS1 (volatile unsigned long *)SPORT0_MRCS1 +#define pSPORT0_MRCS2 (volatile unsigned long *)SPORT0_MRCS2 +#define pSPORT0_MRCS3 (volatile unsigned long *)SPORT0_MRCS3 + +/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ +#define pSPORT1_TCR1 (volatile unsigned short *)SPORT1_TCR1 +#define pSPORT1_TCR2 (volatile unsigned short *)SPORT1_TCR2 +#define pSPORT1_TCLKDIV (volatile unsigned short *)SPORT1_TCLKDIV +#define pSPORT1_TFSDIV (volatile unsigned short *)SPORT1_TFSDIV +#define pSPORT1_TX (volatile unsigned long *)SPORT1_TX +#define pSPORT1_RX (volatile unsigned long *)SPORT1_RX +#define pSPORT1_TX32 ((volatile long *)SPORT1_TX) +#define pSPORT1_RX32 ((volatile long *)SPORT1_RX) +#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX) +#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX) +#define pSPORT1_RCR1 (volatile unsigned short *)SPORT1_RCR1 +#define pSPORT1_RCR2 (volatile unsigned short *)SPORT1_RCR2 +#define pSPORT1_RCLKDIV (volatile unsigned short *)SPORT1_RCLKDIV +#define pSPORT1_RFSDIV (volatile unsigned short *)SPORT1_RFSDIV +#define pSPORT1_STAT (volatile unsigned short *)SPORT1_STAT +#define pSPORT1_CHNL (volatile unsigned short *)SPORT1_CHNL +#define pSPORT1_MCMC1 (volatile unsigned short *)SPORT1_MCMC1 +#define pSPORT1_MCMC2 (volatile unsigned short *)SPORT1_MCMC2 +#define pSPORT1_MTCS0 (volatile unsigned long *)SPORT1_MTCS0 +#define pSPORT1_MTCS1 (volatile unsigned long *)SPORT1_MTCS1 +#define pSPORT1_MTCS2 (volatile unsigned long *)SPORT1_MTCS2 +#define pSPORT1_MTCS3 (volatile unsigned long *)SPORT1_MTCS3 +#define pSPORT1_MRCS0 (volatile unsigned long *)SPORT1_MRCS0 +#define pSPORT1_MRCS1 (volatile unsigned long *)SPORT1_MRCS1 +#define pSPORT1_MRCS2 (volatile unsigned long *)SPORT1_MRCS2 +#define pSPORT1_MRCS3 (volatile unsigned long *)SPORT1_MRCS3 + +/* Asynchronous Memory Controller - External Bus Interface Unit */ +#define pEBIU_AMGCTL (volatile unsigned short *)EBIU_AMGCTL +#define pEBIU_AMBCTL0 (volatile unsigned long *)EBIU_AMBCTL0 +#define pEBIU_AMBCTL1 (volatile unsigned long *)EBIU_AMBCTL1 + +/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ +#define pEBIU_SDGCTL (volatile unsigned long *)EBIU_SDGCTL +#define pEBIU_SDBCTL (volatile unsigned long *)EBIU_SDBCTL +#define pEBIU_SDRRC (volatile unsigned short *)EBIU_SDRRC +#define pEBIU_SDSTAT (volatile unsigned short *)EBIU_SDSTAT + +/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)*/ +#define pPPI0_CONTROL (volatile unsigned short *)PPI0_CONTROL +#define pPPI0_STATUS (volatile unsigned short *)PPI0_STATUS +#define pPPI0_COUNT (volatile unsigned short *)PPI0_COUNT +#define pPPI0_DELAY (volatile unsigned short *)PPI0_DELAY +#define pPPI0_FRAME (volatile unsigned short *)PPI0_FRAME + +/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF)*/ +#define pPPI1_CONTROL (volatile unsigned short *)PPI1_CONTROL +#define pPPI1_STATUS (volatile unsigned short *)PPI1_STATUS +#define pPPI1_COUNT (volatile unsigned short *)PPI1_COUNT +#define pPPI1_DELAY (volatile unsigned short *)PPI1_DELAY +#define pPPI1_FRAME (volatile unsigned short *)PPI1_FRAME + +/*DMA Traffic controls*/ +#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER) +#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT) +#define pDMA_TC_PER ((volatile unsigned short *)DMA_TC_PER) +#define pDMA_TC_CNT ((volatile unsigned short *)DMA_TC_CNT) + +/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ +#define pDMA1_0_CONFIG (volatile unsigned short *)DMA1_0_CONFIG +#define pDMA1_0_NEXT_DESC_PTR (volatile void **)DMA1_0_NEXT_DESC_PTR +#define pDMA1_0_START_ADDR (volatile void **)DMA1_0_START_ADDR +#define pDMA1_0_X_COUNT (volatile unsigned short *)DMA1_0_X_COUNT +#define pDMA1_0_Y_COUNT (volatile unsigned short *)DMA1_0_Y_COUNT +#define pDMA1_0_X_MODIFY (volatile unsigned short *)DMA1_0_X_MODIFY +#define pDMA1_0_Y_MODIFY (volatile unsigned short *)DMA1_0_Y_MODIFY +#define pDMA1_0_CURR_DESC_PTR (volatile void **)DMA1_0_CURR_DESC_PTR +#define pDMA1_0_CURR_ADDR (volatile void **)DMA1_0_CURR_ADDR +#define pDMA1_0_CURR_X_COUNT (volatile unsigned short *)DMA1_0_CURR_X_COUNT +#define pDMA1_0_CURR_Y_COUNT (volatile unsigned short *)DMA1_0_CURR_Y_COUNT +#define pDMA1_0_IRQ_STATUS (volatile unsigned short *)DMA1_0_IRQ_STATUS +#define pDMA1_0_PERIPHERAL_MAP (volatile unsigned short *)DMA1_0_PERIPHERAL_MAP +#define pDMA1_1_CONFIG (volatile unsigned short *)DMA1_1_CONFIG +#define pDMA1_1_NEXT_DESC_PTR (volatile void **)DMA1_1_NEXT_DESC_PTR +#define pDMA1_1_START_ADDR (volatile void **)DMA1_1_START_ADDR +#define pDMA1_1_X_COUNT (volatile unsigned short *)DMA1_1_X_COUNT +#define pDMA1_1_Y_COUNT (volatile unsigned short *)DMA1_1_Y_COUNT +#define pDMA1_1_X_MODIFY (volatile unsigned short *)DMA1_1_X_MODIFY +#define pDMA1_1_Y_MODIFY (volatile unsigned short *)DMA1_1_Y_MODIFY +#define pDMA1_1_CURR_DESC_PTR (volatile void **)DMA1_1_CURR_DESC_PTR +#define pDMA1_1_CURR_ADDR (volatile void **)DMA1_1_CURR_ADDR +#define pDMA1_1_CURR_X_COUNT (volatile unsigned short *)DMA1_1_CURR_X_COUNT +#define pDMA1_1_CURR_Y_COUNT (volatile unsigned short *)DMA1_1_CURR_Y_COUNT +#define pDMA1_1_IRQ_STATUS (volatile unsigned short *)DMA1_1_IRQ_STATUS +#define pDMA1_1_PERIPHERAL_MAP (volatile unsigned short *)DMA1_1_PERIPHERAL_MAP +#define pDMA1_2_CONFIG (volatile unsigned short *)DMA1_2_CONFIG +#define pDMA1_2_NEXT_DESC_PTR (volatile void **)DMA1_2_NEXT_DESC_PTR +#define pDMA1_2_START_ADDR (volatile void **)DMA1_2_START_ADDR +#define pDMA1_2_X_COUNT (volatile unsigned short *)DMA1_2_X_COUNT +#define pDMA1_2_Y_COUNT (volatile unsigned short *)DMA1_2_Y_COUNT +#define pDMA1_2_X_MODIFY (volatile unsigned short *)DMA1_2_X_MODIFY +#define pDMA1_2_Y_MODIFY (volatile unsigned short *)DMA1_2_Y_MODIFY +#define pDMA1_2_CURR_DESC_PTR (volatile void **)DMA1_2_CURR_DESC_PTR +#define pDMA1_2_CURR_ADDR (volatile void **)DMA1_2_CURR_ADDR +#define pDMA1_2_CURR_X_COUNT (volatile unsigned short *)DMA1_2_CURR_X_COUNT +#define pDMA1_2_CURR_Y_COUNT (volatile unsigned short *)DMA1_2_CURR_Y_COUNT +#define pDMA1_2_IRQ_STATUS (volatile unsigned short *)DMA1_2_IRQ_STATUS +#define pDMA1_2_PERIPHERAL_MAP (volatile unsigned short *)DMA1_2_PERIPHERAL_MAP +#define pDMA1_3_CONFIG (volatile unsigned short *)DMA1_3_CONFIG +#define pDMA1_3_NEXT_DESC_PTR (volatile void **)DMA1_3_NEXT_DESC_PTR +#define pDMA1_3_START_ADDR (volatile void **)DMA1_3_START_ADDR +#define pDMA1_3_X_COUNT (volatile unsigned short *)DMA1_3_X_COUNT +#define pDMA1_3_Y_COUNT (volatile unsigned short *)DMA1_3_Y_COUNT +#define pDMA1_3_X_MODIFY (volatile unsigned short *)DMA1_3_X_MODIFY +#define pDMA1_3_Y_MODIFY (volatile unsigned short *)DMA1_3_Y_MODIFY +#define pDMA1_3_CURR_DESC_PTR (volatile void **)DMA1_3_CURR_DESC_PTR +#define pDMA1_3_CURR_ADDR (volatile void **)DMA1_3_CURR_ADDR +#define pDMA1_3_CURR_X_COUNT (volatile unsigned short *)DMA1_3_CURR_X_COUNT +#define pDMA1_3_CURR_Y_COUNT (volatile unsigned short *)DMA1_3_CURR_Y_COUNT +#define pDMA1_3_IRQ_STATUS (volatile unsigned short *)DMA1_3_IRQ_STATUS +#define pDMA1_3_PERIPHERAL_MAP (volatile unsigned short *)DMA1_3_PERIPHERAL_MAP +#define pDMA1_4_CONFIG (volatile unsigned short *)DMA1_4_CONFIG +#define pDMA1_4_NEXT_DESC_PTR (volatile void **)DMA1_4_NEXT_DESC_PTR +#define pDMA1_4_START_ADDR (volatile void **)DMA1_4_START_ADDR +#define pDMA1_4_X_COUNT (volatile unsigned short *)DMA1_4_X_COUNT +#define pDMA1_4_Y_COUNT (volatile unsigned short *)DMA1_4_Y_COUNT +#define pDMA1_4_X_MODIFY (volatile unsigned short *)DMA1_4_X_MODIFY +#define pDMA1_4_Y_MODIFY (volatile unsigned short *)DMA1_4_Y_MODIFY +#define pDMA1_4_CURR_DESC_PTR (volatile void **)DMA1_4_CURR_DESC_PTR +#define pDMA1_4_CURR_ADDR (volatile void **)DMA1_4_CURR_ADDR +#define pDMA1_4_CURR_X_COUNT (volatile unsigned short *)DMA1_4_CURR_X_COUNT +#define pDMA1_4_CURR_Y_COUNT (volatile unsigned short *)DMA1_4_CURR_Y_COUNT +#define pDMA1_4_IRQ_STATUS (volatile unsigned short *)DMA1_4_IRQ_STATUS +#define pDMA1_4_PERIPHERAL_MAP (volatile unsigned short *)DMA1_4_PERIPHERAL_MAP +#define pDMA1_5_CONFIG (volatile unsigned short *)DMA1_5_CONFIG +#define pDMA1_5_NEXT_DESC_PTR (volatile void **)DMA1_5_NEXT_DESC_PTR +#define pDMA1_5_START_ADDR (volatile void **)DMA1_5_START_ADDR +#define pDMA1_5_X_COUNT (volatile unsigned short *)DMA1_5_X_COUNT +#define pDMA1_5_Y_COUNT (volatile unsigned short *)DMA1_5_Y_COUNT +#define pDMA1_5_X_MODIFY (volatile unsigned short *)DMA1_5_X_MODIFY +#define pDMA1_5_Y_MODIFY (volatile unsigned short *)DMA1_5_Y_MODIFY +#define pDMA1_5_CURR_DESC_PTR (volatile void **)DMA1_5_CURR_DESC_PTR +#define pDMA1_5_CURR_ADDR (volatile void **)DMA1_5_CURR_ADDR +#define pDMA1_5_CURR_X_COUNT (volatile unsigned short *)DMA1_5_CURR_X_COUNT +#define pDMA1_5_CURR_Y_COUNT (volatile unsigned short *)DMA1_5_CURR_Y_COUNT +#define pDMA1_5_IRQ_STATUS (volatile unsigned short *)DMA1_5_IRQ_STATUS +#define pDMA1_5_PERIPHERAL_MAP (volatile unsigned short *)DMA1_5_PERIPHERAL_MAP +#define pDMA1_6_CONFIG (volatile unsigned short *)DMA1_6_CONFIG +#define pDMA1_6_NEXT_DESC_PTR (volatile void **)DMA1_6_NEXT_DESC_PTR +#define pDMA1_6_START_ADDR (volatile void **)DMA1_6_START_ADDR +#define pDMA1_6_X_COUNT (volatile unsigned short *)DMA1_6_X_COUNT +#define pDMA1_6_Y_COUNT (volatile unsigned short *)DMA1_6_Y_COUNT +#define pDMA1_6_X_MODIFY (volatile unsigned short *)DMA1_6_X_MODIFY +#define pDMA1_6_Y_MODIFY (volatile unsigned short *)DMA1_6_Y_MODIFY +#define pDMA1_6_CURR_DESC_PTR (volatile void **)DMA1_6_CURR_DESC_PTR +#define pDMA1_6_CURR_ADDR (volatile void **)DMA1_6_CURR_ADDR +#define pDMA1_6_CURR_X_COUNT (volatile unsigned short *)DMA1_6_CURR_X_COUNT +#define pDMA1_6_CURR_Y_COUNT (volatile unsigned short *)DMA1_6_CURR_Y_COUNT +#define pDMA1_6_IRQ_STATUS (volatile unsigned short *)DMA1_6_IRQ_STATUS +#define pDMA1_6_PERIPHERAL_MAP (volatile unsigned short *)DMA1_6_PERIPHERAL_MAP +#define pDMA1_7_CONFIG (volatile unsigned short *)DMA1_7_CONFIG +#define pDMA1_7_NEXT_DESC_PTR (volatile void **)DMA1_7_NEXT_DESC_PTR +#define pDMA1_7_START_ADDR (volatile void **)DMA1_7_START_ADDR +#define pDMA1_7_X_COUNT (volatile unsigned short *)DMA1_7_X_COUNT +#define pDMA1_7_Y_COUNT (volatile unsigned short *)DMA1_7_Y_COUNT +#define pDMA1_7_X_MODIFY (volatile unsigned short *)DMA1_7_X_MODIFY +#define pDMA1_7_Y_MODIFY (volatile unsigned short *)DMA1_7_Y_MODIFY +#define pDMA1_7_CURR_DESC_PTR (volatile void **)DMA1_7_CURR_DESC_PTR +#define pDMA1_7_CURR_ADDR (volatile void **)DMA1_7_CURR_ADDR +#define pDMA1_7_CURR_X_COUNT (volatile unsigned short *)DMA1_7_CURR_X_COUNT +#define pDMA1_7_CURR_Y_COUNT (volatile unsigned short *)DMA1_7_CURR_Y_COUNT +#define pDMA1_7_IRQ_STATUS (volatile unsigned short *)DMA1_7_IRQ_STATUS +#define pDMA1_7_PERIPHERAL_MAP (volatile unsigned short *)DMA1_7_PERIPHERAL_MAP +#define pDMA1_8_CONFIG (volatile unsigned short *)DMA1_8_CONFIG +#define pDMA1_8_NEXT_DESC_PTR (volatile void **)DMA1_8_NEXT_DESC_PTR +#define pDMA1_8_START_ADDR (volatile void **)DMA1_8_START_ADDR +#define pDMA1_8_X_COUNT (volatile unsigned short *)DMA1_8_X_COUNT +#define pDMA1_8_Y_COUNT (volatile unsigned short *)DMA1_8_Y_COUNT +#define pDMA1_8_X_MODIFY (volatile unsigned short *)DMA1_8_X_MODIFY +#define pDMA1_8_Y_MODIFY (volatile unsigned short *)DMA1_8_Y_MODIFY +#define pDMA1_8_CURR_DESC_PTR (volatile void **)DMA1_8_CURR_DESC_PTR +#define pDMA1_8_CURR_ADDR (volatile void **)DMA1_8_CURR_ADDR +#define pDMA1_8_CURR_X_COUNT (volatile unsigned short *)DMA1_8_CURR_X_COUNT +#define pDMA1_8_CURR_Y_COUNT (volatile unsigned short *)DMA1_8_CURR_Y_COUNT +#define pDMA1_8_IRQ_STATUS (volatile unsigned short *)DMA1_8_IRQ_STATUS +#define pDMA1_8_PERIPHERAL_MAP (volatile unsigned short *)DMA1_8_PERIPHERAL_MAP +#define pDMA1_9_CONFIG (volatile unsigned short *)DMA1_9_CONFIG +#define pDMA1_9_NEXT_DESC_PTR (volatile void **)DMA1_9_NEXT_DESC_PTR +#define pDMA1_9_START_ADDR (volatile void **)DMA1_9_START_ADDR +#define pDMA1_9_X_COUNT (volatile unsigned short *)DMA1_9_X_COUNT +#define pDMA1_9_Y_COUNT (volatile unsigned short *)DMA1_9_Y_COUNT +#define pDMA1_9_X_MODIFY (volatile unsigned short *)DMA1_9_X_MODIFY +#define pDMA1_9_Y_MODIFY (volatile unsigned short *)DMA1_9_Y_MODIFY +#define pDMA1_9_CURR_DESC_PTR (volatile void **)DMA1_9_CURR_DESC_PTR +#define pDMA1_9_CURR_ADDR (volatile void **)DMA1_9_CURR_ADDR +#define pDMA1_9_CURR_X_COUNT (volatile unsigned short *)DMA1_9_CURR_X_COUNT +#define pDMA1_9_CURR_Y_COUNT (volatile unsigned short *)DMA1_9_CURR_Y_COUNT +#define pDMA1_9_IRQ_STATUS (volatile unsigned short *)DMA1_9_IRQ_STATUS +#define pDMA1_9_PERIPHERAL_MAP (volatile unsigned short *)DMA1_9_PERIPHERAL_MAP +#define pDMA1_10_CONFIG (volatile unsigned short *)DMA1_10_CONFIG +#define pDMA1_10_NEXT_DESC_PTR (volatile void **)DMA1_10_NEXT_DESC_PTR +#define pDMA1_10_START_ADDR (volatile void **)DMA1_10_START_ADDR +#define pDMA1_10_X_COUNT (volatile unsigned short *)DMA1_10_X_COUNT +#define pDMA1_10_Y_COUNT (volatile unsigned short *)DMA1_10_Y_COUNT +#define pDMA1_10_X_MODIFY (volatile unsigned short *)DMA1_10_X_MODIFY +#define pDMA1_10_Y_MODIFY (volatile unsigned short *)DMA1_10_Y_MODIFY +#define pDMA1_10_CURR_DESC_PTR (volatile void **)DMA1_10_CURR_DESC_PTR +#define pDMA1_10_CURR_ADDR (volatile void **)DMA1_10_CURR_ADDR +#define pDMA1_10_CURR_X_COUNT (volatile unsigned short *)DMA1_10_CURR_X_COUNT +#define pDMA1_10_CURR_Y_COUNT (volatile unsigned short *)DMA1_10_CURR_Y_COUNT +#define pDMA1_10_IRQ_STATUS (volatile unsigned short *)DMA1_10_IRQ_STATUS +#define pDMA1_10_PERIPHERAL_MAP (volatile unsigned short *)DMA1_10_PERIPHERAL_MAP +#define pDMA1_11_CONFIG (volatile unsigned short *)DMA1_11_CONFIG +#define pDMA1_11_NEXT_DESC_PTR (volatile void **)DMA1_11_NEXT_DESC_PTR +#define pDMA1_11_START_ADDR (volatile void **)DMA1_11_START_ADDR +#define pDMA1_11_X_COUNT (volatile unsigned short *)DMA1_11_X_COUNT +#define pDMA1_11_Y_COUNT (volatile unsigned short *)DMA1_11_Y_COUNT +#define pDMA1_11_X_MODIFY (volatile signed short *)DMA1_11_X_MODIFY +#define pDMA1_11_Y_MODIFY (volatile signed short *)DMA1_11_Y_MODIFY +#define pDMA1_11_CURR_DESC_PTR (volatile void **)DMA1_11_CURR_DESC_PTR +#define pDMA1_11_CURR_ADDR (volatile void **)DMA1_11_CURR_ADDR +#define pDMA1_11_CURR_X_COUNT (volatile unsigned short *)DMA1_11_CURR_X_COUNT +#define pDMA1_11_CURR_Y_COUNT (volatile unsigned short *)DMA1_11_CURR_Y_COUNT +#define pDMA1_11_IRQ_STATUS (volatile unsigned short *)DMA1_11_IRQ_STATUS +#define pDMA1_11_PERIPHERAL_MAP (volatile unsigned short *)DMA1_11_PERIPHERAL_MAP + +/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF)*/ +#define pMDMA1_D0_CONFIG (volatile unsigned short *)MDMA1_D0_CONFIG +#define pMDMA1_D0_NEXT_DESC_PTR (volatile void **)MDMA1_D0_NEXT_DESC_PTR +#define pMDMA1_D0_START_ADDR (volatile void **)MDMA1_D0_START_ADDR +#define pMDMA1_D0_X_COUNT (volatile unsigned short *)MDMA1_D0_X_COUNT +#define pMDMA1_D0_Y_COUNT (volatile unsigned short *)MDMA1_D0_Y_COUNT +#define pMDMA1_D0_X_MODIFY (volatile signed short *)MDMA1_D0_X_MODIFY +#define pMDMA1_D0_Y_MODIFY (volatile signed short *)MDMA1_D0_Y_MODIFY +#define pMDMA1_D0_CURR_DESC_PTR (volatile void **)MDMA1_D0_CURR_DESC_PTR +#define pMDMA1_D0_CURR_ADDR (volatile void **)MDMA1_D0_CURR_ADDR +#define pMDMA1_D0_CURR_X_COUNT (volatile unsigned short *)MDMA1_D0_CURR_X_COUNT +#define pMDMA1_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT +#define pMDMA1_D0_IRQ_STATUS (volatile unsigned short *)MDMA1_D0_IRQ_STATUS +#define pMDMA1_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP +#define pMDMA1_S0_CONFIG (volatile unsigned short *)MDMA1_S0_CONFIG +#define pMDMA1_S0_NEXT_DESC_PTR (volatile void **)MDMA1_S0_NEXT_DESC_PTR +#define pMDMA1_S0_START_ADDR (volatile void **)MDMA1_S0_START_ADDR +#define pMDMA1_S0_X_COUNT (volatile unsigned short *)MDMA1_S0_X_COUNT +#define pMDMA1_S0_Y_COUNT (volatile unsigned short *)MDMA1_S0_Y_COUNT +#define pMDMA1_S0_X_MODIFY (volatile signed short *)MDMA1_S0_X_MODIFY +#define pMDMA1_S0_Y_MODIFY (volatile signed short *)MDMA1_S0_Y_MODIFY +#define pMDMA1_S0_CURR_DESC_PTR (volatile void **)MDMA1_S0_CURR_DESC_PTR +#define pMDMA1_S0_CURR_ADDR (volatile void **)MDMA1_S0_CURR_ADDR +#define pMDMA1_S0_CURR_X_COUNT (volatile unsigned short *)MDMA1_S0_CURR_X_COUNT +#define pMDMA1_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT +#define pMDMA1_S0_IRQ_STATUS (volatile unsigned short *)MDMA1_S0_IRQ_STATUS +#define pMDMA1_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP +#define pMDMA1_D1_CONFIG (volatile unsigned short *)MDMA1_D1_CONFIG +#define pMDMA1_D1_NEXT_DESC_PTR (volatile void **)MDMA1_D1_NEXT_DESC_PTR +#define pMDMA1_D1_START_ADDR (volatile void **)MDMA1_D1_START_ADDR +#define pMDMA1_D1_X_COUNT (volatile unsigned short *)MDMA1_D1_X_COUNT +#define pMDMA1_D1_Y_COUNT (volatile unsigned short *)MDMA1_D1_Y_COUNT +#define pMDMA1_D1_X_MODIFY (volatile signed short *)MDMA1_D1_X_MODIFY +#define pMDMA1_D1_Y_MODIFY (volatile signed short *)MDMA1_D1_Y_MODIFY +#define pMDMA1_D1_CURR_DESC_PTR (volatile void **)MDMA1_D1_CURR_DESC_PTR +#define pMDMA1_D1_CURR_ADDR (volatile void **)MDMA1_D1_CURR_ADDR +#define pMDMA1_D1_CURR_X_COUNT (volatile unsigned short *)MDMA1_D1_CURR_X_COUNT +#define pMDMA1_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT +#define pMDMA1_D1_IRQ_STATUS (volatile unsigned short *)MDMA1_D1_IRQ_STATUS +#define pMDMA1_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP +#define pMDMA1_S1_CONFIG (volatile unsigned short *)MDMA1_S1_CONFIG +#define pMDMA1_S1_NEXT_DESC_PTR (volatile void **)MDMA1_S1_NEXT_DESC_PTR +#define pMDMA1_S1_START_ADDR (volatile void **)MDMA1_S1_START_ADDR +#define pMDMA1_S1_X_COUNT (volatile unsigned short *)MDMA1_S1_X_COUNT +#define pMDMA1_S1_Y_COUNT (volatile unsigned short *)MDMA1_S1_Y_COUNT +#define pMDMA1_S1_X_MODIFY (volatile signed short *)MDMA1_S1_X_MODIFY +#define pMDMA1_S1_Y_MODIFY (volatile signed short *)MDMA1_S1_Y_MODIFY +#define pMDMA1_S1_CURR_DESC_PTR (volatile void **)MDMA1_S1_CURR_DESC_PTR +#define pMDMA1_S1_CURR_ADDR (volatile void **)MDMA1_S1_CURR_ADDR +#define pMDMA1_S1_CURR_X_COUNT (volatile unsigned short *)MDMA1_S1_CURR_X_COUNT +#define pMDMA1_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT +#define pMDMA1_S1_IRQ_STATUS (volatile unsigned short *)MDMA1_S1_IRQ_STATUS +#define pMDMA1_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP + +/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ +#define pDMA2_0_CONFIG (volatile unsigned short *)DMA2_0_CONFIG +#define pDMA2_0_NEXT_DESC_PTR (volatile void **)DMA2_0_NEXT_DESC_PTR +#define pDMA2_0_START_ADDR (volatile void **)DMA2_0_START_ADDR +#define pDMA2_0_X_COUNT (volatile unsigned short *)DMA2_0_X_COUNT +#define pDMA2_0_Y_COUNT (volatile unsigned short *)DMA2_0_Y_COUNT +#define pDMA2_0_X_MODIFY (volatile signed short *)DMA2_0_X_MODIFY +#define pDMA2_0_Y_MODIFY (volatile signed short *)DMA2_0_Y_MODIFY +#define pDMA2_0_CURR_DESC_PTR (volatile void **)DMA2_0_CURR_DESC_PTR +#define pDMA2_0_CURR_ADDR (volatile void **)DMA2_0_CURR_ADDR +#define pDMA2_0_CURR_X_COUNT (volatile unsigned short *)DMA2_0_CURR_X_COUNT +#define pDMA2_0_CURR_Y_COUNT (volatile unsigned short *)DMA2_0_CURR_Y_COUNT +#define pDMA2_0_IRQ_STATUS (volatile unsigned short *)DMA2_0_IRQ_STATUS +#define pDMA2_0_PERIPHERAL_MAP (volatile unsigned short *)DMA2_0_PERIPHERAL_MAP +#define pDMA2_1_CONFIG (volatile unsigned short *)DMA2_1_CONFIG +#define pDMA2_1_NEXT_DESC_PTR (volatile void **)DMA2_1_NEXT_DESC_PTR +#define pDMA2_1_START_ADDR (volatile void **)DMA2_1_START_ADDR +#define pDMA2_1_X_COUNT (volatile unsigned short *)DMA2_1_X_COUNT +#define pDMA2_1_Y_COUNT (volatile unsigned short *)DMA2_1_Y_COUNT +#define pDMA2_1_X_MODIFY (volatile signed short *)DMA2_1_X_MODIFY +#define pDMA2_1_Y_MODIFY (volatile signed short *)DMA2_1_Y_MODIFY +#define pDMA2_1_CURR_DESC_PTR (volatile void **)DMA2_1_CURR_DESC_PTR +#define pDMA2_1_CURR_ADDR (volatile void **)DMA2_1_CURR_ADDR +#define pDMA2_1_CURR_X_COUNT (volatile unsigned short *)DMA2_1_CURR_X_COUNT +#define pDMA2_1_CURR_Y_COUNT (volatile unsigned short *)DMA2_1_CURR_Y_COUNT +#define pDMA2_1_IRQ_STATUS (volatile unsigned short *)DMA2_1_IRQ_STATUS +#define pDMA2_1_PERIPHERAL_MAP (volatile unsigned short *)DMA2_1_PERIPHERAL_MAP +#define pDMA2_2_CONFIG (volatile unsigned short *)DMA2_2_CONFIG +#define pDMA2_2_NEXT_DESC_PTR (volatile void **)DMA2_2_NEXT_DESC_PTR +#define pDMA2_2_START_ADDR (volatile void **)DMA2_2_START_ADDR +#define pDMA2_2_X_COUNT (volatile unsigned short *)DMA2_2_X_COUNT +#define pDMA2_2_Y_COUNT (volatile unsigned short *)DMA2_2_Y_COUNT +#define pDMA2_2_X_MODIFY (volatile signed short *)DMA2_2_X_MODIFY +#define pDMA2_2_Y_MODIFY (volatile signed short *)DMA2_2_Y_MODIFY +#define pDMA2_2_CURR_DESC_PTR (volatile void **)DMA2_2_CURR_DESC_PTR +#define pDMA2_2_CURR_ADDR (volatile void **)DMA2_2_CURR_ADDR +#define pDMA2_2_CURR_X_COUNT (volatile unsigned short *)DMA2_2_CURR_X_COUNT +#define pDMA2_2_CURR_Y_COUNT (volatile unsigned short *)DMA2_2_CURR_Y_COUNT +#define pDMA2_2_IRQ_STATUS (volatile unsigned short *)DMA2_2_IRQ_STATUS +#define pDMA2_2_PERIPHERAL_MAP (volatile unsigned short *)DMA2_2_PERIPHERAL_MAP +#define pDMA2_3_CONFIG (volatile unsigned short *)DMA2_3_CONFIG +#define pDMA2_3_NEXT_DESC_PTR (volatile void **)DMA2_3_NEXT_DESC_PTR +#define pDMA2_3_START_ADDR (volatile void **)DMA2_3_START_ADDR +#define pDMA2_3_X_COUNT (volatile unsigned short *)DMA2_3_X_COUNT +#define pDMA2_3_Y_COUNT (volatile unsigned short *)DMA2_3_Y_COUNT +#define pDMA2_3_X_MODIFY (volatile signed short *)DMA2_3_X_MODIFY +#define pDMA2_3_Y_MODIFY (volatile signed short *)DMA2_3_Y_MODIFY +#define pDMA2_3_CURR_DESC_PTR (volatile void **)DMA2_3_CURR_DESC_PTR +#define pDMA2_3_CURR_ADDR (volatile void **)DMA2_3_CURR_ADDR +#define pDMA2_3_CURR_X_COUNT (volatile unsigned short *)DMA2_3_CURR_X_COUNT +#define pDMA2_3_CURR_Y_COUNT (volatile unsigned short *)DMA2_3_CURR_Y_COUNT +#define pDMA2_3_IRQ_STATUS (volatile unsigned short *)DMA2_3_IRQ_STATUS +#define pDMA2_3_PERIPHERAL_MAP (volatile unsigned short *)DMA2_3_PERIPHERAL_MAP +#define pDMA2_4_CONFIG (volatile unsigned short *)DMA2_4_CONFIG +#define pDMA2_4_NEXT_DESC_PTR (volatile void **)DMA2_4_NEXT_DESC_PTR +#define pDMA2_4_START_ADDR (volatile void **)DMA2_4_START_ADDR +#define pDMA2_4_X_COUNT (volatile unsigned short *)DMA2_4_X_COUNT +#define pDMA2_4_Y_COUNT (volatile unsigned short *)DMA2_4_Y_COUNT +#define pDMA2_4_X_MODIFY (volatile signed short *)DMA2_4_X_MODIFY +#define pDMA2_4_Y_MODIFY (volatile signed short *)DMA2_4_Y_MODIFY +#define pDMA2_4_CURR_DESC_PTR (volatile void **)DMA2_4_CURR_DESC_PTR +#define pDMA2_4_CURR_ADDR (volatile void **)DMA2_4_CURR_ADDR +#define pDMA2_4_CURR_X_COUNT (volatile unsigned short *)DMA2_4_CURR_X_COUNT +#define pDMA2_4_CURR_Y_COUNT (volatile unsigned short *)DMA2_4_CURR_Y_COUNT +#define pDMA2_4_IRQ_STATUS (volatile unsigned short *)DMA2_4_IRQ_STATUS +#define pDMA2_4_PERIPHERAL_MAP (volatile unsigned short *)DMA2_4_PERIPHERAL_MAP +#define pDMA2_5_CONFIG (volatile unsigned short *)DMA2_5_CONFIG +#define pDMA2_5_NEXT_DESC_PTR (volatile void **)DMA2_5_NEXT_DESC_PTR +#define pDMA2_5_START_ADDR (volatile void **)DMA2_5_START_ADDR +#define pDMA2_5_X_COUNT (volatile unsigned short *)DMA2_5_X_COUNT +#define pDMA2_5_Y_COUNT (volatile unsigned short *)DMA2_5_Y_COUNT +#define pDMA2_5_X_MODIFY (volatile signed short *)DMA2_5_X_MODIFY +#define pDMA2_5_Y_MODIFY (volatile signed short *)DMA2_5_Y_MODIFY +#define pDMA2_5_CURR_DESC_PTR (volatile void **)DMA2_5_CURR_DESC_PTR +#define pDMA2_5_CURR_ADDR (volatile void **)DMA2_5_CURR_ADDR +#define pDMA2_5_CURR_X_COUNT (volatile unsigned short *)DMA2_5_CURR_X_COUNT +#define pDMA2_5_CURR_Y_COUNT (volatile unsigned short *)DMA2_5_CURR_Y_COUNT +#define pDMA2_5_IRQ_STATUS (volatile unsigned short *)DMA2_5_IRQ_STATUS +#define pDMA2_5_PERIPHERAL_MAP (volatile unsigned short *)DMA2_5_PERIPHERAL_MAP +#define pDMA2_6_CONFIG (volatile unsigned short *)DMA2_6_CONFIG +#define pDMA2_6_NEXT_DESC_PTR (volatile void **)DMA2_6_NEXT_DESC_PTR +#define pDMA2_6_START_ADDR (volatile void **)DMA2_6_START_ADDR +#define pDMA2_6_X_COUNT (volatile unsigned short *)DMA2_6_X_COUNT +#define pDMA2_6_Y_COUNT (volatile unsigned short *)DMA2_6_Y_COUNT +#define pDMA2_6_X_MODIFY (volatile signed short *)DMA2_6_X_MODIFY +#define pDMA2_6_Y_MODIFY (volatile signed short *)DMA2_6_Y_MODIFY +#define pDMA2_6_CURR_DESC_PTR (volatile void **)DMA2_6_CURR_DESC_PTR +#define pDMA2_6_CURR_ADDR (volatile void **)DMA2_6_CURR_ADDR +#define pDMA2_6_CURR_X_COUNT (volatile unsigned short *)DMA2_6_CURR_X_COUNT +#define pDMA2_6_CURR_Y_COUNT (volatile unsigned short *)DMA2_6_CURR_Y_COUNT +#define pDMA2_6_IRQ_STATUS (volatile unsigned short *)DMA2_6_IRQ_STATUS +#define pDMA2_6_PERIPHERAL_MAP (volatile unsigned short *)DMA2_6_PERIPHERAL_MAP +#define pDMA2_7_CONFIG (volatile unsigned short *)DMA2_7_CONFIG +#define pDMA2_7_NEXT_DESC_PTR (volatile void **)DMA2_7_NEXT_DESC_PTR +#define pDMA2_7_START_ADDR (volatile void **)DMA2_7_START_ADDR +#define pDMA2_7_X_COUNT (volatile unsigned short *)DMA2_7_X_COUNT +#define pDMA2_7_Y_COUNT (volatile unsigned short *)DMA2_7_Y_COUNT +#define pDMA2_7_X_MODIFY (volatile signed short *)DMA2_7_X_MODIFY +#define pDMA2_7_Y_MODIFY (volatile signed short *)DMA2_7_Y_MODIFY +#define pDMA2_7_CURR_DESC_PTR (volatile void **)DMA2_7_CURR_DESC_PTR +#define pDMA2_7_CURR_ADDR (volatile void **)DMA2_7_CURR_ADDR +#define pDMA2_7_CURR_X_COUNT (volatile unsigned short *)DMA2_7_CURR_X_COUNT +#define pDMA2_7_CURR_Y_COUNT (volatile unsigned short *)DMA2_7_CURR_Y_COUNT +#define pDMA2_7_IRQ_STATUS (volatile unsigned short *)DMA2_7_IRQ_STATUS +#define pDMA2_7_PERIPHERAL_MAP (volatile unsigned short *)DMA2_7_PERIPHERAL_MAP +#define pDMA2_8_CONFIG (volatile unsigned short *)DMA2_8_CONFIG +#define pDMA2_8_NEXT_DESC_PTR (volatile void **)DMA2_8_NEXT_DESC_PTR +#define pDMA2_8_START_ADDR (volatile void **)DMA2_8_START_ADDR +#define pDMA2_8_X_COUNT (volatile unsigned short *)DMA2_8_X_COUNT +#define pDMA2_8_Y_COUNT (volatile unsigned short *)DMA2_8_Y_COUNT +#define pDMA2_8_X_MODIFY (volatile signed short *)DMA2_8_X_MODIFY +#define pDMA2_8_Y_MODIFY (volatile signed short *)DMA2_8_Y_MODIFY +#define pDMA2_8_CURR_DESC_PTR (volatile void **)DMA2_8_CURR_DESC_PTR +#define pDMA2_8_CURR_ADDR (volatile void **)DMA2_8_CURR_ADDR +#define pDMA2_8_CURR_X_COUNT (volatile unsigned short *)DMA2_8_CURR_X_COUNT +#define pDMA2_8_CURR_Y_COUNT (volatile unsigned short *)DMA2_8_CURR_Y_COUNT +#define pDMA2_8_IRQ_STATUS (volatile unsigned short *)DMA2_8_IRQ_STATUS +#define pDMA2_8_PERIPHERAL_MAP (volatile unsigned short *)DMA2_8_PERIPHERAL_MAP +#define pDMA2_9_CONFIG (volatile unsigned short *)DMA2_9_CONFIG +#define pDMA2_9_NEXT_DESC_PTR (volatile void **)DMA2_9_NEXT_DESC_PTR +#define pDMA2_9_START_ADDR (volatile void **)DMA2_9_START_ADDR +#define pDMA2_9_X_COUNT (volatile unsigned short *)DMA2_9_X_COUNT +#define pDMA2_9_Y_COUNT (volatile unsigned short *)DMA2_9_Y_COUNT +#define pDMA2_9_X_MODIFY (volatile signed short *)DMA2_9_X_MODIFY +#define pDMA2_9_Y_MODIFY (volatile signed short *)DMA2_9_Y_MODIFY +#define pDMA2_9_CURR_DESC_PTR (volatile void **)DMA2_9_CURR_DESC_PTR +#define pDMA2_9_CURR_ADDR (volatile void **)DMA2_9_CURR_ADDR +#define pDMA2_9_CURR_X_COUNT (volatile unsigned short *)DMA2_9_CURR_X_COUNT +#define pDMA2_9_CURR_Y_COUNT (volatile unsigned short *)DMA2_9_CURR_Y_COUNT +#define pDMA2_9_IRQ_STATUS (volatile unsigned short *)DMA2_9_IRQ_STATUS +#define pDMA2_9_PERIPHERAL_MAP (volatile unsigned short *)DMA2_9_PERIPHERAL_MAP +#define pDMA2_10_CONFIG (volatile unsigned short *)DMA2_10_CONFIG +#define pDMA2_10_NEXT_DESC_PTR (volatile void **)DMA2_10_NEXT_DESC_PTR +#define pDMA2_10_START_ADDR (volatile void **)DMA2_10_START_ADDR +#define pDMA2_10_X_COUNT (volatile unsigned short *)DMA2_10_X_COUNT +#define pDMA2_10_Y_COUNT (volatile unsigned short *)DMA2_10_Y_COUNT +#define pDMA2_10_X_MODIFY (volatile signed short *)DMA2_10_X_MODIFY +#define pDMA2_10_Y_MODIFY (volatile signed short *)DMA2_10_Y_MODIFY +#define pDMA2_10_CURR_DESC_PTR (volatile void **)DMA2_10_CURR_DESC_PTR +#define pDMA2_10_CURR_ADDR (volatile void **)DMA2_10_CURR_ADDR +#define pDMA2_10_CURR_X_COUNT (volatile unsigned short *)DMA2_10_CURR_X_COUNT +#define pDMA2_10_CURR_Y_COUNT (volatile unsigned short *)DMA2_10_CURR_Y_COUNT +#define pDMA2_10_IRQ_STATUS (volatile unsigned short *)DMA2_10_IRQ_STATUS +#define pDMA2_10_PERIPHERAL_MAP (volatile unsigned short *)DMA2_10_PERIPHERAL_MAP +#define pDMA2_11_CONFIG (volatile unsigned short *)DMA2_11_CONFIG +#define pDMA2_11_NEXT_DESC_PTR (volatile void **)DMA2_11_NEXT_DESC_PTR +#define pDMA2_11_START_ADDR (volatile void **)DMA2_11_START_ADDR +#define pDMA2_11_X_COUNT (volatile unsigned short *)DMA2_11_X_COUNT +#define pDMA2_11_Y_COUNT (volatile unsigned short *)DMA2_11_Y_COUNT +#define pDMA2_11_X_MODIFY (volatile signed short *)DMA2_11_X_MODIFY +#define pDMA2_11_Y_MODIFY (volatile signed short *)DMA2_11_Y_MODIFY +#define pDMA2_11_CURR_DESC_PTR (volatile void **)DMA2_11_CURR_DESC_PTR +#define pDMA2_11_CURR_ADDR (volatile void **)DMA2_11_CURR_ADDR +#define pDMA2_11_CURR_X_COUNT (volatile unsigned short *)DMA2_11_CURR_X_COUNT +#define pDMA2_11_CURR_Y_COUNT (volatile unsigned short *)DMA2_11_CURR_Y_COUNT +#define pDMA2_11_IRQ_STATUS (volatile unsigned short *)DMA2_11_IRQ_STATUS +#define pDMA2_11_PERIPHERAL_MAP (volatile unsigned short *)DMA2_11_PERIPHERAL_MAP + +/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ +#define pMDMA2_D0_CONFIG (volatile unsigned short *)MDMA2_D0_CONFIG +#define pMDMA2_D0_NEXT_DESC_PTR (volatile void **)MDMA2_D0_NEXT_DESC_PTR +#define pMDMA2_D0_START_ADDR (volatile void **)MDMA2_D0_START_ADDR +#define pMDMA2_D0_X_COUNT (volatile unsigned short *)MDMA2_D0_X_COUNT +#define pMDMA2_D0_Y_COUNT (volatile unsigned short *)MDMA2_D0_Y_COUNT +#define pMDMA2_D0_X_MODIFY (volatile signed short *)MDMA2_D0_X_MODIFY +#define pMDMA2_D0_Y_MODIFY (volatile signed short *)MDMA2_D0_Y_MODIFY +#define pMDMA2_D0_CURR_DESC_PTR (volatile void **)MDMA2_D0_CURR_DESC_PTR +#define pMDMA2_D0_CURR_ADDR (volatile void **)MDMA2_D0_CURR_ADDR +#define pMDMA2_D0_CURR_X_COUNT (volatile unsigned short *)MDMA2_D0_CURR_X_COUNT +#define pMDMA2_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D0_CURR_Y_COUNT +#define pMDMA2_D0_IRQ_STATUS (volatile unsigned short *)MDMA2_D0_IRQ_STATUS +#define pMDMA2_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D0_PERIPHERAL_MAP +#define pMDMA2_S0_CONFIG (volatile unsigned short *)MDMA2_S0_CONFIG +#define pMDMA2_S0_NEXT_DESC_PTR (volatile void **)MDMA2_S0_NEXT_DESC_PTR +#define pMDMA2_S0_START_ADDR (volatile void **)MDMA2_S0_START_ADDR +#define pMDMA2_S0_X_COUNT (volatile unsigned short *)MDMA2_S0_X_COUNT +#define pMDMA2_S0_Y_COUNT (volatile unsigned short *)MDMA2_S0_Y_COUNT +#define pMDMA2_S0_X_MODIFY (volatile signed short *)MDMA2_S0_X_MODIFY +#define pMDMA2_S0_Y_MODIFY (volatile signed short *)MDMA2_S0_Y_MODIFY +#define pMDMA2_S0_CURR_DESC_PTR (volatile void **)MDMA2_S0_CURR_DESC_PTR +#define pMDMA2_S0_CURR_ADDR (volatile void **)MDMA2_S0_CURR_ADDR +#define pMDMA2_S0_CURR_X_COUNT (volatile unsigned short *)MDMA2_S0_CURR_X_COUNT +#define pMDMA2_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S0_CURR_Y_COUNT +#define pMDMA2_S0_IRQ_STATUS (volatile unsigned short *)MDMA2_S0_IRQ_STATUS +#define pMDMA2_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S0_PERIPHERAL_MAP +#define pMDMA2_D1_CONFIG (volatile unsigned short *)MDMA2_D1_CONFIG +#define pMDMA2_D1_NEXT_DESC_PTR (volatile void **)MDMA2_D1_NEXT_DESC_PTR +#define pMDMA2_D1_START_ADDR (volatile void **)MDMA2_D1_START_ADDR +#define pMDMA2_D1_X_COUNT (volatile unsigned short *)MDMA2_D1_X_COUNT +#define pMDMA2_D1_Y_COUNT (volatile unsigned short *)MDMA2_D1_Y_COUNT +#define pMDMA2_D1_X_MODIFY (volatile signed short *)MDMA2_D1_X_MODIFY +#define pMDMA2_D1_Y_MODIFY (volatile signed short *)MDMA2_D1_Y_MODIFY +#define pMDMA2_D1_CURR_DESC_PTR (volatile void **)MDMA2_D1_CURR_DESC_PTR +#define pMDMA2_D1_CURR_ADDR (volatile void **)MDMA2_D1_CURR_ADDR +#define pMDMA2_D1_CURR_X_COUNT (volatile unsigned short *)MDMA2_D1_CURR_X_COUNT +#define pMDMA2_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D1_CURR_Y_COUNT +#define pMDMA2_D1_IRQ_STATUS (volatile unsigned short *)MDMA2_D1_IRQ_STATUS +#define pMDMA2_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D1_PERIPHERAL_MAP +#define pMDMA2_S1_CONFIG (volatile unsigned short *)MDMA2_S1_CONFIG +#define pMDMA2_S1_NEXT_DESC_PTR (volatile void **)MDMA2_S1_NEXT_DESC_PTR +#define pMDMA2_S1_START_ADDR (volatile void **)MDMA2_S1_START_ADDR +#define pMDMA2_S1_X_COUNT (volatile unsigned short *)MDMA2_S1_X_COUNT +#define pMDMA2_S1_Y_COUNT (volatile unsigned short *)MDMA2_S1_Y_COUNT +#define pMDMA2_S1_X_MODIFY (volatile signed short *)MDMA2_S1_X_MODIFY +#define pMDMA2_S1_Y_MODIFY (volatile signed short *)MDMA2_S1_Y_MODIFY +#define pMDMA2_S1_CURR_DESC_PTR (volatile void **)MDMA2_S1_CURR_DESC_PTR +#define pMDMA2_S1_CURR_ADDR (volatile void **)MDMA2_S1_CURR_ADDR +#define pMDMA2_S1_CURR_X_COUNT (volatile unsigned short *)MDMA2_S1_CURR_X_COUNT +#define pMDMA2_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S1_CURR_Y_COUNT +#define pMDMA2_S1_IRQ_STATUS (volatile unsigned short *)MDMA2_S1_IRQ_STATUS +#define pMDMA2_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S1_PERIPHERAL_MAP + +/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ +#define pIMDMA_D0_CONFIG (volatile unsigned short *)IMDMA_D0_CONFIG +#define pIMDMA_D0_NEXT_DESC_PTR (volatile void **)IMDMA_D0_NEXT_DESC_PTR +#define pIMDMA_D0_START_ADDR (volatile void **)IMDMA_D0_START_ADDR +#define pIMDMA_D0_X_COUNT (volatile unsigned short *)IMDMA_D0_X_COUNT +#define pIMDMA_D0_Y_COUNT (volatile unsigned short *)IMDMA_D0_Y_COUNT +#define pIMDMA_D0_X_MODIFY (volatile signed short *)IMDMA_D0_X_MODIFY +#define pIMDMA_D0_Y_MODIFY (volatile signed short *)IMDMA_D0_Y_MODIFY +#define pIMDMA_D0_CURR_DESC_PTR (volatile void **)IMDMA_D0_CURR_DESC_PTR +#define pIMDMA_D0_CURR_ADDR (volatile void **)IMDMA_D0_CURR_ADDR +#define pIMDMA_D0_CURR_X_COUNT (volatile unsigned short *)IMDMA_D0_CURR_X_COUNT +#define pIMDMA_D0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D0_CURR_Y_COUNT +#define pIMDMA_D0_IRQ_STATUS (volatile unsigned short *)IMDMA_D0_IRQ_STATUS +#define pIMDMA_S0_CONFIG (volatile unsigned short *)IMDMA_S0_CONFIG +#define pIMDMA_S0_NEXT_DESC_PTR (volatile void **)IMDMA_S0_NEXT_DESC_PTR +#define pIMDMA_S0_START_ADDR (volatile void **)IMDMA_S0_START_ADDR +#define pIMDMA_S0_X_COUNT (volatile unsigned short *)IMDMA_S0_X_COUNT +#define pIMDMA_S0_Y_COUNT (volatile unsigned short *)IMDMA_S0_Y_COUNT +#define pIMDMA_S0_X_MODIFY (volatile signed short *)IMDMA_S0_X_MODIFY +#define pIMDMA_S0_Y_MODIFY (volatile signed short *)IMDMA_S0_Y_MODIFY +#define pIMDMA_S0_CURR_DESC_PTR (volatile void **)IMDMA_S0_CURR_DESC_PTR +#define pIMDMA_S0_CURR_ADDR (volatile void **)IMDMA_S0_CURR_ADDR +#define pIMDMA_S0_CURR_X_COUNT (volatile unsigned short *)IMDMA_S0_CURR_X_COUNT +#define pIMDMA_S0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S0_CURR_Y_COUNT +#define pIMDMA_S0_IRQ_STATUS (volatile unsigned short *)IMDMA_S0_IRQ_STATUS +#define pIMDMA_D1_CONFIG (volatile unsigned short *)IMDMA_D1_CONFIG +#define pIMDMA_D1_NEXT_DESC_PTR (volatile void **)IMDMA_D1_NEXT_DESC_PTR +#define pIMDMA_D1_START_ADDR (volatile void **)IMDMA_D1_START_ADDR +#define pIMDMA_D1_X_COUNT (volatile unsigned short *)IMDMA_D1_X_COUNT +#define pIMDMA_D1_Y_COUNT (volatile unsigned short *)IMDMA_D1_Y_COUNT +#define pIMDMA_D1_X_MODIFY (volatile signed short *)IMDMA_D1_X_MODIFY +#define pIMDMA_D1_Y_MODIFY (volatile signed short *)IMDMA_D1_Y_MODIFY +#define pIMDMA_D1_CURR_DESC_PTR (volatile void **)IMDMA_D1_CURR_DESC_PTR +#define pIMDMA_D1_CURR_ADDR (volatile void **)IMDMA_D1_CURR_ADDR +#define pIMDMA_D1_CURR_X_COUNT (volatile unsigned short *)IMDMA_D1_CURR_X_COUNT +#define pIMDMA_D1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D1_CURR_Y_COUNT +#define pIMDMA_D1_IRQ_STATUS (volatile unsigned short *)IMDMA_D1_IRQ_STATUS +#define pIMDMA_S1_CONFIG (volatile unsigned short *)IMDMA_S1_CONFIG +#define pIMDMA_S1_NEXT_DESC_PTR (volatile void **)IMDMA_S1_NEXT_DESC_PTR +#define pIMDMA_S1_START_ADDR (volatile void **)IMDMA_S1_START_ADDR +#define pIMDMA_S1_X_COUNT (volatile unsigned short *)IMDMA_S1_X_COUNT +#define pIMDMA_S1_Y_COUNT (volatile unsigned short *)IMDMA_S1_Y_COUNT +#define pIMDMA_S1_X_MODIFY (volatile signed short *)IMDMA_S1_X_MODIFY +#define pIMDMA_S1_Y_MODIFY (volatile signed short *)IMDMA_S1_Y_MODIFY +#define pIMDMA_S1_CURR_DESC_PTR (volatile void **)IMDMA_S1_CURR_DESC_PTR +#define pIMDMA_S1_CURR_ADDR (volatile void **)IMDMA_S1_CURR_ADDR +#define pIMDMA_S1_CURR_X_COUNT (volatile unsigned short *)IMDMA_S1_CURR_X_COUNT +#define pIMDMA_S1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S1_CURR_Y_COUNT +#define pIMDMA_S1_IRQ_STATUS (volatile unsigned short *)IMDMA_S1_IRQ_STATUS + +/* + * System Reset and Interrupt Controller registers for + * core A (0xFFC0 0100-0xFFC0 01FF) + */ +#define pSWRST (volatile unsigned short *)SICA_SWRST +#define pSYSCR (volatile unsigned short *)SICA_SYSCR +#define pRVECT (volatile unsigned short *)SICA_RVECT +#define pSIC_SWRST (volatile unsigned short *)SICA_SWRST +#define pSIC_SYSCR (volatile unsigned short *)SICA_SYSCR +#define pSIC_RVECT (volatile unsigned short *)SICA_RVECT +#define pSIC_IMASK (volatile unsigned long *)SICA_IMASK +#define pSIC_IAR0 ((volatile unsigned long *)SICA_IAR0) +#define pSIC_IAR1 (volatile unsigned long *)SICA_IAR1 +#define pSIC_IAR2 (volatile unsigned long *)SICA_IAR2 +#define pSIC_ISR (volatile unsigned long *)SICA_ISR0 +#define pSIC_IWR (volatile unsigned long *)SICA_IWR0 + +/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ +#define pWDOG_CTL (volatile unsigned short *)WDOGA_CTL +#define pWDOG_CNT (volatile unsigned long *)WDOGA_CNT +#define pWDOG_STAT (volatile unsigned long *)WDOGA_STAT + +/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ +#define pFIO_FLAG_D (volatile unsigned short *)FIO0_FLAG_D +#define pFIO_FLAG_C (volatile unsigned short *)FIO0_FLAG_C +#define pFIO_FLAG_S (volatile unsigned short *)FIO0_FLAG_S +#define pFIO_FLAG_T (volatile unsigned short *)FIO0_FLAG_T +#define pFIO_MASKA_D (volatile unsigned short *)FIO0_MASKA_D +#define pFIO_MASKA_C (volatile unsigned short *)FIO0_MASKA_C +#define pFIO_MASKA_S (volatile unsigned short *)FIO0_MASKA_S +#define pFIO_MASKA_T (volatile unsigned short *)FIO0_MASKA_T +#define pFIO_MASKB_D (volatile unsigned short *)FIO0_MASKB_D +#define pFIO_MASKB_C (volatile unsigned short *)FIO0_MASKB_C +#define pFIO_MASKB_S (volatile unsigned short *)FIO0_MASKB_S +#define pFIO_MASKB_T (volatile unsigned short *)FIO0_MASKB_T +#define pFIO_DIR (volatile unsigned short *)FIO0_DIR +#define pFIO_POLAR (volatile unsigned short *)FIO0_POLAR +#define pFIO_EDGE (volatile unsigned short *)FIO0_EDGE +#define pFIO_BOTH (volatile unsigned short *)FIO0_BOTH +#define pFIO_INEN (volatile unsigned short *)FIO0_INEN + +/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)*/ +#define pPPI_CONTROL (volatile unsigned short *)PPI0_CONTROL +#define pPPI_STATUS (volatile unsigned short *)PPI0_STATUS +#define pPPI_COUNT (volatile unsigned short *)PPI0_COUNT +#define pPPI_DELAY (volatile unsigned short *)PPI0_DELAY +#define pPPI_FRAME (volatile unsigned short *)PPI0_FRAME + +/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ +#define pDMA0_CONFIG (volatile unsigned short *)DMA1_0_CONFIG +#define pDMA0_NEXT_DESC_PTR (volatile void **)DMA1_0_NEXT_DESC_PTR +#define pDMA0_START_ADDR (volatile void **)DMA1_0_START_ADDR +#define pDMA0_X_COUNT (volatile unsigned short *)DMA1_0_X_COUNT +#define pDMA0_Y_COUNT (volatile unsigned short *)DMA1_0_Y_COUNT +#define pDMA0_X_MODIFY (volatile unsigned short *)DMA1_0_X_MODIFY +#define pDMA0_Y_MODIFY (volatile unsigned short *)DMA1_0_Y_MODIFY +#define pDMA0_CURR_DESC_PTR (volatile void **)DMA1_0_CURR_DESC_PTR +#define pDMA0_CURR_ADDR (volatile void **)DMA1_0_CURR_ADDR +#define pDMA0_CURR_X_COUNT (volatile unsigned short *)DMA1_0_CURR_X_COUNT +#define pDMA0_CURR_Y_COUNT (volatile unsigned short *)DMA1_0_CURR_Y_COUNT +#define pDMA0_IRQ_STATUS (volatile unsigned short *)DMA1_0_IRQ_STATUS +#define pDMA0_PERIPHERAL_MAP (volatile unsigned short *)DMA1_0_PERIPHERAL_MAP + +/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ +#define pMDMA_D0_CONFIG (volatile unsigned short *)MDMA1_D0_CONFIG +#define pMDMA_D0_NEXT_DESC_PTR (volatile void **)MDMA1_D0_NEXT_DESC_PTR +#define pMDMA_D0_START_ADDR (volatile void **)MDMA1_D0_START_ADDR +#define pMDMA_D0_X_COUNT (volatile unsigned short *)MDMA1_D0_X_COUNT +#define pMDMA_D0_Y_COUNT (volatile unsigned short *)MDMA1_D0_Y_COUNT +#define pMDMA_D0_X_MODIFY (volatile unsigned short *)MDMA1_D0_X_MODIFY +#define pMDMA_D0_Y_MODIFY (volatile unsigned short *)MDMA1_D0_Y_MODIFY +#define pMDMA_D0_CURR_DESC_PTR (volatile void **)MDMA1_D0_CURR_DESC_PTR +#define pMDMA_D0_CURR_ADDR (volatile void **)MDMA1_D0_CURR_ADDR +#define pMDMA_D0_CURR_X_COUNT (volatile unsigned short *)MDMA1_D0_CURR_X_COUNT +#define pMDMA_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT +#define pMDMA_D0_IRQ_STATUS (volatile unsigned short *)MDMA1_D0_IRQ_STATUS +#define pMDMA_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP +#define pMDMA_S0_CONFIG (volatile unsigned short *)MDMA1_S0_CONFIG +#define pMDMA_S0_NEXT_DESC_PTR (volatile void **)MDMA1_S0_NEXT_DESC_PTR +#define pMDMA_S0_START_ADDR (volatile void **)MDMA1_S0_START_ADDR +#define pMDMA_S0_X_COUNT (volatile unsigned short *)MDMA1_S0_X_COUNT +#define pMDMA_S0_Y_COUNT (volatile unsigned short *)MDMA1_S0_Y_COUNT +#define pMDMA_S0_X_MODIFY (volatile unsigned short *)MDMA1_S0_X_MODIFY +#define pMDMA_S0_Y_MODIFY (volatile unsigned short *)MDMA1_S0_Y_MODIFY +#define pMDMA_S0_CURR_DESC_PTR (volatile void **)MDMA1_S0_CURR_DESC_PTR +#define pMDMA_S0_CURR_ADDR (volatile void **)MDMA1_S0_CURR_ADDR +#define pMDMA_S0_CURR_X_COUNT (volatile unsigned short *)MDMA1_S0_CURR_X_COUNT +#define pMDMA_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT +#define pMDMA_S0_IRQ_STATUS (volatile unsigned short *)MDMA1_S0_IRQ_STATUS +#define pMDMA_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP +#define pMDMA_D1_CONFIG (volatile unsigned short *)MDMA1_D1_CONFIG +#define pMDMA_D1_NEXT_DESC_PTR (volatile void **)MDMA1_D1_NEXT_DESC_PTR +#define pMDMA_D1_START_ADDR (volatile void **)MDMA1_D1_START_ADDR +#define pMDMA_D1_X_COUNT (volatile unsigned short *)MDMA1_D1_X_COUNT +#define pMDMA_D1_Y_COUNT (volatile unsigned short *)MDMA1_D1_Y_COUNT +#define pMDMA_D1_X_MODIFY (volatile unsigned short *)MDMA1_D1_X_MODIFY +#define pMDMA_D1_Y_MODIFY (volatile unsigned short *)MDMA1_D1_Y_MODIFY +#define pMDMA_D1_CURR_DESC_PTR (volatile void **)MDMA1_D1_CURR_DESC_PTR +#define pMDMA_D1_CURR_ADDR (volatile void **)MDMA1_D1_CURR_ADDR +#define pMDMA_D1_CURR_X_COUNT (volatile unsigned short *)MDMA1_D1_CURR_X_COUNT +#define pMDMA_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT +#define pMDMA_D1_IRQ_STATUS (volatile unsigned short *)MDMA1_D1_IRQ_STATUS +#define pMDMA_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP +#define pMDMA_S1_CONFIG (volatile unsigned short *)MDMA1_S1_CONFIG +#define pMDMA_S1_NEXT_DESC_PTR (volatile void **)MDMA1_S1_NEXT_DESC_PTR +#define pMDMA_S1_START_ADDR (volatile void **)MDMA1_S1_START_ADDR +#define pMDMA_S1_X_COUNT (volatile unsigned short *)MDMA1_S1_X_COUNT +#define pMDMA_S1_Y_COUNT (volatile unsigned short *)MDMA1_S1_Y_COUNT +#define pMDMA_S1_X_MODIFY (volatile unsigned short *)MDMA1_S1_X_MODIFY +#define pMDMA_S1_Y_MODIFY (volatile unsigned short *)MDMA1_S1_Y_MODIFY +#define pMDMA_S1_CURR_DESC_PTR (volatile void **)MDMA1_S1_CURR_DESC_PTR +#define pMDMA_S1_CURR_ADDR (volatile void **)MDMA1_S1_CURR_ADDR +#define pMDMA_S1_CURR_X_COUNT (volatile unsigned short *)MDMA1_S1_CURR_X_COUNT +#define pMDMA_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT +#define pMDMA_S1_IRQ_STATUS (volatile unsigned short *)MDMA1_S1_IRQ_STATUS +#define pMDMA_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP + +/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ +#define pDMA1_CONFIG (volatile unsigned short *)DMA2_0_CONFIG +#define pDMA1_NEXT_DESC_PTR (volatile void **)DMA2_0_NEXT_DESC_PTR +#define pDMA1_START_ADDR (volatile void **)DMA2_0_START_ADDR +#define pDMA1_X_COUNT (volatile unsigned short *)DMA2_0_X_COUNT +#define pDMA1_Y_COUNT (volatile unsigned short *)DMA2_0_Y_COUNT +#define pDMA1_X_MODIFY (volatile unsigned short *)DMA2_0_X_MODIFY +#define pDMA1_Y_MODIFY (volatile unsigned short *)DMA2_0_Y_MODIFY +#define pDMA1_CURR_DESC_PTR (volatile void **)DMA2_0_CURR_DESC_PTR +#define pDMA1_CURR_ADDR (volatile void **)DMA2_0_CURR_ADDR +#define pDMA1_CURR_X_COUNT (volatile unsigned short *)DMA2_0_CURR_X_COUNT +#define pDMA1_CURR_Y_COUNT (volatile unsigned short *)DMA2_0_CURR_Y_COUNT +#define pDMA1_IRQ_STATUS (volatile unsigned short *)DMA2_0_IRQ_STATUS +#define pDMA1_PERIPHERAL_MAP (volatile unsigned short *)DMA2_0_PERIPHERAL_MAP +#define pDMA2_CONFIG (volatile unsigned short *)DMA2_1_CONFIG +#define pDMA2_NEXT_DESC_PTR (volatile void **)DMA2_1_NEXT_DESC_PTR +#define pDMA2_START_ADDR (volatile void **)DMA2_1_START_ADDR +#define pDMA2_X_COUNT (volatile unsigned short *)DMA2_1_X_COUNT +#define pDMA2_Y_COUNT (volatile unsigned short *)DMA2_1_Y_COUNT +#define pDMA2_X_MODIFY (volatile unsigned short *)DMA2_1_X_MODIFY +#define pDMA2_Y_MODIFY (volatile unsigned short *)DMA2_1_Y_MODIFY +#define pDMA2_CURR_DESC_PTR (volatile void **)DMA2_1_CURR_DESC_PTR +#define pDMA2_CURR_ADDR (volatile void **)DMA2_1_CURR_ADDR +#define pDMA2_CURR_X_COUNT (volatile unsigned short *)DMA2_1_CURR_X_COUNT +#define pDMA2_CURR_Y_COUNT (volatile unsigned short *)DMA2_1_CURR_Y_COUNT +#define pDMA2_IRQ_STATUS (volatile unsigned short *)DMA2_1_IRQ_STATUS +#define pDMA2_PERIPHERAL_MAP (volatile unsigned short *)DMA2_1_PERIPHERAL_MAP +#define pDMA3_CONFIG (volatile unsigned short *)DMA2_2_CONFIG +#define pDMA3_NEXT_DESC_PTR (volatile void **)DMA2_2_NEXT_DESC_PTR +#define pDMA3_START_ADDR (volatile void **)DMA2_2_START_ADDR +#define pDMA3_X_COUNT (volatile unsigned short *)DMA2_2_X_COUNT +#define pDMA3_Y_COUNT (volatile unsigned short *)DMA2_2_Y_COUNT +#define pDMA3_X_MODIFY (volatile unsigned short *)DMA2_2_X_MODIFY +#define pDMA3_Y_MODIFY (volatile unsigned short *)DMA2_2_Y_MODIFY +#define pDMA3_CURR_DESC_PTR (volatile void **)DMA2_2_CURR_DESC_PTR +#define pDMA3_CURR_ADDR (volatile void **)DMA2_2_CURR_ADDR +#define pDMA3_CURR_X_COUNT (volatile unsigned short *)DMA2_2_CURR_X_COUNT +#define pDMA3_CURR_Y_COUNT (volatile unsigned short *)DMA2_2_CURR_Y_COUNT +#define pDMA3_IRQ_STATUS (volatile unsigned short *)DMA2_2_IRQ_STATUS +#define pDMA3_PERIPHERAL_MAP (volatile unsigned short *)DMA2_2_PERIPHERAL_MAP +#define pDMA4_CONFIG (volatile unsigned short *)DMA2_3_CONFIG +#define pDMA4_NEXT_DESC_PTR (volatile void **)DMA2_3_NEXT_DESC_PTR +#define pDMA4_START_ADDR (volatile void **)DMA2_3_START_ADDR +#define pDMA4_X_COUNT (volatile unsigned short *)DMA2_3_X_COUNT +#define pDMA4_Y_COUNT (volatile unsigned short *)DMA2_3_Y_COUNT +#define pDMA4_X_MODIFY (volatile unsigned short *)DMA2_3_X_MODIFY +#define pDMA4_Y_MODIFY (volatile unsigned short *)DMA2_3_Y_MODIFY +#define pDMA4_CURR_DESC_PTR (volatile void **)DMA2_3_CURR_DESC_PTR +#define pDMA4_CURR_ADDR (volatile void **)DMA2_3_CURR_ADDR +#define pDMA4_CURR_X_COUNT (volatile unsigned short *)DMA2_3_CURR_X_COUNT +#define pDMA4_CURR_Y_COUNT (volatile unsigned short *)DMA2_3_CURR_Y_COUNT +#define pDMA4_IRQ_STATUS (volatile unsigned short *)DMA2_3_IRQ_STATUS +#define pDMA4_PERIPHERAL_MAP (volatile unsigned short *)DMA2_3_PERIPHERAL_MAP +#define pDMA5_CONFIG (volatile unsigned short *)DMA2_4_CONFIG +#define pDMA5_NEXT_DESC_PTR (volatile void **)DMA2_4_NEXT_DESC_PTR +#define pDMA5_START_ADDR (volatile void **)DMA2_4_START_ADDR +#define pDMA5_X_COUNT (volatile unsigned short *)DMA2_4_X_COUNT +#define pDMA5_Y_COUNT (volatile unsigned short *)DMA2_4_Y_COUNT +#define pDMA5_X_MODIFY (volatile unsigned short *)DMA2_4_X_MODIFY +#define pDMA5_Y_MODIFY (volatile unsigned short *)DMA2_4_Y_MODIFY +#define pDMA5_CURR_DESC_PTR (volatile void **)DMA2_4_CURR_DESC_PTR +#define pDMA5_CURR_ADDR (volatile void **)DMA2_4_CURR_ADDR +#define pDMA5_CURR_X_COUNT (volatile unsigned short *)DMA2_4_CURR_X_COUNT +#define pDMA5_CURR_Y_COUNT (volatile unsigned short *)DMA2_4_CURR_Y_COUNT +#define pDMA5_IRQ_STATUS (volatile unsigned short *)DMA2_4_IRQ_STATUS +#define pDMA5_PERIPHERAL_MAP (volatile unsigned short *)DMA2_4_PERIPHERAL_MAP +#define pDMA6_CONFIG (volatile unsigned short *)DMA2_5_CONFIG +#define pDMA6_NEXT_DESC_PTR (volatile void **)DMA2_5_NEXT_DESC_PTR +#define pDMA6_START_ADDR (volatile void **)DMA2_5_START_ADDR +#define pDMA6_X_COUNT (volatile unsigned short *)DMA2_5_X_COUNT +#define pDMA6_Y_COUNT (volatile unsigned short *)DMA2_5_Y_COUNT +#define pDMA6_X_MODIFY (volatile unsigned short *)DMA2_5_X_MODIFY +#define pDMA6_Y_MODIFY (volatile unsigned short *)DMA2_5_Y_MODIFY +#define pDMA6_CURR_DESC_PTR (volatile void **)DMA2_5_CURR_DESC_PTR +#define pDMA6_CURR_ADDR (volatile void **)DMA2_5_CURR_ADDR +#define pDMA6_CURR_X_COUNT (volatile unsigned short *)DMA2_5_CURR_X_COUNT +#define pDMA6_CURR_Y_COUNT (volatile unsigned short *)DMA2_5_CURR_Y_COUNT +#define pDMA6_IRQ_STATUS (volatile unsigned short *)DMA2_5_IRQ_STATUS +#define pDMA6_PERIPHERAL_MAP (volatile unsigned short *)DMA2_5_PERIPHERAL_MAP +#define pDMA7_CONFIG (volatile unsigned short *)DMA2_6_CONFIG +#define pDMA7_NEXT_DESC_PTR (volatile void **)DMA2_6_NEXT_DESC_PTR +#define pDMA7_START_ADDR (volatile void **)DMA2_6_START_ADDR +#define pDMA7_X_COUNT (volatile unsigned short *)DMA2_6_X_COUNT +#define pDMA7_Y_COUNT (volatile unsigned short *)DMA2_6_Y_COUNT +#define pDMA7_X_MODIFY (volatile unsigned short *)DMA2_6_X_MODIFY +#define pDMA7_Y_MODIFY (volatile unsigned short *)DMA2_6_Y_MODIFY +#define pDMA7_CURR_DESC_PTR (volatile void **)DMA2_6_CURR_DESC_PTR +#define pDMA7_CURR_ADDR (volatile void **)DMA2_6_CURR_ADDR +#define pDMA7_CURR_X_COUNT (volatile unsigned short *)DMA2_6_CURR_X_COUNT +#define pDMA7_CURR_Y_COUNT (volatile unsigned short *)DMA2_6_CURR_Y_COUNT +#define pDMA7_IRQ_STATUS (volatile unsigned short *)DMA2_6_IRQ_STATUS +#define pDMA7_PERIPHERAL_MAP (volatile unsigned short *)DMA2_6_PERIPHERAL_MAP + +#endif /* _CDEF_BF561_H */ diff --git a/include/asm-blackfin/arch-bf561/defBF561.h b/include/asm-blackfin/arch-bf561/defBF561.h new file mode 100644 index 0000000000..c6e3de5bf4 --- /dev/null +++ b/include/asm-blackfin/arch-bf561/defBF561.h @@ -0,0 +1,1941 @@ +/* + * defBF561.h + * + * (c) Copyright 2001-2003 Analog Devices, Inc. All rights reserved. + * + */ + +/* SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */ + +#ifndef _DEF_BF561_H +#define _DEF_BF561_H + +/* + * #if !defined(__ADSPBF561__) + * #warning defBF561.h should only be included for BF561 chip. + * #endif + */ + +/* include all Core registers and bit definitions */ +#include + +/* + * Helper macros + * usage: + * P0.H = HI(UART_THR); + * P0.L = LO(UART_THR); + */ + +#define LO(con32) ((con32) & 0xFFFF) +#define lo(con32) ((con32) & 0xFFFF) +#define HI(con32) (((con32) >> 16) & 0xFFFF) +#define hi(con32) (((con32) >> 16) & 0xFFFF) + +/* + * System MMR Register Map + */ + +/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ +#define PLL_CTL 0xFFC00000 /* PLL Control register */ +#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ +#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ +#define PLL_STAT 0xFFC0000C /* PLL Status register */ +#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register */ + +/* + * System Reset and Interrupt Controller registers for + * core A (0xFFC0 0100-0xFFC0 01FF) + */ +#define SICA_SWRST 0xFFC00100 /* Software Reset register */ +#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ +#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ +#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 */ +#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ +#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ +#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ +#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ +#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ +#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ +#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ +#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ +#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ +#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ +#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ +#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ +#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ +#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ + +/* + * System Reset and Interrupt Controller registers for + * Core B (0xFFC0 1100-0xFFC0 11FF) + */ +#define SICB_SWRST 0xFFC01100 /* reserved */ +#define SICB_SYSCR 0xFFC01104 /* reserved */ +#define SICB_RVECT 0xFFC01108 /* SIC Reset Vector Address Register */ +#define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */ +#define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */ +#define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */ +#define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */ +#define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */ +#define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */ +#define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */ +#define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */ +#define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */ +#define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */ +#define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */ +#define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */ +#define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */ +#define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */ + +/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ +#define WDOGA_CTL 0xFFC00200 /* Watchdog Control register */ +#define WDOGA_CNT 0xFFC00204 /* Watchdog Count register */ +#define WDOGA_STAT 0xFFC00208 /* Watchdog Status register */ + +/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */ +#define WDOGB_CTL 0xFFC01200 /* Watchdog Control register */ +#define WDOGB_CNT 0xFFC01204 /* Watchdog Count register */ +#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */ + +/* UART Controller (0xFFC00400 - 0xFFC004FF) */ +#define UART_THR 0xFFC00400 /* Transmit Holding register */ +#define UART_RBR 0xFFC00400 /* Receive Buffer register */ +#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ +#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ +#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ +#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ +#define UART_LCR 0xFFC0040C /* Line Control Register */ +#define UART_MCR 0xFFC00410 /* Modem Control Register */ +#define UART_LSR 0xFFC00414 /* Line Status Register */ +#define UART_MSR 0xFFC00418 /* Modem Status Register */ +#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ +#define UART_GCTL 0xFFC00424 /* Global Control Register */ + +/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define SPI_CTL 0xFFC00500 /* SPI Control Register */ +#define SPI_FLG 0xFFC00504 /* SPI Flag register */ +#define SPI_STAT 0xFFC00508 /* SPI Status register */ +#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ +#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ +#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ +#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ + +/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */ +#define TIMER0_CONFIG 0xFFC00600 /* Timer0 Configuration register */ +#define TIMER0_COUNTER 0xFFC00604 /* Timer0 Counter register */ +#define TIMER0_PERIOD 0xFFC00608 /* Timer0 Period register */ +#define TIMER0_WIDTH 0xFFC0060C /* Timer0 Width register */ +#define TIMER1_CONFIG 0xFFC00610 /* Timer1 Configuration register */ +#define TIMER1_COUNTER 0xFFC00614 /* Timer1 Counter register */ +#define TIMER1_PERIOD 0xFFC00618 /* Timer1 Period register */ +#define TIMER1_WIDTH 0xFFC0061C /* Timer1 Width register */ +#define TIMER2_CONFIG 0xFFC00620 /* Timer2 Configuration register */ +#define TIMER2_COUNTER 0xFFC00624 /* Timer2 Counter register */ +#define TIMER2_PERIOD 0xFFC00628 /* Timer2 Period register */ +#define TIMER2_WIDTH 0xFFC0062C /* Timer2 Width register */ +#define TIMER3_CONFIG 0xFFC00630 /* Timer3 Configuration register */ +#define TIMER3_COUNTER 0xFFC00634 /* Timer3 Counter register */ +#define TIMER3_PERIOD 0xFFC00638 /* Timer3 Period register */ +#define TIMER3_WIDTH 0xFFC0063C /* Timer3 Width register */ +#define TIMER4_CONFIG 0xFFC00640 /* Timer4 Configuration register */ +#define TIMER4_COUNTER 0xFFC00644 /* Timer4 Counter register */ +#define TIMER4_PERIOD 0xFFC00648 /* Timer4 Period register */ +#define TIMER4_WIDTH 0xFFC0064C /* Timer4 Width register */ +#define TIMER5_CONFIG 0xFFC00650 /* Timer5 Configuration register */ +#define TIMER5_COUNTER 0xFFC00654 /* Timer5 Counter register */ +#define TIMER5_PERIOD 0xFFC00658 /* Timer5 Period register */ +#define TIMER5_WIDTH 0xFFC0065C /* Timer5 Width register */ +#define TIMER6_CONFIG 0xFFC00660 /* Timer6 Configuration register */ +#define TIMER6_COUNTER 0xFFC00664 /* Timer6 Counter register */ +#define TIMER6_PERIOD 0xFFC00668 /* Timer6 Period register */ +#define TIMER6_WIDTH 0xFFC0066C /* Timer6 Width register */ +#define TIMER7_CONFIG 0xFFC00670 /* Timer7 Configuration register */ +#define TIMER7_COUNTER 0xFFC00674 /* Timer7 Counter register */ +#define TIMER7_PERIOD 0xFFC00678 /* Timer7 Period register */ +#define TIMER7_WIDTH 0xFFC0067C /* Timer7 Width register */ +#define TMRS8_ENABLE 0xFFC00680 /* Timer Enable Register */ +#define TMRS8_DISABLE 0xFFC00684 /* Timer Disable register */ +#define TMRS8_STATUS 0xFFC00688 /* Timer Status register */ + +/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */ +#define TIMER8_CONFIG 0xFFC01600 /* Timer8 Configuration register */ +#define TIMER8_COUNTER 0xFFC01604 /* Timer8 Counter register */ +#define TIMER8_PERIOD 0xFFC01608 /* Timer8 Period register */ +#define TIMER8_WIDTH 0xFFC0160C /* Timer8 Width register */ +#define TIMER9_CONFIG 0xFFC01610 /* Timer9 Configuration register */ +#define TIMER9_COUNTER 0xFFC01614 /* Timer9 Counter register */ +#define TIMER9_PERIOD 0xFFC01618 /* Timer9 Period register */ +#define TIMER9_WIDTH 0xFFC0161C /* Timer9 Width register */ +#define TIMER10_CONFIG 0xFFC01620 /* Timer10 Configuration register */ +#define TIMER10_COUNTER 0xFFC01624 /* Timer10 Counter register */ +#define TIMER10_PERIOD 0xFFC01628 /* Timer10 Period register */ +#define TIMER10_WIDTH 0xFFC0162C /* Timer10 Width register */ +#define TIMER11_CONFIG 0xFFC01630 /* Timer11 Configuration register */ +#define TIMER11_COUNTER 0xFFC01634 /* Timer11 Counter register */ +#define TIMER11_PERIOD 0xFFC01638 /* Timer11 Period register */ +#define TIMER11_WIDTH 0xFFC0163C /* Timer11 Width register */ +#define TMRS4_ENABLE 0xFFC01640 /* Timer Enable Register */ +#define TMRS4_DISABLE 0xFFC01644 /* Timer Disable register */ +#define TMRS4_STATUS 0xFFC01648 /* Timer Status register */ + +/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ +#define FIO0_FLAG_D 0xFFC00700 /* Flag Data register */ +#define FIO0_FLAG_C 0xFFC00704 /* Flag Clear register */ +#define FIO0_FLAG_S 0xFFC00708 /* Flag Set register */ +#define FIO0_FLAG_T 0xFFC0070C /* Flag Toggle register */ +#define FIO0_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */ +#define FIO0_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */ +#define FIO0_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */ +#define FIO0_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */ +#define FIO0_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */ +#define FIO0_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */ +#define FIO0_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */ +#define FIO0_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */ +#define FIO0_DIR 0xFFC00730 /* Flag Direction register */ +#define FIO0_POLAR 0xFFC00734 /* Flag Polarity register */ +#define FIO0_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */ +#define FIO0_BOTH 0xFFC0073C /* Flag Set on Both Edges register */ +#define FIO0_INEN 0xFFC00740 /* Flag Input Enable register */ + +/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */ +#define FIO1_FLAG_D 0xFFC01500 /* Flag Data register */ +#define FIO1_FLAG_C 0xFFC01504 /* Flag Clear register */ +#define FIO1_FLAG_S 0xFFC01508 /* Flag Set register */ +#define FIO1_FLAG_T 0xFFC0150C /* Flag Toggle register */ +#define FIO1_MASKA_D 0xFFC01510 /* Flag Mask Interrupt A Data register */ +#define FIO1_MASKA_C 0xFFC01514 /* Flag Mask Interrupt A Clear register */ +#define FIO1_MASKA_S 0xFFC01518 /* Flag Mask Interrupt A Set register */ +#define FIO1_MASKA_T 0xFFC0151C /* Flag Mask Interrupt A Toggle register */ +#define FIO1_MASKB_D 0xFFC01520 /* Flag Mask Interrupt B Data register */ +#define FIO1_MASKB_C 0xFFC01524 /* Flag Mask Interrupt B Clear register */ +#define FIO1_MASKB_S 0xFFC01528 /* Flag Mask Interrupt B Set register */ +#define FIO1_MASKB_T 0xFFC0152C /* Flag Mask Interrupt B Toggle register */ +#define FIO1_DIR 0xFFC01530 /* Flag Direction register */ +#define FIO1_POLAR 0xFFC01534 /* Flag Polarity register */ +#define FIO1_EDGE 0xFFC01538 /* Flag Interrupt Sensitivity register */ +#define FIO1_BOTH 0xFFC0153C /* Flag Set on Both Edges register */ +#define FIO1_INEN 0xFFC01540 /* Flag Input Enable register */ + +/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */ +#define FIO2_FLAG_D 0xFFC01700 /* Flag Data register */ +#define FIO2_FLAG_C 0xFFC01704 /* Flag Clear register */ +#define FIO2_FLAG_S 0xFFC01708 /* Flag Set register */ +#define FIO2_FLAG_T 0xFFC0170C /* Flag Toggle register */ +#define FIO2_MASKA_D 0xFFC01710 /* Flag Mask Interrupt A Data register */ +#define FIO2_MASKA_C 0xFFC01714 /* Flag Mask Interrupt A Clear register */ +#define FIO2_MASKA_S 0xFFC01718 /* Flag Mask Interrupt A Set register */ +#define FIO2_MASKA_T 0xFFC0171C /* Flag Mask Interrupt A Toggle register */ +#define FIO2_MASKB_D 0xFFC01720 /* Flag Mask Interrupt B Data register */ +#define FIO2_MASKB_C 0xFFC01724 /* Flag Mask Interrupt B Clear register */ +#define FIO2_MASKB_S 0xFFC01728 /* Flag Mask Interrupt B Set register */ +#define FIO2_MASKB_T 0xFFC0172C /* Flag Mask Interrupt B Toggle register */ +#define FIO2_DIR 0xFFC01730 /* Flag Direction register */ +#define FIO2_POLAR 0xFFC01734 /* Flag Polarity register */ +#define FIO2_EDGE 0xFFC01738 /* Flag Interrupt Sensitivity register */ +#define FIO2_BOTH 0xFFC0173C /* Flag Set on Both Edges register */ +#define FIO2_INEN 0xFFC01740 /* Flag Input Enable register */ + +/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ +#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ +#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ +#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ +#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ +#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ +#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ +#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ + +/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ +#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ +#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ +#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ +#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ +#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ +#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ +#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ +#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ +#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ +#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ +#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ +#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ +#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ +#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ +#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ +#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ +#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ +#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ + +/* Asynchronous Memory Controller - External Bus Interface Unit */ +#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ +#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ +#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ + +/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ +#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ +#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ +#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ +#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ + +/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */ +#define PPI0_CONTROL 0xFFC01000 /* PPI0 Control register */ +#define PPI0_STATUS 0xFFC01004 /* PPI0 Status register */ +#define PPI0_COUNT 0xFFC01008 /* PPI0 Transfer Count register */ +#define PPI0_DELAY 0xFFC0100C /* PPI0 Delay Count register */ +#define PPI0_FRAME 0xFFC01010 /* PPI0 Frame Length register */ + +/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */ +#define PPI1_CONTROL 0xFFC01300 /* PPI1 Control register */ +#define PPI1_STATUS 0xFFC01304 /* PPI1 Status register */ +#define PPI1_COUNT 0xFFC01308 /* PPI1 Transfer Count register */ +#define PPI1_DELAY 0xFFC0130C /* PPI1 Delay Count register */ +#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */ + +/* DMA Traffic controls */ +#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ +#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ +#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ +#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ + +/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ +#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */ +#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */ +#define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */ +#define DMA1_0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */ +#define DMA1_0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */ +#define DMA1_0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */ +#define DMA1_0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */ +#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */ +#define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */ +#define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */ +#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */ +#define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt Status Register */ +#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */ + +#define DMA1_1_CONFIG 0xFFC01C48 /* DMA1 Channel 1 Configuration register */ +#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */ +#define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */ +#define DMA1_1_X_COUNT 0xFFC01C50 /* DMA1 Channel 1 Inner Loop Count */ +#define DMA1_1_Y_COUNT 0xFFC01C58 /* DMA1 Channel 1 Outer Loop Count */ +#define DMA1_1_X_MODIFY 0xFFC01C54 /* DMA1 Channel 1 Inner Loop Addr Increment */ +#define DMA1_1_Y_MODIFY 0xFFC01C5C /* DMA1 Channel 1 Outer Loop Addr Increment */ +#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */ +#define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */ +#define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */ +#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */ +#define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt Status Register */ +#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */ + +#define DMA1_2_CONFIG 0xFFC01C88 /* DMA1 Channel 2 Configuration register */ +#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */ +#define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */ +#define DMA1_2_X_COUNT 0xFFC01C90 /* DMA1 Channel 2 Inner Loop Count */ +#define DMA1_2_Y_COUNT 0xFFC01C98 /* DMA1 Channel 2 Outer Loop Count */ +#define DMA1_2_X_MODIFY 0xFFC01C94 /* DMA1 Channel 2 Inner Loop Addr Increment */ +#define DMA1_2_Y_MODIFY 0xFFC01C9C /* DMA1 Channel 2 Outer Loop Addr Increment */ +#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */ +#define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */ +#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */ +#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */ +#define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt Status Register */ +#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */ + +#define DMA1_3_CONFIG 0xFFC01CC8 /* DMA1 Channel 3 Configuration register */ +#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */ +#define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */ +#define DMA1_3_X_COUNT 0xFFC01CD0 /* DMA1 Channel 3 Inner Loop Count */ +#define DMA1_3_Y_COUNT 0xFFC01CD8 /* DMA1 Channel 3 Outer Loop Count */ +#define DMA1_3_X_MODIFY 0xFFC01CD4 /* DMA1 Channel 3 Inner Loop Addr Increment */ +#define DMA1_3_Y_MODIFY 0xFFC01CDC /* DMA1 Channel 3 Outer Loop Addr Increment */ +#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */ +#define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */ +#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */ +#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */ +#define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt Status Register */ +#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */ + +#define DMA1_4_CONFIG 0xFFC01D08 /* DMA1 Channel 4 Configuration register */ +#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */ +#define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */ +#define DMA1_4_X_COUNT 0xFFC01D10 /* DMA1 Channel 4 Inner Loop Count */ +#define DMA1_4_Y_COUNT 0xFFC01D18 /* DMA1 Channel 4 Outer Loop Count */ +#define DMA1_4_X_MODIFY 0xFFC01D14 /* DMA1 Channel 4 Inner Loop Addr Increment */ +#define DMA1_4_Y_MODIFY 0xFFC01D1C /* DMA1 Channel 4 Outer Loop Addr Increment */ +#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */ +#define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */ +#define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */ +#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */ +#define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt Status Register */ +#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */ + +#define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */ +#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */ +#define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */ +#define DMA1_5_X_COUNT 0xFFC01D50 /* DMA1 Channel 5 Inner Loop Count */ +#define DMA1_5_Y_COUNT 0xFFC01D58 /* DMA1 Channel 5 Outer Loop Count */ +#define DMA1_5_X_MODIFY 0xFFC01D54 /* DMA1 Channel 5 Inner Loop Addr Increment */ +#define DMA1_5_Y_MODIFY 0xFFC01D5C /* DMA1 Channel 5 Outer Loop Addr Increment */ +#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */ +#define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */ +#define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */ +#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */ +#define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt Status Register */ +#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */ + +#define DMA1_6_CONFIG 0xFFC01D88 /* DMA1 Channel 6 Configuration register */ +#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */ +#define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */ +#define DMA1_6_X_COUNT 0xFFC01D90 /* DMA1 Channel 6 Inner Loop Count */ +#define DMA1_6_Y_COUNT 0xFFC01D98 /* DMA1 Channel 6 Outer Loop Count */ +#define DMA1_6_X_MODIFY 0xFFC01D94 /* DMA1 Channel 6 Inner Loop Addr Increment */ +#define DMA1_6_Y_MODIFY 0xFFC01D9C /* DMA1 Channel 6 Outer Loop Addr Increment */ +#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */ +#define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */ +#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */ +#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */ +#define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt Status Register */ +#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */ + +#define DMA1_7_CONFIG 0xFFC01DC8 /* DMA1 Channel 7 Configuration register */ +#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */ +#define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */ +#define DMA1_7_X_COUNT 0xFFC01DD0 /* DMA1 Channel 7 Inner Loop Count */ +#define DMA1_7_Y_COUNT 0xFFC01DD8 /* DMA1 Channel 7 Outer Loop Count */ +#define DMA1_7_X_MODIFY 0xFFC01DD4 /* DMA1 Channel 7 Inner Loop Addr Increment */ +#define DMA1_7_Y_MODIFY 0xFFC01DDC /* DMA1 Channel 7 Outer Loop Addr Increment */ +#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */ +#define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */ +#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */ +#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */ +#define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt Status Register */ +#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */ + +#define DMA1_8_CONFIG 0xFFC01E08 /* DMA1 Channel 8 Configuration register */ +#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */ +#define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */ +#define DMA1_8_X_COUNT 0xFFC01E10 /* DMA1 Channel 8 Inner Loop Count */ +#define DMA1_8_Y_COUNT 0xFFC01E18 /* DMA1 Channel 8 Outer Loop Count */ +#define DMA1_8_X_MODIFY 0xFFC01E14 /* DMA1 Channel 8 Inner Loop Addr Increment */ +#define DMA1_8_Y_MODIFY 0xFFC01E1C /* DMA1 Channel 8 Outer Loop Addr Increment */ +#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */ +#define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */ +#define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */ +#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */ +#define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt Status Register */ +#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */ + +#define DMA1_9_CONFIG 0xFFC01E48 /* DMA1 Channel 9 Configuration register */ +#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */ +#define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */ +#define DMA1_9_X_COUNT 0xFFC01E50 /* DMA1 Channel 9 Inner Loop Count */ +#define DMA1_9_Y_COUNT 0xFFC01E58 /* DMA1 Channel 9 Outer Loop Count */ +#define DMA1_9_X_MODIFY 0xFFC01E54 /* DMA1 Channel 9 Inner Loop Addr Increment */ +#define DMA1_9_Y_MODIFY 0xFFC01E5C /* DMA1 Channel 9 Outer Loop Addr Increment */ +#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */ +#define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */ +#define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */ +#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */ +#define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt Status Register */ +#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */ + +#define DMA1_10_CONFIG 0xFFC01E88 /* DMA1 Channel 10 Configuration register */ +#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 /* DMA1 Channel 10 Next Descripter Ptr Reg */ +#define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */ +#define DMA1_10_X_COUNT 0xFFC01E90 /* DMA1 Channel 10 Inner Loop Count */ +#define DMA1_10_Y_COUNT 0xFFC01E98 /* DMA1 Channel 10 Outer Loop Count */ +#define DMA1_10_X_MODIFY 0xFFC01E94 /* DMA1 Channel 10 Inner Loop Addr Increment */ +#define DMA1_10_Y_MODIFY 0xFFC01E9C /* DMA1 Channel 10 Outer Loop Addr Increment */ +#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */ +#define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */ +#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */ +#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */ +#define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt Status Register */ +#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */ + +#define DMA1_11_CONFIG 0xFFC01EC8 /* DMA1 Channel 11 Configuration register */ +#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 /* DMA1 Channel 11 Next Descripter Ptr Reg */ +#define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */ +#define DMA1_11_X_COUNT 0xFFC01ED0 /* DMA1 Channel 11 Inner Loop Count */ +#define DMA1_11_Y_COUNT 0xFFC01ED8 /* DMA1 Channel 11 Outer Loop Count */ +#define DMA1_11_X_MODIFY 0xFFC01ED4 /* DMA1 Channel 11 Inner Loop Addr Increment */ +#define DMA1_11_Y_MODIFY 0xFFC01EDC /* DMA1 Channel 11 Outer Loop Addr Increment */ +#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */ +#define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */ +#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */ +#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */ +#define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt Status Register */ +#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */ + +/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ +#define MDMA1_D0_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration */ +#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */ +#define MDMA1_D0_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address */ +#define MDMA1_D0_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination Inner-Loop Count */ +#define MDMA1_D0_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Outer-Loop Count */ +#define MDMA1_D0_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */ +#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */ +#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */ +#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address */ +#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Dest Current Inner-Loop Count */ +#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Dest Current Outer-Loop Count */ +#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status */ +#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map */ + +#define MDMA1_S0_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration */ +#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */ +#define MDMA1_S0_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address */ +#define MDMA1_S0_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source Inner-Loop Count */ +#define MDMA1_S0_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Outer-Loop Count */ +#define MDMA1_S0_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source Inner-Loop Address-Increment */ +#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Outer-Loop Address-Increment */ +#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Ptr reg */ +#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address */ +#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current Inner-Loop Count */ +#define MDMA1_S0_CURR_Y_COUNT ` 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Outer-Loop Count */ +#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status */ +#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map */ + +#define MDMA1_D1_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration */ +#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */ +#define MDMA1_D1_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address */ +#define MDMA1_D1_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination Inner-Loop Count */ +#define MDMA1_D1_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Outer-Loop Count */ +#define MDMA1_D1_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */ +#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */ +#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */ +#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Dest Current Address */ +#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Dest Current Inner-Loop Count */ +#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Dest Current Outer-Loop Count */ +#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Dest Interrupt/Status */ +#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Dest Peripheral Map */ + +#define MDMA1_S1_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration */ +#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */ +#define MDMA1_S1_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address */ +#define MDMA1_S1_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source Inner-Loop Count */ +#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Outer-Loop Count */ +#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source Inner-Loop Address-Increment */ +#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Outer-Loop Address-Increment */ +#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Ptr reg */ +#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address */ +#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current Inner-Loop Count */ +#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Outer-Loop Count */ +#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status */ +#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map */ + +/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ +#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */ +#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */ +#define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */ +#define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */ +#define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */ +#define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */ +#define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */ +#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */ +#define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */ +#define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */ +#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */ +#define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt Status Register */ +#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */ + +#define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */ +#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */ +#define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */ +#define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */ +#define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */ +#define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */ +#define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */ +#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */ +#define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */ +#define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */ +#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */ +#define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt Status Register */ +#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */ + +#define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */ +#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */ +#define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */ +#define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */ +#define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */ +#define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */ +#define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */ +#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */ +#define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */ +#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */ +#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */ +#define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt Status Register */ +#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */ + +#define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */ +#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */ +#define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */ +#define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */ +#define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */ +#define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */ +#define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */ +#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */ +#define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */ +#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */ +#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */ +#define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt Status Register */ +#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */ + +#define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */ +#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */ +#define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */ +#define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */ +#define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */ +#define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */ +#define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */ +#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */ +#define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */ +#define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */ +#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */ +#define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt Status Register */ +#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */ + +#define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */ +#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */ +#define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */ +#define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */ +#define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */ +#define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */ +#define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */ +#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */ +#define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */ +#define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */ +#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */ +#define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt Status Register */ +#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */ + +#define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */ +#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */ +#define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */ +#define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */ +#define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */ +#define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */ +#define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */ +#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */ +#define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */ +#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */ +#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */ +#define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt Status Register */ +#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */ + +#define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */ +#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */ +#define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */ +#define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */ +#define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */ +#define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */ +#define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */ +#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */ +#define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */ +#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */ +#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */ +#define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt Status Register */ +#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */ + +#define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */ +#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */ +#define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */ +#define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */ +#define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */ +#define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */ +#define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */ +#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */ +#define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */ +#define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */ +#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */ +#define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt Status Register */ +#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */ + +#define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */ +#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */ +#define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */ +#define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */ +#define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */ +#define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */ +#define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */ +#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */ +#define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */ +#define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */ +#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */ +#define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt Status Register */ +#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */ + +#define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */ +#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */ +#define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */ +#define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */ +#define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */ +#define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */ +#define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */ +#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */ +#define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */ +#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */ +#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */ +#define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt Status Register */ +#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */ + +#define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */ +#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */ +#define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */ +#define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */ +#define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */ +#define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */ +#define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */ +#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */ +#define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */ +#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */ +#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */ +#define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt Status Register */ +#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */ + +/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ +#define MDMA2_D0_CONFIG 0xFFC00F08 /* MemDMA2 Stream 0 Destination Configuration register */ +#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */ +#define MDMA2_D0_START_ADDR 0xFFC00F04 /* MemDMA2 Stream 0 Destination Start Address */ +#define MDMA2_D0_X_COUNT 0xFFC00F10 /* MemDMA2 Stream 0 Dest Inner-Loop Count register */ +#define MDMA2_D0_Y_COUNT 0xFFC00F18 /* MemDMA2 Stream 0 Dest Outer-Loop Count register */ +#define MDMA2_D0_X_MODIFY 0xFFC00F14 /* MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */ +#define MDMA2_D0_Y_MODIFY 0xFFC00F1C /* MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */ +#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */ +#define MDMA2_D0_CURR_ADDR 0xFFC00F24 /* MemDMA2 Stream 0 Destination Current Address */ +#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */ +#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */ +#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA2 Stream 0 Dest Interrupt/Status Register */ +#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA2 Stream 0 Destination Peripheral Map register */ + +#define MDMA2_S0_CONFIG 0xFFC00F48 /* MemDMA2 Stream 0 Source Configuration register */ +#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */ +#define MDMA2_S0_START_ADDR 0xFFC00F44 /* MemDMA2 Stream 0 Source Start Address */ +#define MDMA2_S0_X_COUNT 0xFFC00F50 /* MemDMA2 Stream 0 Source Inner-Loop Count register */ +#define MDMA2_S0_Y_COUNT 0xFFC00F58 /* MemDMA2 Stream 0 Source Outer-Loop Count register */ +#define MDMA2_S0_X_MODIFY 0xFFC00F54 /* MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */ +#define MDMA2_S0_Y_MODIFY 0xFFC00F5C /* MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */ +#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA2 Stream 0 Source Current Descriptor Ptr reg */ +#define MDMA2_S0_CURR_ADDR 0xFFC00F64 /* MemDMA2 Stream 0 Source Current Address */ +#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA2 Stream 0 Src Current Inner-Loop Count reg */ +#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA2 Stream 0 Src Current Outer-Loop Count reg */ +#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA2 Stream 0 Source Interrupt/Status Register */ +#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA2 Stream 0 Source Peripheral Map register */ + +#define MDMA2_D1_CONFIG 0xFFC00F88 /* MemDMA2 Stream 1 Destination Configuration register */ +#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */ +#define MDMA2_D1_START_ADDR 0xFFC00F84 /* MemDMA2 Stream 1 Destination Start Address */ +#define MDMA2_D1_X_COUNT 0xFFC00F90 /* MemDMA2 Stream 1 Dest Inner-Loop Count register */ +#define MDMA2_D1_Y_COUNT 0xFFC00F98 /* MemDMA2 Stream 1 Dest Outer-Loop Count register */ +#define MDMA2_D1_X_MODIFY 0xFFC00F94 /* MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */ +#define MDMA2_D1_Y_MODIFY 0xFFC00F9C /* MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */ +#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA2 Stream 1 Destination Current Descriptor Ptr */ +#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA2 Stream 1 Destination Current Address reg */ +#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */ +#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */ +#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA2 Stream 1 Destination Interrupt/Status Reg */ +#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA2 Stream 1 Destination Peripheral Map register */ + +#define MDMA2_S1_CONFIG 0xFFC00FC8 /* MemDMA2 Stream 1 Source Configuration register */ +#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */ +#define MDMA2_S1_START_ADDR 0xFFC00FC4 /* MemDMA2 Stream 1 Source Start Address */ +#define MDMA2_S1_X_COUNT 0xFFC00FD0 /* MemDMA2 Stream 1 Source Inner-Loop Count register */ +#define MDMA2_S1_Y_COUNT 0xFFC00FD8 /* MemDMA2 Stream 1 Source Outer-Loop Count register */ +#define MDMA2_S1_X_MODIFY 0xFFC00FD4 /* MemDMA2 Stream 1 Src Inner-Loop Address-Increment */ +#define MDMA2_S1_Y_MODIFY 0xFFC00FDC /* MemDMA2 Stream 1 Source Outer-Loop Address-Increment */ +#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA2 Stream 1 Source Current Descriptor Ptr reg */ +#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA2 Stream 1 Source Current Address */ +#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA2 Stream 1 Source Current Inner-Loop Count */ +#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA2 Stream 1 Source Current Outer-Loop Count */ +#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA2 Stream 1 Source Interrupt/Status Register */ +#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA2 Stream 1 Source Peripheral Map register */ + +/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ +#define IMDMA_D0_CONFIG 0xFFC01808 /* IMDMA Stream 0 Destination Configuration */ +#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /* IMDMA Stream 0 Destination Next Descriptor Ptr Reg */ +#define IMDMA_D0_START_ADDR 0xFFC01804 /* IMDMA Stream 0 Destination Start Address */ +#define IMDMA_D0_X_COUNT 0xFFC01810 /* IMDMA Stream 0 Destination Inner-Loop Count */ +#define IMDMA_D0_Y_COUNT 0xFFC01818 /* IMDMA Stream 0 Destination Outer-Loop Count */ +#define IMDMA_D0_X_MODIFY 0xFFC01814 /* IMDMA Stream 0 Dest Inner-Loop Address-Increment */ +#define IMDMA_D0_Y_MODIFY 0xFFC0181C /* IMDMA Stream 0 Dest Outer-Loop Address-Increment */ +#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /* IMDMA Stream 0 Destination Current Descriptor Ptr */ +#define IMDMA_D0_CURR_ADDR 0xFFC01824 /* IMDMA Stream 0 Destination Current Address */ +#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /* IMDMA Stream 0 Destination Current Inner-Loop Count */ +#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /* IMDMA Stream 0 Destination Current Outer-Loop Count */ +#define IMDMA_D0_IRQ_STATUS 0xFFC01828 /* IMDMA Stream 0 Destination Interrupt/Status */ + +#define IMDMA_S0_CONFIG 0xFFC01848 /* IMDMA Stream 0 Source Configuration */ +#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 /* IMDMA Stream 0 Source Next Descriptor Ptr Reg */ +#define IMDMA_S0_START_ADDR 0xFFC01844 /* IMDMA Stream 0 Source Start Address */ +#define IMDMA_S0_X_COUNT 0xFFC01850 /* IMDMA Stream 0 Source Inner-Loop Count */ +#define IMDMA_S0_Y_COUNT 0xFFC01858 /* IMDMA Stream 0 Source Outer-Loop Count */ +#define IMDMA_S0_X_MODIFY 0xFFC01854 /* IMDMA Stream 0 Source Inner-Loop Address-Increment */ +#define IMDMA_S0_Y_MODIFY 0xFFC0185C /* IMDMA Stream 0 Source Outer-Loop Address-Increment */ +#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /* IMDMA Stream 0 Source Current Descriptor Ptr reg */ +#define IMDMA_S0_CURR_ADDR 0xFFC01864 /* IMDMA Stream 0 Source Current Address */ +#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /* IMDMA Stream 0 Source Current Inner-Loop Count */ +#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /* IMDMA Stream 0 Source Current Outer-Loop Count */ +#define IMDMA_S0_IRQ_STATUS 0xFFC01868 /* IMDMA Stream 0 Source Interrupt/Status */ + +#define IMDMA_D1_CONFIG 0xFFC01888 /* IMDMA Stream 1 Destination Configuration */ +#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /* IMDMA Stream 1 Destination Next Descriptor Ptr Reg */ +#define IMDMA_D1_START_ADDR 0xFFC01884 /* IMDMA Stream 1 Destination Start Address */ +#define IMDMA_D1_X_COUNT 0xFFC01890 /* IMDMA Stream 1 Destination Inner-Loop Count */ +#define IMDMA_D1_Y_COUNT 0xFFC01898 /* IMDMA Stream 1 Destination Outer-Loop Count */ +#define IMDMA_D1_X_MODIFY 0xFFC01894 /* IMDMA Stream 1 Dest Inner-Loop Address-Increment */ +#define IMDMA_D1_Y_MODIFY 0xFFC0189C /* IMDMA Stream 1 Dest Outer-Loop Address-Increment */ +#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /* IMDMA Stream 1 Destination Current Descriptor Ptr */ +#define IMDMA_D1_CURR_ADDR 0xFFC018A4 /* IMDMA Stream 1 Destination Current Address */ +#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /* IMDMA Stream 1 Destination Current Inner-Loop Count */ +#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /* IMDMA Stream 1 Destination Current Outer-Loop Count */ +#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /* IMDMA Stream 1 Destination Interrupt/Status */ + +#define IMDMA_S1_CONFIG 0xFFC018C8 /* IMDMA Stream 1 Source Configuration */ +#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /* IMDMA Stream 1 Source Next Descriptor Ptr Reg */ +#define IMDMA_S1_START_ADDR 0xFFC018C4 /* IMDMA Stream 1 Source Start Address */ +#define IMDMA_S1_X_COUNT 0xFFC018D0 /* IMDMA Stream 1 Source Inner-Loop Count */ +#define IMDMA_S1_Y_COUNT 0xFFC018D8 /* IMDMA Stream 1 Source Outer-Loop Count */ +#define IMDMA_S1_X_MODIFY 0xFFC018D4 /* IMDMA Stream 1 Source Inner-Loop Address-Increment */ +#define IMDMA_S1_Y_MODIFY 0xFFC018DC /* IMDMA Stream 1 Source Outer-Loop Address-Increment */ +#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /* IMDMA Stream 1 Source Current Descriptor Ptr reg */ +#define IMDMA_S1_CURR_ADDR 0xFFC018E4 /* IMDMA Stream 1 Source Current Address */ +#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /* IMDMA Stream 1 Source Current Inner-Loop Count */ +#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /* IMDMA Stream 1 Source Current Outer-Loop Count */ +#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /* IMDMA Stream 1 Source Interrupt/Status */ + +/* + * System MMR Register Bits + */ + +/* PLL AND RESET MASKS */ + +/* PLL_CTL Masks */ +#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ +#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ +#define PLL_OFF 0x00000002 /* Shut off PLL clocks */ +#define STOPCK_OFF 0x00000008 /* Core clock off */ +#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ +#define BYPASS 0x00000100 /* Bypass the PLL */ + +/* PLL_DIV Masks */ + +#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ + +#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ + +/* SWRST Mask */ +#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ +#define SWRST_DBL_FAULT_B 0x00000800 /* SWRST Core B Double Fault */ +#define SWRST_DBL_FAULT_A 0x00001000 /* SWRST Core A Double Fault */ +#define SWRST_WDT_B 0x00002000 /* SWRST Watchdog B */ +#define SWRST_WDT_A 0x00004000 /* SWRST Watchdog A */ +#define SWRST_OCCURRED 0x00008000 /* SWRST Status */ + +/* + * SYSTEM INTERRUPT CONTROLLER MASKS + * SICu_IARv Masks + * u = A or B + * v = 0 to 7 + * w = 0 or 1 + + * Per_number = 0 to 63 + * IVG_number = 7 to 15 + * Peripheral #Per_number assigned IVG #IVG_number + * Usage: + * r0.l = lo(Peripheral_IVG(62, 10)); + * r0.h = hi(Peripheral_IVG(62, 10)); + */ +#define Peripheral_IVG(Per_number, IVG_number) \ + ( (IVG_number) -7) << ( ((Per_number)%8) *4) + +/* SICx_IMASKw Masks */ +/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */ +#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ +#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ +#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ +#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x)))/* Unmask Peripheral #x interrupt */ + +/* SIC_IWR Masks */ +#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ +#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ +/* x = pos 0 to 31, for 32-63 use value-32 */ +#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ +/* Wakeup Disable Peripheral #x */ +#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) + +/* + * WATCHDOG TIMER MASKS + */ + +/* Watchdog Timer WDOG_CTL Register */ +#define WDOGA_CTL 0xFFC00200 +#define WDOGA_CNT 0xFFC00204 +#define WDOGA_STAT 0xFFC00208 +#define WDOGB_CTL 0xFFC01200 +#define WDOGB_CNT 0xFFC01204 +#define WDOGB_STAT 0xFFC01208 +#define ICTL(x) ((x<<1) & 0x0006) +#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */ +#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */ +#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */ +#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */ + +#define TMR_EN 0x0000 +#define TMR_DIS 0x0AD0 +#define TRO 0x8000 + +#define ICTL_P0 0x01 +#define ICTL_P1 0x02 +#define TRO_P 0x0F + +/* + * UART CONTROLLER MASKS + */ + +/* UART_LCR Register */ + +#define DLAB 0x80 +#define SB 0x40 +#define STP 0x20 +#define EPS 0x10 +#define PEN 0x08 +#define STB 0x04 +#define WLS(x) ((x-5) & 0x03) + +#define DLAB_P 0x07 +#define SB_P 0x06 +#define STP_P 0x05 +#define EPS_P 0x04 +#define PEN_P 0x03 +#define STB_P 0x02 +#define WLS_P1 0x01 +#define WLS_P0 0x00 + +/* UART_MCR Register */ +#define LOOP_ENA 0x10 +#define LOOP_ENA_P 0x04 + +/* UART_LSR Register */ +#define TEMT 0x40 +#define THRE 0x20 +#define BI 0x10 +#define FE 0x08 +#define PE 0x04 +#define OE 0x02 +#define DR 0x01 + +#define TEMP_P 0x06 +#define THRE_P 0x05 +#define BI_P 0x04 +#define FE_P 0x03 +#define PE_P 0x02 +#define OE_P 0x01 +#define DR_P 0x00 + +/* UART_IER Register */ +#define ELSI 0x04 +#define ETBEI 0x02 +#define ERBFI 0x01 + +#define ELSI_P 0x02 +#define ETBEI_P 0x01 +#define ERBFI_P 0x00 + +/* UART_IIR Register */ +#define STATUS(x) ((x << 1) & 0x06) +#define NINT 0x01 +#define STATUS_P1 0x02 +#define STATUS_P0 0x01 +#define NINT_P 0x00 + +/* UART_GCTL Register */ +#define FFE 0x20 +#define FPE 0x10 +#define RPOLC 0x08 +#define TPOLC 0x04 +#define IREN 0x02 +#define UCEN 0x01 + +#define FFE_P 0x05 +#define FPE_P 0x04 +#define RPOLC_P 0x03 +#define TPOLC_P 0x02 +#define IREN_P 0x01 +#define UCEN_P 0x00 + +/* + * SERIAL PORT MASKS + */ + +/* SPORTx_TCR1 Masks */ +#define TSPEN 0x0001 /* TX enable */ +#define ITCLK 0x0002 /* Internal TX Clock Select */ +#define TDTYPE 0x000C /* TX Data Formatting Select */ +#define TLSBIT 0x0010 /* TX Bit Order */ +#define ITFS 0x0200 /* Internal TX Frame Sync Select */ +#define TFSR 0x0400 /* TX Frame Sync Required Select */ +#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ +#define LTFS 0x1000 /* Low TX Frame Sync Select */ +#define LATFS 0x2000 /* Late TX Frame Sync Select */ +#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ + +/* SPORTx_TCR2 Masks */ +#define SLEN 0x001F /* TX Word Length */ +#define TXSE 0x0100 /* TX Secondary Enable */ +#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */ +#define TRFST 0x0400 /* TX Right-First Data Order */ + +/* SPORTx_RCR1 Masks */ +#define RSPEN 0x0001 /* RX enable */ +#define IRCLK 0x0002 /* Internal RX Clock Select */ +#define RDTYPE 0x000C /* RX Data Formatting Select */ +#define RULAW 0x0008 /* u-Law enable */ +#define RALAW 0x000C /* A-Law enable */ +#define RLSBIT 0x0010 /* RX Bit Order */ +#define IRFS 0x0200 /* Internal RX Frame Sync Select */ +#define RFSR 0x0400 /* RX Frame Sync Required Select */ +#define LRFS 0x1000 /* Low RX Frame Sync Select */ +#define LARFS 0x2000 /* Late RX Frame Sync Select */ +#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ + +/* SPORTx_RCR2 Masks */ +#define SLEN 0x001F /* RX Word Length */ +#define RXSE 0x0100 /* RX Secondary Enable */ +#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ +#define RRFST 0x0400 /* Right-First Data Order */ + +/* SPORTx_STAT Masks */ +#define RXNE 0x0001 /* RX FIFO Not Empty Status */ +#define RUVF 0x0002 /* RX Underflow Status */ +#define ROVF 0x0004 /* RX Overflow Status */ +#define TXF 0x0008 /* TX FIFO Full Status */ +#define TUVF 0x0010 /* TX Underflow Status */ +#define TOVF 0x0020 /* TX Overflow Status */ +#define TXHRE 0x0040 /* TX Hold Register Empty */ + +/* SPORTx_MCMC1 Masks */ +#define WSIZE 0x0000F000 /* Multichannel Window Size Field */ +#define WOFF 0x000003FF /* Multichannel Window Offset Field */ + +/* SPORTx_MCMC2 Masks */ +#define MCCRM 0x00000003 /* Multichannel Clock Recovery Mode */ +#define MCDTXPE 0x00000004 /* Multichannel DMA Transmit Packing */ +#define MCDRXPE 0x00000008 /* Multichannel DMA Receive Packing */ +#define MCMEN 0x00000010 /* Multichannel Frame Mode Enable */ +#define FSDR 0x00000080 /* Multichannel Frame Sync to Data Relationship */ +#define MFD 0x0000F000 /* Multichannel Frame Delay */ + +/* + * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS + */ + +/* PPI_CONTROL Masks */ +#define PORT_EN 0x00000001 /* PPI Port Enable */ +#define PORT_DIR 0x00000002 /* PPI Port Direction */ +#define XFR_TYPE 0x0000000C /* PPI Transfer Type */ +#define PORT_CFG 0x00000030 /* PPI Port Configuration */ +#define FLD_SEL 0x00000040 /* PPI Active Field Select */ +#define PACK_EN 0x00000080 /* PPI Packing Mode */ +#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ +#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ +#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ +#define DLENGTH 0x00003800 /* PPI Data Length */ +#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ +#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ +#define POL 0x0000C000 /* PPI Signal Polarities */ + +/* PPI_STATUS Masks */ +#define FLD 0x00000400 /* Field Indicator */ +#define FT_ERR 0x00000800 /* Frame Track Error */ +#define OVR 0x00001000 /* FIFO Overflow Error */ +#define UNDR 0x00002000 /* FIFO Underrun Error */ +#define ERR_DET 0x00004000 /* Error Detected Indicator */ +#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ + +/* + * DMA CONTROLLER MASKS + */ + +/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */ +#define DMAEN 0x00000001 /* Channel Enable */ +#define WNR 0x00000002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x00000000 /* Word Size 8 bits */ +#define WDSIZE_16 0x00000004 /* Word Size 16 bits */ +#define WDSIZE_32 0x00000008 /* Word Size 32 bits */ +#define DMA2D 0x00000010 /* 2D/1D* Mode */ +#define RESTART 0x00000020 /* Restart */ +#define DI_SEL 0x00000040 /* Data Interrupt Select */ +#define DI_EN 0x00000080 /* Data Interrupt Enable */ +#define NDSIZE 0x00000900 /* Next Descriptor Size */ +#define FLOW 0x00007000 /* Flow Control */ + +#define DMAEN_P 0 /* Channel Enable */ +#define WNR_P 1 /* Channel Direction (W/R*) */ +#define DMA2D_P 4 /* 2D/1D* Mode */ +#define RESTART_P 5 /* Restart */ +#define DI_SEL_P 6 /* Data Interrupt Select */ +#define DI_EN_P 7 /* Data Interrupt Enable */ + +/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */ + +#define DMA_DONE 0x00000001 /* DMA Done Indicator */ +#define DMA_ERR 0x00000002 /* DMA Error Indicator */ +#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ +#define DMA_RUN 0x00000008 /* DMA Running Indicator */ + +#define DMA_DONE_P 0 /* DMA Done Indicator */ +#define DMA_ERR_P 1 /* DMA Error Indicator */ +#define DFETCH_P 2 /* Descriptor Fetch Indicator */ +#define DMA_RUN_P 3 /* DMA Running Indicator */ + +/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */ + +#define CTYPE 0x00000040 /* DMA Channel Type Indicator */ +#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ +#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ +#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ +#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ +#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ +#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ +#define PMAP 0x00007000 /* DMA Peripheral Map Field */ + +/* + * GENERAL PURPOSE TIMER MASKS + */ + +/* PWM Timer bit definitions */ + +/* TIMER_ENABLE Register */ +#define TIMEN0 0x0001 +#define TIMEN1 0x0002 +#define TIMEN2 0x0004 +#define TIMEN3 0x0008 +#define TIMEN4 0x0010 +#define TIMEN5 0x0020 +#define TIMEN6 0x0040 +#define TIMEN7 0x0080 +#define TIMEN8 0x0001 +#define TIMEN9 0x0002 +#define TIMEN10 0x0004 +#define TIMEN11 0x0008 + +#define TIMEN0_P 0x00 +#define TIMEN1_P 0x01 +#define TIMEN2_P 0x02 +#define TIMEN3_P 0x03 +#define TIMEN4_P 0x04 +#define TIMEN5_P 0x05 +#define TIMEN6_P 0x06 +#define TIMEN7_P 0x07 +#define TIMEN8_P 0x00 +#define TIMEN9_P 0x01 +#define TIMEN10_P 0x02 +#define TIMEN11_P 0x03 + +/* TIMER_DISABLE Register */ +#define TIMDIS0 0x0001 +#define TIMDIS1 0x0002 +#define TIMDIS2 0x0004 +#define TIMDIS3 0x0008 +#define TIMDIS4 0x0010 +#define TIMDIS5 0x0020 +#define TIMDIS6 0x0040 +#define TIMDIS7 0x0080 +#define TIMDIS8 0x0001 +#define TIMDIS9 0x0002 +#define TIMDIS10 0x0004 +#define TIMDIS11 0x0008 + +#define TIMDIS0_P 0x00 +#define TIMDIS1_P 0x01 +#define TIMDIS2_P 0x02 +#define TIMDIS3_P 0x03 +#define TIMDIS4_P 0x04 +#define TIMDIS5_P 0x05 +#define TIMDIS6_P 0x06 +#define TIMDIS7_P 0x07 +#define TIMDIS8_P 0x00 +#define TIMDIS9_P 0x01 +#define TIMDIS10_P 0x02 +#define TIMDIS11_P 0x03 + +/* TIMER_STATUS Register */ +#define TIMIL0 0x00000001 +#define TIMIL1 0x00000002 +#define TIMIL2 0x00000004 +#define TIMIL3 0x00000008 +#define TIMIL4 0x00010000 +#define TIMIL5 0x00020000 +#define TIMIL6 0x00040000 +#define TIMIL7 0x00080000 +#define TIMIL8 0x0001 +#define TIMIL9 0x0002 +#define TIMIL10 0x0004 +#define TIMIL11 0x0008 +#define TOVL_ERR0 0x00000010 +#define TOVL_ERR1 0x00000020 +#define TOVL_ERR2 0x00000040 +#define TOVL_ERR3 0x00000080 +#define TOVL_ERR4 0x00100000 +#define TOVL_ERR5 0x00200000 +#define TOVL_ERR6 0x00400000 +#define TOVL_ERR7 0x00800000 +#define TOVL_ERR8 0x0010 +#define TOVL_ERR9 0x0020 +#define TOVL_ERR10 0x0040 +#define TOVL_ERR11 0x0080 +#define TRUN0 0x00001000 +#define TRUN1 0x00002000 +#define TRUN2 0x00004000 +#define TRUN3 0x00008000 +#define TRUN4 0x10000000 +#define TRUN5 0x20000000 +#define TRUN6 0x40000000 +#define TRUN7 0x80000000 +#define TRUN8 0x1000 +#define TRUN9 0x2000 +#define TRUN10 0x4000 +#define TRUN11 0x8000 + +#define TIMIL0_P 0x00 +#define TIMIL1_P 0x01 +#define TIMIL2_P 0x02 +#define TIMIL3_P 0x03 +#define TIMIL4_P 0x10 +#define TIMIL5_P 0x11 +#define TIMIL6_P 0x12 +#define TIMIL7_P 0x13 +#define TIMIL8_P 0x00 +#define TIMIL9_P 0x01 +#define TIMIL10_P 0x02 +#define TIMIL11_P 0x03 +#define TOVL_ERR0_P 0x04 +#define TOVL_ERR1_P 0x05 +#define TOVL_ERR2_P 0x06 +#define TOVL_ERR3_P 0x07 +#define TOVL_ERR4_P 0x14 +#define TOVL_ERR5_P 0x15 +#define TOVL_ERR6_P 0x16 +#define TOVL_ERR7_P 0x17 +#define TOVL_ERR8_P 0x04 +#define TOVL_ERR9_P 0x05 +#define TOVL_ERR10_P 0x06 +#define TOVL_ERR11_P 0x07 +#define TRUN0_P 0x0C +#define TRUN1_P 0x0D +#define TRUN2_P 0x0E +#define TRUN3_P 0x0F +#define TRUN4_P 0x1C +#define TRUN5_P 0x1D +#define TRUN6_P 0x1E +#define TRUN7_P 0x1F +#define TRUN8_P 0x0C +#define TRUN9_P 0x0D +#define TRUN10_P 0x0E +#define TRUN11_P 0x0F + +/* TIMERx_CONFIG Registers */ +#define PWM_OUT 0x0001 +#define WDTH_CAP 0x0002 +#define EXT_CLK 0x0003 +#define PULSE_HI 0x0004 +#define PERIOD_CNT 0x0008 +#define IRQ_ENA 0x0010 +#define TIN_SEL 0x0020 +#define OUT_DIS 0x0040 +#define CLK_SEL 0x0080 +#define TOGGLE_HI 0x0100 +#define EMU_RUN 0x0200 +#define ERR_TYP(x) ((x & 0x03) << 14) + +#define TMODE_P0 0x00 +#define TMODE_P1 0x01 +#define PULSE_HI_P 0x02 +#define PERIOD_CNT_P 0x03 +#define IRQ_ENA_P 0x04 +#define TIN_SEL_P 0x05 +#define OUT_DIS_P 0x06 +#define CLK_SEL_P 0x07 +#define TOGGLE_HI_P 0x08 +#define EMU_RUN_P 0x09 +#define ERR_TYP_P0 0x0E +#define ERR_TYP_P1 0x0F + +/* + * PROGRAMMABLE FLAG MASKS + */ + +/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ +#define PF0 0x0001 +#define PF1 0x0002 +#define PF2 0x0004 +#define PF3 0x0008 +#define PF4 0x0010 +#define PF5 0x0020 +#define PF6 0x0040 +#define PF7 0x0080 +#define PF8 0x0100 +#define PF9 0x0200 +#define PF10 0x0400 +#define PF11 0x0800 +#define PF12 0x1000 +#define PF13 0x2000 +#define PF14 0x4000 +#define PF15 0x8000 + +/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ +#define PF0_P 0 +#define PF1_P 1 +#define PF2_P 2 +#define PF3_P 3 +#define PF4_P 4 +#define PF5_P 5 +#define PF6_P 6 +#define PF7_P 7 +#define PF8_P 8 +#define PF9_P 9 +#define PF10_P 10 +#define PF11_P 11 +#define PF12_P 12 +#define PF13_P 13 +#define PF14_P 14 +#define PF15_P 15 + +/* + * SERIAL PERIPHERAL INTERFACE (SPI) MASKS + */ + +/* SPI_CTL Masks */ +#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ +#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ +#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ +#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ +#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ +#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ +#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ + +/* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer.*/ +#define CPHA 0x00000400 +#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ +#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ +#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ +#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ + +/* SPI_FLG Masks */ +#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ +#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ + +/* SPI_FLG Bit Positions */ +#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ +#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ + +/* SPI_STAT Masks */ +#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ +#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */ +#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ +#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ +#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ +#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ +#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ + +/* + * ASYNCHRONOUS MEMORY CONTROLLER MASKS + */ + +/* AMGCTL Masks */ +#define AMCKEN 0x0001 /* Enable CLKOUT */ +#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */ +#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */ +#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0,/ 1, and 2 */ +#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ +#define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */ +#define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */ +#define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */ +#define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */ + +/* AMGCTL Bit Positions */ +#define AMCKEN_P 0x00000000 /* Enable CLKOUT */ +#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ +#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ +#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ +#define B0_PEN_P 0x004 /* Enable 16-bit packing Bank 0 */ +#define B1_PEN_P 0x005 /* Enable 16-bit packing Bank 1 */ +#define B2_PEN_P 0x006 /* Enable 16-bit packing Bank 2 */ +#define B3_PEN_P 0x007 /* Enable 16-bit packing Bank 3 */ + +/* AMBCTL0 Masks */ +#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ +#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ +#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ +#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ +#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ +#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ +#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ +#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ +#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ +#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ +#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ +#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ +#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ +#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ +#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ +#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ +#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ +#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ +#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ +#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ +#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ +#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ +#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ +#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ +#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ +#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ +#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ +#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ +#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ +#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ +#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ +#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ +#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ +#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ +#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ +#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ +#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ +#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ +#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ +#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ +#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ +#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ +#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ +#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ +#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ +#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ +#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ +#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ +#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ +#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ +#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ +#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ +#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ +#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ +#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ +#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ +#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ +#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ +#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ +#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ +#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ +#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ +#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ +#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ +#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ +#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ +#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ +#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ +#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ +#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ +#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ +#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ +#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ +#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ +#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ +#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ +#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ +#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ +#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ +#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ + +/* AMBCTL1 Masks */ +#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ +#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ +#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ +#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ +#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ +#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ +#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ +#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ +#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ +#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ +#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ +#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ +#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ +#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ +#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ +#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ +#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ +#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ +#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ +#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ +#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ +#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ +#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ +#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ +#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ +#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ +#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ +#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ +#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ +#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ +#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ +#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ +#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ +#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ +#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ +#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ +#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ +#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ +#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ +#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ +#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ +#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ +#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ +#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ +#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ +#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ +#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ +#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ +#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ +#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ +#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ +#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ +#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ +#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ +#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ +#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ +#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ +#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ +#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ +#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ +#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ +#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ +#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ +#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ +#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ +#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ +#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ +#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ +#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ +#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ +#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ +#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ + +/* + * SDRAM CONTROLLER MASKS + */ + +/* EBIU_SDGCTL Masks */ +#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ +#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ +#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ +#define PFE 0x00000010 /* Enable SDRAM prefetch */ +#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ +#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ +#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ +#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ +#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ +#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ +#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ +#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ +#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ +#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ +#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ +#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ +#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ +#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ +#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ +#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ +#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ +#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ +#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ +#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ +#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ +#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ +#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ +#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ +#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ +#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ +#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ +#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ +#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ +#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ +#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ +#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ +#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ +#define PUPSD 0x00200000 /* Power-up start delay */ +#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ +#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ +#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ +#define EBUFE 0x02000000 /* Enable external buffering timing */ +#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ +#define EMREN 0x10000000 /* Extended mode register enable */ +#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ +#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ + +/* EBIU_SDBCTL Masks */ +#define EB0_E 0x00000001 /* Enable SDRAM external bank 0 */ +#define EB0_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ +#define EB0_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */ +#define EB0_SZ_64 0x00000004 /* SDRAM external bank size = 64MB */ +#define EB0_SZ_128 0x00000006 /* SDRAM external bank size = 128MB */ +#define EB0_CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ +#define EB0_CAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ +#define EB0_CAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ +#define EB0_CAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ + +#define EB1_E 0x00000100 /* Enable SDRAM external bank 1 */ +#define EB1__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ +#define EB1__SZ_32 0x00000200 /* SDRAM external bank size = 32MB */ +#define EB1__SZ_64 0x00000400 /* SDRAM external bank size = 64MB */ +#define EB1__SZ_128 0x00000600 /* SDRAM external bank size = 128MB */ +#define EB1__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ +#define EB1__CAW_9 0x00001000 /* SDRAM external bank column address width = 9 bits */ +#define EB1__CAW_10 0x00002000 /* SDRAM external bank column address width = 9 bits */ +#define EB1__CAW_11 0x00003000 /* SDRAM external bank column address width = 9 bits */ + +#define EB2__E 0x00010000 /* Enable SDRAM external bank 2 */ +#define EB2__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ +#define EB2__SZ_32 0x00020000 /* SDRAM external bank size = 32MB */ +#define EB2__SZ_64 0x00040000 /* SDRAM external bank size = 64MB */ +#define EB2__SZ_128 0x00060000 /* SDRAM external bank size = 128MB */ +#define EB2__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ +#define EB2__CAW_9 0x00100000 /* SDRAM external bank column address width = 9 bits */ +#define EB2__CAW_10 0x00200000 /* SDRAM external bank column address width = 9 bits */ +#define EB2__CAW_11 0x00300000 /* SDRAM external bank column address width = 9 bits */ + +#define EB3__E 0x01000000 /* Enable SDRAM external bank 3 */ +#define EB3__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ +#define EB3__SZ_32 0x02000000 /* SDRAM external bank size = 32MB */ +#define EB3__SZ_64 0x04000000 /* SDRAM external bank size = 64MB */ +#define EB3__SZ_128 0x06000000 /* SDRAM external bank size = 128MB */ +#define EB3__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ +#define EB3__CAW_9 0x10000000 /* SDRAM external bank column address width = 9 bits */ +#define EB3__CAW_10 0x20000000 /* SDRAM external bank column address width = 9 bits */ +#define EB3__CAW_11 0x30000000 /* SDRAM external bank column address width = 9 bits */ + +/* EBIU_SDSTAT Masks */ +#define SDCI 0x00000001 /* SDRAM controller is idle */ +#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ +#define SDPUA 0x00000004 /* SDRAM power up active */ +#define SDRS 0x00000008 /* SDRAM is in reset state */ +#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ +#define BGSTAT 0x00000020 /* Bus granted */ + +#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ +#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ + +/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ +#define WDOG_CTL 0xFFC00200 /* Watchdog Control register */ +#define WDOG_CNT 0xFFC00204 /* Watchdog Count register */ +#define WDOG_STAT 0xFFC00208 /* Watchdog Status register */ + +/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ +#define FIO_FLAG_D 0xFFC00700 /* Flag Data register */ +#define FIO_FLAG_C 0xFFC00704 /* Flag Clear register */ +#define FIO_FLAG_S 0xFFC00708 /* Flag Set register */ +#define FIO_FLAG_T 0xFFC0070C /* Flag Toggle register */ +#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */ +#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */ +#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */ +#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */ +#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */ +#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */ +#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */ +#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */ +#define FIO_DIR 0xFFC00730 /* Flag Direction register */ +#define FIO_POLAR 0xFFC00734 /* Flag Polarity register */ +#define FIO_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */ +#define FIO_BOTH 0xFFC0073C /* Flag Set on Both Edges register */ +#define FIO_INEN 0xFFC00740 /* Flag Input Enable register */ + +/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */ +#define PPI_CONTROL 0xFFC01000 /* PPI0 Control register */ +#define PPI_STATUS 0xFFC01004 /* PPI0 Status register */ +#define PPI_COUNT 0xFFC01008 /* PPI0 Transfer Count register */ +#define PPI_DELAY 0xFFC0100C /* PPI0 Delay Count register */ +#define PPI_FRAME 0xFFC01010 /* PPI0 Frame Length register */ + +/* + * System Reset and Interrupt Controller registers for + * core A (0xFFC0 0100-0xFFC0 01FF) + */ +#define SWRST 0xFFC00100 /* Software Reset register */ +#define SYSCR 0xFFC00104 /* System Reset Configuration register */ +#define RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ +#define SIC_SWRST 0xFFC00100 /* Software Reset register */ +#define SIC_SYSCR 0xFFC00104 /* System Reset Configuration register */ +#define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ +#define SIC_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */ +#define SIC_IAR 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ +#define SIC_ISR 0xFFC00114 /* SIC Interrupt Status register 0 */ +#define SIC_IWR 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ + +/* EBIU_SDBCTL Masks */ +#define EB_E 0x00000001 /* Enable SDRAM external bank 0 */ +#define EB_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ +#define EB_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */ +#define EB_SZ_64 0x00000004 /* SDRAM external bank size = 64MB */ +#define EB_SZ_128 0x00000006 /* SDRAM external bank size = 128MB */ +#define EB_CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ +#define EB_CAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ +#define EB_CAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ +#define EB_CAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ + +/* EBIU_SDBCTL Masks */ +#define EBE 0x00000001 /* Enable SDRAM external bank 0 */ +#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ +#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ +#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ +#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ +#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ +#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ +#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ +#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ + +/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ +#define MDMA_D0_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration */ +#define MDMA_D0_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */ +#define MDMA_D0_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address */ +#define MDMA_D0_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination Inner-Loop Count */ +#define MDMA_D0_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Outer-Loop Count */ +#define MDMA_D0_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */ +#define MDMA_D0_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */ +#define MDMA_D0_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */ +#define MDMA_D0_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address */ +#define MDMA_D0_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Dest Current Inner-Loop Count */ +#define MDMA_D0_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Dest Current Outer-Loop Count */ +#define MDMA_D0_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status */ +#define MDMA_D0_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map */ + +#define MDMA_S0_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration */ +#define MDMA_S0_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */ +#define MDMA_S0_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address */ +#define MDMA_S0_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source Inner-Loop Count */ +#define MDMA_S0_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Outer-Loop Count */ +#define MDMA_S0_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source Inner-Loop Address-Increment */ +#define MDMA_S0_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Outer-Loop Address-Increment */ +#define MDMA_S0_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Ptr reg */ +#define MDMA_S0_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address */ +#define MDMA_S0_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current Inner-Loop Count */ +#define MDMA_S0_CURR_Y_COUNT ` 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Outer-Loop Count */ +#define MDMA_S0_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status */ +#define MDMA_S0_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map */ + +#define MDMA_D1_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration */ +#define MDMA_D1_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */ +#define MDMA_D1_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address */ +#define MDMA_D1_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination Inner-Loop Count */ +#define MDMA_D1_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Outer-Loop Count */ +#define MDMA_D1_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */ +#define MDMA_D1_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */ +#define MDMA_D1_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */ +#define MDMA_D1_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Dest Current Address */ +#define MDMA_D1_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Dest Current Inner-Loop Count */ +#define MDMA_D1_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Dest Current Outer-Loop Count */ +#define MDMA_D1_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Dest Interrupt/Status */ +#define MDMA_D1_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Dest Peripheral Map */ + +#define MDMA_S1_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration */ +#define MDMA_S1_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */ +#define MDMA_S1_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address */ +#define MDMA_S1_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source Inner-Loop Count */ +#define MDMA_S1_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Outer-Loop Count */ +#define MDMA_S1_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source Inner-Loop Address-Increment */ +#define MDMA_S1_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Outer-Loop Address-Increment */ +#define MDMA_S1_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Ptr reg */ +#define MDMA_S1_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address */ +#define MDMA_S1_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current Inner-Loop Count */ +#define MDMA_S1_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Outer-Loop Count */ +#define MDMA_S1_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status */ +#define MDMA_S1_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map */ + +#define DMA0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */ +#define DMA0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */ +#define DMA0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */ +#define DMA0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */ +#define DMA0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */ +#define DMA0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */ +#define DMA0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */ +#define DMA0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */ +#define DMA0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */ +#define DMA0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */ +#define DMA0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */ +#define DMA0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt Status Register */ +#define DMA0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */ + +#define DMA1_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */ +#define DMA1_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */ +#define DMA1_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */ +#define DMA1_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */ +#define DMA1_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */ +#define DMA1_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */ +#define DMA1_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */ +#define DMA1_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */ +#define DMA1_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */ +#define DMA1_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */ +#define DMA1_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */ +#define DMA1_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt /Status Register */ +#define DMA1_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */ + +#define DMA2_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */ +#define DMA2_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */ +#define DMA2_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */ +#define DMA2_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */ +#define DMA2_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */ +#define DMA2_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */ +#define DMA2_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */ +#define DMA2_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */ +#define DMA2_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */ +#define DMA2_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */ +#define DMA2_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */ +#define DMA2_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt /Status Register */ +#define DMA2_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */ + +#define DMA3_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */ +#define DMA3_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */ +#define DMA3_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */ +#define DMA3_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */ +#define DMA3_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */ +#define DMA3_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */ +#define DMA3_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */ +#define DMA3_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */ +#define DMA3_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */ +#define DMA3_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */ +#define DMA3_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */ +#define DMA3_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt /Status Register */ +#define DMA3_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */ + +#define DMA4_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */ +#define DMA4_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */ +#define DMA4_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */ +#define DMA4_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */ +#define DMA4_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */ +#define DMA4_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */ +#define DMA4_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */ +#define DMA4_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */ +#define DMA4_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */ +#define DMA4_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */ +#define DMA4_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */ +#define DMA4_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt /Status Register */ +#define DMA4_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */ + +#define DMA5_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */ +#define DMA5_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */ +#define DMA5_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */ +#define DMA5_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */ +#define DMA5_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */ +#define DMA5_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */ +#define DMA5_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */ +#define DMA5_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */ +#define DMA5_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */ +#define DMA5_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */ +#define DMA5_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */ +#define DMA5_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt /Status Register */ +#define DMA5_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */ + +#define DMA6_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */ +#define DMA6_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */ +#define DMA6_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */ +#define DMA6_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */ +#define DMA6_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */ +#define DMA6_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */ +#define DMA6_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */ +#define DMA6_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */ +#define DMA6_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */ +#define DMA6_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */ +#define DMA6_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */ +#define DMA6_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt /Status Register */ +#define DMA6_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */ + +#define DMA7_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */ +#define DMA7_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */ +#define DMA7_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */ +#define DMA7_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */ +#define DMA7_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */ +#define DMA7_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */ +#define DMA7_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */ +#define DMA7_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */ +#define DMA7_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */ +#define DMA7_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */ +#define DMA7_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */ +#define DMA7_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt /Status Register */ +#define DMA7_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */ + +#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ +#define TIMER_DISABLE 0xFFC00684 /* Timer Disable register */ +#define TIMER_STATUS 0xFFC00688 /* Timer Status register */ + +/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */ +#define WDSIZE8 0x00000000 /* Word Size 8 bits */ +#define WDSIZE16 0x00000004 /* Word Size 16 bits */ +#define WDSIZE32 0x00000008 /* Word Size 32 bits */ + +#endif /* _DEF_BF561_H */ diff --git a/include/asm-blackfin/arch-bf561/defBF561_extn.h b/include/asm-blackfin/arch-bf561/defBF561_extn.h new file mode 100644 index 0000000000..b309b748de --- /dev/null +++ b/include/asm-blackfin/arch-bf561/defBF561_extn.h @@ -0,0 +1,76 @@ +/* + * defBF561_extn.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _DEF_BF561_EXTN_H +#define _DEF_BF561_EXTN_H + +#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */ +/* Delay inserted for PLL transition */ +#define PLL_DELAY 0x1000 + +#define L1_ISRAM 0xFFA00000 +#define L1_ISRAM_END 0xFFA10000 +#define DATA_BANKA_SRAM 0xFF800000 +#define DATA_BANKA_SRAM_END 0xFF808000 +#define DATA_BANKB_SRAM 0xFF900000 +#define DATA_BANKB_SRAM_END 0xFF908000 +#define SYSMMR_BASE 0xFFC00000 +#define WDSIZE16 0x00000004 + +/* Event Vector Table Address */ +#define EVT_EMULATION_ADDR 0xffe02000 +#define EVT_RESET_ADDR 0xffe02004 +#define EVT_NMI_ADDR 0xffe02008 +#define EVT_EXCEPTION_ADDR 0xffe0200c +#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010 +#define EVT_HARDWARE_ERROR_ADDR 0xffe02014 +#define EVT_TIMER_ADDR 0xffe02018 +#define EVT_IVG7_ADDR 0xffe0201c +#define EVT_IVG8_ADDR 0xffe02020 +#define EVT_IVG9_ADDR 0xffe02024 +#define EVT_IVG10_ADDR 0xffe02028 +#define EVT_IVG11_ADDR 0xffe0202c +#define EVT_IVG12_ADDR 0xffe02030 +#define EVT_IVG13_ADDR 0xffe02034 +#define EVT_IVG14_ADDR 0xffe02038 +#define EVT_IVG15_ADDR 0xffe0203c +#define EVT_OVERRIDE_ADDR 0xffe02100 + +/* IMASK Bit values */ +#define IVG15_POS 0x00008000 +#define IVG14_POS 0x00004000 +#define IVG13_POS 0x00002000 +#define IVG12_POS 0x00001000 +#define IVG11_POS 0x00000800 +#define IVG10_POS 0x00000400 +#define IVG9_POS 0x00000200 +#define IVG8_POS 0x00000100 +#define IVG7_POS 0x00000080 +#define IVGTMR_POS 0x00000040 +#define IVGHW_POS 0x00000020 + +#define WDOG_TMR_DISABLE (0xAD << 4) +#define ICTL_RST 0x00000000 +#define ICTL_NMI 0x00000002 +#define ICTL_GP 0x00000004 +#define ICTL_DISABLE 0x00000003 + +/* Watch Dog timer values setup */ +#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE + +#endif /* _DEF_BF561_EXTN_H */ diff --git a/include/asm-blackfin/arch-bf561/irq.h b/include/asm-blackfin/arch-bf561/irq.h new file mode 100644 index 0000000000..2f7dd99e7d --- /dev/null +++ b/include/asm-blackfin/arch-bf561/irq.h @@ -0,0 +1,137 @@ +/* + * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + * Changed by HuTao Apr18, 2003 + * + * Copyright was missing when I got the code so took from MIPS arch ...MaTed--- + * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle + * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle + * + * Adapted for BlackFin (ADI) by Ted Ma + * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) + * Copyright (c) 2002 Lineo, Inc. + * + * Adapted for BlackFin BF533 by Bas Vermeulen + * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl) + * Copyright (c) 2004 LG Soft India. + * Copyright (c) 2004 HHTech. + * + * Adapted for BlackFin BF561 by Bas Vermeulen + * Copyright (c) 2005 BuyWays B.V. (www.buyways.nl) + */ + +#ifndef _BF561_IRQ_H_ +#define _BF561_IRQ_H_ + +/* + * Interrupt source definitions: + * Event Source Core Event Name IRQ No + * Emulation Events EMU 0 + * Reset RST 1 + * NMI NMI 2 + * Exception EVX 3 + * Reserved -- 4 + * Hardware Error IVHW 5 + * Core Timer IVTMR 6 + * + * PLL Wakeup Interrupt IVG7 7 + * DMA1 Error (generic) IVG7 8 + * DMA2 Error (generic) IVG7 9 + * IMDMA Error (generic) IVG7 10 + * PPI1 Error Interrupt IVG7 11 + * PPI2 Error Interrupt IVG7 12 + * SPORT0 Error Interrupt IVG7 13 + * SPORT1 Error Interrupt IVG7 14 + * SPI Error Interrupt IVG7 15 + * UART Error Interrupt IVG7 16 + * Reserved Interrupt IVG7 17 + * + * DMA1 0 Interrupt(PPI1) IVG8 18 + * DMA1 1 Interrupt(PPI2) IVG8 19 + * DMA1 2 Interrupt IVG8 20 + * DMA1 3 Interrupt IVG8 21 + * DMA1 4 Interrupt IVG8 22 + * DMA1 5 Interrupt IVG8 23 + * DMA1 6 Interrupt IVG8 24 + * DMA1 7 Interrupt IVG8 25 + * DMA1 8 Interrupt IVG8 26 + * DMA1 9 Interrupt IVG8 27 + * DMA1 10 Interrupt IVG8 28 + * DMA1 11 Interrupt IVG8 29 + * + * DMA2 0 (SPORT0 RX) IVG9 30 + * DMA2 1 (SPORT0 TX) IVG9 31 + * DMA2 2 (SPORT1 RX) IVG9 32 + * DMA2 3 (SPORT2 TX) IVG9 33 + * DMA2 4 (SPI) IVG9 34 + * DMA2 5 (UART RX) IVG9 35 + * DMA2 6 (UART TX) IVG9 36 + * DMA2 7 Interrupt IVG9 37 + * DMA2 8 Interrupt IVG9 38 + * DMA2 9 Interrupt IVG9 39 + * DMA2 10 Interrupt IVG9 40 + * DMA2 11 Interrupt IVG9 41 + * + * TIMER 0 Interrupt IVG10 42 + * TIMER 1 Interrupt IVG10 43 + * TIMER 2 Interrupt IVG10 44 + * TIMER 3 Interrupt IVG10 45 + * TIMER 4 Interrupt IVG10 46 + * TIMER 5 Interrupt IVG10 47 + * TIMER 6 Interrupt IVG10 48 + * TIMER 7 Interrupt IVG10 49 + * TIMER 8 Interrupt IVG10 50 + * TIMER 9 Interrupt IVG10 51 + * TIMER 10 Interrupt IVG10 52 + * TIMER 11 Interrupt IVG10 53 + * + * Programmable Flags0 A (8) IVG11 54 + * Programmable Flags0 B (8) IVG11 55 + * Programmable Flags1 A (8) IVG11 56 + * Programmable Flags1 B (8) IVG11 57 + * Programmable Flags2 A (8) IVG11 58 + * Programmable Flags2 B (8) IVG11 59 + * + * MDMA1 0 write/read INT IVG8 60 + * MDMA1 1 write/read INT IVG8 61 + * + * MDMA2 0 write/read INT IVG9 62 + * MDMA2 1 write/read INT IVG9 63 + * + * IMDMA 0 write/read INT IVG12 64 + * IMDMA 1 write/read INT IVG12 65 + * + * Watch Dog Timer IVG13 66 + * + * Reserved interrupt IVG7 67 + * Reserved interrupt IVG7 68 + * Supplemental interrupt 0 IVG7 69 + * supplemental interrupt 1 IVG7 70 + * + * Software Interrupt 1 IVG14 71 + * Software Interrupt 2 IVG15 72 + */ + +/* + * The ABSTRACT IRQ definitions + * the first seven of the following are fixed, + * the rest you change if you need to. + */ +/* IVG 0-6 */ +#define IRQ_EMU 0 /* Emulation */ +#define IRQ_RST 1 /* Reset */ +#define IRQ_NMI 2 /* Non Maskable Interrupt */ +#define IRQ_EVX 3 /* Exception */ +#define IRQ_UNUSED 4 /* Reserved interrupt */ +#define IRQ_HWERR 5 /* Hardware Error */ +#define IRQ_CORETMR 6 /* Core timer */ + +#define IRQ_UART_RX_BIT 0x10000000 +#define IRQ_UART_TX_BIT 0x20000000 +#define IRQ_UART_ERROR_BIT 0x200 + +#endif /* _BF561_IRQ_H_ */ diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h new file mode 100644 index 0000000000..8d826faaa0 --- /dev/null +++ b/include/configs/bf561-ezkit.h @@ -0,0 +1,244 @@ +/* + * U-boot - Configuration file for BF561 EZKIT board + */ + +#ifndef __CONFIG_EZKIT561_H__ +#define __CONFIG_EZKIT561_H__ + +#define CONFIG_VDSP 1 +#define CONFIG_BF561 1 + +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_BAUDRATE 57600 +/* Set default serial console for bf537 */ +#define CONFIG_UART_CONSOLE 0 +#define CONFIG_EZKIT561 1 +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_PANIC_HANG 1 + +/* +* Boot Mode Set +* Blackfin can support several boot modes +*/ +#define BF561_BYPASS_BOOT 0x21 +#define BF561_PARA_BOOT 0x22 +#define BF561_SPI_BOOT 0x24 +/* Define the boot mode */ +#define BFIN_BOOT_MODE BF561_BYPASS_BOOT + +/* This sets the default state of the cache on U-Boot's boot */ +#define CONFIG_ICACHE_ON +#define CONFIG_DCACHE_ON + +/* Define where the uboot will be loaded by on-chip boot rom */ +#define APP_ENTRY 0x00001000 + +/* + * Stringize definitions - needed for environmental settings + */ +#define STRINGIZE2(x) #x +#define STRINGIZE(x) STRINGIZE2(x) + +/* + * Board settings + */ +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x2C010300 +#define CONFIG_ASYNC_EBIU_BASE CONFIG_SMC91111_BASE & ~(4*1024*1024) +#define CONFIG_SMC_USE_32_BIT 1 +#define CONFIG_MISC_INIT_R 1 + +/* + * Clock settings + */ + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 30000000 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 20 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 +/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ +/* Values can range from 2-65535 */ +/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ +#define CONFIG_SPI_BAUD 2 +#define CONFIG_SPI_BAUD_INITBLOCK 4 + +/* + * Network settings + */ +#if (CONFIG_DRIVER_SMC91111) +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME ezkit561 +#define CONFIG_ROOTPATH /arm-cross-build/BF561/uClinux-dist/romfs +#endif /* CONFIG_DRIVER_SMC91111 */ + +/* + * Flash settings + */ + +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_FLASH_BASE 0x20000000 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 135 /* max number of sectors on one chip */ +#define CFG_ENV_ADDR 0x20020000 +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ +/* JFFS Partition offset set */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CFG_JFFS2_FIRST_SECTOR 8 + +/* + * SDRAM settings & memory map + */ + +#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC16M16A2TG_75 1 + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024) + +#define CFG_MEMTEST_START 0x0 /* memtest works on */ +#define CFG_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024*1024) /* 1 ... 63 MB in DRAM */ + +#define CONFIG_LOADADDR 0x01000000 /* default load address */ +#define CFG_LOAD_ADDR CONFIG_LOADADDR +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) + +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) + +#define CFG_GBL_DATA_SIZE 0x4000 +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#if ( CONFIG_CLKIN_HALF == 0 ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#else +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#endif + +#if (CONFIG_PLL_BYPASS == 0) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +/* + * Command settings + */ + +#define CFG_AUTOLOAD "no" /* rarpb, bootp, dhcp commands will */ + /* only perform a configuration */ + /* lookup from the BOOTP/DHCP server */ + /* but not try to load any image */ + /* using TFTP */ +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, */ + /* currently its disabled */ +#define CONFIG_BOOTCOMMAND "run ramboot" +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600" + +#if (CONFIG_DRIVER_SMC91111) +#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DHCP) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \ + "$(rootpath) console=ttyBF0,57600\0" \ + "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ + "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \ + "ramboot=tftpboot $(loadaddr) linux; " \ + "run ramargs; run addip; bootelf\0" \ + "nfsboot=tftpboot $(loadaddr) linux; " \ + "run nfsargs; run addip; bootelf\0" \ + "update=tftpboot $(loadaddr) u-boot.bin; " \ + "protect off 0x20000000 0x2003FFFF; " \ + "erase 0x20000000 0x2003FFFF; " \ + "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \ + "" +#else +#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ + CFG_CMD_ELF | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "flashboot=bootm 0x20100000\0" \ + "" +#endif + +#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2 ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Console settings + */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_LOADS_ECHO 1 + +/* + * Miscellaneous configurable options + */ +#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ +#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ + +/* + * FLASH organization and environment definitions + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define AMGCTLVAL 0x3F +#define AMBCTL0VAL 0x7BB07BB0 +#define AMBCTL1VAL 0xFFC27BB0 + +#ifdef CONFIG_VDSP +#define ET_EXEC_VDSP 0x8 +#define SHT_STRTAB_VDSP 0x1 +#define ELFSHDRSIZE_VDSP 0x2C +#define VDSP_ENTRY_ADDR 0xFFA00000 +#endif + +#endif /* __CONFIG_EZKIT561_H__ */ -- cgit v1.2.1 From e01bd218b00af73499331a1a701625a852cd286f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 21 Mar 2007 13:38:59 +0100 Subject: [PATCH] Add AMCC PPC405EZ support This patch adds support for the new AMCC 405EZ PPC. It is in preparation for the AMCC Acadia board support. Please note that this Acadia/405EZ support is still in a beta stage. Still lot's of cleanup needed but we need a preliminary release now. Signed-off-by: Stefan Roese --- include/asm-ppc/processor.h | 9 + include/asm-ppc/u-boot.h | 4 +- include/ppc405.h | 540 ++++++++++++++++++++++++++++++++++++++++++++ include/ppc4xx_enet.h | 217 +++++++++--------- 4 files changed, 656 insertions(+), 114 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index ad9fd49ad4..058596275f 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -298,6 +298,10 @@ #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ +#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ +#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ +#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ +#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ @@ -529,6 +533,10 @@ #define SPRG1 SPRN_SPRG1 #define SPRG2 SPRN_SPRG2 #define SPRG3 SPRN_SPRG3 +#define SPRG4 SPRN_SPRG4 +#define SPRG5 SPRN_SPRG5 +#define SPRG6 SPRN_SPRG6 +#define SPRG7 SPRN_SPRG7 #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ #define SVR SPRN_SVR /* System Version Register */ @@ -731,6 +739,7 @@ #define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ #define PVR_405EP_RA 0x51210950 #define PVR_405GPR_RB 0x50910951 +#define PVR_405EZ_RA 0x41511460 #define PVR_440GP_RB 0x40120440 #define PVR_440GP_RC 0x40120481 #define PVR_440EP_RA 0x42221850 diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index 30b44e3d22..464f6b5756 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -83,6 +83,7 @@ typedef struct bd_info { defined(CONFIG_405GP) || \ defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || \ + defined(CONFIG_405EZ) || \ defined(CONFIG_440) unsigned char bi_s_version[4]; /* Version of this structure */ unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ @@ -107,7 +108,8 @@ typedef struct bd_info { unsigned char bi_enet3addr[6]; #endif -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \ +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ + defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) unsigned int bi_opbfreq; /* OPB clock in Hz */ diff --git a/include/ppc405.h b/include/ppc405.h index a49912cabb..08f10d27b2 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -117,6 +117,48 @@ /*-----------------------------------------------------------------------------+ | Universal interrupt controller interrupts +-----------------------------------------------------------------------------*/ +#if defined(CONFIG_405EZ) +#define UIC_DMA0 0x80000000 /* DMA chan. 0 */ +#define UIC_DMA1 0x40000000 /* DMA chan. 1 */ +#define UIC_DMA2 0x20000000 /* DMA chan. 2 */ +#define UIC_DMA3 0x10000000 /* DMA chan. 3 */ +#define UIC_1588 0x08000000 /* IEEE 1588 network synchronization */ +#define UIC_UART0 0x04000000 /* UART 0 */ +#define UIC_UART1 0x02000000 /* UART 1 */ +#define UIC_CAN0 0x01000000 /* CAN 0 */ +#define UIC_CAN1 0x00800000 /* CAN 1 */ +#define UIC_SPI 0x00400000 /* SPI */ +#define UIC_IIC 0x00200000 /* IIC */ +#define UIC_CHT0 0x00100000 /* Chameleon timer high pri interrupt */ +#define UIC_CHT1 0x00080000 /* Chameleon timer high pri interrupt */ +#define UIC_USBH1 0x00040000 /* USB Host 1 */ +#define UIC_USBH2 0x00020000 /* USB Host 2 */ +#define UIC_USBDEV 0x00010000 /* USB Device */ +#define UIC_ENET 0x00008000 /* Ethernet interrupt status */ +#define UIC_ENET1 0x00008000 /* dummy define */ +#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */ + +#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */ +#define UIC_MAL_SERR 0x00002000 /* MAL SERR */ +#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */ +#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */ + +#define UIC_MAL_TXEOB 0x00001000 /* MAL TXEOB */ +#define UIC_MAL_TXEOB1 0x00000800 /* MAL TXEOB1 */ +#define UIC_MAL_RXEOB 0x00000400 /* MAL RXEOB */ +#define UIC_NAND 0x00000200 /* NAND Flash controller */ +#define UIC_ADC 0x00000100 /* ADC */ +#define UIC_DAC 0x00000080 /* DAC */ +#define UIC_OPB2PLB 0x00000040 /* OPB to PLB bridge interrupt */ +#define UIC_RESERVED0 0x00000020 /* Reserved */ +#define UIC_EXT0 0x00000010 /* External interrupt 0 */ +#define UIC_EXT1 0x00000008 /* External interrupt 1 */ +#define UIC_EXT2 0x00000004 /* External interrupt 2 */ +#define UIC_EXT3 0x00000002 /* External interrupt 3 */ +#define UIC_EXT4 0x00000001 /* External interrupt 4 */ + +#else /* !defined(CONFIG_405EZ) */ + #define UIC_UART0 0x80000000 /* UART 0 */ #define UIC_UART1 0x40000000 /* UART 1 */ #define UIC_IIC 0x20000000 /* IIC */ @@ -144,6 +186,7 @@ #define UIC_EXT4 0x00000004 /* External interrupt 4 */ #define UIC_EXT5 0x00000002 /* External interrupt 5 */ #define UIC_EXT6 0x00000001 /* External interrupt 6 */ +#endif /* defined(CONFIG_405EZ) */ /****************************************************************************** * SDRAM Controller @@ -496,6 +539,325 @@ */ #define VCO_MIN 500 #define VCO_MAX 1000 +#elif defined(CONFIG_405EZ) +/****************************************************************************** + * SDR Registers + ******************************************************************************/ +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */ +#define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */ + +#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data) +#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd) + +#define sdrnand0 0x4000 +#define sdrultra0 0x4040 +#define sdrultra1 0x4050 +#define sdricintstat 0x4510 + +#define SDR_NAND0_NDEN 0x80000000 + +#define SDR_ULTRA0_NDGPIOBP 0x80000000 +#define SDR_ULTRA0_CSN_MASK 0x78000000 +#define SDR_ULTRA0_CSNSEL0 0x40000000 +#define SDR_ULTRA0_CSNSEL1 0x20000000 +#define SDR_ULTRA0_CSNSEL2 0x10000000 +#define SDR_ULTRA0_CSNSEL3 0x08000000 + +#define SDR_ULTRA1_LEDNENABLE 0x40000000 + +#define SDR_ICRX_STAT 0x80000000 +#define SDR_ICTX0_STAT 0x40000000 +#define SDR_ICTX1_STAT 0x20000000 + +/****************************************************************************** + * Control + ******************************************************************************/ +#define CNTRL_DCR_BASE 0x0C +#define cprcfga (CNTRL_DCR_BASE+0x0) /* CPR addr reg */ +#define cprcfgd (CNTRL_DCR_BASE+0x1) /* CPR data reg */ + +/* CPR Registers */ +#define cprclkupd 0x020 /* CPR_CLKUPD */ +#define cprpllc 0x040 /* CPR_PLLC */ +#define cprplld 0x060 /* CPR_PLLD */ +#define cprprimad 0x080 /* CPR_PRIMAD */ +#define cprperd0 0x0e0 /* CPR_PERD0 */ +#define cprperd1 0x0e1 /* CPR_PERD1 */ +#define cprperc0 0x180 /* CPR_PERC0 */ +#define cprmisc0 0x181 /* CPR_MISC0 */ +#define cprmisc1 0x182 /* CPR_MISC1 */ + +/* + * Macro for accessing the indirect CPR register + */ +#define mtcpr(reg, data) mtdcr(cprcfga,reg);mtdcr(cprcfgd,data) +#define mfcpr(reg, data) mtdcr(cprcfga,reg);data = mfdcr(cprcfgd) + +#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ +#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ +#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ + +#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ +#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ + +#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */ +#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */ +#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */ +#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */ + +#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */ +#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */ +#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ +#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ + +#if 0 /* Deprecated */ +#define CNTRL_DCR_BASE 0x0f0 +#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ +#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ +#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ +#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ +#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ +#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ + +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ +#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ +#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ +#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ +#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ +#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ + +/* Bit definitions */ +#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ +#define PLLMR0_CPU_DIV_BYPASS 0x00000000 +#define PLLMR0_CPU_DIV_2 0x00100000 +#define PLLMR0_CPU_DIV_3 0x00200000 +#define PLLMR0_CPU_DIV_4 0x00300000 + +#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ +#define PLLMR0_CPU_PLB_DIV_1 0x00000000 +#define PLLMR0_CPU_PLB_DIV_2 0x00010000 +#define PLLMR0_CPU_PLB_DIV_3 0x00020000 +#define PLLMR0_CPU_PLB_DIV_4 0x00030000 + +#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ +#define PLLMR0_OPB_PLB_DIV_1 0x00000000 +#define PLLMR0_OPB_PLB_DIV_2 0x00001000 +#define PLLMR0_OPB_PLB_DIV_3 0x00002000 +#define PLLMR0_OPB_PLB_DIV_4 0x00003000 + +#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ +#define PLLMR0_EXB_PLB_DIV_2 0x00000000 +#define PLLMR0_EXB_PLB_DIV_3 0x00000100 +#define PLLMR0_EXB_PLB_DIV_4 0x00000200 +#define PLLMR0_EXB_PLB_DIV_5 0x00000300 + +#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ +#define PLLMR0_MAL_PLB_DIV_1 0x00000000 +#define PLLMR0_MAL_PLB_DIV_2 0x00000010 +#define PLLMR0_MAL_PLB_DIV_3 0x00000020 +#define PLLMR0_MAL_PLB_DIV_4 0x00000030 + +#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ +#define PLLMR0_PCI_PLB_DIV_1 0x00000000 +#define PLLMR0_PCI_PLB_DIV_2 0x00000001 +#define PLLMR0_PCI_PLB_DIV_3 0x00000002 +#define PLLMR0_PCI_PLB_DIV_4 0x00000003 + +#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ +#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ +#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ +#define PLLMR1_FBMUL_DIV_16 0x00000000 +#define PLLMR1_FBMUL_DIV_1 0x00100000 +#define PLLMR1_FBMUL_DIV_2 0x00200000 +#define PLLMR1_FBMUL_DIV_3 0x00300000 +#define PLLMR1_FBMUL_DIV_4 0x00400000 +#define PLLMR1_FBMUL_DIV_5 0x00500000 +#define PLLMR1_FBMUL_DIV_6 0x00600000 +#define PLLMR1_FBMUL_DIV_7 0x00700000 +#define PLLMR1_FBMUL_DIV_8 0x00800000 +#define PLLMR1_FBMUL_DIV_9 0x00900000 +#define PLLMR1_FBMUL_DIV_10 0x00A00000 +#define PLLMR1_FBMUL_DIV_11 0x00B00000 +#define PLLMR1_FBMUL_DIV_12 0x00C00000 +#define PLLMR1_FBMUL_DIV_13 0x00D00000 +#define PLLMR1_FBMUL_DIV_14 0x00E00000 +#define PLLMR1_FBMUL_DIV_15 0x00F00000 + +#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ +#define PLLMR1_FWDVA_DIV_8 0x00000000 +#define PLLMR1_FWDVA_DIV_7 0x00010000 +#define PLLMR1_FWDVA_DIV_6 0x00020000 +#define PLLMR1_FWDVA_DIV_5 0x00030000 +#define PLLMR1_FWDVA_DIV_4 0x00040000 +#define PLLMR1_FWDVA_DIV_3 0x00050000 +#define PLLMR1_FWDVA_DIV_2 0x00060000 +#define PLLMR1_FWDVA_DIV_1 0x00070000 +#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ +#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ + +/* Defines for CPC0_EPRCSR register */ +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 + +/* Defines for CPC0_BOOR Register */ +#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ + +/* Defines for CPC0_PLLMR1 Register fields */ +#define PLL_ACTIVE 0x80000000 +#define CPC0_PLLMR1_SSCS 0x80000000 +#define PLL_RESET 0x40000000 +#define CPC0_PLLMR1_PLLR 0x40000000 + /* Feedback multiplier */ +#define PLL_FBKDIV 0x00F00000 +#define CPC0_PLLMR1_FBDV 0x00F00000 +#define PLL_FBKDIV_16 0x00000000 +#define PLL_FBKDIV_1 0x00100000 +#define PLL_FBKDIV_2 0x00200000 +#define PLL_FBKDIV_3 0x00300000 +#define PLL_FBKDIV_4 0x00400000 +#define PLL_FBKDIV_5 0x00500000 +#define PLL_FBKDIV_6 0x00600000 +#define PLL_FBKDIV_7 0x00700000 +#define PLL_FBKDIV_8 0x00800000 +#define PLL_FBKDIV_9 0x00900000 +#define PLL_FBKDIV_10 0x00A00000 +#define PLL_FBKDIV_11 0x00B00000 +#define PLL_FBKDIV_12 0x00C00000 +#define PLL_FBKDIV_13 0x00D00000 +#define PLL_FBKDIV_14 0x00E00000 +#define PLL_FBKDIV_15 0x00F00000 + /* Forward A divisor */ +#define PLL_FWDDIVA 0x00070000 +#define CPC0_PLLMR1_FWDVA 0x00070000 +#define PLL_FWDDIVA_8 0x00000000 +#define PLL_FWDDIVA_7 0x00010000 +#define PLL_FWDDIVA_6 0x00020000 +#define PLL_FWDDIVA_5 0x00030000 +#define PLL_FWDDIVA_4 0x00040000 +#define PLL_FWDDIVA_3 0x00050000 +#define PLL_FWDDIVA_2 0x00060000 +#define PLL_FWDDIVA_1 0x00070000 + /* Forward B divisor */ +#define PLL_FWDDIVB 0x00007000 +#define CPC0_PLLMR1_FWDVB 0x00007000 +#define PLL_FWDDIVB_8 0x00000000 +#define PLL_FWDDIVB_7 0x00001000 +#define PLL_FWDDIVB_6 0x00002000 +#define PLL_FWDDIVB_5 0x00003000 +#define PLL_FWDDIVB_4 0x00004000 +#define PLL_FWDDIVB_3 0x00005000 +#define PLL_FWDDIVB_2 0x00006000 +#define PLL_FWDDIVB_1 0x00007000 + /* PLL tune bits */ +#define PLL_TUNE_MASK 0x000003FF +#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ +#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ +#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ +#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ +#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ +#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ +#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ + +/* Defines for CPC0_PLLMR0 Register fields */ + /* CPU divisor */ +#define PLL_CPUDIV 0x00300000 +#define CPC0_PLLMR0_CCDV 0x00300000 +#define PLL_CPUDIV_1 0x00000000 +#define PLL_CPUDIV_2 0x00100000 +#define PLL_CPUDIV_3 0x00200000 +#define PLL_CPUDIV_4 0x00300000 + /* PLB divisor */ +#define PLL_PLBDIV 0x00030000 +#define CPC0_PLLMR0_CBDV 0x00030000 +#define PLL_PLBDIV_1 0x00000000 +#define PLL_PLBDIV_2 0x00010000 +#define PLL_PLBDIV_3 0x00020000 +#define PLL_PLBDIV_4 0x00030000 + /* OPB divisor */ +#define PLL_OPBDIV 0x00003000 +#define CPC0_PLLMR0_OPDV 0x00003000 +#define PLL_OPBDIV_1 0x00000000 +#define PLL_OPBDIV_2 0x00001000 +#define PLL_OPBDIV_3 0x00002000 +#define PLL_OPBDIV_4 0x00003000 + /* EBC divisor */ +#define PLL_EXTBUSDIV 0x00000300 +#define CPC0_PLLMR0_EPDV 0x00000300 +#define PLL_EXTBUSDIV_2 0x00000000 +#define PLL_EXTBUSDIV_3 0x00000100 +#define PLL_EXTBUSDIV_4 0x00000200 +#define PLL_EXTBUSDIV_5 0x00000300 + /* MAL divisor */ +#define PLL_MALDIV 0x00000030 +#define CPC0_PLLMR0_MPDV 0x00000030 +#define PLL_MALDIV_1 0x00000000 +#define PLL_MALDIV_2 0x00000010 +#define PLL_MALDIV_3 0x00000020 +#define PLL_MALDIV_4 0x00000030 + /* PCI divisor */ +#define PLL_PCIDIV 0x00000003 +#define CPC0_PLLMR0_PPFD 0x00000003 +#define PLL_PCIDIV_1 0x00000000 +#define PLL_PCIDIV_2 0x00000001 +#define PLL_PCIDIV_3 0x00000002 +#define PLL_PCIDIV_4 0x00000003 + +/* + *------------------------------------------------------------------------------- + * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, + * assuming a 33.3MHz input clock to the 405EP. + *------------------------------------------------------------------------------- + */ +#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +/* + * PLL Voltage Controlled Oscillator (VCO) definitions + * Maximum and minimum values (in MHz) for correct PLL operation. + */ +#define VCO_MIN 500 +#define VCO_MAX 1000 +#endif /* #if 0 */ #else /* #ifdef CONFIG_405EP */ /****************************************************************************** * Control @@ -578,6 +940,121 @@ /****************************************************************************** * Memory Access Layer ******************************************************************************/ +#if defined(CONFIG_405EZ) +#define MAL_DCR_BASE 0x380 +#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ +#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/ +#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ +#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ +#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/ +#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ +#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ +#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ +/* 0x08-0x0F Reserved */ +#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/ +#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ +#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ +#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ +/* 0x14-0x1F Reserved */ +#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */ +#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */ +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */ +#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */ +#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */ +#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */ +#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */ +#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */ +#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */ +#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */ +#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */ +#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */ +#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */ +#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */ +#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */ +#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */ +#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */ +#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */ +#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */ +#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */ +#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */ +#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */ +#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */ +#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */ +#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */ +#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */ +#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */ +#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */ +#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */ +#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */ +#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */ +#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */ +#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */ +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */ +#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */ +#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */ +#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */ +#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */ +#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */ +#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */ +#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */ +#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */ +#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */ +#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */ +#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */ +#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */ +#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */ +#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */ +#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */ +#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */ +#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */ +#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */ +#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */ +#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */ +#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */ +#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */ +#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */ +#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */ +#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */ +#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */ +#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */ +#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */ +#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */ +#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */ +#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ +#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ +#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */ +#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */ +#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */ +#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */ +#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ +#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */ +#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */ +#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */ +#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */ +#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */ +#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */ +#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */ +#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ +#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */ +#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */ +#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */ +#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */ +#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */ +#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */ +#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */ +#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ +#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */ +#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */ +#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */ +#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */ +#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */ +#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */ +#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */ + +#else /* !defined(CONFIG_405EZ) */ + #define MAL_DCR_BASE 0x180 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ @@ -598,6 +1075,7 @@ #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#endif /* defined(CONFIG_405EZ) */ /*----------------------------------------------------------------------------- | IIC Register Offsets @@ -635,15 +1113,76 @@ /****************************************************************************** * On Chip Memory ******************************************************************************/ +#if defined(CONFIG_405EZ) +#define OCM_DCR_BASE 0x020 +#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */ +#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */ +#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */ +#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */ +#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */ +#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */ +#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */ +#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */ +#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */ +#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */ +#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */ +#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */ +#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/ +#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/ +#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/ +#else #define OCM_DCR_BASE 0x018 #define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ #define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ #define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ #define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ +#endif /* CONFIG_405EZ */ /****************************************************************************** * GPIO macro register defines ******************************************************************************/ +#if defined(CONFIG_405EZ) +/* Only the 405EZ has 2 GPIOs */ +#define GPIO_BASE 0xEF600700 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_RR3 (GPIO_BASE+0x28) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) + +#define GPIO1_BASE 0xEF600800 +#define GPIO1_OR (GPIO1_BASE+0x0) +#define GPIO1_TCR (GPIO1_BASE+0x4) +#define GPIO1_OSRL (GPIO1_BASE+0x8) +#define GPIO1_OSRH (GPIO1_BASE+0xC) +#define GPIO1_TSRL (GPIO1_BASE+0x10) +#define GPIO1_TSRH (GPIO1_BASE+0x14) +#define GPIO1_ODR (GPIO1_BASE+0x18) +#define GPIO1_IR (GPIO1_BASE+0x1C) +#define GPIO1_RR1 (GPIO1_BASE+0x20) +#define GPIO1_RR2 (GPIO1_BASE+0x24) +#define GPIO1_RR3 (GPIO1_BASE+0x28) +#define GPIO1_ISR1L (GPIO1_BASE+0x30) +#define GPIO1_ISR1H (GPIO1_BASE+0x34) +#define GPIO1_ISR2L (GPIO1_BASE+0x38) +#define GPIO1_ISR2H (GPIO1_BASE+0x3C) +#define GPIO1_ISR3L (GPIO1_BASE+0x40) +#define GPIO1_ISR3H (GPIO1_BASE+0x44) + +#else /* !405EZ */ + #define GPIO_BASE 0xEF600700 #define GPIO0_OR (GPIO_BASE+0x0) #define GPIO0_TCR (GPIO_BASE+0x4) @@ -660,6 +1199,7 @@ #define GPIO0_ISR2H (GPIO_BASE+0x38) #define GPIO0_ISR2L (GPIO_BASE+0x3C) +#endif /* CONFIG_405EZ */ /* * Macro for accessing the indirect EBC register diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index 43c5ca451e..3d8ca09060 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -130,13 +130,13 @@ typedef struct emac_4xx_hw_st { #if defined(CONFIG_440GX) -#define EMAC_NUM_DEV 4 +#define EMAC_NUM_DEV 4 #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \ defined(CONFIG_NET_MULTI) && \ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) -#define EMAC_NUM_DEV 2 +#define EMAC_NUM_DEV 2 #else -#define EMAC_NUM_DEV 1 +#define EMAC_NUM_DEV 1 #endif #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */ @@ -153,16 +153,16 @@ typedef struct emac_4xx_hw_st { /*ZMII Bridge Register addresses */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00) +#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00) #else -#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780) +#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780) #endif -#define ZMII_FER (ZMII_BASE) -#define ZMII_SSR (ZMII_BASE + 4) -#define ZMII_SMIISR (ZMII_BASE + 8) +#define ZMII_FER (ZMII_BASE) +#define ZMII_SSR (ZMII_BASE + 4) +#define ZMII_SMIISR (ZMII_BASE + 8) -#define ZMII_RMII 0x22000000 -#define ZMII_MDI0 0x80000000 +#define ZMII_RMII 0x22000000 +#define ZMII_MDI0 0x80000000 /* ZMII FER Register Bit Definitions */ #define ZMII_FER_DIS (0x0) @@ -299,49 +299,41 @@ typedef struct emac_4xx_hw_st { #if defined(CONFIG_440) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00) +#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00) #else -#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) +#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) #endif #else -#define EMAC_BASE 0xEF600800 +#if defined(CONFIG_405EZ) +#define EMAC_BASE 0xEF600900 +#else +#define EMAC_BASE 0xEF600800 +#endif #endif -#define EMAC_M0 (EMAC_BASE) -#define EMAC_M1 (EMAC_BASE + 4) -#define EMAC_TXM0 (EMAC_BASE + 8) -#define EMAC_TXM1 (EMAC_BASE + 12) -#define EMAC_RXM (EMAC_BASE + 16) -#define EMAC_ISR (EMAC_BASE + 20) -#define EMAC_IER (EMAC_BASE + 24) -#define EMAC_IAH (EMAC_BASE + 28) -#define EMAC_IAL (EMAC_BASE + 32) -#define EMAC_VLAN_TPID_REG (EMAC_BASE + 36) -#define EMAC_VLAN_TCI_REG (EMAC_BASE + 40) +#define EMAC_M0 (EMAC_BASE) +#define EMAC_M1 (EMAC_BASE + 4) +#define EMAC_TXM0 (EMAC_BASE + 8) +#define EMAC_TXM1 (EMAC_BASE + 12) +#define EMAC_RXM (EMAC_BASE + 16) +#define EMAC_ISR (EMAC_BASE + 20) +#define EMAC_IER (EMAC_BASE + 24) +#define EMAC_IAH (EMAC_BASE + 28) +#define EMAC_IAL (EMAC_BASE + 32) #define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44) -#define EMAC_IND_HASH_1 (EMAC_BASE + 48) -#define EMAC_IND_HASH_2 (EMAC_BASE + 52) -#define EMAC_IND_HASH_3 (EMAC_BASE + 56) -#define EMAC_IND_HASH_4 (EMAC_BASE + 60) -#define EMAC_GRP_HASH_1 (EMAC_BASE + 64) -#define EMAC_GRP_HASH_2 (EMAC_BASE + 68) -#define EMAC_GRP_HASH_3 (EMAC_BASE + 72) -#define EMAC_GRP_HASH_4 (EMAC_BASE + 76) -#define EMAC_LST_SRC_LOW (EMAC_BASE + 80) -#define EMAC_LST_SRC_HI (EMAC_BASE + 84) #define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88) -#define EMAC_STACR (EMAC_BASE + 92) -#define EMAC_TRTR (EMAC_BASE + 96) -#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100) +#define EMAC_STACR (EMAC_BASE + 92) +#define EMAC_TRTR (EMAC_BASE + 96) +#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100) /* bit definitions */ /* MODE REG 0 */ -#define EMAC_M0_RXI (0x80000000) -#define EMAC_M0_TXI (0x40000000) -#define EMAC_M0_SRST (0x20000000) -#define EMAC_M0_TXE (0x10000000) -#define EMAC_M0_RXE (0x08000000) -#define EMAC_M0_WKE (0x04000000) +#define EMAC_M0_RXI (0x80000000) +#define EMAC_M0_TXI (0x40000000) +#define EMAC_M0_SRST (0x20000000) +#define EMAC_M0_TXE (0x10000000) +#define EMAC_M0_RXE (0x08000000) +#define EMAC_M0_WKE (0x04000000) /* on 440GX EMAC_MR1 has a different layout! */ #if defined(CONFIG_440GX) || \ @@ -351,23 +343,23 @@ typedef struct emac_4xx_hw_st { #define EMAC_M1_FDE (0x80000000) #define EMAC_M1_ILE (0x40000000) #define EMAC_M1_VLE (0x20000000) -#define EMAC_M1_EIFC (0x10000000) -#define EMAC_M1_APP (0x08000000) -#define EMAC_M1_RSVD (0x06000000) -#define EMAC_M1_IST (0x01000000) -#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */ -#define EMAC_M1_MF_100MBPS (0x00400000) -#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */ -#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */ -#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */ -#define EMAC_M1_RFS_2K (0x00100000) -#define EMAC_M1_RFS_1K (0x00080000) -#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */ -#define EMAC_M1_TX_FIFO_8K (0x00040000) -#define EMAC_M1_TX_FIFO_4K (0x00030000) +#define EMAC_M1_EIFC (0x10000000) +#define EMAC_M1_APP (0x08000000) +#define EMAC_M1_RSVD (0x06000000) +#define EMAC_M1_IST (0x01000000) +#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */ +#define EMAC_M1_MF_100MBPS (0x00400000) +#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */ +#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */ +#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */ +#define EMAC_M1_RFS_2K (0x00100000) +#define EMAC_M1_RFS_1K (0x00080000) +#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */ +#define EMAC_M1_TX_FIFO_8K (0x00040000) +#define EMAC_M1_TX_FIFO_4K (0x00030000) #define EMAC_M1_TX_FIFO_2K (0x00020000) -#define EMAC_M1_TX_FIFO_1K (0x00010000) -#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */ +#define EMAC_M1_TX_FIFO_1K (0x00010000) +#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */ #define EMAC_M1_MWSW (0x00007000) #define EMAC_M1_JUMBO_ENABLE (0x00000800) #define EMAC_M1_IPPA (0x000007c0) @@ -378,34 +370,34 @@ typedef struct emac_4xx_hw_st { #define EMAC_M1_RSVD1 (0x00000007) #else /* defined(CONFIG_440GX) */ /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */ -#define EMAC_M1_FDE 0x80000000 -#define EMAC_M1_ILE 0x40000000 -#define EMAC_M1_VLE 0x20000000 -#define EMAC_M1_EIFC 0x10000000 -#define EMAC_M1_APP 0x08000000 -#define EMAC_M1_AEMI 0x02000000 -#define EMAC_M1_IST 0x01000000 -#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */ -#define EMAC_M1_MF_100MBPS 0x00400000 -#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */ -#define EMAC_M1_RFS_2K 0x00200000 -#define EMAC_M1_RFS_1K 0x00100000 -#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */ -#define EMAC_M1_TX_FIFO_1K 0x00040000 -#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */ -#define EMAC_M1_TR0_MULTI 0x00008000 -#define EMAC_M1_TR1_DEPEND 0x00004000 -#define EMAC_M1_TR1_MULTI 0x00002000 +#define EMAC_M1_FDE 0x80000000 +#define EMAC_M1_ILE 0x40000000 +#define EMAC_M1_VLE 0x20000000 +#define EMAC_M1_EIFC 0x10000000 +#define EMAC_M1_APP 0x08000000 +#define EMAC_M1_AEMI 0x02000000 +#define EMAC_M1_IST 0x01000000 +#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */ +#define EMAC_M1_MF_100MBPS 0x00400000 +#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */ +#define EMAC_M1_RFS_2K 0x00200000 +#define EMAC_M1_RFS_1K 0x00100000 +#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */ +#define EMAC_M1_TX_FIFO_1K 0x00040000 +#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */ +#define EMAC_M1_TR0_MULTI 0x00008000 +#define EMAC_M1_TR1_DEPEND 0x00004000 +#define EMAC_M1_TR1_MULTI 0x00002000 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) -#define EMAC_M1_JUMBO_ENABLE 0x00001000 +#define EMAC_M1_JUMBO_ENABLE 0x00001000 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ #endif /* defined(CONFIG_440GX) */ /* Transmit Mode Register 0 */ -#define EMAC_TXM0_GNP0 (0x80000000) -#define EMAC_TXM0_GNP1 (0x40000000) -#define EMAC_TXM0_GNPD (0x20000000) -#define EMAC_TXM0_FC (0x10000000) +#define EMAC_TXM0_GNP0 (0x80000000) +#define EMAC_TXM0_GNP1 (0x40000000) +#define EMAC_TXM0_GNPD (0x20000000) +#define EMAC_TXM0_FC (0x10000000) /* Receive Mode Register */ #define EMAC_RMR_SP (0x80000000) @@ -427,39 +419,38 @@ typedef struct emac_4xx_hw_st { #define EMAC_ISR_PP (0x01000000) #define EMAC_ISR_BP (0x00800000) #define EMAC_ISR_RP (0x00400000) -#define EMAC_ISR_SE (0x00200000) -#define EMAC_ISR_SYE (0x00100000) -#define EMAC_ISR_BFCS (0x00080000) -#define EMAC_ISR_PTLE (0x00040000) -#define EMAC_ISR_ORE (0x00020000) -#define EMAC_ISR_IRE (0x00010000) -#define EMAC_ISR_DBDM (0x00000200) -#define EMAC_ISR_DB0 (0x00000100) -#define EMAC_ISR_SE0 (0x00000080) -#define EMAC_ISR_TE0 (0x00000040) -#define EMAC_ISR_DB1 (0x00000020) -#define EMAC_ISR_SE1 (0x00000010) -#define EMAC_ISR_TE1 (0x00000008) -#define EMAC_ISR_MOS (0x00000002) -#define EMAC_ISR_MOF (0x00000001) - +#define EMAC_ISR_SE (0x00200000) +#define EMAC_ISR_SYE (0x00100000) +#define EMAC_ISR_BFCS (0x00080000) +#define EMAC_ISR_PTLE (0x00040000) +#define EMAC_ISR_ORE (0x00020000) +#define EMAC_ISR_IRE (0x00010000) +#define EMAC_ISR_DBDM (0x00000200) +#define EMAC_ISR_DB0 (0x00000100) +#define EMAC_ISR_SE0 (0x00000080) +#define EMAC_ISR_TE0 (0x00000040) +#define EMAC_ISR_DB1 (0x00000020) +#define EMAC_ISR_SE1 (0x00000010) +#define EMAC_ISR_TE1 (0x00000008) +#define EMAC_ISR_MOS (0x00000002) +#define EMAC_ISR_MOF (0x00000001) /* STA CONTROL REG */ -#define EMAC_STACR_OC (0x00008000) -#define EMAC_STACR_PHYE (0x00004000) +#define EMAC_STACR_OC (0x00008000) +#define EMAC_STACR_PHYE (0x00004000) #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */ -#define EMAC_STACR_INDIRECT_MODE (0x00002000) -#define EMAC_STACR_WRITE (0x00000800) /* $BUC */ -#define EMAC_STACR_READ (0x00001000) /* $BUC */ -#define EMAC_STACR_OP_MASK (0x00001800) -#define EMAC_STACR_MDIO_ADDR (0x00000000) -#define EMAC_STACR_MDIO_WRITE (0x00000800) -#define EMAC_STACR_MDIO_READ (0x00001800) -#define EMAC_STACR_MDIO_READ_INC (0x00001000) +#define EMAC_STACR_INDIRECT_MODE (0x00002000) +#define EMAC_STACR_WRITE (0x00000800) /* $BUC */ +#define EMAC_STACR_READ (0x00001000) /* $BUC */ +#define EMAC_STACR_OP_MASK (0x00001800) +#define EMAC_STACR_MDIO_ADDR (0x00000000) +#define EMAC_STACR_MDIO_WRITE (0x00000800) +#define EMAC_STACR_MDIO_READ (0x00001800) +#define EMAC_STACR_MDIO_READ_INC (0x00001000) #else -#define EMAC_STACR_WRITE (0x00002000) -#define EMAC_STACR_READ (0x00001000) +#define EMAC_STACR_WRITE (0x00002000) +#define EMAC_STACR_READ (0x00001000) #endif #define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */ @@ -467,9 +458,9 @@ typedef struct emac_4xx_hw_st { #define EMAC_STACR_CLK_100MHZ (0x00000C00) /* Transmit Request Threshold Register */ -#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */ -#define EMAC_TRTR_192 (0x10000000) -#define EMAC_TRTR_128 (0x01000000) +#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */ +#define EMAC_TRTR_192 (0x10000000) +#define EMAC_TRTR_128 (0x01000000) /* the follwing defines are for the MadMAL status and control registers. */ /* For bits 0..5 look at the mal.h file */ -- cgit v1.2.1 From 16c0cc1c82081a493ab87c51980b28336ce1bce8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 21 Mar 2007 13:39:57 +0100 Subject: [PATCH] Add AMCC Acadia (405EZ) eval board support This patch adds support for the new AMCC Acadia eval board. Please note that this Acadia/405EZ support is still in a beta stage. Still lot's of cleanup needed but we need a preliminary release now. Signed-off-by: Stefan Roese --- include/configs/acadia.h | 424 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 424 insertions(+) create mode 100755 include/configs/acadia.h (limited to 'include') diff --git a/include/configs/acadia.h b/include/configs/acadia.h new file mode 100755 index 0000000000..9e02ca31b4 --- /dev/null +++ b/include/configs/acadia.h @@ -0,0 +1,424 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * acadia.h - configuration for AMCC Acadia (405EZ) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_ACADIA 1 /* Board is Acadia */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EZ 1 /* Specifc 405EZ support*/ +#undef CFG_DRAM_TEST /* Disable-takes long time */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ + +#define CONFIG_NO_SERIAL_EEPROM +/*#undef CONFIG_NO_SERIAL_EEPROM*/ + +#ifdef CONFIG_NO_SERIAL_EEPROM + +/*---------------------------------------------------------------------------- + * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, + * assuming a 66MHz input clock to the 405EZ. + *---------------------------------------------------------------------------*/ +/* #define PLLMR0_100_100_12 */ +#define PLLMR0_200_133_66 +/* #define PLLMR0_266_160_80 */ +/* #define PLLMR0_333_166_83 */ +#endif + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (384 * 1024)/* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */ + +/* + * Define here the location of the environment variables (FLASH). + * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only + * supported for backward compatibility. + */ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) + #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else + #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#endif + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=acadia\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=acadia/uImage\0" \ + "kernel_addr=fff10000\0" \ + "ramdisk_addr=fff20000\0" \ + "initrd_high=30000000\0" \ + "load=tftp 200000 acadia/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b ${fileaddr} fffc0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "kozio=bootm ffc60000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +#if 0 /* test-only */ +#define TEST_ONLY_NAND +#endif + +#ifdef TEST_ONLY_NAND +#define CMD_NAND CFG_CMD_NAND +#else +#define CMD_NAND 0 +#endif + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#define CONFIG_SUPPORT_VFAT + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DTT | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CMD_NAND | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_USB) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_BAUDRATE 115200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_AD7414 1 /* use AD7414 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +#if 0 /* test-only... */ +/*----------------------------------------------------------------------- + * SPI stuff - Define to include SPI control + *----------------------------------------------------------------------- + */ +#define CONFIG_SPI +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +#ifdef TEST_ONLY_NAND +/*----------------------------------------------------------------------- + * NAND FLASH + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE (CFG_NAND + CFG_NAND_CS) +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EZ CPU */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ +#endif + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ +#define CFG_NAND 0xd0000000 +#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ + +/* Memory Bank 0 (Flash) initialization */ +#define CFG_EBC_PB0AP 0x03337200 +#define CFG_EBC_PB0CR 0xfe0bc000 /* BAS=0xFE0,BS=32MB,BU=R/W,BW=32bit */ + +/* Memory Bank 1 (CRAM) initialization */ +#define CFG_EBC_PB1AP 0x030400c0 +#define CFG_EBC_PB1CR 0x000bc000 + +/* Memory Bank 2 (CRAM) initialization */ +#define CFG_EBC_PB2AP 0x030400c0 +#define CFG_EBC_PB2CR 0x020bc000 + +/* Memory Bank 3 (NAND-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x018003c0 +#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) + +/* Memory Bank 4 (CPLD) initialization */ +#define CFG_EBC_PB4AP 0x04006000 +#define CFG_EBC_PB4CR 0x80018000 /* BAS=0x000,BS=16MB,BU=R/W,BW=32bit */ + +#define CFG_EBC_CFG 0xf8400000 + +/*----------------------------------------------------------------------- + * Definitions for GPIO_0 setup (PPC405EZ specific) + * + * GPIO0[0-3] - External Bus Controller CS_4 - CS_7 Outputs + * GPIO0[4] - External Bus Controller Hold Input + * GPIO0[5] - External Bus Controller Priority Input + * GPIO0[6] - External Bus Controller HLDA Output + * GPIO0[7] - External Bus Controller Bus Request Output + * GPIO0[8] - CRAM Clk Output + * GPIO0[9] - External Bus Controller Ready Input + * GPIO0[10] - CRAM Adv Output + * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled + * GPIO0[25] - External DMA Request Input + * GPIO0[26] - External DMA EOT I/O + * GPIO0[25] - External DMA Ack_n Output + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[28-30] - Trace Outputs / PWM Inputs + * GPIO0[31] - PWM_8 I/O + */ +#define CFG_GPIO0_TCR 0xC0000000 +#define CFG_GPIO0_OSRL 0x50000000 +#define CFG_GPIO0_OSRH 0x00000055 +#define CFG_GPIO0_ISR1L 0x00000000 +#define CFG_GPIO0_ISR1H 0x00000055 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TSRH 0x00000055 + +/*----------------------------------------------------------------------- + * Definitions for GPIO_1 setup (PPC405EZ specific) + * + * GPIO1[0-6] - PWM_9 to PWM_15 I/O + * GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input + * GPIO1[8] - TS5 Output / DAC_IP_TRIG Input + * GPIO1[9] - TS6 Output / ADC_IP_TRIG Input + * GPIO1[10-12] - UART0 Control Inputs + * GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input + * GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output + * GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input + * GPIO1[16] - SPI_SS_1_N Output + * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs + */ +#define CFG_GPIO1_OSRH 0x55455555 +#define CFG_GPIO1_OSRL 0x40000110 +#define CFG_GPIO1_ISR1H 0x00000000 +#define CFG_GPIO1_ISR1L 0x15555445 +#define CFG_GPIO1_TSRH 0x00000000 +#define CFG_GPIO1_TSRL 0x00000000 +#define CFG_GPIO1_TCR 0xFFFF8014 + +/*----------------------------------------------------------------------- + * EPLD Regs. + */ +#define EPLD_BASE 0x80000000 +#define EPLD_ETHRSTBOOT 0x10 +#define EPLD_CTRL 0x14 +#define EPLD_MUXOE 0x16 + +/* + * State definations + */ +#define LOAK_INIT 0x494e4954 /* ASCII "INIT" */ +#define LOAK_NONE 0x4e4f4e45 /* ASCII "NONE" */ +#define LOAK_CRAM 0x4352414d /* ASCII "CRAM" */ +#define LOAK_PSRAM 0x50535241 /* ASCII "PSRA" - PSRAM */ +#define LOAK_OCM 0x4f434d20 /* ASCII "OCM " */ +#define LOAK_ZERO 0x5a45524f /* ASCII "ZERO" */ +#define LOAK_SPL 0x53504c20 /* ASCII "SPL" */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ + #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#endif /* __CONFIG_H */ -- cgit v1.2.1 From e6615ecf4eaf4dd52696934aed8f5c6474cfd286 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 21 Mar 2007 14:54:29 +0100 Subject: ppc4xx: Fix file mode of include/configs/acadia.h Signed-off-by: Stefan Roese --- include/configs/acadia.h | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 include/configs/acadia.h (limited to 'include') diff --git a/include/configs/acadia.h b/include/configs/acadia.h old mode 100755 new mode 100644 -- cgit v1.2.1 From 5a58a73ceb0a4059c42ef64cedbc1a45e0aaa00e Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Thu, 7 Dec 2006 10:32:35 -0600 Subject: Add flash cmd function to 8641HPCN ramboot Also fixes some commmand for 8641 HPCN ramboot case. Signed-off-by: Jason Jin Signed-off-by: Jon Loeliger --- include/configs/MPC8641HPCN.h | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 246ac7f316..bbe35053dd 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -212,7 +212,6 @@ #endif #if defined(CFG_RAMBOOT) -#undef CFG_FLASH_CFI_DRIVER #undef CONFIG_SPD_EEPROM #define CFG_SDRAM_SIZE 256 #endif @@ -468,7 +467,6 @@ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 #else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) #define CFG_ENV_SIZE 0x2000 @@ -486,21 +484,13 @@ | CFG_CMD_SCSI \ | CFG_CMD_EXT2) \ & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_IMLS \ - | CFG_CMD_FLASH \ - | CFG_CMD_LOADS)) + ~(CFG_CMD_ENV)) #else #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_SCSI \ - | CGF_CMD_EXT2) \ + | CFG_CMD_I2C) \ & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_IMLS \ - | CFG_CMD_FLASH \ - | CFG_CMD_LOADS)) + ~(CFG_CMD_ENV)) #endif #else #if defined(CONFIG_PCI) -- cgit v1.2.1 From 9964a4dd0d4ef5a037febaebf1aa494b1a72991c Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Thu, 7 Dec 2006 10:35:55 -0600 Subject: Set Rev 2.x 86xx PIC in mixed mode. Prevent false interrupt from hanging Linux as MSR[EE] is set to enable interrupts by changing the PIC out of the default pass through mode into mixed mode. Signed-off-by: Haiying Wang Signed-off-by: Jon Loeliger --- include/asm-ppc/immap_86xx.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index a5552c48ee..0e3fc3403d 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -721,6 +721,8 @@ typedef struct ccsr_pic { uint frr; /* 0x41000 - Feature Reporting Register */ char res10[28]; uint gcr; /* 0x41020 - Global Configuration Register */ +#define MPC86xx_PICGCR_RST 0x80000000 +#define MPC86xx_PICGCR_MODE 0x20000000 char res11[92]; uint vir; /* 0x41080 - Vendor Identification Register */ char res12[12]; -- cgit v1.2.1 From 3cb86f3e40d2a80356177434a99f75bc8baa9caf Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 24 Mar 2007 15:45:34 +0100 Subject: [PATCH] Clean up 40EZ/Acadia support This patch cleans up all the open issue of the preliminary Acadia support. Signed-off-by: Stefan Roese --- include/configs/acadia.h | 300 +++++++++++++++++++++++------------------------ include/serial.h | 2 +- 2 files changed, 149 insertions(+), 153 deletions(-) (limited to 'include') diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 9e02ca31b4..35b6a519e3 100755 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -31,20 +31,18 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_ACADIA 1 /* Board is Acadia */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_405EZ 1 /* Specifc 405EZ support*/ -#undef CFG_DRAM_TEST /* Disable-takes long time */ +#define CONFIG_ACADIA 1 /* Board is Acadia */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EZ 1 /* Specifc 405EZ support*/ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */ #define CONFIG_NO_SERIAL_EEPROM /*#undef CONFIG_NO_SERIAL_EEPROM*/ #ifdef CONFIG_NO_SERIAL_EEPROM - /*---------------------------------------------------------------------------- * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, * assuming a 66MHz input clock to the 405EZ. @@ -59,24 +57,125 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFE000000 #define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (384 * 1024)/* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */ + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xfe000000 #define CFG_MONITOR_BASE TEXT_BASE +#define CFG_CPLD_BASE 0x80000000 +#define CFG_NAND_ADDR 0xd0000000 #define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */ -/* - * Define here the location of the environment variables (FLASH). - * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only - * supported for backward compatibility. - */ +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */ + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #else - #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ #endif +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * RAM (CRAM) + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_RAM 64 /* 64MB */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_AD7414 1 /* use AD7414 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +#if 0 /* test-only... */ +/*----------------------------------------------------------------------- + * SPI stuff - Define to include SPI control + *----------------------------------------------------------------------- + */ +#define CONFIG_SPI +#endif + +/*----------------------------------------------------------------------- + * Ethernet + *----------------------------------------------------------------------*/ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 16 /* # of rx buffers & descriptors*/ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" @@ -122,13 +221,6 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - #define CONFIG_USB_OHCI #define CONFIG_USB_STORAGE @@ -166,7 +258,6 @@ CFG_CMD_PCI | \ CFG_CMD_PING | \ CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ CFG_CMD_USB) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -174,76 +265,34 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -/* +/*----------------------------------------------------------------------- * Miscellaneous configurable options - */ + *----------------------------------------------------------------------*/ #define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ -#define CFG_BASE_BAUD 691200 -#define CONFIG_BAUDRATE 115200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_AD7414 1 /* use AD7414 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CFG_DTT_MAX_TEMP 70 -#define CFG_DTT_LOW_TEMP -30 -#define CFG_DTT_HYSTERESIS 3 - -#if 0 /* test-only... */ -/*----------------------------------------------------------------------- - * SPI stuff - Define to include SPI control - *----------------------------------------------------------------------- - */ -#define CONFIG_SPI -#endif - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is @@ -251,39 +300,13 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - -#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif - #ifdef TEST_ONLY_NAND /*----------------------------------------------------------------------- * NAND FLASH *----------------------------------------------------------------------*/ #define CFG_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 -#define CFG_NAND_BASE (CFG_NAND + CFG_NAND_CS) +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #endif @@ -296,50 +319,42 @@ #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ #endif -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */ -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup - */ -#define CFG_NAND 0xd0000000 + *----------------------------------------------------------------------*/ #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ -/* Memory Bank 0 (Flash) initialization */ +/* Memory Bank 0 (Flash) initialization */ #define CFG_EBC_PB0AP 0x03337200 -#define CFG_EBC_PB0CR 0xfe0bc000 /* BAS=0xFE0,BS=32MB,BU=R/W,BW=32bit */ +#define CFG_EBC_PB0CR 0xfe0bc000 -/* Memory Bank 1 (CRAM) initialization */ +/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/ +/* Memory Bank 1 (CRAM) initialization */ #define CFG_EBC_PB1AP 0x030400c0 #define CFG_EBC_PB1CR 0x000bc000 -/* Memory Bank 2 (CRAM) initialization */ +/* Memory Bank 2 (CRAM) initialization */ #define CFG_EBC_PB2AP 0x030400c0 #define CFG_EBC_PB2CR 0x020bc000 /* Memory Bank 3 (NAND-FLASH) initialization */ #define CFG_EBC_PB3AP 0x018003c0 -#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) +#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000) -/* Memory Bank 4 (CPLD) initialization */ +/* Memory Bank 4 (CPLD) initialization */ #define CFG_EBC_PB4AP 0x04006000 -#define CFG_EBC_PB4CR 0x80018000 /* BAS=0x000,BS=16MB,BU=R/W,BW=32bit */ +#define CFG_EBC_PB4CR (CFG_CPLD_BASE | 0x18000) #define CFG_EBC_CFG 0xf8400000 +/*----------------------------------------------------------------------- + * GPIO Setup + *----------------------------------------------------------------------*/ +#define CFG_GPIO_CRAM_CLK 8 +#define CFG_GPIO_CRAM_WAIT 9 +#define CFG_GPIO_CRAM_ADV 10 +#define CFG_GPIO_CRAM_CRE (32 + 21) + /*----------------------------------------------------------------------- * Definitions for GPIO_0 setup (PPC405EZ specific) * @@ -389,25 +404,6 @@ #define CFG_GPIO1_TSRL 0x00000000 #define CFG_GPIO1_TCR 0xFFFF8014 -/*----------------------------------------------------------------------- - * EPLD Regs. - */ -#define EPLD_BASE 0x80000000 -#define EPLD_ETHRSTBOOT 0x10 -#define EPLD_CTRL 0x14 -#define EPLD_MUXOE 0x16 - -/* - * State definations - */ -#define LOAK_INIT 0x494e4954 /* ASCII "INIT" */ -#define LOAK_NONE 0x4e4f4e45 /* ASCII "NONE" */ -#define LOAK_CRAM 0x4352414d /* ASCII "CRAM" */ -#define LOAK_PSRAM 0x50535241 /* ASCII "PSRA" - PSRAM */ -#define LOAK_OCM 0x4f434d20 /* ASCII "OCM " */ -#define LOAK_ZERO 0x5a45524f /* ASCII "ZERO" */ -#define LOAK_SPL 0x53504c20 /* ASCII "SPL" */ - /* * Internal Definitions * diff --git a/include/serial.h b/include/serial.h index 48800595d7..f7412fd173 100644 --- a/include/serial.h +++ b/include/serial.h @@ -23,7 +23,7 @@ extern struct serial_device serial_scc_device; extern struct serial_device * default_serial_console (void); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ - || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx) + || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CFG_NS16550_SERIAL) -- cgit v1.2.1 From 2db633658bbf366ab0c8dad7a0727e1fb2ae6b11 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 24 Mar 2007 15:55:58 +0100 Subject: [PATCH] Small Sequoia cleanup Signed-off-by: Stefan Roese --- include/configs/sequoia.h | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 29f3b408d2..8a319250de 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -75,9 +75,7 @@ * Initial RAM & stack pointer *----------------------------------------------------------------------*/ /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ - #define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) @@ -381,9 +379,6 @@ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ -#define CFG_FLASH CFG_FLASH_BASE -#define CFG_NAND 0xD0000000 -#define CFG_CPLD 0xC0000000 /* * On Sequoia CS0 and CS3 are switched when configuring for NAND booting @@ -392,25 +387,25 @@ #define CFG_NAND_CS 3 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ #define CFG_EBC_PB0AP 0x03017200 -#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) +#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000) /* Memory Bank 3 (NAND-FLASH) initialization */ #define CFG_EBC_PB3AP 0x018003c0 -#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) +#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000) #else #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ /* Memory Bank 3 (NOR-FLASH) initialization */ #define CFG_EBC_PB3AP 0x03017200 -#define CFG_EBC_PB3CR (CFG_FLASH | 0xda000) +#define CFG_EBC_PB3CR (CFG_FLASH_BASE | 0xda000) /* Memory Bank 0 (NAND-FLASH) initialization */ #define CFG_EBC_PB0AP 0x018003c0 -#define CFG_EBC_PB0CR (CFG_NAND | 0x1c000) +#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000) #endif /* Memory Bank 2 (CPLD) initialization */ #define CFG_EBC_PB2AP 0x24814580 -#define CFG_EBC_PB2CR (CFG_CPLD | 0x38000) +#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000) /*----------------------------------------------------------------------- * NAND FLASH -- cgit v1.2.1 From 0d974d5297349504a2ddfa09314be573b5df320a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 24 Mar 2007 15:57:09 +0100 Subject: [PATCH] Add 4xx GPIO functions This patch adds some 4xx GPIO functions. It also moves some of the common code and defines into a common 4xx GPIO header file. Signed-off-by: Stefan Roese --- include/asm-ppc/gpio.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/ppc440.h | 23 --------------------- 2 files changed, 56 insertions(+), 23 deletions(-) create mode 100644 include/asm-ppc/gpio.h (limited to 'include') diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h new file mode 100644 index 0000000000..114dc92db9 --- /dev/null +++ b/include/asm-ppc/gpio.h @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* 4xx PPC's have 2 GPIO controllers */ +#if defined(CONFIG_405EZ) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define GPIO_GROUP_MAX 2 +#else +#define GPIO_GROUP_MAX 1 +#endif + +#define GPIO_MAX 32 +#define GPIO_ALT1_SEL 0x40000000 +#define GPIO_ALT2_SEL 0x80000000 +#define GPIO_ALT3_SEL 0xc0000000 +#define GPIO_IN_SEL 0x40000000 +#define GPIO_MASK 0xc0000000 + +#define GPIO_VAL(gpio) (0x80000000 >> (gpio)) + +#ifndef __ASSEMBLY__ +typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; +typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; +typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t; + +typedef struct { + unsigned long add; /* gpio core base address */ + gpio_driver_t in_out; /* Driver Setting */ + gpio_select_t alt_nb; /* Selected Alternate */ +} gpio_param_s; +#endif + +void gpio_config(int pin, int in_out, int gpio_alt, int out_val); +void gpio_write_bit(int pin, int val); +void gpio_set_chip_configuration(void); diff --git a/include/ppc440.h b/include/ppc440.h index 1c7f11c488..d8272287c3 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -3267,29 +3267,6 @@ #define GPIO1_ISR3H (GPIO1_BASE+0x44) #endif -#define GPIO_GROUP_MAX 2 -#define GPIO_MAX 32 -#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */ -#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */ -#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */ -#define GPIO_MASK 0xC0000000 /* GPIO_MASK */ -#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ - /* For the other GPIO number, you must shift */ - -#define GPIO_VAL(gpio) (0x80000000 >> (gpio)) - -#ifndef __ASSEMBLY__ - -typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; -typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; - -typedef struct { unsigned long add; /* gpio core base address */ - gpio_driver_t in_out; /* Driver Setting */ - gpio_select_t alt_nb; /* Selected Alternate */ -} gpio_param_s; - -#endif /* __ASSEMBLY__ */ - /* * Macros for accessing the indirect EBC registers */ -- cgit v1.2.1 From 430f1b0f9a670c2f13eaa52e66a10db96dd3647d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 28 Mar 2007 15:03:16 +0200 Subject: Merge some AMCC make targets to keep the top-level Makefile smaller Signed-off-by: Stefan Roese --- include/configs/sequoia.h | 1 - include/configs/yosemite.h | 1 - 2 files changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 8a319250de..1f19621f44 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -33,7 +33,6 @@ *----------------------------------------------------------------------*/ /* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ #ifndef CONFIG_RAINIER -#define CONFIG_SEQUOIA 1 /* Board is Sequoia */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ #else #define CONFIG_440GRX 1 /* Specific PPC440GRx */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 818462eede..b68ae54b94 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -32,7 +32,6 @@ *----------------------------------------------------------------------*/ /* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/ #ifndef CONFIG_YELLOWSTONE -#define CONFIG_YOSEMITE 1 /* Board is Yosemite */ #define CONFIG_440EP 1 /* Specific PPC440EP support */ #define CONFIG_HOSTNAME yosemite #else -- cgit v1.2.1 From 60723803431ac75cad085690789e433d5ab9174e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 31 Mar 2007 08:48:36 +0200 Subject: ppc4xx: Change Yucca config file to support ECC With the updated 44x DDR2 driver the Yucca board now supports ECC generation and checking. Signed-off-by: Stefan Roese --- include/configs/yucca.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/yucca.h b/include/configs/yucca.h index eb4859c3e9..7f8b0228ae 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -120,7 +120,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ #define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ -#undef CONFIG_DDR_ECC /* no ECC support for now */ +#define CONFIG_DDR_ECC 1 /* with ECC support */ /*----------------------------------------------------------------------- * I2C -- cgit v1.2.1 From 7cd5da0fe877e7171a4cdd44880bce783132871a Mon Sep 17 00:00:00 2001 From: Gerald Van Baren Date: Sat, 31 Mar 2007 11:59:59 -0400 Subject: libfdt: Import libfdt source (1 of 2) This adds the applicable libfdt source files (unmodified) and a README to explain where the source came from. --- include/fdt.h | 60 +++++++++++++++++++++++ include/libfdt.h | 135 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/libfdt_env.h | 22 +++++++++ 3 files changed, 217 insertions(+) create mode 100644 include/fdt.h create mode 100644 include/libfdt.h create mode 100644 include/libfdt_env.h (limited to 'include') diff --git a/include/fdt.h b/include/fdt.h new file mode 100644 index 0000000000..e00559ad6d --- /dev/null +++ b/include/fdt.h @@ -0,0 +1,60 @@ +#ifndef _FDT_H +#define _FDT_H + +#ifndef __ASSEMBLY__ + +struct fdt_header { + uint32_t magic; /* magic word FDT_MAGIC */ + uint32_t totalsize; /* total size of DT block */ + uint32_t off_dt_struct; /* offset to structure */ + uint32_t off_dt_strings; /* offset to strings */ + uint32_t off_mem_rsvmap; /* offset to memory reserve map */ + uint32_t version; /* format version */ + uint32_t last_comp_version; /* last compatible version */ + + /* version 2 fields below */ + uint32_t boot_cpuid_phys; /* Which physical CPU id we're + booting on */ + /* version 3 fields below */ + uint32_t size_dt_strings; /* size of the strings block */ + + /* version 17 fields below */ + uint32_t size_dt_struct; /* size of the structure block */ +}; + +struct fdt_reserve_entry { + uint64_t address; + uint64_t size; +}; + +struct fdt_node_header { + uint32_t tag; + char name[0]; +}; + +struct fdt_property { + uint32_t tag; + uint32_t len; + uint32_t nameoff; + char data[0]; +}; + +#endif /* !__ASSEMBLY */ + +#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ +#define FDT_TAGSIZE sizeof(uint32_t) + +#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ +#define FDT_END_NODE 0x2 /* End node */ +#define FDT_PROP 0x3 /* Property: name off, + size, content */ +#define FDT_NOP 0x4 /* nop */ +#define FDT_END 0x9 + +#define FDT_V1_SIZE (7*sizeof(uint32_t)) +#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(uint32_t)) +#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(uint32_t)) +#define FDT_V16_SIZE FDT_V3_SIZE +#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(uint32_t)) + +#endif /* _FDT_H */ diff --git a/include/libfdt.h b/include/libfdt.h new file mode 100644 index 0000000000..acdc72eac6 --- /dev/null +++ b/include/libfdt.h @@ -0,0 +1,135 @@ +#ifndef _LIBFDT_H +#define _LIBFDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 of + * the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +#define FDT_FIRST_SUPPORTED_VERSION 0x10 +#define FDT_LAST_SUPPORTED_VERSION 0x11 + +/* Error codes: informative error codes */ +#define FDT_ERR_NOTFOUND 1 +#define FDT_ERR_EXISTS 2 +#define FDT_ERR_NOSPACE 3 + +/* Error codes: codes for bad parameters */ +#define FDT_ERR_BADOFFSET 4 +#define FDT_ERR_BADPATH 5 +#define FDT_ERR_BADSTATE 6 + +/* Error codes: codes for bad device tree blobs */ +#define FDT_ERR_TRUNCATED 7 +#define FDT_ERR_BADMAGIC 8 +#define FDT_ERR_BADVERSION 9 +#define FDT_ERR_BADSTRUCTURE 10 +#define FDT_ERR_BADLAYOUT 11 + +#define FDT_ERR_MAX 11 + +#define fdt_get_header(fdt, field) \ + (fdt32_to_cpu(((struct fdt_header *)(fdt))->field)) +#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) +#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) +#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) +#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) +#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) +#define fdt_version(fdt) (fdt_get_header(fdt, version)) +#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) +#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) +#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) +#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) + +#define fdt_set_header(fdt, field, val) \ + ((struct fdt_header *)(fdt))->field = cpu_to_fdt32(val) + +void *fdt_offset_ptr(const void *fdt, int offset, int checklen); + +#define fdt_offset_ptr_typed(fdt, offset, var) \ + ((typeof(var))(fdt_offset_ptr((fdt), (offset), sizeof(*(var))))) + +int fdt_move(const void *fdt, void *buf, int bufsize); + +/* Read-only functions */ +char *fdt_string(const void *fdt, int stroffset); + +int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, + const char *name, int namelen); +int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); + +int fdt_path_offset(const void *fdt, const char *path); + +struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, + const char *name, int *lenp); +void *fdt_getprop(const void *fdt, int nodeoffset, + const char *name, int *lenp); + +/* Write-in-place functions */ +int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +#define fdt_setprop_inplace_typed(fdt, nodeoffset, name, val) \ + ({ \ + typeof(val) x = val; \ + fdt_setprop_inplace(fdt, nodeoffset, name, &x, sizeof(x)); \ + }) + +int fdt_nop_property(void *fdt, int nodeoffset, const char *name); +int fdt_nop_node(void *fdt, int nodeoffset); + +/* Sequential-write functions */ +int fdt_create(void *buf, int bufsize); +int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); +int fdt_finish_reservemap(void *fdt); +int fdt_begin_node(void *fdt, const char *name); +int fdt_property(void *fdt, const char *name, const void *val, int len); +#define fdt_property_typed(fdt, name, val) \ + ({ \ + typeof(val) x = (val); \ + fdt_property((fdt), (name), &x, sizeof(x)); \ + }) +#define fdt_property_string(fdt, name, str) \ + fdt_property(fdt, name, str, strlen(str)+1) +int fdt_end_node(void *fdt); +int fdt_finish(void *fdt); + +/* Read-write functions */ +int fdt_open_into(void *fdt, void *buf, int bufsize); +int fdt_pack(void *fdt); + +int fdt_setprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); +#define fdt_setprop_typed(fdt, nodeoffset, name, val) \ + ({ \ + typeof(val) x = (val); \ + fdt_setprop((fdt), (nodeoffset), (name), &x, sizeof(x)); \ + }) +#define fdt_setprop_string(fdt, nodeoffset, name, str) \ + fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) +int fdt_delprop(void *fdt, int nodeoffset, const char *name); +int fdt_add_subnode_namelen(void *fdt, int parentoffset, + const char *name, int namelen); +int fdt_add_subnode(void *fdt, int parentoffset, const char *name); +int fdt_del_node(void *fdt, int nodeoffset); + +/* Extra functions */ +const char *fdt_strerror(int errval); + +#endif /* _LIBFDT_H */ diff --git a/include/libfdt_env.h b/include/libfdt_env.h new file mode 100644 index 0000000000..59f2536d28 --- /dev/null +++ b/include/libfdt_env.h @@ -0,0 +1,22 @@ +#ifndef _LIBFDT_ENV_H +#define _LIBFDT_ENV_H + +#include +#include +#include +#include +#include + +#if __BYTE_ORDER == __BIG_ENDIAN +#define fdt32_to_cpu(x) (x) +#define cpu_to_fdt32(x) (x) +#define fdt64_to_cpu(x) (x) +#define cpu_to_fdt64(x) (x) +#else +#define fdt32_to_cpu(x) (bswap_32((x))) +#define cpu_to_fdt32(x) (bswap_32((x))) +#define fdt64_to_cpu(x) (bswap_64((x))) +#define cpu_to_fdt64(x) (bswap_64((x))) +#endif + +#endif /* _LIBFDT_ENV_H */ -- cgit v1.2.1 From fa3a74cec73dfd06a5ae35a9a3368200273aaa71 Mon Sep 17 00:00:00 2001 From: Gerald Van Baren Date: Sat, 31 Mar 2007 12:05:39 -0400 Subject: libfdt: Customizations for use by u-boot. Changes to David Gibson's original source to fit into u-boot's environment. No functionality changes. --- include/libfdt_env.h | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/include/libfdt_env.h b/include/libfdt_env.h index 59f2536d28..6c77852540 100644 --- a/include/libfdt_env.h +++ b/include/libfdt_env.h @@ -2,21 +2,15 @@ #define _LIBFDT_ENV_H #include -#include -#include -#include -#include +#include +#include +#include -#if __BYTE_ORDER == __BIG_ENDIAN -#define fdt32_to_cpu(x) (x) -#define cpu_to_fdt32(x) (x) -#define fdt64_to_cpu(x) (x) -#define cpu_to_fdt64(x) (x) -#else -#define fdt32_to_cpu(x) (bswap_32((x))) -#define cpu_to_fdt32(x) (bswap_32((x))) -#define fdt64_to_cpu(x) (bswap_64((x))) -#define cpu_to_fdt64(x) (bswap_64((x))) -#endif +struct fdt_header *fdt; /* Pointer to the working fdt */ + +#define fdt32_to_cpu(x) __be32_to_cpu(x) +#define cpu_to_fdt32(x) __cpu_to_be32(x) +#define fdt64_to_cpu(x) __be64_to_cpu(x) +#define cpu_to_fdt64(x) __cpu_to_be64(x) #endif /* _LIBFDT_ENV_H */ -- cgit v1.2.1 From 3af0d587d93e0be5f96e1b30fa41e662f8b0803e Mon Sep 17 00:00:00 2001 From: Gerald Van Baren Date: Sat, 31 Mar 2007 12:13:43 -0400 Subject: libfdt: Enhanced and published fdt_next_tag() Enhanced the formerly private function _fdt_next_tag() to allow stepping through the tree, used to produce a human-readable dump, and made it part of the published interface. Also added some comments. --- include/libfdt.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/libfdt.h b/include/libfdt.h index acdc72eac6..c4b3c249bf 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -81,6 +81,9 @@ struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, void *fdt_getprop(const void *fdt, int nodeoffset, const char *name, int *lenp); +uint32_t fdt_next_tag(const void *fdt, int offset, + int *nextoffset, char **namep); + /* Write-in-place functions */ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, const void *val, int len); -- cgit v1.2.1 From 213bf8c822de8eecaf69860684469cdaba2e9e6a Mon Sep 17 00:00:00 2001 From: Gerald Van Baren Date: Sat, 31 Mar 2007 12:23:51 -0400 Subject: Add a flattened device tree (fdt) command (2 of 2) Modifications to the existing code to support the new fdt command. --- include/configs/MPC8360EMDS.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index d2af0e1dfc..79937dcd8f 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -342,8 +342,12 @@ #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 +#undef CONFIG_OF_FLAT_TREE #define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_HAS_BD_T 1 +#define CONFIG_OF_HAS_UBOOT_ENV 1 + /* maximum size of the flat tree (8K) */ #define OF_FLAT_TREE_MAX_SIZE 8192 -- cgit v1.2.1 From a65c5768e5537530bd1780af3d3fddc3113a163c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 2 Apr 2007 10:09:30 +0200 Subject: ppc4xx: Change SysACE address on Katmai With this new base address of the Xilinx SystemACE controller the Linux driver will be easier to adapt, since it can now be mapped via the "normal" ioremap() call. Signed-off-by: Stefan Roese --- include/configs/katmai.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 1606d0da17..7f55366ca5 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -78,7 +78,7 @@ #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) -#define CFG_ACE_BASE 0xe0000000 /* Xilinx ACE controller - Compact Flash */ +#define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */ /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in internal SRAM) -- cgit v1.2.1 From 94abd7c0583ebe01e799b25f451201deeaab550d Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 4 Apr 2007 01:49:15 +0200 Subject: Minor cleanup. --- include/fdt.h | 32 ++++++++++++++++---------------- include/libfdt.h | 10 +++++----- 2 files changed, 21 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/include/fdt.h b/include/fdt.h index e00559ad6d..48ccfd9100 100644 --- a/include/fdt.h +++ b/include/fdt.h @@ -4,22 +4,22 @@ #ifndef __ASSEMBLY__ struct fdt_header { - uint32_t magic; /* magic word FDT_MAGIC */ - uint32_t totalsize; /* total size of DT block */ - uint32_t off_dt_struct; /* offset to structure */ - uint32_t off_dt_strings; /* offset to strings */ - uint32_t off_mem_rsvmap; /* offset to memory reserve map */ - uint32_t version; /* format version */ - uint32_t last_comp_version; /* last compatible version */ - - /* version 2 fields below */ - uint32_t boot_cpuid_phys; /* Which physical CPU id we're + uint32_t magic; /* magic word FDT_MAGIC */ + uint32_t totalsize; /* total size of DT block */ + uint32_t off_dt_struct; /* offset to structure */ + uint32_t off_dt_strings; /* offset to strings */ + uint32_t off_mem_rsvmap; /* offset to memory reserve map */ + uint32_t version; /* format version */ + uint32_t last_comp_version; /* last compatible version */ + + /* version 2 fields below */ + uint32_t boot_cpuid_phys; /* Which physical CPU id we're booting on */ /* version 3 fields below */ - uint32_t size_dt_strings; /* size of the strings block */ + uint32_t size_dt_strings; /* size of the strings block */ /* version 17 fields below */ - uint32_t size_dt_struct; /* size of the structure block */ + uint32_t size_dt_struct; /* size of the structure block */ }; struct fdt_reserve_entry { @@ -41,12 +41,12 @@ struct fdt_property { #endif /* !__ASSEMBLY */ -#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ +#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ #define FDT_TAGSIZE sizeof(uint32_t) -#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ -#define FDT_END_NODE 0x2 /* End node */ -#define FDT_PROP 0x3 /* Property: name off, +#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ +#define FDT_END_NODE 0x2 /* End node */ +#define FDT_PROP 0x3 /* Property: name off, size, content */ #define FDT_NOP 0x4 /* nop */ #define FDT_END 0x9 diff --git a/include/libfdt.h b/include/libfdt.h index c4b3c249bf..a0b4d55034 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -46,15 +46,15 @@ #define fdt_get_header(fdt, field) \ (fdt32_to_cpu(((struct fdt_header *)(fdt))->field)) -#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) +#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) #define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) #define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) #define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) #define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) #define fdt_version(fdt) (fdt_get_header(fdt, version)) -#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) -#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) -#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) +#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) +#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) +#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) #define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) #define fdt_set_header(fdt, field, val) \ @@ -82,7 +82,7 @@ void *fdt_getprop(const void *fdt, int nodeoffset, const char *name, int *lenp); uint32_t fdt_next_tag(const void *fdt, int offset, - int *nextoffset, char **namep); + int *nextoffset, char **namep); /* Write-in-place functions */ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, -- cgit v1.2.1 From 31c98a88228021b314c89ebb8104fb6473da4471 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 4 Apr 2007 02:09:30 +0200 Subject: Minor coding style cleanup. --- include/asm-microblaze/microblaze_intc.h | 1 - include/asm-microblaze/microblaze_timer.h | 1 - include/configs/ml401.h | 2 +- include/configs/xupv2p.h | 2 +- 4 files changed, 2 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/asm-microblaze/microblaze_intc.h b/include/asm-microblaze/microblaze_intc.h index 73f732c566..6635aeacba 100644 --- a/include/asm-microblaze/microblaze_intc.h +++ b/include/asm-microblaze/microblaze_intc.h @@ -38,4 +38,3 @@ struct irq_action { void *arg; int count; /* number of interrupt */ }; - diff --git a/include/asm-microblaze/microblaze_timer.h b/include/asm-microblaze/microblaze_timer.h index b3d194bd47..844c8db115 100644 --- a/include/asm-microblaze/microblaze_timer.h +++ b/include/asm-microblaze/microblaze_timer.h @@ -39,4 +39,3 @@ typedef volatile struct microblaze_timer_t { int loadreg; /* load register TLR */ int counter; /* timer/counter register */ } microblaze_timer_t; - diff --git a/include/configs/ml401.h b/include/configs/ml401.h index f4a8a1f228..cb159e79dc 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -66,7 +66,7 @@ * * CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000 * CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000 - * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 + * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 * * 0x1000_0000 CFG_SDRAM_BASE * FREE diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h index 224db5c8be..a2f48102f0 100644 --- a/include/configs/xupv2p.h +++ b/include/configs/xupv2p.h @@ -41,7 +41,7 @@ /* * setting reset address - * + * * TEXT_BASE is set to place, where the U-BOOT run in RAM, but * if you want to store U-BOOT in flash, set CFG_RESET_ADDRESS * to FLASH memory and after loading bitstream jump to FLASH. -- cgit v1.2.1 From e0df1c921b788289564e4c1ee7120a6a9cd3ab05 Mon Sep 17 00:00:00 2001 From: Aubrey Li Date: Thu, 5 Apr 2007 18:29:17 +0800 Subject: [Blackfin][PATCH] remove asm/page.h as we do not actually use/want any of these definitions nor does any other arch include it --- include/asm-blackfin/entry.h | 1 - include/asm-blackfin/page.h | 123 ------------------------------------- include/asm-blackfin/string.h | 1 - include/asm-blackfin/virtconvert.h | 1 - 4 files changed, 126 deletions(-) delete mode 100644 include/asm-blackfin/page.h (limited to 'include') diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h index b64d406992..a5db071ff6 100644 --- a/include/asm-blackfin/entry.h +++ b/include/asm-blackfin/entry.h @@ -27,7 +27,6 @@ #include #include -#include /* * Stack layout in 'ret_from_exception': diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h deleted file mode 100644 index d59828cdac..0000000000 --- a/include/asm-blackfin/page.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * U-boot - page.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BLACKFIN_PAGE_H -#define _BLACKFIN_PAGE_H - -#include - -/* PAGE_SHIFT determines the page size */ - -#define PAGE_SHIFT (12) -#define PAGE_SIZE (4096) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -#ifdef __KERNEL__ - -#include - -#if PAGE_SHIFT < 13 -#define KTHREAD_SIZE (8192) -#else -#define KTHREAD_SIZE PAGE_SIZE -#endif - -#ifndef __ASSEMBLY__ - -#define get_user_page(vaddr) __get_free_page(GFP_KERNEL) -#define free_user_page(page, addr) free_page(addr) - -#define clear_page(page) memset((page), 0, PAGE_SIZE) -#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE) - -#define clear_user_page(page, vaddr) clear_page(page) -#define copy_user_page(to, from, vaddr) copy_page(to, from) - -/* - * These are used to make use of C type-checking.. - */ -typedef struct { - unsigned long pte; -} pte_t; -typedef struct { - unsigned long pmd[16]; -} pmd_t; -typedef struct { - unsigned long pgd; -} pgd_t; -typedef struct { - unsigned long pgprot; -} pgprot_t; - -#define pte_val(x) ((x).pte) -#define pmd_val(x) ((&x)->pmd[0]) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) -#define __pgd(x) ((pgd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -/* to align the pointer to the (next) page boundary */ -#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) - -/* Pure 2^n version of get_order */ -extern __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size - 1) >> (PAGE_SHIFT - 1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - -#endif /* !__ASSEMBLY__ */ - -#include - -#define PAGE_OFFSET (PAGE_OFFSET_RAW) - -#ifndef __ASSEMBLY__ - -#define __pa(vaddr) virt_to_phys((void *)vaddr) -#define __va(paddr) phys_to_virt((unsigned long)paddr) - -#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT) -#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)) -#define VALID_PAGE(page) ((page - mem_map) < max_mapnr) - -#define PAGE_BUG(page) do { \ - BUG(); \ -} while (0) - -#endif - -#endif - -#endif diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h index aac6bc99f5..83d931e192 100644 --- a/include/asm-blackfin/string.h +++ b/include/asm-blackfin/string.h @@ -30,7 +30,6 @@ #ifdef __KERNEL__ /* only set these up for kernel code */ #include -#include #include #include diff --git a/include/asm-blackfin/virtconvert.h b/include/asm-blackfin/virtconvert.h index 769f5a089c..08b4cc01a8 100644 --- a/include/asm-blackfin/virtconvert.h +++ b/include/asm-blackfin/virtconvert.h @@ -33,7 +33,6 @@ #include #include -#include #define mm_vtop(vaddr) ((unsigned long) vaddr) #define mm_ptov(vaddr) ((unsigned long) vaddr) -- cgit v1.2.1 From 889256e8604e0c68db1d866d720894dffede9df6 Mon Sep 17 00:00:00 2001 From: Aubrey Li Date: Thu, 5 Apr 2007 18:29:55 +0800 Subject: [Blackfin][PATCH] call real the system synchronize instruction --- include/asm-blackfin/io.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index 6bab6e766a..c435fef2fe 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -37,6 +37,7 @@ extern void cf_outb(unsigned char val, volatile unsigned char *addr); static inline void sync(void) { + __builtin_bfin_ssync(); } /* -- cgit v1.2.1 From 155fd766573981090e638b493d5857562151862e Mon Sep 17 00:00:00 2001 From: Aubrey Li Date: Thu, 5 Apr 2007 18:31:18 +0800 Subject: [Blackfin][PATCH] Fix copyright and update license --- include/asm-blackfin/arch-bf533/bf533_serial.h | 6 +++--- include/asm-blackfin/arch-bf533/bf5xx_rtc.h | 6 +++--- include/asm-blackfin/arch-bf533/irq.h | 6 +++--- include/asm-blackfin/arch-bf537/bf537_serial.h | 6 +++--- include/asm-blackfin/arch-bf537/bf5xx_rtc.h | 6 +++--- include/asm-blackfin/arch-bf537/irq.h | 6 +++--- include/asm-blackfin/arch-bf561/bf561_serial.h | 6 +++--- include/asm-blackfin/arch-common/bf53x_rtc.h | 6 +++--- include/asm-blackfin/bitops.h | 6 +++--- include/asm-blackfin/blackfin.h | 6 +++--- include/asm-blackfin/blackfin_defs.h | 6 +++--- include/asm-blackfin/byteorder.h | 6 +++--- include/asm-blackfin/current.h | 6 +++--- include/asm-blackfin/delay.h | 6 +++--- include/asm-blackfin/entry.h | 6 +++--- include/asm-blackfin/errno.h | 6 +++--- include/asm-blackfin/global_data.h | 6 +++--- include/asm-blackfin/hw_irq.h | 6 +++--- include/asm-blackfin/io-kernel.h | 6 +++--- include/asm-blackfin/io.h | 6 +++--- include/asm-blackfin/irq.h | 6 +++--- include/asm-blackfin/linkage.h | 6 +++--- include/asm-blackfin/machdep.h | 6 +++--- include/asm-blackfin/mem_init.h | 6 +++--- include/asm-blackfin/page_offset.h | 6 +++--- include/asm-blackfin/posix_types.h | 6 +++--- include/asm-blackfin/processor.h | 6 +++--- include/asm-blackfin/ptrace.h | 6 +++--- include/asm-blackfin/segment.h | 6 +++--- include/asm-blackfin/setup.h | 6 +++--- include/asm-blackfin/shared_resources.h | 6 +++--- include/asm-blackfin/string.h | 6 +++--- include/asm-blackfin/system.h | 6 +++--- include/asm-blackfin/traps.h | 6 +++--- include/asm-blackfin/types.h | 6 +++--- include/asm-blackfin/u-boot.h | 6 +++--- include/asm-blackfin/uaccess.h | 6 +++--- include/asm-blackfin/virtconvert.h | 6 +++--- 38 files changed, 114 insertions(+), 114 deletions(-) (limited to 'include') diff --git a/include/asm-blackfin/arch-bf533/bf533_serial.h b/include/asm-blackfin/arch-bf533/bf533_serial.h index ce58863b10..65749ee458 100644 --- a/include/asm-blackfin/arch-bf533/bf533_serial.h +++ b/include/asm-blackfin/arch-bf533/bf533_serial.h @@ -1,7 +1,7 @@ /* * U-boot bf533_serial.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BF533_SERIAL_H_ diff --git a/include/asm-blackfin/arch-bf533/bf5xx_rtc.h b/include/asm-blackfin/arch-bf533/bf5xx_rtc.h index bc09922a5e..f4440a8d47 100644 --- a/include/asm-blackfin/arch-bf533/bf5xx_rtc.h +++ b/include/asm-blackfin/arch-bf533/bf5xx_rtc.h @@ -1,7 +1,7 @@ /* * U-boot - bf533_rtc.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BF533_RTC_H_ diff --git a/include/asm-blackfin/arch-bf533/irq.h b/include/asm-blackfin/arch-bf533/irq.h index 9c5230db41..323574590b 100644 --- a/include/asm-blackfin/arch-bf533/irq.h +++ b/include/asm-blackfin/arch-bf533/irq.h @@ -1,7 +1,7 @@ /* * U-boot bf533_irq.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c @@ -33,8 +33,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BF533_IRQ_H_ diff --git a/include/asm-blackfin/arch-bf537/bf537_serial.h b/include/asm-blackfin/arch-bf537/bf537_serial.h index 1610411ee9..64088f243c 100644 --- a/include/asm-blackfin/arch-bf537/bf537_serial.h +++ b/include/asm-blackfin/arch-bf537/bf537_serial.h @@ -1,7 +1,7 @@ /* * U-boot bf537_serial.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BF537_SERIAL_H_ diff --git a/include/asm-blackfin/arch-bf537/bf5xx_rtc.h b/include/asm-blackfin/arch-bf537/bf5xx_rtc.h index 0043e42bf2..db5cc6f226 100644 --- a/include/asm-blackfin/arch-bf537/bf5xx_rtc.h +++ b/include/asm-blackfin/arch-bf537/bf5xx_rtc.h @@ -1,7 +1,7 @@ /* * U-boot - bf537_rtc.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BF537_RTC_H_ diff --git a/include/asm-blackfin/arch-bf537/irq.h b/include/asm-blackfin/arch-bf537/irq.h index 4cb4c1502f..527d8a21f2 100644 --- a/include/asm-blackfin/arch-bf537/irq.h +++ b/include/asm-blackfin/arch-bf537/irq.h @@ -1,7 +1,7 @@ /* * U-boot bf537_irq.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c @@ -33,8 +33,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BF537_IRQ_H_ diff --git a/include/asm-blackfin/arch-bf561/bf561_serial.h b/include/asm-blackfin/arch-bf561/bf561_serial.h index 0810228397..eb01ca25ba 100644 --- a/include/asm-blackfin/arch-bf561/bf561_serial.h +++ b/include/asm-blackfin/arch-bf561/bf561_serial.h @@ -1,7 +1,7 @@ /* * U-boot bf561_serial.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BF561_SERIAL_H_ diff --git a/include/asm-blackfin/arch-common/bf53x_rtc.h b/include/asm-blackfin/arch-common/bf53x_rtc.h index bc09922a5e..f4440a8d47 100644 --- a/include/asm-blackfin/arch-common/bf53x_rtc.h +++ b/include/asm-blackfin/arch-common/bf53x_rtc.h @@ -1,7 +1,7 @@ /* * U-boot - bf533_rtc.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BF533_RTC_H_ diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h index 7766c4ab06..438e50b8e8 100644 --- a/include/asm-blackfin/bitops.h +++ b/include/asm-blackfin/bitops.h @@ -1,7 +1,7 @@ /* * U-boot - bitops.h Routines for bit operations * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_BITOPS_H diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h index 0ec92071b5..bf502a4e62 100644 --- a/include/asm-blackfin/blackfin.h +++ b/include/asm-blackfin/blackfin.h @@ -1,7 +1,7 @@ /* * U-boot - blackfin.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_H_ diff --git a/include/asm-blackfin/blackfin_defs.h b/include/asm-blackfin/blackfin_defs.h index 2190215971..451d29c3cf 100644 --- a/include/asm-blackfin/blackfin_defs.h +++ b/include/asm-blackfin/blackfin_defs.h @@ -1,7 +1,7 @@ /* * U-boot - blackfin_defs.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __BLACKFIN_DEFS_H__ diff --git a/include/asm-blackfin/byteorder.h b/include/asm-blackfin/byteorder.h index 3b4df4e134..a1a52a5c1a 100644 --- a/include/asm-blackfin/byteorder.h +++ b/include/asm-blackfin/byteorder.h @@ -1,7 +1,7 @@ /* * U-boot - byteorder.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_BYTEORDER_H diff --git a/include/asm-blackfin/current.h b/include/asm-blackfin/current.h index 108c2792a0..ed2b851e95 100644 --- a/include/asm-blackfin/current.h +++ b/include/asm-blackfin/current.h @@ -1,7 +1,7 @@ /* * U-boot - current.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_CURRENT_H diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h index 0c01e9fb7d..ea0b3664e0 100644 --- a/include/asm-blackfin/delay.h +++ b/include/asm-blackfin/delay.h @@ -1,7 +1,7 @@ /* * U-boot - delay.h Routines for introducing delays * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_DELAY_H diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h index a5db071ff6..eb84f11bdb 100644 --- a/include/asm-blackfin/entry.h +++ b/include/asm-blackfin/entry.h @@ -1,7 +1,7 @@ /* * U-boot - entry.h Routines for context saving and restoring * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __BLACKFIN_ENTRY_H diff --git a/include/asm-blackfin/errno.h b/include/asm-blackfin/errno.h index 713bba0b22..0d2c618030 100644 --- a/include/asm-blackfin/errno.h +++ b/include/asm-blackfin/errno.h @@ -1,7 +1,7 @@ /* * U-boot - errno.h Error number defines * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_ERRNO_H diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h index 1c738533c8..9024d0a06e 100644 --- a/include/asm-blackfin/global_data.h +++ b/include/asm-blackfin/global_data.h @@ -1,7 +1,7 @@ /* * U-boot - global_data.h Declarations for global data of u-boot * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __ASM_GBL_DATA_H diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h index baa3e0c5c3..9b360553cb 100644 --- a/include/asm-blackfin/hw_irq.h +++ b/include/asm-blackfin/hw_irq.h @@ -1,7 +1,7 @@ /* * U-boot - hw_irq.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * linux/arch/$(ARCH)/platform/$(PLATFORM)/hw_irq.h @@ -24,8 +24,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include diff --git a/include/asm-blackfin/io-kernel.h b/include/asm-blackfin/io-kernel.h index 3c087c33ee..5d0ad06184 100644 --- a/include/asm-blackfin/io-kernel.h +++ b/include/asm-blackfin/io-kernel.h @@ -1,7 +1,7 @@ /* * U-boot - io-kernel.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_IO_H diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index c435fef2fe..332d2c6437 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -1,7 +1,7 @@ /* * U-boot - io.h IO routines * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_IO_H diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h index aede742120..1fff316881 100644 --- a/include/asm-blackfin/irq.h +++ b/include/asm-blackfin/irq.h @@ -1,7 +1,7 @@ /* * U-boot - irq.h Interrupt related header file * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file was based on * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c @@ -31,8 +31,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_IRQ_H_ diff --git a/include/asm-blackfin/linkage.h b/include/asm-blackfin/linkage.h index 18f0c36d24..4fc1acf0ba 100644 --- a/include/asm-blackfin/linkage.h +++ b/include/asm-blackfin/linkage.h @@ -1,7 +1,7 @@ /* * U-boot - linkage.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _LINUX_LINKAGE_H diff --git a/include/asm-blackfin/machdep.h b/include/asm-blackfin/machdep.h index 4fea74c6c9..8bf94738ec 100644 --- a/include/asm-blackfin/machdep.h +++ b/include/asm-blackfin/machdep.h @@ -1,7 +1,7 @@ /* * U-boot - machdep.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_MACHDEP_H diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h index d9d8bf9ba2..cb448ad61e 100644 --- a/include/asm-blackfin/mem_init.h +++ b/include/asm-blackfin/mem_init.h @@ -1,7 +1,7 @@ /* * U-boot - mem_init.h Header file for memory initialization * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #if (CONFIG_MEM_MT48LC16M16A2TG_75 || \ diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h index 262473fc3d..cfd8f1fef3 100644 --- a/include/asm-blackfin/page_offset.h +++ b/include/asm-blackfin/page_offset.h @@ -1,7 +1,7 @@ /* * U-boot - page_offset.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ /* diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h index f1f2b5ffc2..27889e8e85 100644 --- a/include/asm-blackfin/posix_types.h +++ b/include/asm-blackfin/posix_types.h @@ -1,7 +1,7 @@ /* * U-boot - posix_types.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __ARCH_BLACKFIN_POSIX_TYPES_H diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h index df49bedc0a..6cd4f567fc 100644 --- a/include/asm-blackfin/processor.h +++ b/include/asm-blackfin/processor.h @@ -1,7 +1,7 @@ /* * U-boot - processor.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * include/asm-m68k/processor.h @@ -23,8 +23,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __ASM_BLACKFIN_PROCESSOR_H diff --git a/include/asm-blackfin/ptrace.h b/include/asm-blackfin/ptrace.h index afd57773ac..f1b7d0064b 100644 --- a/include/asm-blackfin/ptrace.h +++ b/include/asm-blackfin/ptrace.h @@ -1,7 +1,7 @@ /* * U-boot - ptrace.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_PTRACE_H diff --git a/include/asm-blackfin/segment.h b/include/asm-blackfin/segment.h index 9e6d817fc7..f309543742 100644 --- a/include/asm-blackfin/segment.h +++ b/include/asm-blackfin/segment.h @@ -1,7 +1,7 @@ /* * U-boot - segment.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_SEGMENT_H diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h index a3c1715b4a..b6b82679ec 100644 --- a/include/asm-blackfin/setup.h +++ b/include/asm-blackfin/setup.h @@ -1,7 +1,7 @@ /* * U-boot - setup.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * asm/setup.h -- Definition of the Linux/Blackfin setup information @@ -22,8 +22,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_SETUP_H diff --git a/include/asm-blackfin/shared_resources.h b/include/asm-blackfin/shared_resources.h index fbef18618c..d280ffeeaa 100644 --- a/include/asm-blackfin/shared_resources.h +++ b/include/asm-blackfin/shared_resources.h @@ -1,7 +1,7 @@ /* * U-boot - setup.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _SHARED_RESOURCES_H_ diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h index 83d931e192..dd50207092 100644 --- a/include/asm-blackfin/string.h +++ b/include/asm-blackfin/string.h @@ -1,7 +1,7 @@ /* * U-boot - string.h String functions * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ /* Changed by Lineo Inc. May 2001 */ diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h index 0e53adfe0f..eda887fb62 100644 --- a/include/asm-blackfin/system.h +++ b/include/asm-blackfin/system.h @@ -1,7 +1,7 @@ /* * U-boot - system.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_SYSTEM_H diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h index 29e6eba6fa..b90cedacbc 100644 --- a/include/asm-blackfin/traps.h +++ b/include/asm-blackfin/traps.h @@ -1,7 +1,7 @@ /* * U-boot - traps.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * linux/include/asm/traps.h @@ -23,8 +23,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ /* diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h index 942ed275af..665a419f2b 100644 --- a/include/asm-blackfin/types.h +++ b/include/asm-blackfin/types.h @@ -1,7 +1,7 @@ /* * U-boot - types.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_TYPES_H diff --git a/include/asm-blackfin/u-boot.h b/include/asm-blackfin/u-boot.h index e1a435a137..8916433ce0 100644 --- a/include/asm-blackfin/u-boot.h +++ b/include/asm-blackfin/u-boot.h @@ -1,7 +1,7 @@ /* * U-boot - u-boot.h Structure declarations for board specific data * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _U_BOOT_H_ diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h index 61e2bfea7c..6e913bb85b 100644 --- a/include/asm-blackfin/uaccess.h +++ b/include/asm-blackfin/uaccess.h @@ -1,7 +1,7 @@ /* * U-boot - uaccess.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * Based on: include/asm-m68knommu/uaccess.h @@ -22,8 +22,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __BLACKFIN_UACCESS_H diff --git a/include/asm-blackfin/virtconvert.h b/include/asm-blackfin/virtconvert.h index 08b4cc01a8..9eda9f8554 100644 --- a/include/asm-blackfin/virtconvert.h +++ b/include/asm-blackfin/virtconvert.h @@ -1,7 +1,7 @@ /* * U-boot - virtconvert.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __BLACKFIN_VIRT_CONVERT__ -- cgit v1.2.1 From 0445e3a264251d75b1be45ef713c70726a2952f0 Mon Sep 17 00:00:00 2001 From: Aubrey Li Date: Thu, 5 Apr 2007 18:31:47 +0800 Subject: [Blackfin][PATCH] minior cleanup --- include/asm-blackfin/u-boot.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-blackfin/u-boot.h b/include/asm-blackfin/u-boot.h index 8916433ce0..b4928da4f5 100644 --- a/include/asm-blackfin/u-boot.h +++ b/include/asm-blackfin/u-boot.h @@ -29,7 +29,7 @@ #define _U_BOOT_H_ 1 typedef struct bd_info { - int bi_baudrate; /* serial console baudrate */ + int bi_baudrate; /* serial console baudrate */ unsigned long bi_ip_addr; /* IP Address */ unsigned char bi_enetaddr[6]; /* Ethernet adress */ unsigned long bi_arch_number; /* unique id for this board */ -- cgit v1.2.1 From 7b7e30aa64bb6657a1bfd32fdbdbfeb561e6a48d Mon Sep 17 00:00:00 2001 From: Aubrey Li Date: Thu, 5 Apr 2007 18:33:04 +0800 Subject: [Blackfin][PATCH] Fix dynamic CPLB generation issue --- include/asm-blackfin/arch-bf533/cplbtab.h | 482 ------------------------------ include/asm-blackfin/arch-bf537/cplbtab.h | 408 ------------------------- include/asm-blackfin/cplb.h | 10 +- 3 files changed, 5 insertions(+), 895 deletions(-) delete mode 100644 include/asm-blackfin/arch-bf533/cplbtab.h delete mode 100644 include/asm-blackfin/arch-bf537/cplbtab.h (limited to 'include') diff --git a/include/asm-blackfin/arch-bf533/cplbtab.h b/include/asm-blackfin/arch-bf533/cplbtab.h deleted file mode 100644 index 89f0325381..0000000000 --- a/include/asm-blackfin/arch-bf533/cplbtab.h +++ /dev/null @@ -1,482 +0,0 @@ -/*This file is subject to the terms and conditions of the GNU General Public - * License. - * - * Blackfin BF533/2.6 support : LG Soft India - * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd - * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's - * shouldn't be victimized. cplbmgr.S search logic is corrected - * to findout the appropriate victim. - * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC - * : LG Soft India - */ -#include - -#ifndef __ARCH_BFINNOMMU_CPLBTAB_H -#define __ARCH_BFINNOMMU_CPLBTAB_H - -/************************************************************************* - * ICPLB TABLE - *************************************************************************/ - -.data -/* This table is configurable */ - .align 4; - -/* Data Attibutes*/ - -#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) -#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) - -/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ - -#define ANOMALY_05000158 0x200 -#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) -#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) - -#else /*Write Through */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) -#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) -#endif - -.align 4; -.global _ipdt_table _ipdt_table:.byte4 0x00000000; -.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */ -.byte4 0x00400000; -.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */ -.byte4 0x00800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */ -.byte4 0x00C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */ -.byte4 0x01000000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */ -.byte4 0x01400000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */ -.byte4 0x01800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */ -.byte4 0x01C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */ -#ifndef CONFIG_EZKIT /*STAMP Memory regions */ -.byte4 0x02000000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */ -.byte4 0x02400000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */ -.byte4 0x02800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */ -.byte4 0x02C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */ -.byte4 0x03000000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */ -.byte4 0x03400000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */ -.byte4 0x03800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */ -.byte4 0x03C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */ -#endif -.byte4 0x20000000; -.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */ - -#ifdef CONFIG_STAMP -.byte4 0x04000000; -.byte4(SDRAM_IGENERIC); -.byte4 0x04400000; -.byte4(SDRAM_IGENERIC); -.byte4 0x04800000; -.byte4(SDRAM_IGENERIC); -.byte4 0x04C00000; -.byte4(SDRAM_IGENERIC); -.byte4 0x05000000; -.byte4(SDRAM_IGENERIC); -.byte4 0x05400000; -.byte4(SDRAM_IGENERIC); -.byte4 0x05800000; -.byte4(SDRAM_IGENERIC); -.byte4 0x05C00000; -.byte4(SDRAM_IGENERIC); -.byte4 0x06000000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page25 */ -.byte4 0x06400000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page26 */ -.byte4 0x06800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page27 */ -.byte4 0x06C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page28 */ -.byte4 0x07000000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page29 */ -.byte4 0x07400000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page30 */ -.byte4 0x07800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page31 */ -.byte4 0x07C00000; -.byte4(SDRAM_IKERNEL); /*SDRAM_Page32 */ -#endif -.byte4 0xffffffff; /* end of section - termination */ - -/********************************************************************** - * PAGE DESCRIPTOR TABLE - * - **********************************************************************/ - -/* Till here we are discussing about the static memory management model. - * However, the operating envoronments commonly define more CPLB - * descriptors to cover the entire addressable memory than will fit into - * the available on-chip 16 CPLB MMRs. When this happens, the below table - * will be used which will hold all the potentially required CPLB descriptors - * - * This is how Page descriptor Table is implemented in uClinux/Blackfin. - */ -.global _dpdt_table _dpdt_table:.byte4 0x00000000; -.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */ -.byte4 0x00400000; -.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */ -.byte4 0x00800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */ -.byte4 0x00C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */ -.byte4 0x01000000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */ -.byte4 0x01400000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */ -.byte4 0x01800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */ -.byte4 0x01C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */ - -#ifndef CONFIG_EZKIT -.byte4 0x02000000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */ -.byte4 0x02400000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */ -.byte4 0x02800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */ -.byte4 0x02C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */ -.byte4 0x03000000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */ -.byte4 0x03400000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */ -.byte4 0x03800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */ -.byte4 0x03C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */ -#endif - -#ifdef CONFIG_STAMP -.byte4 0x04000000; -.byte4(SDRAM_DGENERIC); -.byte4 0x04400000; -.byte4(SDRAM_DGENERIC); -.byte4 0x04800000; -.byte4(SDRAM_DGENERIC); -.byte4 0x04C00000; -.byte4(SDRAM_DGENERIC); -.byte4 0x05000000; -.byte4(SDRAM_DGENERIC); -.byte4 0x05400000; -.byte4(SDRAM_DGENERIC); -.byte4 0x05800000; -.byte4(SDRAM_DGENERIC); -.byte4 0x05C00000; -.byte4(SDRAM_DGENERIC); -.byte4 0x06000000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page25 */ -.byte4 0x06400000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page26 */ -.byte4 0x06800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page27 */ -.byte4 0x06C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page28 */ -.byte4 0x07000000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page29 */ -.byte4 0x07400000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page30 */ -.byte4 0x07800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page31 */ -.byte4 0x07C00000; -.byte4(SDRAM_DKERNEL); /*SDRAM_Page32 */ -#endif - -.byte4 0x20000000; -.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */ - -#if (BFIN_CPU == ADSP_BF533) -.byte4 0xFF800000; -.byte4(L1_DMEMORY); -.byte4 0xFF801000; -.byte4(L1_DMEMORY); -.byte4 0xFF802000; -.byte4(L1_DMEMORY); -.byte4 0xFF803000; -.byte4(L1_DMEMORY); -#endif -.byte4 0xFF804000; -.byte4(L1_DMEMORY); -.byte4 0xFF805000; -.byte4(L1_DMEMORY); -.byte4 0xFF806000; -.byte4(L1_DMEMORY); -.byte4 0xFF807000; -.byte4(L1_DMEMORY); -#if (BFIN_CPU == ADSP_BF533) -.byte4 0xFF900000; -.byte4(L1_DMEMORY); -.byte4 0xFF901000; -.byte4(L1_DMEMORY); -.byte4 0xFF902000; -.byte4(L1_DMEMORY); -.byte4 0xFF903000; -.byte4(L1_DMEMORY); -#endif -#if ((BFIN_CPU == ADSP_BF532) || (BFIN_CPU == ADSP_BF533)) -.byte4 0xFF904000; -.byte4(L1_DMEMORY); -.byte4 0xFF905000; -.byte4(L1_DMEMORY); -.byte4 0xFF906000; -.byte4(L1_DMEMORY); -.byte4 0xFF907000; -.byte4(L1_DMEMORY); -#endif -.byte4 0xFFB00000; -.byte4(L1_DMEMORY); - -.byte4 0xffffffff; /*end of section - termination */ - -#ifdef CONFIG_CPLB_INFO -.global _ipdt_swapcount_table; /* swapin count first, then swapout count */ -_ipdt_swapcount_table: -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 10 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 20 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 30 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 40 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 50 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 60 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 70 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 80 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 90 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 100 */ - -.global _dpdt_swapcount_table; /* swapin count first, then swapout count */ -_dpdt_swapcount_table: -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 10 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 20 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 30 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 40 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 50 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 60 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 70 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 80 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 80 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 100 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 110 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 120 */ -#endif - -#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/ diff --git a/include/asm-blackfin/arch-bf537/cplbtab.h b/include/asm-blackfin/arch-bf537/cplbtab.h deleted file mode 100644 index c5151bb4ab..0000000000 --- a/include/asm-blackfin/arch-bf537/cplbtab.h +++ /dev/null @@ -1,408 +0,0 @@ -/*This file is subject to the terms and conditions of the GNU General Public - * License. - * - * Blackfin BF533/2.6 support : LG Soft India - * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd - * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's - * shouldn't be victimized. cplbmgr.S search logic is corrected - * to findout the appropriate victim. - * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC - * : LG Soft India - */ -#include - -#ifndef __ARCH_BFINNOMMU_CPLBTAB_H -#define __ARCH_BFINNOMMU_CPLBTAB_H - -/* - * ICPLB TABLE - */ - -.data -/* This table is configurable */ - .align 4; - -/* Data Attibutes*/ - -#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) -#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) - -/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ - -#define ANOMALY_05000158 0x200 -#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) -#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) - -#else /*Write Through */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) -#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) -#endif - -.align 4; -.global _ipdt_table _ipdt_table:.byte4 0x00000000; -.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */ -.byte4 0x00400000; -.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */ -.byte4 0x00800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */ -.byte4 0x00C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */ -.byte4 0x01000000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */ -.byte4 0x01400000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */ -.byte4 0x01800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */ -.byte4 0x01C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */ -.byte4 0x02000000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */ -.byte4 0x02400000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */ -.byte4 0x02800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */ -.byte4 0x02C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */ -.byte4 0x03000000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */ -.byte4 0x03400000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */ -.byte4 0x03800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */ -.byte4 0x03C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */ -.byte4 0x20000000; -.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */ - -.byte4 0xffffffff; /* end of section - termination */ - -/* - * PAGE DESCRIPTOR TABLE - * - */ - -/* - * Till here we are discussing about the static memory management model. - * However, the operating envoronments commonly define more CPLB - * descriptors to cover the entire addressable memory than will fit into - * the available on-chip 16 CPLB MMRs. When this happens, the below table - * will be used which will hold all the potentially required CPLB descriptors - * - * This is how Page descriptor Table is implemented in uClinux/Blackfin. - */ -.global _dpdt_table _dpdt_table:.byte4 0x00000000; -.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */ -.byte4 0x00400000; -.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */ -.byte4 0x00800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */ -.byte4 0x00C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */ -.byte4 0x01000000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */ -.byte4 0x01400000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */ -.byte4 0x01800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */ -.byte4 0x01C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */ -.byte4 0x02000000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */ -.byte4 0x02400000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */ -.byte4 0x02800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */ -.byte4 0x02C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */ -.byte4 0x03000000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */ -.byte4 0x03400000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */ -.byte4 0x03800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */ -.byte4 0x03C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */ -.byte4 0x20000000; -.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */ - -#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537)) -.byte4 0xFF800000; -.byte4(L1_DMEMORY); -.byte4 0xFF801000; -.byte4(L1_DMEMORY); -.byte4 0xFF802000; -.byte4(L1_DMEMORY); -.byte4 0xFF803000; -.byte4(L1_DMEMORY); -#endif -.byte4 0xFF804000; -.byte4(L1_DMEMORY); -.byte4 0xFF805000; -.byte4(L1_DMEMORY); -.byte4 0xFF806000; -.byte4(L1_DMEMORY); -.byte4 0xFF807000; -.byte4(L1_DMEMORY); -#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537)) -.byte4 0xFF900000; -.byte4(L1_DMEMORY); -.byte4 0xFF901000; -.byte4(L1_DMEMORY); -.byte4 0xFF902000; -.byte4(L1_DMEMORY); -.byte4 0xFF903000; -.byte4(L1_DMEMORY); -#endif -.byte4 0xFF904000; -.byte4(L1_DMEMORY); -.byte4 0xFF905000; -.byte4(L1_DMEMORY); -.byte4 0xFF906000; -.byte4(L1_DMEMORY); -.byte4 0xFF907000; -.byte4(L1_DMEMORY); - -.byte4 0xFFB00000; -.byte4(L1_DMEMORY); - -.byte4 0xffffffff; /*end of section - termination */ - -#ifdef CONFIG_CPLB_INFO -.global _ipdt_swapcount_table; /* swapin count first, then swapout count */ -_ipdt_swapcount_table: -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 10 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 20 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 30 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 40 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 50 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 60 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 70 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 80 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 90 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 100 */ - -.global _dpdt_swapcount_table; /* swapin count first, then swapout count */ -_dpdt_swapcount_table: -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 10 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 20 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 30 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 40 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 50 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 60 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 70 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 80 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 80 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 100 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 110 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 120 */ - -#endif - -#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/ diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h index dd695e10ad..9d8d9ecc87 100644 --- a/include/asm-blackfin/cplb.h +++ b/include/asm-blackfin/cplb.h @@ -50,7 +50,7 @@ #define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) #define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ @@ -61,20 +61,20 @@ #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) -#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) #define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) #else /*Write Through */ #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) -#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) #define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) #endif #if defined(CONFIG_BF561) -#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM +L1 + ASYNC_Memory */ +#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 4) /* SDRAM +L1 + ASYNC_Memory */ #else -#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 3) /* SDRAM + L1 + ASYNC_Memory */ +#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM + L1 + ASYNC_Memory */ #endif #endif /* _CPLB_H */ -- cgit v1.2.1 From 6679f9299534e488a171a9bb8f9bb891de247aab Mon Sep 17 00:00:00 2001 From: Gerald Van Baren Date: Fri, 6 Apr 2007 14:17:14 -0400 Subject: libfdt: Make fdt_check_header() public Changed _fdt_check_header() to fdt_check_header() and made it part of the interface - it is a useful routine. Also did some asthetics cleanup to the include files (headers). --- include/fdt.h | 19 +++++++++++++++++++ include/libfdt.h | 7 +++++-- include/libfdt_env.h | 20 ++++++++++++++++++++ 3 files changed, 44 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/fdt.h b/include/fdt.h index 48ccfd9100..3dd3aca3b6 100644 --- a/include/fdt.h +++ b/include/fdt.h @@ -1,3 +1,22 @@ +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 of + * the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef _FDT_H #define _FDT_H diff --git a/include/libfdt.h b/include/libfdt.h index a0b4d55034..61f56ec0d5 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -1,5 +1,3 @@ -#ifndef _LIBFDT_H -#define _LIBFDT_H /* * libfdt - Flat Device Tree manipulation * Copyright (C) 2006 David Gibson, IBM Corporation. @@ -19,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef _LIBFDT_H +#define _LIBFDT_H + #include #include @@ -60,6 +61,8 @@ #define fdt_set_header(fdt, field, val) \ ((struct fdt_header *)(fdt))->field = cpu_to_fdt32(val) +int fdt_check_header(const void *fdt); + void *fdt_offset_ptr(const void *fdt, int offset, int checklen); #define fdt_offset_ptr_typed(fdt, offset, var) \ diff --git a/include/libfdt_env.h b/include/libfdt_env.h index 6c77852540..e746314b1e 100644 --- a/include/libfdt_env.h +++ b/include/libfdt_env.h @@ -1,3 +1,23 @@ +/* + * libfdt - Flat Device Tree manipulation (build/run environment adaptation) + * Copyright (C) 2007 Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com + * Original version written by David Gibson, IBM Corporation. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 of + * the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef _LIBFDT_ENV_H #define _LIBFDT_ENV_H -- cgit v1.2.1 From 64dbbd40c58349b64f43fd33dbb5ca0adb67d642 Mon Sep 17 00:00:00 2001 From: Gerald Van Baren Date: Fri, 6 Apr 2007 14:19:43 -0400 Subject: Moved fdt command support code to fdt_support.c ...in preparation for improving the bootm command's handling of fdt blobs. Also cleaned up some coding sloppiness. --- include/fdt_support.h | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 include/fdt_support.h (limited to 'include') diff --git a/include/fdt_support.h b/include/fdt_support.h new file mode 100644 index 0000000000..a276834740 --- /dev/null +++ b/include/fdt_support.h @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2007 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FDT_SUPPORT_H +#define __FDT_SUPPORT_H + +#ifdef CONFIG_OF_LIBFDT + +#include + +int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force); + +#ifdef CONFIG_OF_HAS_UBOOT_ENV +int fdt_env(void *fdt); +#endif + +#ifdef CONFIG_OF_HAS_BD_T +int fdt_bd_t(void *fdt); +#endif + +#endif /* ifdef CONFIG_OF_LIBFDT */ +#endif /* ifndef __FDT_SUPPORT_H */ -- cgit v1.2.1 From 51056dd9863e6a1bc363afbbe1775c58cd967418 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 11 Apr 2007 17:22:55 +0200 Subject: Update for SC3 board * Make IDE timeout configurable through ide_reset_timeout variable. * Use Newline as "password" string * Use just a single partition in NAND flash --- include/configs/sc3.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 8298084f1e..6b6acfa875 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -133,8 +133,8 @@ #if 1 /* feel free to disable for development */ #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with S\n" -#define CONFIG_AUTOBOOT_DELAY_STR "S" /* 1st "password" */ +#define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with ENTER\n" +#define CONFIG_AUTOBOOT_DELAY_STR "\n" /* 1st "password" */ #endif /* @@ -416,11 +416,11 @@ extern unsigned long offsetOfEnvironment; #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -/* No command line, one static partition Partition 3 contains jffs2 rootfs */ +/* No command line, one static partition */ #undef CONFIG_JFFS2_CMDLINE #define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_SIZE 0x00400000 -#define CONFIG_JFFS2_PART_OFFSET 0x00c00000 +#define CONFIG_JFFS2_PART_SIZE 0x01000000 +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 /*----------------------------------------------------------------------- * Cache Configuration -- cgit v1.2.1 From 03d1e1365796cd15d1726e8a51fd8b5be50b2fe9 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Sat, 18 Nov 2006 18:01:13 +0100 Subject: AVR32: Clean up memory-map.h for at32ap7000 Convert spaces to tabs (must have missed this one last time around), sort the entries by address and group them together by bus connectivity. Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/arch-at32ap7000/memory-map.h | 81 ++++++++++++++------------ 1 file changed, 43 insertions(+), 38 deletions(-) (limited to 'include') diff --git a/include/asm-avr32/arch-at32ap7000/memory-map.h b/include/asm-avr32/arch-at32ap7000/memory-map.h index 8ffe851c89..5513e88e7b 100644 --- a/include/asm-avr32/arch-at32ap7000/memory-map.h +++ b/include/asm-avr32/arch-at32ap7000/memory-map.h @@ -19,43 +19,48 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef __ASM_AVR32_PART_MEMORY_MAP_H__ -#define __ASM_AVR32_PART_MEMORY_MAP_H__ +#ifndef __AT32AP7000_MEMORY_MAP_H__ +#define __AT32AP7000_MEMORY_MAP_H__ -#define AUDIOC_BASE 0xFFF02800 -#define DAC_BASE 0xFFF02000 -#define DMAC_BASE 0xFF200000 -#define ECC_BASE 0xFFF03C00 -#define HISI_BASE 0xFFF02C00 -#define HMATRIX_BASE 0xFFF00800 -#define HSDRAMC_BASE 0xFFF03800 -#define HSMC_BASE 0xFFF03400 -#define LCDC_BASE 0xFF000000 -#define MACB0_BASE 0xFFF01800 -#define MACB1_BASE 0xFFF01C00 -#define MMCI_BASE 0xFFF02400 -#define PIOA_BASE 0xFFE02800 -#define PIOB_BASE 0xFFE02C00 -#define PIOC_BASE 0xFFE03000 -#define PIOD_BASE 0xFFE03400 -#define PIOE_BASE 0xFFE03800 -#define PSIF_BASE 0xFFE03C00 -#define PWM_BASE 0xFFF01400 -#define SM_BASE 0xFFF00000 -#define INTC_BASE 0XFFF00400 -#define SPI0_BASE 0xFFE00000 -#define SPI1_BASE 0xFFE00400 -#define SSC0_BASE 0xFFE01C00 -#define SSC1_BASE 0xFFE02000 -#define SSC2_BASE 0xFFE02400 -#define TIMER0_BASE 0xFFF00C00 -#define TIMER1_BASE 0xFFF01000 -#define TWI_BASE 0xFFE00800 -#define USART0_BASE 0xFFE00C00 -#define USART1_BASE 0xFFE01000 -#define USART2_BASE 0xFFE01400 -#define USART3_BASE 0xFFE01800 -#define USB_FIFO 0xFF300000 -#define USB_BASE 0xFFF03000 +/* Devices on the High Speed Bus (HSB) */ +#define LCDC_BASE 0xFF000000 +#define DMAC_BASE 0xFF200000 +#define USB_FIFO 0xFF300000 -#endif /* __ASM_AVR32_PART_MEMORY_MAP_H__ */ +/* Devices on Peripheral Bus A (PBA) */ +#define SPI0_BASE 0xFFE00000 +#define SPI1_BASE 0xFFE00400 +#define TWI_BASE 0xFFE00800 +#define USART0_BASE 0xFFE00C00 +#define USART1_BASE 0xFFE01000 +#define USART2_BASE 0xFFE01400 +#define USART3_BASE 0xFFE01800 +#define SSC0_BASE 0xFFE01C00 +#define SSC1_BASE 0xFFE02000 +#define SSC2_BASE 0xFFE02400 +#define PIOA_BASE 0xFFE02800 +#define PIOB_BASE 0xFFE02C00 +#define PIOC_BASE 0xFFE03000 +#define PIOD_BASE 0xFFE03400 +#define PIOE_BASE 0xFFE03800 +#define PSIF_BASE 0xFFE03C00 + +/* Devices on Peripheral Bus B (PBB) */ +#define SM_BASE 0xFFF00000 +#define INTC_BASE 0xFFF00400 +#define HMATRIX_BASE 0xFFF00800 +#define TIMER0_BASE 0xFFF00C00 +#define TIMER1_BASE 0xFFF01000 +#define PWM_BASE 0xFFF01400 +#define MACB0_BASE 0xFFF01800 +#define MACB1_BASE 0xFFF01C00 +#define DAC_BASE 0xFFF02000 +#define MMCI_BASE 0xFFF02400 +#define AUDIOC_BASE 0xFFF02800 +#define HISI_BASE 0xFFF02C00 +#define USB_BASE 0xFFF03000 +#define HSMC_BASE 0xFFF03400 +#define HSDRAMC_BASE 0xFFF03800 +#define ECC_BASE 0xFFF03C00 + +#endif /* __AT32AP7000_MEMORY_MAP_H__ */ -- cgit v1.2.1 From df548d3c3e2bbc40258713167859ffc2ce99a900 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Sun, 19 Nov 2006 18:06:53 +0100 Subject: AVR32: Resource management rewrite Rewrite the resource management code (i.e. I/O memory, clock gating, gpio) so it doesn't depend on any global state. This is necessary because this code is heavily used before relocation to RAM, so we can't write to any global variables. As an added bonus, this makes u-boot's memory footprint a bit smaller, although some functionality has been left out; all clocks are enabled all the time, and there's no checking for gpio line conflicts. Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/arch-at32ap7000/clk.h | 58 ++++++++ include/asm-avr32/arch-at32ap7000/gpio.h | 210 +++++++++++++++++++++++++++ include/asm-avr32/arch-at32ap7000/hmatrix2.h | 8 +- include/asm-avr32/arch-at32ap7000/platform.h | 146 ------------------- include/asm-avr32/global_data.h | 2 - include/configs/atstk1002.h | 7 +- 6 files changed, 276 insertions(+), 155 deletions(-) create mode 100644 include/asm-avr32/arch-at32ap7000/clk.h create mode 100644 include/asm-avr32/arch-at32ap7000/gpio.h delete mode 100644 include/asm-avr32/arch-at32ap7000/platform.h (limited to 'include') diff --git a/include/asm-avr32/arch-at32ap7000/clk.h b/include/asm-avr32/arch-at32ap7000/clk.h new file mode 100644 index 0000000000..4a25b17ad4 --- /dev/null +++ b/include/asm-avr32/arch-at32ap7000/clk.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ARCH_CLK_H__ +#define __ASM_AVR32_ARCH_CLK_H__ + +#ifdef CONFIG_PLL +#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) +#else +#define MAIN_CLK_RATE (CFG_OSC0_HZ) +#endif + +static inline unsigned long get_cpu_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_CPU; +} +static inline unsigned long get_hsb_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_HSB; +} +static inline unsigned long get_pba_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_PBA; +} +static inline unsigned long get_pbb_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_PBB; +} + +/* Accessors for specific devices. More will be added as needed. */ +static inline unsigned long get_sdram_clk_rate(void) +{ + return get_hsb_clk_rate(); +} +static inline unsigned long get_usart_clk_rate(unsigned int dev_id) +{ + return get_pba_clk_rate(); +} + +#endif /* __ASM_AVR32_ARCH_CLK_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/gpio.h b/include/asm-avr32/arch-at32ap7000/gpio.h new file mode 100644 index 0000000000..adec2083f2 --- /dev/null +++ b/include/asm-avr32/arch-at32ap7000/gpio.h @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ARCH_GPIO_H__ +#define __ASM_AVR32_ARCH_GPIO_H__ + +#include + +#define NR_GPIO_CONTROLLERS 5 + +/* + * Pin numbers identifying specific GPIO pins on the chip. + */ +#define GPIO_PIOA_BASE (0) +#define GPIO_PIN_PA0 (GPIO_PIOA_BASE + 0) +#define GPIO_PIN_PA1 (GPIO_PIOA_BASE + 1) +#define GPIO_PIN_PA2 (GPIO_PIOA_BASE + 2) +#define GPIO_PIN_PA3 (GPIO_PIOA_BASE + 3) +#define GPIO_PIN_PA4 (GPIO_PIOA_BASE + 4) +#define GPIO_PIN_PA5 (GPIO_PIOA_BASE + 5) +#define GPIO_PIN_PA6 (GPIO_PIOA_BASE + 6) +#define GPIO_PIN_PA7 (GPIO_PIOA_BASE + 7) +#define GPIO_PIN_PA8 (GPIO_PIOA_BASE + 8) +#define GPIO_PIN_PA9 (GPIO_PIOA_BASE + 9) +#define GPIO_PIN_PA10 (GPIO_PIOA_BASE + 10) +#define GPIO_PIN_PA11 (GPIO_PIOA_BASE + 11) +#define GPIO_PIN_PA12 (GPIO_PIOA_BASE + 12) +#define GPIO_PIN_PA13 (GPIO_PIOA_BASE + 13) +#define GPIO_PIN_PA14 (GPIO_PIOA_BASE + 14) +#define GPIO_PIN_PA15 (GPIO_PIOA_BASE + 15) +#define GPIO_PIN_PA16 (GPIO_PIOA_BASE + 16) +#define GPIO_PIN_PA17 (GPIO_PIOA_BASE + 17) +#define GPIO_PIN_PA18 (GPIO_PIOA_BASE + 18) +#define GPIO_PIN_PA19 (GPIO_PIOA_BASE + 19) +#define GPIO_PIN_PA20 (GPIO_PIOA_BASE + 20) +#define GPIO_PIN_PA21 (GPIO_PIOA_BASE + 21) +#define GPIO_PIN_PA22 (GPIO_PIOA_BASE + 22) +#define GPIO_PIN_PA23 (GPIO_PIOA_BASE + 23) +#define GPIO_PIN_PA24 (GPIO_PIOA_BASE + 24) +#define GPIO_PIN_PA25 (GPIO_PIOA_BASE + 25) +#define GPIO_PIN_PA26 (GPIO_PIOA_BASE + 26) +#define GPIO_PIN_PA27 (GPIO_PIOA_BASE + 27) +#define GPIO_PIN_PA28 (GPIO_PIOA_BASE + 28) +#define GPIO_PIN_PA29 (GPIO_PIOA_BASE + 29) +#define GPIO_PIN_PA30 (GPIO_PIOA_BASE + 30) +#define GPIO_PIN_PA31 (GPIO_PIOA_BASE + 31) + +#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) +#define GPIO_PIN_PB0 (GPIO_PIOB_BASE + 0) +#define GPIO_PIN_PB1 (GPIO_PIOB_BASE + 1) +#define GPIO_PIN_PB2 (GPIO_PIOB_BASE + 2) +#define GPIO_PIN_PB3 (GPIO_PIOB_BASE + 3) +#define GPIO_PIN_PB4 (GPIO_PIOB_BASE + 4) +#define GPIO_PIN_PB5 (GPIO_PIOB_BASE + 5) +#define GPIO_PIN_PB6 (GPIO_PIOB_BASE + 6) +#define GPIO_PIN_PB7 (GPIO_PIOB_BASE + 7) +#define GPIO_PIN_PB8 (GPIO_PIOB_BASE + 8) +#define GPIO_PIN_PB9 (GPIO_PIOB_BASE + 9) +#define GPIO_PIN_PB10 (GPIO_PIOB_BASE + 10) +#define GPIO_PIN_PB11 (GPIO_PIOB_BASE + 11) +#define GPIO_PIN_PB12 (GPIO_PIOB_BASE + 12) +#define GPIO_PIN_PB13 (GPIO_PIOB_BASE + 13) +#define GPIO_PIN_PB14 (GPIO_PIOB_BASE + 14) +#define GPIO_PIN_PB15 (GPIO_PIOB_BASE + 15) +#define GPIO_PIN_PB16 (GPIO_PIOB_BASE + 16) +#define GPIO_PIN_PB17 (GPIO_PIOB_BASE + 17) +#define GPIO_PIN_PB18 (GPIO_PIOB_BASE + 18) +#define GPIO_PIN_PB19 (GPIO_PIOB_BASE + 19) +#define GPIO_PIN_PB20 (GPIO_PIOB_BASE + 20) +#define GPIO_PIN_PB21 (GPIO_PIOB_BASE + 21) +#define GPIO_PIN_PB22 (GPIO_PIOB_BASE + 22) +#define GPIO_PIN_PB23 (GPIO_PIOB_BASE + 23) +#define GPIO_PIN_PB24 (GPIO_PIOB_BASE + 24) +#define GPIO_PIN_PB25 (GPIO_PIOB_BASE + 25) +#define GPIO_PIN_PB26 (GPIO_PIOB_BASE + 26) +#define GPIO_PIN_PB27 (GPIO_PIOB_BASE + 27) +#define GPIO_PIN_PB28 (GPIO_PIOB_BASE + 28) +#define GPIO_PIN_PB29 (GPIO_PIOB_BASE + 29) +#define GPIO_PIN_PB30 (GPIO_PIOB_BASE + 30) + +#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) +#define GPIO_PIN_PC0 (GPIO_PIOC_BASE + 0) +#define GPIO_PIN_PC1 (GPIO_PIOC_BASE + 1) +#define GPIO_PIN_PC2 (GPIO_PIOC_BASE + 2) +#define GPIO_PIN_PC3 (GPIO_PIOC_BASE + 3) +#define GPIO_PIN_PC4 (GPIO_PIOC_BASE + 4) +#define GPIO_PIN_PC5 (GPIO_PIOC_BASE + 5) +#define GPIO_PIN_PC6 (GPIO_PIOC_BASE + 6) +#define GPIO_PIN_PC7 (GPIO_PIOC_BASE + 7) +#define GPIO_PIN_PC8 (GPIO_PIOC_BASE + 8) +#define GPIO_PIN_PC9 (GPIO_PIOC_BASE + 9) +#define GPIO_PIN_PC10 (GPIO_PIOC_BASE + 10) +#define GPIO_PIN_PC11 (GPIO_PIOC_BASE + 11) +#define GPIO_PIN_PC12 (GPIO_PIOC_BASE + 12) +#define GPIO_PIN_PC13 (GPIO_PIOC_BASE + 13) +#define GPIO_PIN_PC14 (GPIO_PIOC_BASE + 14) +#define GPIO_PIN_PC15 (GPIO_PIOC_BASE + 15) +#define GPIO_PIN_PC16 (GPIO_PIOC_BASE + 16) +#define GPIO_PIN_PC17 (GPIO_PIOC_BASE + 17) +#define GPIO_PIN_PC18 (GPIO_PIOC_BASE + 18) +#define GPIO_PIN_PC19 (GPIO_PIOC_BASE + 19) +#define GPIO_PIN_PC20 (GPIO_PIOC_BASE + 20) +#define GPIO_PIN_PC21 (GPIO_PIOC_BASE + 21) +#define GPIO_PIN_PC22 (GPIO_PIOC_BASE + 22) +#define GPIO_PIN_PC23 (GPIO_PIOC_BASE + 23) +#define GPIO_PIN_PC24 (GPIO_PIOC_BASE + 24) +#define GPIO_PIN_PC25 (GPIO_PIOC_BASE + 25) +#define GPIO_PIN_PC26 (GPIO_PIOC_BASE + 26) +#define GPIO_PIN_PC27 (GPIO_PIOC_BASE + 27) +#define GPIO_PIN_PC28 (GPIO_PIOC_BASE + 28) +#define GPIO_PIN_PC29 (GPIO_PIOC_BASE + 29) +#define GPIO_PIN_PC30 (GPIO_PIOC_BASE + 30) +#define GPIO_PIN_PC31 (GPIO_PIOC_BASE + 31) + +#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32) +#define GPIO_PIN_PD0 (GPIO_PIOD_BASE + 0) +#define GPIO_PIN_PD1 (GPIO_PIOD_BASE + 1) +#define GPIO_PIN_PD2 (GPIO_PIOD_BASE + 2) +#define GPIO_PIN_PD3 (GPIO_PIOD_BASE + 3) +#define GPIO_PIN_PD4 (GPIO_PIOD_BASE + 4) +#define GPIO_PIN_PD5 (GPIO_PIOD_BASE + 5) +#define GPIO_PIN_PD6 (GPIO_PIOD_BASE + 6) +#define GPIO_PIN_PD7 (GPIO_PIOD_BASE + 7) +#define GPIO_PIN_PD8 (GPIO_PIOD_BASE + 8) +#define GPIO_PIN_PD9 (GPIO_PIOD_BASE + 9) +#define GPIO_PIN_PD10 (GPIO_PIOD_BASE + 10) +#define GPIO_PIN_PD11 (GPIO_PIOD_BASE + 11) +#define GPIO_PIN_PD12 (GPIO_PIOD_BASE + 12) +#define GPIO_PIN_PD13 (GPIO_PIOD_BASE + 13) +#define GPIO_PIN_PD14 (GPIO_PIOD_BASE + 14) +#define GPIO_PIN_PD15 (GPIO_PIOD_BASE + 15) +#define GPIO_PIN_PD16 (GPIO_PIOD_BASE + 16) +#define GPIO_PIN_PD17 (GPIO_PIOD_BASE + 17) + +#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32) +#define GPIO_PIN_PE0 (GPIO_PIOE_BASE + 0) +#define GPIO_PIN_PE1 (GPIO_PIOE_BASE + 1) +#define GPIO_PIN_PE2 (GPIO_PIOE_BASE + 2) +#define GPIO_PIN_PE3 (GPIO_PIOE_BASE + 3) +#define GPIO_PIN_PE4 (GPIO_PIOE_BASE + 4) +#define GPIO_PIN_PE5 (GPIO_PIOE_BASE + 5) +#define GPIO_PIN_PE6 (GPIO_PIOE_BASE + 6) +#define GPIO_PIN_PE7 (GPIO_PIOE_BASE + 7) +#define GPIO_PIN_PE8 (GPIO_PIOE_BASE + 8) +#define GPIO_PIN_PE9 (GPIO_PIOE_BASE + 9) +#define GPIO_PIN_PE10 (GPIO_PIOE_BASE + 10) +#define GPIO_PIN_PE11 (GPIO_PIOE_BASE + 11) +#define GPIO_PIN_PE12 (GPIO_PIOE_BASE + 12) +#define GPIO_PIN_PE13 (GPIO_PIOE_BASE + 13) +#define GPIO_PIN_PE14 (GPIO_PIOE_BASE + 14) +#define GPIO_PIN_PE15 (GPIO_PIOE_BASE + 15) +#define GPIO_PIN_PE16 (GPIO_PIOE_BASE + 16) +#define GPIO_PIN_PE17 (GPIO_PIOE_BASE + 17) +#define GPIO_PIN_PE18 (GPIO_PIOE_BASE + 18) +#define GPIO_PIN_PE19 (GPIO_PIOE_BASE + 19) +#define GPIO_PIN_PE20 (GPIO_PIOE_BASE + 20) +#define GPIO_PIN_PE21 (GPIO_PIOE_BASE + 21) +#define GPIO_PIN_PE22 (GPIO_PIOE_BASE + 22) +#define GPIO_PIN_PE23 (GPIO_PIOE_BASE + 23) +#define GPIO_PIN_PE24 (GPIO_PIOE_BASE + 24) +#define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25) +#define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26) + +static inline void *gpio_pin_to_addr(unsigned int pin) +{ + switch (pin >> 5) { + case 0: + return (void *)PIOA_BASE; + case 1: + return (void *)PIOB_BASE; + case 2: + return (void *)PIOC_BASE; + case 3: + return (void *)PIOD_BASE; + case 4: + return (void *)PIOE_BASE; + default: + return NULL; + } +} + +void gpio_select_periph_A(unsigned int pin, int use_pullup); +void gpio_select_periph_B(unsigned int pin, int use_pullup); + +void gpio_enable_ebi(void); +void gpio_enable_usart0(void); +void gpio_enable_usart1(void); +void gpio_enable_usart2(void); +void gpio_enable_usart3(void); + +#endif /* __ASM_AVR32_ARCH_GPIO_H__ */ + diff --git a/include/asm-avr32/arch-at32ap7000/hmatrix2.h b/include/asm-avr32/arch-at32ap7000/hmatrix2.h index e6df4b7fe3..b0e787a92f 100644 --- a/include/asm-avr32/arch-at32ap7000/hmatrix2.h +++ b/include/asm-avr32/arch-at32ap7000/hmatrix2.h @@ -224,9 +224,9 @@ | HMATRIX2_BF(name,value)) /* Register access macros */ -#define hmatrix2_readl(port,reg) \ - readl((port)->regs + HMATRIX2_##reg) -#define hmatrix2_writel(port,reg,value) \ - writel((value), (port)->regs + HMATRIX2_##reg) +#define hmatrix2_readl(reg) \ + readl((void *)HMATRIX_BASE + HMATRIX2_##reg) +#define hmatrix2_writel(reg,value) \ + writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg) #endif /* __ASM_AVR32_HMATRIX2_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/platform.h b/include/asm-avr32/arch-at32ap7000/platform.h deleted file mode 100644 index 759050116a..0000000000 --- a/include/asm-avr32/arch-at32ap7000/platform.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _ASM_AVR32_ARCH_PM_H -#define _ASM_AVR32_ARCH_PM_H - -#include - -enum clock_domain_id { - CLOCK_CPU, - CLOCK_HSB, - CLOCK_PBA, - CLOCK_PBB, - NR_CLOCK_DOMAINS, -}; - -enum resource_type { - RESOURCE_GPIO, - RESOURCE_CLOCK, -}; - -enum gpio_func { - GPIO_FUNC_GPIO, - GPIO_FUNC_A, - GPIO_FUNC_B, -}; - -enum device_id { - DEVICE_HEBI, - DEVICE_PBA_BRIDGE, - DEVICE_PBB_BRIDGE, - DEVICE_HRAMC, - /* GPIO controllers must be kept together */ - DEVICE_PIOA, - DEVICE_PIOB, - DEVICE_PIOC, - DEVICE_PIOD, - DEVICE_PIOE, - DEVICE_SM, - DEVICE_INTC, - DEVICE_HMATRIX, -#if defined(CFG_HPDC) - DEVICE_HPDC, -#endif -#if defined(CFG_MACB0) - DEVICE_MACB0, -#endif -#if defined(CFG_MACB1) - DEVICE_MACB1, -#endif -#if defined(CFG_LCDC) - DEVICE_LCDC, -#endif -#if defined(CFG_USART0) - DEVICE_USART0, -#endif -#if defined(CFG_USART1) - DEVICE_USART1, -#endif -#if defined(CFG_USART2) - DEVICE_USART2, -#endif -#if defined(CFG_USART3) - DEVICE_USART3, -#endif -#if defined(CFG_MMCI) - DEVICE_MMCI, -#endif -#if defined(CFG_DMAC) - DEVICE_DMAC, -#endif - NR_DEVICES, - NO_DEVICE = -1, -}; - -struct resource { - enum resource_type type; - union { - struct { - unsigned long base; - } iomem; - struct { - unsigned char nr_pins; - enum device_id gpio_dev; - enum gpio_func func; - unsigned short start; - } gpio; - struct { - enum clock_domain_id id; - unsigned char index; - } clock; - } u; -}; - -struct device { - void *regs; - unsigned int nr_resources; - const struct resource *resource; -}; - -struct clock_domain { - unsigned short reg; - enum clock_domain_id id; - enum device_id bridge; -}; - -extern const struct device chip_device[NR_DEVICES]; -extern const struct clock_domain chip_clock[NR_CLOCK_DOMAINS]; - -/** - * Set up PIO, clock management and I/O memory for a device. - */ -const struct device *get_device(enum device_id devid); -void put_device(const struct device *dev); - -int gpio_set_func(enum device_id gpio_devid, unsigned int start, - unsigned int nr_pins, enum gpio_func func); -void gpio_free(enum device_id gpio_devid, unsigned int start, - unsigned int nr_pins); - -void pm_init(void); -int pm_enable_clock(enum clock_domain_id id, unsigned int index); -void pm_disable_clock(enum clock_domain_id id, unsigned int index); -unsigned long pm_get_clock_freq(enum clock_domain_id domain); - -void cpu_enable_sdram(void); - -#endif /* _ASM_AVR32_ARCH_PM_H */ diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h index 01d836c639..3b6769b274 100644 --- a/include/asm-avr32/global_data.h +++ b/include/asm-avr32/global_data.h @@ -35,8 +35,6 @@ typedef struct global_data { bd_t *bd; unsigned long flags; - const struct device *console_uart; - const struct device *sm; unsigned long baudrate; unsigned long sdram_size; unsigned long have_console; /* serial_init() was called */ diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 458ebabeb9..717f54022c 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -62,9 +62,10 @@ */ #define CFG_PLL0_OPT 0x04 -#define CFG_USART1 1 - -#define CFG_CONSOLE_UART_DEV DEVICE_USART1 +#undef CONFIG_USART0 +#define CONFIG_USART1 1 +#undef CONFIG_USART2 +#undef CONFIG_USART3 /* User serviceable stuff */ #define CONFIG_CMDLINE_TAG 1 -- cgit v1.2.1 From 1f4f2121c2685182eb87fa9a9b799d1917387a1c Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Mon, 20 Nov 2006 15:53:10 +0100 Subject: AVR32: Relocate u-boot to SDRAM Relocate the u-boot image into SDRAM like everyone else does. This means that we can handle much larger .data and .bss than we used to. Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/global_data.h | 1 + include/configs/atstk1002.h | 10 +--------- 2 files changed, 2 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h index 3b6769b274..7c45b36259 100644 --- a/include/asm-avr32/global_data.h +++ b/include/asm-avr32/global_data.h @@ -37,6 +37,7 @@ typedef struct global_data { unsigned long flags; unsigned long baudrate; unsigned long sdram_size; + unsigned long stack_end; /* highest stack address */ unsigned long have_console; /* serial_init() was called */ unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of env struct */ diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 717f54022c..74636335a5 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -151,16 +151,8 @@ #define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) #define CFG_MALLOC_LEN (256*1024) -#define CFG_MALLOC_END \ - ({ \ - DECLARE_GLOBAL_DATA_PTR; \ - CFG_SDRAM_BASE + gd->sdram_size; \ - }) -#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN) - #define CFG_DMA_ALLOC_LEN (16384) -#define CFG_DMA_ALLOC_END (CFG_MALLOC_START) -#define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN) + /* Allow 2MB for the kernel run-time image */ #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) #define CFG_BOOTPARAMS_LEN (16 * 1024) -- cgit v1.2.1 From 12f099c08167a7a51aeee623bc16dafd0841271c Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Sun, 17 Dec 2006 14:46:06 +0100 Subject: AVR32: Use initdram() instead of board_init_memories() Conform to the "standard" interface and use initdram() instead of board_init_memories() on AVR32. This enables us to get rid of the sdram_size member of the global_data struct as well. Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/global_data.h | 1 - include/asm-avr32/initcalls.h | 2 -- 2 files changed, 3 deletions(-) (limited to 'include') diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h index 7c45b36259..681c514ccf 100644 --- a/include/asm-avr32/global_data.h +++ b/include/asm-avr32/global_data.h @@ -36,7 +36,6 @@ typedef struct global_data { bd_t *bd; unsigned long flags; unsigned long baudrate; - unsigned long sdram_size; unsigned long stack_end; /* highest stack address */ unsigned long have_console; /* serial_init() was called */ unsigned long reloc_off; /* Relocation Offset */ diff --git a/include/asm-avr32/initcalls.h b/include/asm-avr32/initcalls.h index 7ba25cde53..583e5dc101 100644 --- a/include/asm-avr32/initcalls.h +++ b/include/asm-avr32/initcalls.h @@ -26,8 +26,6 @@ extern int cpu_init(void); extern int timer_init(void); -extern void board_init_memories(void); -extern void board_init_pio(void); extern void board_init_info(void); #endif /* __ASM_AVR32_INITCALLS_H__ */ -- cgit v1.2.1 From 9c0deb5ae3ea0189f2e08ac29ef1316f1fb8548d Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Wed, 21 Mar 2007 19:44:48 +0100 Subject: AVR32: Provide a definition of struct stat Copy the definition of struct stat from the Linux kernel. Signed-off-by: Haavard Skinnemoen --- include/linux/stat.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'include') diff --git a/include/linux/stat.h b/include/linux/stat.h index 4d05aa92d9..7d6df8d694 100644 --- a/include/linux/stat.h +++ b/include/linux/stat.h @@ -125,6 +125,31 @@ struct stat { #endif /* __MIPS__ */ +#if defined(__AVR32__) + +struct stat { + unsigned long st_dev; + unsigned long st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned long st_rdev; + unsigned long st_size; + unsigned long st_blksize; + unsigned long st_blocks; + unsigned long st_atime; + unsigned long st_atime_nsec; + unsigned long st_mtime; + unsigned long st_mtime_nsec; + unsigned long st_ctime; + unsigned long st_ctime_nsec; + unsigned long __unused4; + unsigned long __unused5; +}; + +#endif /* __AVR32__ */ + #ifdef __cplusplus } #endif -- cgit v1.2.1 From 1b804b229556a4d862da93c0ec94e79419364b2c Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Wed, 21 Mar 2007 19:47:36 +0100 Subject: AVR32: Include more commands for ATSTK1000 Include the imi, imls and jffs commands sets by default on ATSTK1000. Also define CONFIG_BOOTARGS to something more useful, define CONFIG_BOOTCOMMAND and enable autoboot by default. Signed-off-by: Haavard Skinnemoen --- include/configs/atstk1002.h | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 74636335a5..807d4a4a8b 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -76,12 +76,27 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS \ - "console=ttyUS0 root=/dev/mtdblock1 fbmem=600k" + "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2 fbmem=600k" + +#define CONFIG_BOOTCOMMAND \ + "fsload; bootm $(fileaddr)" + +/* + * Only interrupt autoboot if is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 2 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " #define CONFIG_COMMANDS (CFG_CMD_BDI \ | CFG_CMD_LOADS \ | CFG_CMD_LOADB \ - /* | CFG_CMD_IMI */ \ + | CFG_CMD_IMI \ /* | CFG_CMD_CACHE */ \ | CFG_CMD_FLASH \ | CFG_CMD_MEMORY \ @@ -109,9 +124,10 @@ /* | CFG_CMD_PING */ \ /* | CFG_CMD_MMC */ \ /* | CFG_CMD_FAT */ \ - /* | CFG_CMD_IMLS */ \ + | CFG_CMD_IMLS \ /* | CFG_CMD_ITEST */ \ /* | CFG_CMD_EXT2 */ \ + | CFG_CMD_JFFS2 \ ) #include -- cgit v1.2.1 From 91975b0fea773c9e681fea8cf3349669f27685ee Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Sun, 17 Dec 2006 15:46:02 +0100 Subject: Import from the Linux kernel Instead of creating yet another set of MII register definitions in the macb driver, here's a complete set of definitions for everyone to use. Signed-off-by: Haavard Skinnemoen --- include/linux/mii.h | 158 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 include/linux/mii.h (limited to 'include') diff --git a/include/linux/mii.h b/include/linux/mii.h new file mode 100644 index 0000000000..5b99168c8d --- /dev/null +++ b/include/linux/mii.h @@ -0,0 +1,158 @@ +/* + * linux/mii.h: definitions for MII-compatible transceivers + * Originally drivers/net/sunhme.h. + * + * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com) + */ + +#ifndef __LINUX_MII_H__ +#define __LINUX_MII_H__ + +/* Generic MII registers. */ + +#define MII_BMCR 0x00 /* Basic mode control register */ +#define MII_BMSR 0x01 /* Basic mode status register */ +#define MII_PHYSID1 0x02 /* PHYS ID 1 */ +#define MII_PHYSID2 0x03 /* PHYS ID 2 */ +#define MII_ADVERTISE 0x04 /* Advertisement control reg */ +#define MII_LPA 0x05 /* Link partner ability reg */ +#define MII_EXPANSION 0x06 /* Expansion register */ +#define MII_DCOUNTER 0x12 /* Disconnect counter */ +#define MII_FCSCOUNTER 0x13 /* False carrier counter */ +#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ +#define MII_RERRCOUNTER 0x15 /* Receive error counter */ +#define MII_SREVISION 0x16 /* Silicon revision */ +#define MII_RESV1 0x17 /* Reserved... */ +#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ +#define MII_PHYADDR 0x19 /* PHY address */ +#define MII_RESV2 0x1a /* Reserved... */ +#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ +#define MII_NCONFIG 0x1c /* Network interface config */ + +/* Basic mode control register. */ +#define BMCR_RESV 0x003f /* Unused... */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_CTST 0x0080 /* Collision test */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ +#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define BMCR_RESET 0x8000 /* Reset the DP83840 */ + +/* Basic mode status register. */ +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ +#define BMSR_JCD 0x0002 /* Jabber detected */ +#define BMSR_LSTATUS 0x0004 /* Link status */ +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define BMSR_RFAULT 0x0010 /* Remote fault detected */ +#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ +#define BMSR_RESV 0x07c0 /* Unused... */ +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ + +/* Advertisement control register. */ +#define ADVERTISE_SLCT 0x001f /* Selector bits */ +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ +#define ADVERTISE_RESV 0x1c00 /* Unused... */ +#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ +#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ +#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ + +#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ + ADVERTISE_CSMA) +#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ + ADVERTISE_100HALF | ADVERTISE_100FULL) + +/* Link partner ability register. */ +#define LPA_SLCT 0x001f /* Same as advertise selector */ +#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ +#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ +#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ +#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ +#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ +#define LPA_RESV 0x1c00 /* Unused... */ +#define LPA_RFAULT 0x2000 /* Link partner faulted */ +#define LPA_LPACK 0x4000 /* Link partner acked us */ +#define LPA_NPAGE 0x8000 /* Next page bit */ + +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) + +/* Expansion register for auto-negotiation. */ +#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ +#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ +#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ +#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ +#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ +#define EXPANSION_RESV 0xffe0 /* Unused... */ + +/* N-way test register. */ +#define NWAYTEST_RESV1 0x00ff /* Unused... */ +#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ +#define NWAYTEST_RESV2 0xfe00 /* Unused... */ + + +/** + * mii_nway_result + * @negotiated: value of MII ANAR and'd with ANLPAR + * + * Given a set of MII abilities, check each bit and returns the + * currently supported media, in the priority order defined by + * IEEE 802.3u. We use LPA_xxx constants but note this is not the + * value of LPA solely, as described above. + * + * The one exception to IEEE 802.3u is that 100baseT4 is placed + * between 100T-full and 100T-half. If your phy does not support + * 100T4 this is fine. If your phy places 100T4 elsewhere in the + * priority order, you will need to roll your own function. + */ +static inline unsigned int mii_nway_result (unsigned int negotiated) +{ + unsigned int ret; + + if (negotiated & LPA_100FULL) + ret = LPA_100FULL; + else if (negotiated & LPA_100BASE4) + ret = LPA_100BASE4; + else if (negotiated & LPA_100HALF) + ret = LPA_100HALF; + else if (negotiated & LPA_10FULL) + ret = LPA_10FULL; + else + ret = LPA_10HALF; + + return ret; +} + +/** + * mii_duplex + * @duplex_lock: Non-zero if duplex is locked at full + * @negotiated: value of MII ANAR and'd with ANLPAR + * + * A small helper function for a common case. Returns one + * if the media is operating or locked at full duplex, and + * returns zero otherwise. + */ +static inline unsigned int mii_duplex (unsigned int duplex_lock, + unsigned int negotiated) +{ + if (duplex_lock) + return 1; + if (mii_nway_result(negotiated) & LPA_DUPLEX) + return 1; + return 0; +} + + +#endif /* __LINUX_MII_H__ */ -- cgit v1.2.1 From b4ec9c2d43d894729bb633bfdbdfa95a962c1556 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Sun, 17 Dec 2006 16:56:14 +0100 Subject: AVR32: Add clk and gpio infrastructure for macb0 and macb1 Implement functions for configuring the macb0 and macb1 pins, as well as functions for getting the clock rate of the various busses the macb ethernet controllers are connected to. Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/arch-at32ap7000/clk.h | 8 ++++++++ include/asm-avr32/arch-at32ap7000/gpio.h | 2 ++ 2 files changed, 10 insertions(+) (limited to 'include') diff --git a/include/asm-avr32/arch-at32ap7000/clk.h b/include/asm-avr32/arch-at32ap7000/clk.h index 4a25b17ad4..1ca5b48955 100644 --- a/include/asm-avr32/arch-at32ap7000/clk.h +++ b/include/asm-avr32/arch-at32ap7000/clk.h @@ -54,5 +54,13 @@ static inline unsigned long get_usart_clk_rate(unsigned int dev_id) { return get_pba_clk_rate(); } +static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) +{ + return get_pbb_clk_rate(); +} +static inline unsigned long get_macb_hclk_rate(unsigned int dev_id) +{ + return get_hsb_clk_rate(); +} #endif /* __ASM_AVR32_ARCH_CLK_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/gpio.h b/include/asm-avr32/arch-at32ap7000/gpio.h index adec2083f2..ca966e1342 100644 --- a/include/asm-avr32/arch-at32ap7000/gpio.h +++ b/include/asm-avr32/arch-at32ap7000/gpio.h @@ -205,6 +205,8 @@ void gpio_enable_usart0(void); void gpio_enable_usart1(void); void gpio_enable_usart2(void); void gpio_enable_usart3(void); +void gpio_enable_macb0(void); +void gpio_enable_macb1(void); #endif /* __ASM_AVR32_ARCH_GPIO_H__ */ -- cgit v1.2.1 From 9a24f477a1ed5bb0f74377c985d754ebbfa44872 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Sun, 17 Dec 2006 17:14:30 +0100 Subject: AVR32: Enable networking Implement MACB initialization for AVR32 and ATSTK1000, and turn everything on, including the MACB driver. Signed-off-by: Haavard Skinnemoen --- include/configs/atstk1002.h | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 807d4a4a8b..5e63ef8915 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -93,6 +93,22 @@ #define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " +/* + * These are "locally administered ethernet addresses" generated by + * ./tools/gen_eth_addr + * + * After booting the board for the first time, new addresses should be + * generated and assigned to the environment variables "ethaddr" and + * "eth1addr". + */ +#define CONFIG_ETHADDR "6a:87:71:14:cd:cb" +#define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6" +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_SUBNETMASK \ + | CONFIG_BOOTP_GATEWAY) + #define CONFIG_COMMANDS (CFG_CMD_BDI \ | CFG_CMD_LOADS \ | CFG_CMD_LOADB \ @@ -100,7 +116,7 @@ /* | CFG_CMD_CACHE */ \ | CFG_CMD_FLASH \ | CFG_CMD_MEMORY \ - /* | CFG_CMD_NET */ \ + | CFG_CMD_NET \ | CFG_CMD_ENV \ /* | CFG_CMD_IRQ */ \ | CFG_CMD_BOOTD \ @@ -112,7 +128,7 @@ /* | CFG_CMD_I2C */ \ | CFG_CMD_REGINFO \ /* | CFG_CMD_DATE */ \ - /* | CFG_CMD_DHCP */ \ + | CFG_CMD_DHCP \ /* | CFG_CMD_AUTOSCRIPT */ \ /* | CFG_CMD_MII */ \ | CFG_CMD_MISC \ @@ -133,6 +149,7 @@ #include #define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 #define CONFIG_PIO2 1 #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 -- cgit v1.2.1 From 05fdab1ef6a10d049a50021a86f1226f444d9b9f Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Sun, 17 Dec 2006 18:55:37 +0100 Subject: AVR32: Add clk and gpio infrastructure for mmci Implement functions for configuring the mmci pins, as well as functions for getting the clock rate of the mmci controller. Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/arch-at32ap7000/clk.h | 4 ++++ include/asm-avr32/arch-at32ap7000/gpio.h | 1 + 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/include/asm-avr32/arch-at32ap7000/clk.h b/include/asm-avr32/arch-at32ap7000/clk.h index 1ca5b48955..7e20d97b7f 100644 --- a/include/asm-avr32/arch-at32ap7000/clk.h +++ b/include/asm-avr32/arch-at32ap7000/clk.h @@ -62,5 +62,9 @@ static inline unsigned long get_macb_hclk_rate(unsigned int dev_id) { return get_hsb_clk_rate(); } +static inline unsigned long get_mci_clk_rate(void) +{ + return get_pbb_clk_rate(); +} #endif /* __ASM_AVR32_ARCH_CLK_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/gpio.h b/include/asm-avr32/arch-at32ap7000/gpio.h index ca966e1342..8d9b092750 100644 --- a/include/asm-avr32/arch-at32ap7000/gpio.h +++ b/include/asm-avr32/arch-at32ap7000/gpio.h @@ -207,6 +207,7 @@ void gpio_enable_usart2(void); void gpio_enable_usart3(void); void gpio_enable_macb0(void); void gpio_enable_macb1(void); +void gpio_enable_mmci(void); #endif /* __ASM_AVR32_ARCH_GPIO_H__ */ -- cgit v1.2.1 From fc26c97bb6df41b4a95662c34054fe912387bf38 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Fri, 20 Jan 2006 10:03:53 +0100 Subject: Atmel MCI driver Driver for the Atmel MCI controller (MMC interface) for AT32AP CPUs. The AT91 ARM-based CPUs use basically the same hardware, so it should be possible to share this driver, but no effort has been made so far. Hardware documentation can be found in the AT32AP7000 data sheet, which can be downloaded from http://www.atmel.com/dyn/products/datasheets.asp?family_id=682 Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/arch-at32ap7000/mmc.h | 96 +++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 include/asm-avr32/arch-at32ap7000/mmc.h (limited to 'include') diff --git a/include/asm-avr32/arch-at32ap7000/mmc.h b/include/asm-avr32/arch-at32ap7000/mmc.h new file mode 100644 index 0000000000..fcfbbb3c6c --- /dev/null +++ b/include/asm-avr32/arch-at32ap7000/mmc.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_MMC_H +#define __ASM_AVR32_MMC_H + +struct mmc_cid { + unsigned long psn; + unsigned short oid; + unsigned char mid; + unsigned char prv; + unsigned char mdt; + char pnm[7]; +}; + +struct mmc_csd +{ + u8 csd_structure:2, + spec_vers:4, + rsvd1:2; + u8 taac; + u8 nsac; + u8 tran_speed; + u16 ccc:12, + read_bl_len:4; + u64 read_bl_partial:1, + write_blk_misalign:1, + read_blk_misalign:1, + dsr_imp:1, + rsvd2:2, + c_size:12, + vdd_r_curr_min:3, + vdd_r_curr_max:3, + vdd_w_curr_min:3, + vdd_w_curr_max:3, + c_size_mult:3, + sector_size:5, + erase_grp_size:5, + wp_grp_size:5, + wp_grp_enable:1, + default_ecc:2, + r2w_factor:3, + write_bl_len:4, + write_bl_partial:1, + rsvd3:5; + u8 file_format_grp:1, + copy:1, + perm_write_protect:1, + tmp_write_protect:1, + file_format:2, + ecc:2; + u8 crc:7; + u8 one:1; +}; + +/* MMC Command numbers */ +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RELATIVE_ADDR 3 +#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3 +#define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_WRITE_BLOCK 24 +#define MMC_CMD_APP_CMD 55 + +#define MMC_ACMD_SD_SEND_OP_COND 41 + +#define R1_ILLEGAL_COMMAND (1 << 22) +#define R1_APP_CMD (1 << 5) + +#endif /* __ASM_AVR32_MMC_H */ -- cgit v1.2.1 From 8e6875183cdca91c134408d119d4abcd48ef6856 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Sun, 17 Dec 2006 18:56:46 +0100 Subject: AVR32: Enable MMC support Set up the portmux for the MMC interface and enable the MMC driver along with support for DOS partitions, ext2 and FAT filesystems. Signed-off-by: Haavard Skinnemoen --- include/configs/atstk1002.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 5e63ef8915..ed3ee5a164 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -68,6 +68,8 @@ #undef CONFIG_USART3 /* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMDLINE_TAG 1 #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 @@ -138,11 +140,11 @@ /* | CFG_CMD_SAVES */ \ /* | CFG_CMD_SPI */ \ /* | CFG_CMD_PING */ \ - /* | CFG_CMD_MMC */ \ - /* | CFG_CMD_FAT */ \ + | CFG_CMD_MMC \ + | CFG_CMD_FAT \ | CFG_CMD_IMLS \ /* | CFG_CMD_ITEST */ \ - /* | CFG_CMD_EXT2 */ \ + | CFG_CMD_EXT2 \ | CFG_CMD_JFFS2 \ ) @@ -153,6 +155,7 @@ #define CONFIG_PIO2 1 #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 -- cgit v1.2.1 From 3f9f08cf91c8a6949a5d78a18bd3d8df7b86d888 Mon Sep 17 00:00:00 2001 From: Gerald Van Baren Date: Sat, 14 Apr 2007 22:46:41 -0400 Subject: Add some utilities to manipulate the reserved memory map. --- include/libfdt.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/libfdt.h b/include/libfdt.h index 61f56ec0d5..f8bac73a31 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -86,6 +86,8 @@ void *fdt_getprop(const void *fdt, int nodeoffset, uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset, char **namep); +int fdt_num_reservemap(void *fdt, int *used, int *total); +int fdt_get_reservemap(void *fdt, int n, struct fdt_reserve_entry *re); /* Write-in-place functions */ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, @@ -99,6 +101,8 @@ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, int fdt_nop_property(void *fdt, int nodeoffset, const char *name); int fdt_nop_node(void *fdt, int nodeoffset); +int fdt_insert_reservemap_entry(void *fdt, int n, uint64_t addr, uint64_t size); + /* Sequential-write functions */ int fdt_create(void *buf, int bufsize); @@ -115,6 +119,7 @@ int fdt_property(void *fdt, const char *name, const void *val, int len); fdt_property(fdt, name, str, strlen(str)+1) int fdt_end_node(void *fdt); int fdt_finish(void *fdt); +int fdt_replace_reservemap_entry(void *fdt, int n, uint64_t addr, uint64_t size); /* Read-write functions */ int fdt_open_into(void *fdt, void *buf, int bufsize); -- cgit v1.2.1 From 90e6f41cf09fc98f6ccb510e183d53ab8546cf2f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 18 Apr 2007 12:05:59 +0200 Subject: ppc4xx: Add output for bootrom location to 405EZ ports Now 405EZ ports also show upon bootup from which boot device they are configured to boot: U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05) CPU: AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz) Bootstrap Option E - Boot ROM Location EBC (32 bits) 16 kB I-Cache 16 kB D-Cache Board: Acadia - AMCC PPC405EZ Evaluation Board Signed-off-by: Stefan Roese --- include/ppc405.h | 2 ++ include/ppc440.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/ppc405.h b/include/ppc405.h index 08f10d27b2..a2503a93d2 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -570,6 +570,8 @@ #define SDR_ICTX0_STAT 0x40000000 #define SDR_ICTX1_STAT 0x20000000 +#define SDR_PINSTP 0x40 + /****************************************************************************** * Control ******************************************************************************/ diff --git a/include/ppc440.h b/include/ppc440.h index 51e6b9b28c..bc1d7aad73 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -148,7 +148,7 @@ #define sdrcfgd (SDR_DCR_BASE+0x1) #define sdr_sdstp0 0x0020 /* */ #define sdr_sdstp1 0x0021 /* */ -#define sdr_pinstp 0x0040 +#define SDR_PINSTP 0x0040 #define sdr_sdcs 0x0060 #define sdr_ecid0 0x0080 #define sdr_ecid1 0x0081 -- cgit v1.2.1 From d21686263574e95cb3e9e9b0496f968b1b897fdb Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 19 Apr 2007 09:53:52 +0200 Subject: ppc4xx: Fix chip select timing for SysACE access on AMCC Katmai Previous versions used full wait states for the chip select #1 which is connected to the Xilinix SystemACE controller on the AMCC Katmai evaluation board. This leads to really slow access and therefore low performance. This patch now sets up the chip select a lot faster resulting in much better read/write performance of the Linux driver. Signed-off-by: Stefan Roese --- include/configs/katmai.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 7f55366ca5..cc47a168ed 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -360,7 +360,19 @@ EBC_BXCR_BW_16BIT) /* Memory Bank 1 (Xilinx System ACE controller) initialization */ -#define CFG_EBC_PB1AP 0x7F8FFE80 +#define CFG_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(4) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_NONDELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) #define CFG_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE) | \ EBC_BXCR_BS_1MB | \ EBC_BXCR_BU_RW | \ -- cgit v1.2.1 From 39f23cd90947639ac278a18ff277ec786b5ac167 Mon Sep 17 00:00:00 2001 From: Domen Puncer Date: Fri, 20 Apr 2007 11:13:16 +0200 Subject: [RFC PATCH] icecube/lite5200b: fix OF_TBCLK (timebase-frequency) calculation G2 core reference manual says decrementer and time base are decreasing/increasing once every 4 bus clock cycles. Lets fix it, so time in Linux won't run twice as fast Signed-off-by: Domen Puncer Acked-by: Grant Likely --- include/configs/IceCube.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 0d3825413e..598811240a 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -182,7 +182,7 @@ #define OF_CPU "PowerPC,5200@0" #define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" /* -- cgit v1.2.1 From 6923565db12af34fd5e02d354ee65a8c78ac460f Mon Sep 17 00:00:00 2001 From: Detlev Zundel Date: Fri, 20 Apr 2007 12:01:47 +0200 Subject: Fix breakage of NC650 board with respect to nand support. Signed-off-by: Detlev Zundel --- include/configs/NC650.h | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) (limited to 'include') diff --git a/include/configs/NC650.h b/include/configs/NC650.h index 8da29c4afc..a12c8da13e 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 Detlev Zundel, dzu@denx.de + * (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de * (C) Copyright 2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * @@ -237,18 +237,8 @@ /* * NAND flash support */ -#define CFG_NAND_LEGACY - #define CFG_MAX_NAND_DEVICE 1 -#define NAND_ChipID_UNKNOWN 0x00 -#define SECTORSIZE 512 -#define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define ADDR_COLUMN 1 -#define NAND_NO_RB - /*----------------------------------------------------------------------- * SYPCR - System Protection Control 11-9 -- cgit v1.2.1 From 323bfa8f436dc3bc57187c9b1488bc3146ff1522 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 23 Apr 2007 12:00:22 +0200 Subject: Remove BOARDLIBS usage completely Signed-off-by: Stefan Roese --- include/configs/delta.h | 1 - include/configs/zylonite.h | 1 - 2 files changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/delta.h b/include/configs/delta.h index 91284fdace..15681208b6 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -188,7 +188,6 @@ /* * NAND Flash */ -/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */ #undef CFG_NAND_LEGACY #define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */ diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index c6aa8ece5b..1e8ed7abdf 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -174,7 +174,6 @@ /* * NAND Flash */ -/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */ #define CONFIG_NEW_NAND_CODE #define CFG_NAND0_BASE 0x0 #undef CFG_NAND1_BASE -- cgit v1.2.1 From 41fb7e0f1ec9b91bdae2565bab5f2e3ee15039c7 Mon Sep 17 00:00:00 2001 From: Zang Roy-r61911 Date: Thu, 14 Dec 2006 14:14:55 +0800 Subject: u-boot: Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board. Signed-off-by: Roy Zang --- include/asm-ppc/mmu.h | 1 + include/configs/MPC8548CDS.h | 28 ++++++++++++++++++++-------- 2 files changed, 21 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index b226825ee2..67c2c571ed 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -413,6 +413,7 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 +#define LAWAR_TRGT_IF_PEX 0x00200000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 7c4849fadf..bfd316cb94 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -36,7 +36,7 @@ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ -#undef CONFIG_PCI +#define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ @@ -344,18 +344,30 @@ extern unsigned long get_clock_freq(void); */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ #define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ -#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_BASE 0x90000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS 0xe2100000 -#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_IO_BASE 0xe2800000 +#define CFG_PCI2_IO_PHYS 0xe2800000 +#define CFG_PCI2_IO_SIZE 0x00800000 /* 8M */ + +#define CFG_PEX_MEM_BASE 0xa0000000 +#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE +#define CFG_PEX_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PEX_IO_BASE 0xe3000000 +#define CFG_PEX_IO_PHYS CFG_PEX_IO_BASE +#define CFG_PEX_IO_SIZE 0x1000000 /* 16M */ +/* + * RapidIO MMU + */ +#define CFG_RIO_MEM_BASE 0xC0000000 +#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ #if defined(CONFIG_PCI) -- cgit v1.2.1 From 39b18c4f3e0b6d0dc00f4e68bad2da3766c85f09 Mon Sep 17 00:00:00 2001 From: "ebony.zhu@freescale.com" Date: Mon, 18 Dec 2006 16:25:15 +0800 Subject: u-boot: Disables MPC8548CDS 2T_TIMING for DDR by default This patch disables MPC8548CDS 2T_TIMING for DDR by default. Signed-off-by:Ebony Zhu --- include/configs/MPC8548CDS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index bfd316cb94..687fe84850 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -41,7 +41,7 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -- cgit v1.2.1 From 362dd83077ac04c0296bca3e824ec2fb3d44d9d6 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 27 Dec 2006 22:07:15 +0300 Subject: Fix PCI I/O space mapping on Freescale MPC85x0ADS The PCI I/O space mapping for Freescale MPC8540ADS board was broken by commit 52c7a68b8d587ebcf5a6b051b58b3d3ffa377ddc which failed to update the #define's describing the local address window used for the PCI I/O space accesses -- fix this and carry over the necessary changes into the MPC8560ADS code since the PCI I/O space mapping was also broken for this board (by the earlier commit 087454609e47295443af793a282cddcd91a5f49c). Add the comments clarifying how the PCI I/O space must be mapped to all the MPC85xx board config. headers. Signed-off-by: Sergei Shtylyov board/mpc8540ads/init.S | 4 ++-- board/mpc8560ads/init.S | 4 ++-- include/configs/MPC8540ADS.h | 5 ++--- include/configs/MPC8541CDS.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/MPC8560ADS.h | 8 ++++---- 6 files changed, 12 insertions(+), 13 deletions(-) --- include/configs/MPC8540ADS.h | 5 ++--- include/configs/MPC8541CDS.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/MPC8560ADS.h | 8 ++++---- 4 files changed, 8 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 74a84f4e86..5aeea58680 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -330,13 +330,12 @@ /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ - -#define CFG_PCI1_IO_BASE 0x0 +#define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index db389cfe67..fb360d282c 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -334,7 +334,7 @@ extern unsigned long get_clock_freq(void); /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 687fe84850..14936c28ae 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -340,7 +340,7 @@ extern unsigned long get_clock_freq(void); /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 835bf5cb64..21e6637680 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -320,14 +320,14 @@ /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) -- cgit v1.2.1 From 0cde4b00fc7393b89f379d83a9d436dcb1334bfa Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 11 Apr 2007 16:50:57 -0500 Subject: Add MPC8544DS main configuration file. Signed-off-by: Ed Swarthout Signed-off-by: Jon Loeliger --- include/configs/MPC8544DS.h | 591 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 591 insertions(+) create mode 100644 include/configs/MPC8544DS.h (limited to 'include') diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h new file mode 100644 index 0000000000..4c3430897d --- /dev/null +++ b/include/configs/MPC8544DS.h @@ -0,0 +1,591 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8544ds board configuration file + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8544 1 +#define CONFIG_MPC8544DS 1 + +#undef CONFIG_PCI /* Enable PCI/PCIE */ +#undef CONFIG_PCI1 /* PCI controller 1 */ +#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#undef CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ +#undef CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ +#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#undef CONFIG_DDR_DLL +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_DDR_ECC_CMD + +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash associated with the CDS board. + * This allows booting from a promjet. + */ +#define CONFIG_ASSUME_AMD_FLASH + +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ + +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(unsigned long dummy); +#endif +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00400000 +#define CFG_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) +#define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) +#define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000) + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +/* + * Make sure required options are set + */ +#ifndef CONFIG_SPD_EEPROM +#error ("CONFIG_SPD_EEPROM is required") +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * + * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable + * + * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable + * + * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable + * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable + * + * Localbus cacheable + * + * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable + * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 + * + * Localbus non-cacheable + * + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable + * + */ + +/* + * Local Bus Definitions + */ +#define CFG_BOOT_BLOCK 0xfc000000 /* boot TLB */ + +#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ + +#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ + +#define CFG_BR0_PRELIM 0xff801001 +#define CFG_BR1_PRELIM 0xfe801001 + +#define CFG_OR0_PRELIM 0xff806e65 +#define CFG_OR1_PRELIM 0xff806e65 + +#define CFG_FLASH_BANKS_LIST {0xfe800000,CFG_FLASH_BASE} + +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + +#define CFG_LBC_NONCACHE_BASE 0xf8000000 + +#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ +#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ + +#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ +#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ + +#define PIXIS_BASE 0xf8100000 /* PIXIS registers */ +#define PIXIS_ID 0x0 /* Board ID at offset 0 */ +#define PIXIS_VER 0x1 /* Board version at offset 1 */ +#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ +#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ +#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch + * register */ +#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_VCTL 0x10 /* VELA Control Register */ +#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ +#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ +#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ +#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ +#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ +#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ + + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM 1 +#define CFG_INIT_L1_LOCK 1 +#define CFG_INIT_L1_ADDR 0xf4010000 /* Initial L1 address */ +#define CFG_INIT_L1_END 0x00004000 /* End of used area in RAM */ + +/* define to use L2SRAM as initial stack */ +#undef CONFIG_L2_INIT_RAM +#define CFG_INIT_L2_ADDR 0xf8fc0000 +#define CFG_INIT_L2_END 0x00040000 /* End of used area in RAM */ + +#ifdef CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_ADDR CFG_INIT_L1_ADDR +#define CFG_INIT_RAM_END CFG_INIT_L1_END +#else +#define CFG_INIT_RAM_ADDR CFG_INIT_L2_ADDR +#define CFG_INIT_RAM_END CFG_INIT_L2_END +#endif + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8544@0" +#define OF_SOC "soc8544@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8544@e0000000/serial@4500" + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3100 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CFG_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ +#define CFG_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ + +#define CFG_PCI1_MEM_BASE 0xc0000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe1000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +/* controller 2, Slot 1, tgtid 1, Base address 9000 */ +#define CFG_PCIE2_MEM_BASE 0x80000000 +#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE +#define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE2_IO_BASE 0x00000000 +#define CFG_PCIE2_IO_PHYS 0xe2000000 +#define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */ + +/* controller 1, Slot 2,tgtid 2, Base address a000 */ +#define CFG_PCIE1_MEM_BASE 0xa0000000 +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x08000000 /* 128M */ +#define CFG_PCIE1_MEM_BASE2 0xa8000000 +#define CFG_PCIE1_MEM_PHYS2 CFG_PCIE1_MEM_BASE2 +#define CFG_PCIE1_MEM_SIZE2 0x04000000 /* 64M */ +#define CFG_PCIE1_IO_BASE 0x00000000 /* reuse mem LAW */ +#define CFG_PCIE1_IO_PHYS 0xaf000000 +#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ + +/* controller 3, direct to uli, tgtid 3, Base address b000 */ +#define CFG_PCIE3_MEM_BASE 0xb0000000 +#define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE +#define CFG_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCIE3_IO_BASE 0x00000000 +#define CFG_PCIE3_IO_PHYS 0xe3000000 +#define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP +#define CONFIG_RTL8139 + +#ifdef CONFIG_RTL8139 +/* This macro is used by RTL8139 but not defined in PPC architecture */ +#define KSEG1ADDR(x) (x) +#define _IO_BASE 0x00000000 +#endif + +#ifndef CONFIG_PCI_PNP + #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE + #define PCI_ENET0_MEMADDR CFG_PCI1_IO_BASE + #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#define CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SATA_ULI5288 +#define CFG_SCSI_MAX_SCSI_ID 4 +#define CFG_SCSI_MAX_LUN 1 +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE +#endif /* SCSCI */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC1" +#define CONFIG_MPC85XX_TSEC3 1 +#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC3" +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 0 +#define TSEC3_PHY_ADDR 1 + +#define TSEC1_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#if CFG_MONITOR_BASE > 0xfff80000 +#define CFG_ENV_ADDR 0xfff80000 +#else +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#endif +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII \ + | CFG_CMD_BEDBUG \ + | CFG_CMD_NET) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#endif +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:02:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD +#endif + +#define CONFIG_IPADDR 192.168.1.251 + +#define CONFIG_HOSTNAME 8544ds_unknown +#define CONFIG_ROOTPATH /nfs/mpc85xx +#define CONFIG_BOOTFILE 8544ds_tmt/uImage.uboot + +#define CONFIG_SERVERIP 192.168.0.1 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_NETMASK 255.255.0.0 + +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ + +#define CONFIG_BAUDRATE 115200 + +#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3) +#define PCIE_ENV \ + "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ + "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ + "pcie1regs=setenv a e000a; run pciereg\0" \ + "pcie2regs=setenv a e0009; run pciereg\0" \ + "pcie3regs=setenv a e000b; run pciereg\0" \ + "pcieerr=md ${a}020 1; md ${a}e00;" \ + "pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ + "pci d.w $b.0 56 1;" \ + "pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \ + "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff;" \ + "pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff;" \ + "pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \ + "pci w $b.0 130 ffffffff\0" \ + "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ + "pcie1err=setenv a e000a; run pcieerr\0" \ + "pcie2err=setenv a e0009; run pcieerr\0" \ + "pcie3err=setenv a e000b; run pcieerr\0" \ + "pcie1errc=setenv a e000a; run pcieerrc\0" \ + "pcie2errc=setenv a e0009; run pcieerrc\0" \ + "pcie3errc=setenv a e000b; run pcieerrc\0" +#else +#define PCIE_ENV "" +#endif + +#if defined(CONFIG_PCI1) +#define PCI_ENV \ + "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ + "echo e;md ${a}e00 9\0" \ + "pci1regs=setenv a e0008; run pcireg\0" \ + "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ + "pci d.w $b.0 56 1\0" \ + "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ + "pci w.w $b.0 56 ffff\0" \ + "pci1err=setenv a e0008; run pcierr\0" \ + "pci1errc=setenv a e0008; run pcierrc\0" +#else +#define PCI_ENV "" +#endif + +#if defined(CONFIG_TSEC_ENET) +#define ENET_ENV \ + "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \ + "md ${a}098 2\0" \ + "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \ + "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \ + "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \ + "echo mib;md ${a}680 31\0" \ + "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \ + "enet1regs=setenv a e0024; run enetreg\0" \ + "enet3regs=setenv a e0026; run enetreg\0" +#else +#define ENET_ENV "" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=8544ds_tmt/ramdisk.uboot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=8544ds_tmt/mpc8544ds.dtb\0" \ + "eoi=mw e00400b0 0\0" \ + "iack=md e00400a0 1\0" \ + "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ + "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ + "ddrregs=setenv a e0002; run ddrreg\0" \ + "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \ + "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ + "guregs=setenv a e00e0; run gureg\0" \ + "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ + "ecmregs=setenv a e0001; run ecmreg\0" \ + PCIE_ENV \ + PCI_ENV \ + ENET_ENV + + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs root=/dev/sda3 rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#endif /* __CONFIG_H */ -- cgit v1.2.1 From 45cef612cc601d2d1c890fbbd7cdc9609a189a46 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Fri, 23 Feb 2007 17:11:16 -0600 Subject: Changed BOOKE_PAGESZ_nGB to BOOKE_PAGESZ_nG The other pagesz constants use one letter to specify order of magnitude. Also change the one reference to it in mpc8548cds/init.S Signed-off-by: Andy Fleming --- include/asm-ppc/mmu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 67c2c571ed..48fd982950 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -396,8 +396,8 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define BOOKE_PAGESZ_16M 7 #define BOOKE_PAGESZ_64M 8 #define BOOKE_PAGESZ_256M 9 -#define BOOKE_PAGESZ_1GB 10 -#define BOOKE_PAGESZ_4GB 11 +#define BOOKE_PAGESZ_1G 10 +#define BOOKE_PAGESZ_4G 11 #if defined(CONFIG_MPC86xx) #define LAWBAR_BASE_ADDR 0x00FFFFFF -- cgit v1.2.1 From 81f481ca708ed6a56bf9c410e3191dbad581c565 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 23 Apr 2007 02:24:28 -0500 Subject: Enable 8544 support * Add support to the Makefile * Add 8544 configuration support to the tsec driver * Add 8544 SVR numbers to processor.h Signed-off-by: Ed Swarthout Signed-off-by: Jon Loeliger --- include/asm-ppc/processor.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 058596275f..944cbe90c3 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -232,6 +232,9 @@ #define HID0_BHTE (1<<2) /* Branch History Table Enable */ #define HID0_BTCD (1<<1) /* Branch target cache disable */ #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ +#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ +#define HID1_ASTME (1<<13) /* Address bus streaming mode */ +#define HID1_ABE (1<<12) /* Address broadcast enable */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #ifndef CONFIG_BOOKE #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ @@ -415,10 +418,12 @@ #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ /* e500 definitions */ -#define SPRN_L1CSR0 0x3f2 /* L1 Cache Control and Status Register 0 */ +#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ +#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ -#define SPRN_L1CSR1 0x3f3 /* L1 Cache Control and Status Register 1 */ +#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ +#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ @@ -840,6 +845,8 @@ #define SVR_8560 0x8070 #define SVR_8555 0x8079 #define SVR_8541 0x807A +#define SVR_8544 0x8034 +#define SVR_8544_E 0x803C #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 #define SVR_8641 0x8090 -- cgit v1.2.1 From 8b39501d28754e72726ce7fb02310e56dbdf116a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sun, 29 Apr 2007 14:13:01 +0200 Subject: ppc4xx: Bamboo: Use current NAND driver and *not* the legacy driver Signed-off-by: Stefan Roese --- include/configs/bamboo.h | 67 +++++------------------------------------------- 1 file changed, 7 insertions(+), 60 deletions(-) (limited to 'include') diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index bcc736ceb5..db58a9fa74 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005-2006 + * (C) Copyright 2005-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -43,7 +43,6 @@ * 2nd ethernet port you have to "undef" the following define. */ #define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */ -#define CFG_NAND_LEGACY /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -143,65 +142,13 @@ #endif /* CFG_ENV_IS_IN_FLASH */ /*----------------------------------------------------------------------- - * NAND-FLASH related + * NAND FLASH *----------------------------------------------------------------------*/ -#define NAND_CMD_REG (0x00) /* NandFlash Command Register */ -#define NAND_ADDR_REG (0x04) /* NandFlash Address Register */ -#define NAND_DATA_REG (0x08) /* NandFlash Data Register */ -#define NAND_ECC0_REG (0x10) /* NandFlash ECC Register0 */ -#define NAND_ECC1_REG (0x14) /* NandFlash ECC Register1 */ -#define NAND_ECC2_REG (0x18) /* NandFlash ECC Register2 */ -#define NAND_ECC3_REG (0x1C) /* NandFlash ECC Register3 */ -#define NAND_ECC4_REG (0x20) /* NandFlash ECC Register4 */ -#define NAND_ECC5_REG (0x24) /* NandFlash ECC Register5 */ -#define NAND_ECC6_REG (0x28) /* NandFlash ECC Register6 */ -#define NAND_ECC7_REG (0x2C) /* NandFlash ECC Register7 */ -#define NAND_CR0_REG (0x30) /* NandFlash Device Bank0 Config Register */ -#define NAND_CR1_REG (0x34) /* NandFlash Device Bank1 Config Register */ -#define NAND_CR2_REG (0x38) /* NandFlash Device Bank2 Config Register */ -#define NAND_CR3_REG (0x3C) /* NandFlash Device Bank3 Config Register */ -#define NAND_CCR_REG (0x40) /* NandFlash Core Configuration Register */ -#define NAND_STAT_REG (0x44) /* NandFlash Device Status Register */ -#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */ -#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */ - -/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */ -#define NAND0_CMD_READ1_HALF1 0x00 /* Starting addr for 1rst half of registers */ -#define NAND0_CMD_READ1_HALF2 0x01 /* Starting addr for 2nd half of registers */ -#define NAND0_CMD_READ2 0x50 -#define NAND0_CMD_READ_ID 0x90 -#define NAND0_CMD_READ_STATUS 0x70 -#define NAND0_CMD_RESET 0xFF -#define NAND0_CMD_PAGE_PROG 0x80 -#define NAND0_CMD_PAGE_PROG_TRUE 0x10 -#define NAND0_CMD_PAGE_PROG_DUMMY 0x11 -#define NAND0_CMD_BLOCK_ERASE 0x60 -#define NAND0_CMD_BLOCK_ERASE_END 0xD0 - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0) -#define WRITE_NAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0) -#define READ_NAND(adr) (*(volatile u8 *)((ulong)adr+NAND_DATA_REG)) -#define NAND_WAIT_READY(nand) while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01)) - -/* not needed with 440EP NAND controller */ -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_CS 1 +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ /*----------------------------------------------------------------------- * DDR SDRAM -- cgit v1.2.1 From a75af9bfd8fff0499efdbb90601cec5a2afef117 Mon Sep 17 00:00:00 2001 From: James Yang Date: Wed, 7 Feb 2007 15:28:04 -0600 Subject: Conditionalize 8641 Rev1.0 MCM workarounds Signed-off-by: James Yang Signed-off-by: Jon Loeliger --- include/mpc86xx.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/mpc86xx.h b/include/mpc86xx.h index bc8ba3f2da..673bfed16e 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -9,6 +9,15 @@ #define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ + +/* + * platform register addresses + */ + +#define GUTS_SVR (CFG_CCSRBAR + 0xE00A4) +#define MCM_ABCR (CFG_CCSRBAR + 0x01000) +#define MCM_DBCR (CFG_CCSRBAR + 0x01008) + /* * l2cr values. Look in config_.h for the actual setup */ -- cgit v1.2.1 From 6743105988fc44d5b0d30388c790607835aae7a6 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 23 Apr 2007 02:54:25 -0500 Subject: Add support for the 8568 MDS board This included some changes to common files: * Add 8568 processor SVR to various places * Add support for setting the qe bus-frequency value in the dts * Add the 8568MDS target to the Makefile Signed-off-by: Andy Fleming --- include/asm-ppc/processor.h | 1 + include/configs/MPC8568MDS.h | 505 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 506 insertions(+) create mode 100644 include/configs/MPC8568MDS.h (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 944cbe90c3..e9361c5174 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -850,6 +850,7 @@ #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 #define SVR_8641 0x8090 +#define SVR_8568_E 0x807D /* I am just adding a single entry for 8260 boards. I think we may be diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h new file mode 100644 index 0000000000..66293c5221 --- /dev/null +++ b/include/configs/MPC8568MDS.h @@ -0,0 +1,505 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8568mds board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ +#define CONFIG_MPC8568 1 /* MPC8568 specific */ +#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ + +#undef CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +/*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */ + +/*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */ +/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + + +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash associated with the MDS board. + * This allows booting from a promjet. + */ +#define CONFIG_ASSUME_AMD_FLASH + +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ + +#ifndef __ASSEMBLY__ +extern unsigned long get_clock_freq(void); +#endif /*Replace a call to get_clock_freq (after it is implemented)*/ +#define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +/*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +/* + * Make sure required options are set + */ +#ifndef CONFIG_SPD_EEPROM +#error ("CONFIG_SPD_EEPROM is required") +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + + +/* + * Local Bus Definitions + */ + +/* + * FLASH on the Local Bus + * Two banks, 8M each, using the CFI driver. + * Boot from BR0/OR0 bank at 0xff00_0000 + * Alternate BR1/OR1 bank at 0xff80_0000 + * + * BR0, BR1: + * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 + * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 + * Port Size = 16 bits = BRx[19:20] = 10 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 + * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 + * + * OR0, OR1: + * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 + * Reserved ORx[17:18] = 11, confusion here? + * CSNT = ORx[20] = 1 + * ACS = half cycle delay = ORx[21:22] = 11 + * SCY = 6 = ORx[24:27] = 0110 + * TRLX = use relaxed timing = ORx[29] = 1 + * EAD = use external address latch delay = OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx + */ +#define CFG_BCSR_BASE 0xf8000000 + +#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ + +/*Chip select 0 - Flash*/ +#define CFG_BR0_PRELIM 0xfe001001 +#define CFG_OR0_PRELIM 0xfe006ff7 + +/*Chip slelect 1 - BCSR*/ +#define CFG_BR1_PRELIM 0xf8000801 +#define CFG_OR1_PRELIM 0xffffe9f7 + +//#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 512 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + + +/* + * SDRAM on the LocalBus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + + +/*Chip select 2 - SDRAM*/ +#define CFG_BR2_PRELIM 0xf0001861 +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +/* + * Common settings for all Local Bus SDRAM commands. + * At run time, either BSMA1516 (for CPU 1.1) + * or BSMA1617 (for CPU 1.0) (old) + * is OR'ed in too. + */ +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ + | CFG_LBC_LSDMR_PRETOACT7 \ + | CFG_LBC_LSDMR_ACTTORW7 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC4 \ + | CFG_LBC_LSDMR_CL3 \ + | CFG_LBC_LSDMR_RFEN \ + ) + +/* + * The bcsr registers are connected to CS3 on MDS. + * The new memory map places bcsr at 0xf8000000. + * + * For BR3, need: + * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 + * port-size = 8-bits = BR[19:20] = 01 + * no parity checking = BR[21:22] = 00 + * GPMC for MSEL = BR[24:26] = 000 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 + * + * For OR3, need: + * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 + * disable buffer ctrl OR[19] = 0 + * CSNT OR[20] = 1 + * ACS OR[21:22] = 11 + * XACS OR[23] = 1 + * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe + * SETA OR[28] = 0 + * TRLX OR[29] = 1 + * EHTR OR[30] = 1 + * EAD extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 + */ +#define CFG_BCSR (0xf8000000) + +/*Chip slelect 4 - PIB*/ +#define CFG_BR4_PRELIM 0xf8008801 +#define CFG_OR4_PRELIM 0xffffe9f7 + +/*Chip select 5 - PIB*/ +#define CFG_BR5_PRELIM 0xf8010801 +#define CFG_OR5_PRELIM 0xffff69f7 + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser*/ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8568@0" +#define OF_SOC "soc8568@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600" + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 + +/* + * General PCI + * Memory Addresses are mapped 1-1. I/O is mapped from 0 + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ + +#define CFG_PEX_MEM_BASE 0xa0000000 +#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE +#define CFG_PEX_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PEX_IO_BASE 0x00000000 +#define CFG_PEX_IO_PHYS 0xe2800000 +#define CFG_PEX_IO_SIZE 0x00800000 /* 8M */ + +#define CFG_SRIO_MEM_BASE 0xc0000000 + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" +#undef CONFIG_MPC85XX_TSEC3 +#undef CONFIG_MPC85XX_TSEC4 +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 3 + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: eTSEC[0-3] */ +#define CONFIG_ETHPRIME "eTSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#endif +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#endif + +#define CONFIG_IPADDR 192.168.1.253 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE your.uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs\0" \ + "ramargs=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs\0" \ + + +#define CONFIG_NFSBOOTCOMMAND \ + "run nfsargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + + +#define CONFIG_RAMBOOTCOMMAND \ + "run ramargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ -- cgit v1.2.1 From ffa621a0d12a1ccd81c936c567f8917a213787a8 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Sat, 24 Feb 2007 01:08:13 -0600 Subject: Cleaned up some 85xx PCI bugs * Cleaned up the CDS PCI Config Tables and added NULL entries to the end * Fixed PCIe LAWBAR assignemt to use the cpu-relative address * Fixed 85xx PCI code to assign powar region sizes based on the config values (rather than hard-coding them) * Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address Signed-off-by: Andy Fleming --- include/configs/MPC8548CDS.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 14936c28ae..680009d600 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -352,16 +352,16 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI2_MEM_BASE 0x90000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CFG_PCI2_IO_BASE 0xe2800000 +#define CFG_PCI2_IO_BASE 0x00000000 #define CFG_PCI2_IO_PHYS 0xe2800000 #define CFG_PCI2_IO_SIZE 0x00800000 /* 8M */ #define CFG_PEX_MEM_BASE 0xa0000000 #define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE #define CFG_PEX_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PEX_IO_BASE 0xe3000000 -#define CFG_PEX_IO_PHYS CFG_PEX_IO_BASE -#define CFG_PEX_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PEX_IO_BASE 0x00000000 +#define CFG_PEX_IO_PHYS 0xe3000000 +#define CFG_PEX_IO_SIZE 0x01000000 /* 16M */ /* * RapidIO MMU -- cgit v1.2.1 From 35171dc04e028ecacc23ad916a66295472555dbf Mon Sep 17 00:00:00 2001 From: Dan Malek Date: Fri, 5 Jan 2007 09:15:34 +0100 Subject: Add support for STX GP3SSA (stxssa) Board Signed-off-by Dan Malek, --- include/configs/stxssa.h | 418 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 418 insertions(+) create mode 100644 include/configs/stxssa.h (limited to 'include') diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h new file mode 100644 index 0000000000..f4ecb8fcd2 --- /dev/null +++ b/include/configs/stxssa.h @@ -0,0 +1,418 @@ +/* + * (C) Copyright 2005 Embedded Alley Solutions, Inc. + * Dan Malek + * Copied from STx GP3. + * Updates for Silicon Tx GP3 SSA board. + * + * (C) Copyright 2002,2003 Motorola,Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* mpc8560ads board configuration file */ +/* please refer to doc/README.mpc85xx for more info */ +/* make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ +#define CONFIG_CPM2 1 /* has CPM2 */ +#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/ + +#undef CONFIG_PCI /* pci ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support*/ +#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + + +/* sysclk for MPC85xx + */ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ + +/* Blinkin' LEDs for Robert :-) +*/ +#define CONFIG_SHOW_ACTIVITY 1 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + + +/* Localbus connector. There are many options that can be + * connected here, including sdram or lots of flash. + * This address, however, is used to configure a 256M local bus + * window that includes the Config latch below. + */ +#define CFG_LBC_OPTION_BASE 0xf0000000 /* Localbus Extension */ +#define CFG_LBC_OPTION_SIZE 256 /* 256MB */ + +/* There are various flash options used, we configure for the largest, + * which is 64Mbytes. The CFI works fine and will discover the proper + * sizes. + */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH 64M */ +#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */ +#define CFG_OR0_PRELIM 0xfc000ff7 /* 64 MB Flash */ + +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_FLASH_PROTECTION + +/* The configuration latch is Chip Select 1. + * It's an 8-bit latch in the lower 8 bits of the word. + */ +#define CFG_LBC_CFGLATCH_BASE 0xfb000000 /* Base of config latch */ +#define CFG_BR1_PRELIM 0xfb001801 /* 32-bit port */ +#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#ifdef CFG_RAMBOOT +#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ +#else +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#endif +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + + +/* + * DDR Setup + */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */ + +#undef CONFIG_CLOCKS_IN_MHZ + +/* local bus definitions */ +#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ +#define CFG_OR2_PRELIM 0xfc006901 +#define CFG_LBC_LCRR 0x00030004 /* local bus freq */ +#define CFG_LBC_LBCR 0x00000000 +#define CFG_LBC_LSRT 0x20000000 +#define CFG_LBC_MRTPR 0x20000000 +#define CFG_LBC_LSDMR_1 0x2861b723 +#define CFG_LBC_LSDMR_2 0x0861b723 +#define CFG_LBC_LSDMR_3 0x0861b723 +#define CFG_LBC_LSDMR_4 0x1861b723 +#define CFG_LBC_LSDMR_5 0x4061b723 + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 2 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CONFIG_BAUDRATE 38400 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#if 0 +#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */ +#else +/* I did the 'if 0' so we could keep the syntax above if ever needed. */ +#undef CFG_I2C_NOPROBES +#endif +#define CFG_I2C_OFFSET 0x3000 + +/* I2C EEPROM. AT24C32, we keep our environment in here. +*/ +#define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 + +/* + * Standard 8555 PCI mapping. + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ + +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe3000000 +#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ + +#if defined(CONFIG_PCI) /* PCI Ethernet card */ + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ + +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#undef CONFIG_MPS85XX_FEC + +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 4 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define CONFIG_ETHPRIME "TSEC0" + +#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ + +#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ + +#if (CONFIG_ETHER_INDEX == 2) + /* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - Select bus for bd/buffers + * - Full duplex + */ + #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) + #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) + #define CFG_CPMFCR_RAMTYPE 0 +#if 0 + #define CFG_FCC_PSMR (FCC_PSMR_FDE) +#else + #define CFG_FCC_PSMR 0 +#endif + #define FETH2_RST 0x01 +#elif (CONFIG_ETHER_INDEX == 3) + /* need more definitions here for FE3 */ + #define FETH3_RST 0x80 +#endif /* CONFIG_ETHER_INDEX */ + +/* MDIO is done through the TSEC0 control. +*/ +#define CONFIG_MII /* MII PHY management */ +#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */ + +#endif + +/* Environment */ +/* Config in EEPROM +*/ +#if 1 +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 2048 +#else +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x10000 + +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00030000) +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 0x4000 +#endif + +#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400" +#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000" +#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ + CFG_CMD_PING | CFG_CMD_I2C) & \ + ~(CFG_CMD_ENV | \ + CFG_CMD_LOADS )) + #elif defined(CONFIG_TSEC_ENET) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \ + CFG_CMD_MII | CFG_CMD_I2C ) & \ + ~(CFG_CMD_ENV)) + #elif defined(CONFIG_ETHER_ON_FCC) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ + CFG_CMD_PING | CFG_CMD_I2C) & \ + ~(CFG_CMD_ENV)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ + CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C) + #elif defined(CONFIG_TSEC_ENET) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \ + CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C) + #elif defined(CONFIG_ETHER_ON_FCC) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ + CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C) + #endif +#endif +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "SSA=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x1000000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/*Note: change below for your network setting!!! */ +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c +#endif + +#define CONFIG_SERVERIP 192.168.85.1 +#define CONFIG_IPADDR 192.168.85.60 +#define CONFIG_GATEWAYIP 192.168.85.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_HOSTNAME STX_SSA +#define CONFIG_ROOTPATH /gppproot +#define CONFIG_BOOTFILE uImage +#define CONFIG_LOADADDR 0x1000000 + +#endif /* __CONFIG_H */ -- cgit v1.2.1 From c64a89d6ce8584b9fc64f4e85da9ecac3cfc2c2a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 3 May 2007 16:34:41 +0200 Subject: Update board configuration for STX GP3SSA board: Enable hush shell, environment in flash rather in EEPROM, more user-friendly default environment, etc. The simple EEPROM environment can be selected easily in the board config file. Signed-off-by: Wolfgang Denk --- include/configs/stxssa.h | 87 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 67 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index f4ecb8fcd2..8624f4b74b 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -87,9 +87,9 @@ * which is 64Mbytes. The CFI works fine and will discover the proper * sizes. */ -#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH 64M */ -#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */ -#define CFG_OR0_PRELIM 0xfc000ff7 /* 64 MB Flash */ +#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH 64M */ +#define CFG_BR0_PRELIM 0xFC001801 /* port size 32bit */ +#define CFG_OR0_PRELIM 0xFC000FF7 /* 64 MB Flash */ #define CFG_FLASH_CFI 1 #define CFG_FLASH_CFI_DRIVER 1 @@ -163,7 +163,7 @@ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 2 @@ -173,16 +173,14 @@ #define CFG_NS16550_REG_SIZE 1 #define CFG_NS16550_CLK get_bus_freq(0) -#define CONFIG_BAUDRATE 38400 - #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif @@ -300,29 +298,26 @@ #endif -/* Environment */ -/* Config in EEPROM -*/ -#if 1 +/* Environment - default config is in flash, see below */ +#if 0 /* in EEPROM */ #define CFG_ENV_IS_IN_EEPROM 1 #define CFG_ENV_OFFSET 0 #define CFG_ENV_SIZE 2048 -#else +#else /* in flash */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x40000 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00030000) -#define CFG_ENV_OFFSET 0 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x4000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) #endif -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400" -#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000" -#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ - #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_TIMESTAMP /* Print image info with ts */ + #if defined(CFG_RAMBOOT) #if defined(CONFIG_PCI) #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ @@ -406,6 +401,18 @@ #define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c #endif +/* + * Environment in EEPROM is compatible with different flash sector sizes, + * but only little space is available, so we use a very simple setup. + * With environment in flash, we use a more powerful default configuration. + */ +#ifdef CFG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */ + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ +#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000" +#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate" #define CONFIG_SERVERIP 192.168.85.1 #define CONFIG_IPADDR 192.168.85.60 #define CONFIG_GATEWAYIP 192.168.85.1 @@ -415,4 +422,44 @@ #define CONFIG_BOOTFILE uImage #define CONFIG_LOADADDR 0x1000000 +#else /* ENV IS IN FLASH -- use a full-blown envionment */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=gp3ssa\0" \ + "bootfile=/tftpboot/gp3ssa/uImage\0" \ + "loadaddr=400000\0" \ + "netdev=eth0\0" \ + "consdev=ttyS1\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $bootargs " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ + ":$hostname:$netdev:off panic=1\0" \ + "addcons=setenv bootargs $bootargs " \ + "console=$consdev,$baudrate\0" \ + "flash_nfs=run nfsargs addip addcons;" \ + "bootm $kernel_addr\0" \ + "flash_self=run ramargs addip addcons;" \ + "bootm $kernel_addr $ramdisk_addr\0" \ + "net_nfs=tftp $loadaddr $bootfile;" \ + "run nfsargs addip addcons;bootm\0" \ + "rootpath=/opt/eldk/ppc_85xx\0" \ + "kernel_addr=FC000000\0" \ + "ramdisk_addr=FC200000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#endif /* CFG_ENV_IS_IN_EEPROM */ + #endif /* __CONFIG_H */ -- cgit v1.2.1 From e3b8c78bc2489c27ae020986ef0eaca684866cef Mon Sep 17 00:00:00 2001 From: Jeffrey Mann Date: Sat, 5 May 2007 08:32:14 +0200 Subject: ppc4xx: Detect if the sysclk on Sequoia is 33 or 33.333 MHz The AMCC Secquoia board has been changed in a new revision from using a 33.000 MHz clock to a 33.333 MHz system clock. A bit in the CPLD indicates the difference. This patch reads that bit and uses the correct clock speed for the board. This code is backward compatable will all prior boards. All prior boards will be read as 33.000. Signed-off-by: Jeffrey Mann Signed-off-by: Stefan Roese --- include/configs/sequoia.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 1f19621f44..b7f79c26eb 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -38,7 +38,9 @@ #define CONFIG_440GRX 1 /* Specific PPC440GRx */ #endif #define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_SYS_CLK_FREQ 33000000 /* external freq to pll */ +/* Detect Sequoia PLL input clock automatically via CPLD bit */ +#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \ + 3333333 : 33000000) #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ -- cgit v1.2.1 From 2f15278c2eb911c668b4fe562130b78cf554d139 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 5 May 2007 18:23:11 +0200 Subject: Coding stylke cleanup; update CHANGELOG. Signed-off-by: Wolfgang Denk --- include/configs/MPC8568MDS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 66293c5221..3f65644fdd 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -149,7 +149,7 @@ extern unsigned long get_clock_freq(void); #define CFG_BR1_PRELIM 0xf8000801 #define CFG_OR1_PRELIM 0xffffe9f7 -//#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} +/*#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} */ #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ #define CFG_MAX_FLASH_SECT 512 /* sectors per device */ #undef CFG_FLASH_CHECKSUM -- cgit v1.2.1 From a9d87e2707dcb249f6bb7f7ff7e00acd8cda9fd2 Mon Sep 17 00:00:00 2001 From: Grzegorz Wianecki Date: Sun, 29 Apr 2007 14:01:54 +0200 Subject: [PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot message MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up message. Use PVR to distinguish between the two variants, and print proper CPU information. Signed-off-by: Grzegorz Wianecki Signed-off-by: Bartlomiej Sieka Signed-off-by: Grant Likely --- include/asm-ppc/processor.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index e9361c5174..5efc3ee2ca 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -706,8 +706,6 @@ #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ -/* System-On-Chip Version Numbers (version field only) */ -#define SVR_MPC5200 0x8011 /* Processor Version Register */ @@ -818,6 +816,12 @@ #define PVR_8260_HIP7R1 0x80822013 #define PVR_8260_HIP7RA 0x80822014 +/* + * MPC 52xx + */ +#define PVR_5200 0x80822011 +#define PVR_5200B 0x80822014 + /* * System Version Register -- cgit v1.2.1