nvc0: switch to "standard" RING macros

7 files changed, 212 insertions, 214 deletions

diff --git a/src/nouveau_xv.c b/src/nouveau_xv.c
index e9ccd56..30753fa 100644
--- a/src/nouveau_xv.c
+++ b/src/nouveau_xv.c
@@ -1112,7 +1112,7 @@ NVPutImage(ScrnInfoPtr pScrn, short src_x, short src_y, short drw_x,
 		nouveau_bo_unmap(destination_buffer);
 
 		if (pNv->Architecture >= NV_ARCH_C0) {
-			nvc0_xv_m2mf(chan, pPriv->video_mem, uv_offset, dstPitch,
+			nvc0_xv_m2mf(m2mf, pPriv->video_mem, uv_offset, dstPitch,
 				     nlines, destination_buffer, line_len);
 			goto put_image;
 		}
diff --git a/src/nv_proto.h b/src/nv_proto.h
index c596b1d..2e4fce0 100644
--- a/src/nv_proto.h
+++ b/src/nv_proto.h
@@ -190,7 +190,7 @@ int nvc0_xv_image_put(ScrnInfoPtr, struct nouveau_bo *, int, int, int, int,
 		      BoxPtr, int, int, int, int, uint16_t, uint16_t,
 		      uint16_t, uint16_t, uint16_t, uint16_t,
 		      RegionPtr, PixmapPtr, NVPortPrivPtr);
-void nvc0_xv_m2mf(struct nouveau_channel *, struct nouveau_bo *, int, int, int,
+void nvc0_xv_m2mf(struct nouveau_grobj *, struct nouveau_bo *, int, int, int,
 		  struct nouveau_bo *, int);
 void nvc0_xv_csc_update(NVPtr, float, float *, float *, float *);
 
diff --git a/src/nv_type.h b/src/nv_type.h
index a06859d..4204556 100644
--- a/src/nv_type.h
+++ b/src/nv_type.h
@@ -26,10 +26,6 @@
 #define NV_ARCH_50  0x50
 #define NV_ARCH_C0  0xc0
 
-#define NvSubM2MF 3
-#define NvSub2D   4
-#define NvSub3D   5
-
 /* NV50 */
 typedef struct _NVRec *NVPtr;
 typedef struct _NVRec {
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 96f9a10..521c032 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -38,13 +38,6 @@ NVAccelInitM2MF_NVC0(ScrnInfoPtr pScrn)
 	if (ret)
 		return FALSE;
 
-	BEGIN_RING(chan, NvSubM2MF, 0x0000, 1);
-	OUT_RING  (chan, 0x9039);
-
-	/* XXX: Stupid interface, I want the notifier address ! */
-
-	FIRE_RING (chan);
-
 	return TRUE;
 }
 
@@ -61,31 +54,28 @@ NVAccelInit2D_NVC0(ScrnInfoPtr pScrn)
 	if (ret)
 		return FALSE;
 
-	BEGIN_RING(chan, NvSub2D, 0x0000, 1);
-	OUT_RING  (chan, 0x902d);
-
-	BEGIN_RING(chan, NvSub2D, NV50_2D_CLIP_ENABLE, 1);
+	BEGIN_RING(chan, pNv->Nv2D, NV50_2D_CLIP_ENABLE, 1);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSub2D, NV50_2D_COLOR_KEY_ENABLE, 1);
+	BEGIN_RING(chan, pNv->Nv2D, NV50_2D_COLOR_KEY_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub2D, 0x0884, 1);
+	BEGIN_RING(chan, pNv->Nv2D, 0x0884, 1);
 	OUT_RING  (chan, 0x3f);
-	BEGIN_RING(chan, NvSub2D, 0x0888, 1);
+	BEGIN_RING(chan, pNv->Nv2D, 0x0888, 1);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSub2D, NV50_2D_ROP, 1);
+	BEGIN_RING(chan, pNv->Nv2D, NV50_2D_ROP, 1);
 	OUT_RING  (chan, 0x55);
-	BEGIN_RING(chan, NvSub2D, NV50_2D_OPERATION, 1);
+	BEGIN_RING(chan, pNv->Nv2D, NV50_2D_OPERATION, 1);
 	OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 
-	BEGIN_RING(chan, NvSub2D, NV50_2D_BLIT_DU_DX_FRACT, 4);
+	BEGIN_RING(chan, pNv->Nv2D, NV50_2D_BLIT_DU_DX_FRACT, 4);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 1);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSub2D, NV50_2D_DRAW_SHAPE, 2);
+	BEGIN_RING(chan, pNv->Nv2D, NV50_2D_DRAW_SHAPE, 2);
 	OUT_RING  (chan, 4);
 	OUT_RING  (chan, NV50_SURFACE_FORMAT_R5G6B5_UNORM);
-	BEGIN_RING(chan, NvSub2D, NV50_2D_PATTERN_FORMAT, 2);
+	BEGIN_RING(chan, pNv->Nv2D, NV50_2D_PATTERN_FORMAT, 2);
 	OUT_RING  (chan, 2);
 	OUT_RING  (chan, 1);
 
@@ -100,7 +90,8 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
 {
 	NVPtr pNv = NVPTR(pScrn);
 	struct nouveau_channel *chan = pNv->chan;
-	struct nouveau_bo *bo = pNv->tesla_scratch;
+	struct nouveau_grobj *fermi, *m2mf;
+	struct nouveau_bo *bo;
 	uint32_t tclClass;
 	int ret, i;
 
@@ -126,109 +117,108 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
 		}
 	}
 	bo = pNv->tesla_scratch;
+	m2mf = pNv->NvMemFormat;
+	fermi = pNv->Nv3D;
 
 	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "init NVC0_3D (%x)\n", tclClass);
 
 	if (MARK_RING(chan, 512, 32))
 		return FALSE;
 
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_NOTIFY_ADDRESS_HIGH, 3);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_NOTIFY_ADDRESS_HIGH, 3);
 	OUT_RELOCh(chan, bo, NTFY_OFFSET, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 	OUT_RELOCl(chan, bo, NTFY_OFFSET, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 	OUT_RING  (chan, 0);
 
-	BEGIN_RING(chan, NvSub3D, 0x0000, 1);
-	OUT_RING  (chan, tclClass);
-
-	BEGIN_RING(chan, NvSub3D, NVC0_GRAPH_NOTIFY_ADDRESS_HIGH, 3);
+	BEGIN_RING(chan, fermi, NVC0_GRAPH_NOTIFY_ADDRESS_HIGH, 3);
 	OUT_RELOCh(chan, bo, NTFY_OFFSET, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 	OUT_RELOCl(chan, bo, NTFY_OFFSET, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 	OUT_RING  (chan, 0);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_MULTISAMPLE_COLOR_ENABLE, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_MULTISAMPLE_COLOR_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_MULTISAMPLE_ZETA_ENABLE, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_MULTISAMPLE_ZETA_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_MULTISAMPLE_MODE, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_MULTISAMPLE_MODE, 1);
 	OUT_RING  (chan, NVC0_3D_MULTISAMPLE_MODE_1X);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_COND_MODE, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_COND_MODE, 1);
 	OUT_RING  (chan, NVC0_3D_COND_MODE_ALWAYS);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_RT_CONTROL, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_RT_CONTROL, 1);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_ZETA_ENABLE, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_ZETA_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_VIEWPORT_CLIP_RECTS_EN, 2);
+	BEGIN_RING(chan, fermi, NVC0_3D_VIEWPORT_CLIP_RECTS_EN, 2);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_CLIPID_ENABLE, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_CLIPID_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_VERTEX_TWO_SIDE_ENABLE, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_VERTEX_TWO_SIDE_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, 0x0fac, 1);
+	BEGIN_RING(chan, fermi, 0x0fac, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_COLOR_MASK(0), 8);
+	BEGIN_RING(chan, fermi, NVC0_3D_COLOR_MASK(0), 8);
 	OUT_RING  (chan, 0x1111);
 	for (i = 1; i < 8; ++i)
 		OUT_RING(chan, 0);
 
 	FIRE_RING (chan);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_SCREEN_SCISSOR_HORIZ, 2);
+	BEGIN_RING(chan, fermi, NVC0_3D_SCREEN_SCISSOR_HORIZ, 2);
 	OUT_RING  (chan, (8192 << 16) | 0);
 	OUT_RING  (chan, (8192 << 16) | 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_Y_ORIGIN_BOTTOM, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_Y_ORIGIN_BOTTOM, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_WINDOW_OFFSET_X, 2);
+	BEGIN_RING(chan, fermi, NVC0_3D_WINDOW_OFFSET_X, 2);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, 0x1590, 1);
+	BEGIN_RING(chan, fermi, 0x1590, 1);
 	OUT_RING  (chan, 0);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_LINKED_TSC, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_LINKED_TSC, 1);
 	OUT_RING  (chan, 1);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_VIEWPORT_TRANSFORM_EN, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_VIEWPORT_TRANSFORM_EN, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_VIEW_VOLUME_CLIP_CTRL, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_VIEW_VOLUME_CLIP_CTRL, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_DEPTH_RANGE_NEAR(0), 2);
+	BEGIN_RING(chan, fermi, NVC0_3D_DEPTH_RANGE_NEAR(0), 2);
 	OUT_RINGf (chan, 0.0f);
 	OUT_RINGf (chan, 1.0f);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_TEX_LIMITS(4), 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_TEX_LIMITS(4), 1);
 	OUT_RING  (chan, 0x54);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_BLEND_ENABLE(0), 8);
+	BEGIN_RING(chan, fermi, NVC0_3D_BLEND_ENABLE(0), 8);
 	OUT_RING  (chan, 1);
 	for (i = 1; i < 8; ++i)
 		OUT_RING(chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_BLEND_INDEPENDENT, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_BLEND_INDEPENDENT, 1);
 	OUT_RING  (chan, 0);
 
-	BEGIN_RING(chan, NvSub3D, 0x17bc, 3);
+	BEGIN_RING(chan, fermi, 0x17bc, 3);
 	OUT_RELOCh(chan, bo, MISC_OFFSET, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 	OUT_RELOCl(chan, bo, MISC_OFFSET, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 	OUT_RING  (chan, 1);
 
 	FIRE_RING (chan);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_CODE_ADDRESS_HIGH, 2);
+	BEGIN_RING(chan, fermi, NVC0_3D_CODE_ADDRESS_HIGH, 2);
 	OUT_RELOCh(chan, bo, CODE_OFFSET, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 	OUT_RELOCl(chan, bo, CODE_OFFSET, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
 	if (OUT_RELOCh(chan, bo, PVP_PASS, NOUVEAU_BO(VRAM, VRAM, WR)) ||
 	    OUT_RELOCl(chan, bo, PVP_PASS, NOUVEAU_BO(VRAM, VRAM, WR))) {
 		MARK_UNDO(chan);
 		return FALSE;
 	}
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_LINE_LENGTH_IN, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_LINE_LENGTH_IN, 2);
 	OUT_RING  (chan, 7 * 8 + 20 * 4);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_EXEC, 1);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_EXEC, 1);
 	OUT_RING  (chan, 0x100111);
-	BEGIN_RING_NI(chan, NvSubM2MF, NVC0_M2MF_DATA, 7 * 2 + 20);
+	BEGIN_RING_NI(chan, m2mf, NVC0_M2MF_DATA, 7 * 2 + 20);
 	OUT_RING  (chan, 0x00020461);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
@@ -264,30 +254,30 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
 	OUT_RING  (chan, 0x00001de7);
 	OUT_RING  (chan, 0x80000000); /* exit */
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_SP_SELECT(1), 2);
+	BEGIN_RING(chan, fermi, NVC0_3D_SP_SELECT(1), 2);
 	OUT_RING  (chan, 0x11);
 	OUT_RING  (chan, PVP_PASS);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_SP_GPR_ALLOC(1), 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_SP_GPR_ALLOC(1), 1);
 	OUT_RING  (chan, 8);
-	BEGIN_RING(chan, NvSub3D, 0x163c, 1);
+	BEGIN_RING(chan, fermi, 0x163c, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, 0x2600, 1);
+	BEGIN_RING(chan, fermi, 0x2600, 1);
 	OUT_RING  (chan, 1);
 
 	FIRE_RING (chan); usleep(500);
 
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
 	if (OUT_RELOCh(chan, bo, PFP_S, NOUVEAU_BO(VRAM, VRAM, WR)) ||
 	    OUT_RELOCl(chan, bo, PFP_S, NOUVEAU_BO(VRAM, VRAM, WR))) {
 		MARK_UNDO(chan);
 		return FALSE;
 	}
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_LINE_LENGTH_IN, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_LINE_LENGTH_IN, 2);
 	OUT_RING  (chan, 6 * 8 + 20 * 4);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_EXEC, 1);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_EXEC, 1);
 	OUT_RING  (chan, 0x100111);
-	BEGIN_RING_NI(chan, NvSubM2MF, NVC0_M2MF_DATA, 6 * 2 + 20);
+	BEGIN_RING_NI(chan, m2mf, NVC0_M2MF_DATA, 6 * 2 + 20);
 	OUT_RING  (chan, 0x00021462);
 	OUT_RING  (chan, 0x00000000);
 	OUT_RING  (chan, 0x00000000);
@@ -321,18 +311,18 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
 	OUT_RING  (chan, 0x00001de7);
 	OUT_RING  (chan, 0x80000000); /* exit */
 
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
 	if (OUT_RELOCh(chan, bo, PFP_C, NOUVEAU_BO(VRAM, VRAM, WR)) ||
 	    OUT_RELOCl(chan, bo, PFP_C, NOUVEAU_BO(VRAM, VRAM, WR))) {
 		MARK_UNDO(chan);
 		return FALSE;
 	}
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_LINE_LENGTH_IN, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_LINE_LENGTH_IN, 2);
 	OUT_RING  (chan, 13 * 8 + 20 * 4);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_EXEC, 1);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_EXEC, 1);
 	OUT_RING  (chan, 0x100111);
-	BEGIN_RING_NI(chan, NvSubM2MF, NVC0_M2MF_DATA, 13 * 2 + 20);
+	BEGIN_RING_NI(chan, m2mf, NVC0_M2MF_DATA, 13 * 2 + 20);
 	OUT_RING  (chan, 0x00021462);
 	OUT_RING  (chan, 0x00000000);
 	OUT_RING  (chan, 0x00000000);
@@ -380,18 +370,18 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
 	OUT_RING  (chan, 0x00001de7);
 	OUT_RING  (chan, 0x80000000); /* exit */
 
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
 	if (OUT_RELOCh(chan, bo, PFP_CCA, NOUVEAU_BO(VRAM, VRAM, WR)) ||
 	    OUT_RELOCl(chan, bo, PFP_CCA, NOUVEAU_BO(VRAM, VRAM, WR))) {
 		MARK_UNDO(chan);
 		return FALSE;
 	}
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_LINE_LENGTH_IN, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_LINE_LENGTH_IN, 2);
 	OUT_RING  (chan, 13 * 8 + 20 * 4);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_EXEC, 1);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_EXEC, 1);
 	OUT_RING  (chan, 0x100111);
-	BEGIN_RING_NI(chan, NvSubM2MF, NVC0_M2MF_DATA, 13 * 2 + 20);
+	BEGIN_RING_NI(chan, m2mf, NVC0_M2MF_DATA, 13 * 2 + 20);
 	OUT_RING  (chan, 0x00021462); /* 0x0000c000 = USES_KIL, MULTI_COLORS */
 	OUT_RING  (chan, 0x00000000);
 	OUT_RING  (chan, 0x00000000);
@@ -439,18 +429,18 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
 	OUT_RING  (chan, 0x00001de7);
 	OUT_RING  (chan, 0x80000000); /* exit */
 
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
 	if (OUT_RELOCh(chan, bo, PFP_CCASA, NOUVEAU_BO(VRAM, VRAM, WR)) ||
 	    OUT_RELOCl(chan, bo, PFP_CCASA, NOUVEAU_BO(VRAM, VRAM, WR))) {
 		MARK_UNDO(chan);
 		return FALSE;
 	}
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_LINE_LENGTH_IN, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_LINE_LENGTH_IN, 2);
 	OUT_RING  (chan, 13 * 8 + 20 * 4);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_EXEC, 1);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_EXEC, 1);
 	OUT_RING  (chan, 0x100111);
-	BEGIN_RING_NI(chan, NvSubM2MF, NVC0_M2MF_DATA, 13 * 2 + 20);
+	BEGIN_RING_NI(chan, m2mf, NVC0_M2MF_DATA, 13 * 2 + 20);
 	OUT_RING  (chan, 0x00021462);
 	OUT_RING  (chan, 0x00000000);
 	OUT_RING  (chan, 0x00000000);
@@ -498,18 +488,18 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
 	OUT_RING  (chan, 0x00001de7);
 	OUT_RING  (chan, 0x80000000); /* exit */
 
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
 	if (OUT_RELOCh(chan, bo, PFP_S_A8, NOUVEAU_BO(VRAM, VRAM, WR)) ||
 	    OUT_RELOCl(chan, bo, PFP_S_A8, NOUVEAU_BO(VRAM, VRAM, WR))) {
 		MARK_UNDO(chan);
 		return FALSE;
 	}
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_LINE_LENGTH_IN, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_LINE_LENGTH_IN, 2);
 	OUT_RING  (chan, 9 * 8 + 20 * 4);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_EXEC, 1);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_EXEC, 1);
 	OUT_RING  (chan, 0x100111);
-	BEGIN_RING_NI(chan, NvSubM2MF, NVC0_M2MF_DATA, 9 * 2 + 20);
+	BEGIN_RING_NI(chan, m2mf, NVC0_M2MF_DATA, 9 * 2 + 20);
 	OUT_RING  (chan, 0x00021462);
 	OUT_RING  (chan, 0x00000000);
 	OUT_RING  (chan, 0x00000000);
@@ -549,18 +539,18 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
 	OUT_RING  (chan, 0x00001de7);
 	OUT_RING  (chan, 0x80000000); /* exit */
 
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
 	if (OUT_RELOCh(chan, bo, PFP_C_A8, NOUVEAU_BO(VRAM, VRAM, WR)) ||
 	    OUT_RELOCl(chan, bo, PFP_C_A8, NOUVEAU_BO(VRAM, VRAM, WR))) {
 		MARK_UNDO(chan);
 		return FALSE;
 	}
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_LINE_LENGTH_IN, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_LINE_LENGTH_IN, 2);
 	OUT_RING  (chan, 13 * 8 + 20 * 4);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_EXEC, 1);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_EXEC, 1);
 	OUT_RING  (chan, 0x100111);
-	BEGIN_RING_NI(chan, NvSubM2MF, NVC0_M2MF_DATA, 13 * 2 + 20);
+	BEGIN_RING_NI(chan, m2mf, NVC0_M2MF_DATA, 13 * 2 + 20);
 	OUT_RING  (chan, 0x00021462);
 	OUT_RING  (chan, 0x00000000);
 	OUT_RING  (chan, 0x00000000);
@@ -610,18 +600,18 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
 
 	FIRE_RING (chan);
 
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
 	if (OUT_RELOCh(chan, bo, PFP_NV12, NOUVEAU_BO(VRAM, VRAM, WR)) ||
 	    OUT_RELOCl(chan, bo, PFP_NV12, NOUVEAU_BO(VRAM, VRAM, WR))) {
 		MARK_UNDO(chan);
 		return FALSE;
 	}
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_LINE_LENGTH_IN, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_LINE_LENGTH_IN, 2);
 	OUT_RING  (chan, 19 * 8 + 20 * 4);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_EXEC, 1);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_EXEC, 1);
 	OUT_RING  (chan, 0x100111);
-	BEGIN_RING_NI(chan, NvSubM2MF, NVC0_M2MF_DATA, 19 * 2 + 20);
+	BEGIN_RING_NI(chan, m2mf, NVC0_M2MF_DATA, 19 * 2 + 20);
 	OUT_RING  (chan, 0x00021462);
 	OUT_RING  (chan, 0x00000000);
 	OUT_RING  (chan, 0x00000000);
@@ -681,66 +671,66 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
 	OUT_RING  (chan, 0x00001de7);
 	OUT_RING  (chan, 0x80000000);
 
-	BEGIN_RING(chan, NvSub3D, 0x021c, 1); /* CODE_FLUSH ? */
+	BEGIN_RING(chan, fermi, 0x021c, 1); /* CODE_FLUSH ? */
 	OUT_RING  (chan, 0x1111);
 
 	FIRE_RING (chan);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_SP_SELECT(5), 2);
+	BEGIN_RING(chan, fermi, NVC0_3D_SP_SELECT(5), 2);
 	OUT_RING  (chan, 0x51);
 	OUT_RING  (chan, PFP_S);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_SP_GPR_ALLOC(5), 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_SP_GPR_ALLOC(5), 1);
 	OUT_RING  (chan, 8);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_CB_SIZE, 3);
+	BEGIN_RING(chan, fermi, NVC0_3D_CB_SIZE, 3);
 	OUT_RING  (chan, 256);
 	if (OUT_RELOCh(chan, bo, CB_OFFSET, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR) ||
 	    OUT_RELOCl(chan, bo, CB_OFFSET, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR)) {
 		MARK_UNDO(chan);
 		return FALSE;
 	}
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_CB_BIND(4), 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_CB_BIND(4), 1);
 	OUT_RING  (chan, 0x01);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_EARLY_FRAGMENT_TESTS, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_EARLY_FRAGMENT_TESTS, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, 0x0360, 2);
+	BEGIN_RING(chan, fermi, 0x0360, 2);
 	OUT_RING  (chan, 0x20164010);
 	OUT_RING  (chan, 0x20);
-	BEGIN_RING(chan, NvSub3D, 0x196c, 1);
+	BEGIN_RING(chan, fermi, 0x196c, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, 0x1664, 1);
+	BEGIN_RING(chan, fermi, 0x1664, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_FRAG_COLOR_CLAMP_EN, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_FRAG_COLOR_CLAMP_EN, 1);
 	OUT_RING  (chan, 0x11111111);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_DEPTH_TEST_ENABLE, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_DEPTH_TEST_ENABLE, 1);
 	OUT_RING  (chan, 0);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_RASTERIZE_ENABLE, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_RASTERIZE_ENABLE, 1);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_SP_SELECT(4), 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_SP_SELECT(4), 1);
 	OUT_RING  (chan, 0x40);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_GP_BUILTIN_RESULT_EN, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_GP_BUILTIN_RESULT_EN, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_SP_SELECT(3), 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_SP_SELECT(3), 1);
 	OUT_RING  (chan, 0x30);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_SP_SELECT(2), 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_SP_SELECT(2), 1);
 	OUT_RING  (chan, 0x20);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_SP_SELECT(0), 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_SP_SELECT(0), 1);
 	OUT_RING  (chan, 0x00);
 
-	BEGIN_RING(chan, NvSub3D, 0x1604, 1);
+	BEGIN_RING(chan, fermi, 0x1604, 1);
 	OUT_RING  (chan, 4);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_POINT_SPRITE_ENABLE, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_POINT_SPRITE_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_SCISSOR_ENABLE(0), 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_SCISSOR_ENABLE(0), 1);
 	OUT_RING  (chan, 1);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_VIEWPORT_HORIZ(0), 2);
+	BEGIN_RING(chan, fermi, NVC0_3D_VIEWPORT_HORIZ(0), 2);
 	OUT_RING  (chan, (8192 << 16) | 0);
 	OUT_RING  (chan, (8192 << 16) | 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_SCISSOR_HORIZ(0), 2);
+	BEGIN_RING(chan, fermi, NVC0_3D_SCISSOR_HORIZ(0), 2);
 	OUT_RING  (chan, (8192 << 16) | 0);
 	OUT_RING  (chan, (8192 << 16) | 0);
 
diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
index d0c82fa..5cb3e87 100644
--- a/src/nvc0_accel.h
+++ b/src/nvc0_accel.h
@@ -1,8 +1,7 @@
 #ifndef __NVC0_ACCEL_H__
 #define __NVC0_ACCEL_H__
 
-#define BEGIN_RING(c, g, m, s) BEGIN_RING_NVC0(c, g, m, s)
-#define BEGIN_RING_NI(c, g, m, s) BEGIN_RING_NI_NVC0(c, g, m, s)
+#include "nvc0_pushbuf.h"
 
 /* scratch buffer offsets */
 #define CODE_OFFSET 0x00000 /* Code */
@@ -36,17 +35,18 @@ static __inline__ void
 VTX1s(NVPtr pNv, float sx, float sy, unsigned dx, unsigned dy)
 {
 	struct nouveau_channel *chan = pNv->chan;
+	struct nouveau_grobj *fermi = pNv->Nv3D;
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_VTX_ATTR_DEFINE, 3);
+	BEGIN_RING(chan, fermi, NVC0_3D_VTX_ATTR_DEFINE, 3);
 	OUT_RING  (chan, VTX_ATTR(1, 2, FLOAT, 4));
 	OUT_RINGf (chan, sx);
 	OUT_RINGf (chan, sy);
 #if 1
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_VTX_ATTR_DEFINE, 2);
+	BEGIN_RING(chan, fermi, NVC0_3D_VTX_ATTR_DEFINE, 2);
 	OUT_RING  (chan, VTX_ATTR(0, 2, USCALED, 2));
 	OUT_RING  (chan, (dy << 16) | dx);
 #else
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_VTX_ATTR_DEFINE, 3);
+	BEGIN_RING(chan, fermi, NVC0_3D_VTX_ATTR_DEFINE, 3);
 	OUT_RING  (chan, VTX_ATTR(0, 2, FLOAT, 4));
 	OUT_RINGf (chan, (float)dx);
 	OUT_RINGf (chan, (float)dy);
@@ -58,21 +58,22 @@ VTX2s(NVPtr pNv, float s1x, float s1y, float s2x, float s2y,
       unsigned dx, unsigned dy)
 {
 	struct nouveau_channel *chan = pNv->chan;
+	struct nouveau_grobj *fermi = pNv->Nv3D;
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_VTX_ATTR_DEFINE, 3);
+	BEGIN_RING(chan, fermi, NVC0_3D_VTX_ATTR_DEFINE, 3);
 	OUT_RING  (chan, VTX_ATTR(1, 2, FLOAT, 4));
 	OUT_RINGf (chan, s1x);
 	OUT_RINGf (chan, s1y);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_VTX_ATTR_DEFINE, 3);
+	BEGIN_RING(chan, fermi, NVC0_3D_VTX_ATTR_DEFINE, 3);
 	OUT_RING  (chan, VTX_ATTR(2, 2, FLOAT, 4));
 	OUT_RINGf (chan, s2x);
 	OUT_RINGf (chan, s2y);
 #if 1
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_VTX_ATTR_DEFINE, 2);
+	BEGIN_RING(chan, fermi, NVC0_3D_VTX_ATTR_DEFINE, 2);
 	OUT_RING  (chan, VTX_ATTR(0, 2, USCALED, 2));
 	OUT_RING  (chan, (dy << 16) | dx);
 #else
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_VTX_ATTR_DEFINE, 3);
+	BEGIN_RING(chan, fermi, NVC0_3D_VTX_ATTR_DEFINE, 3);
 	OUT_RING  (chan, VTX_ATTR(0, 2, FLOAT, 4));
 	OUT_RINGf (chan, (float)dx);
 	OUT_RINGf (chan, (float)dy);
diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c
index 338c765..45647ce 100644
--- a/src/nvc0_exa.c
+++ b/src/nvc0_exa.c
@@ -36,6 +36,7 @@ NVC0AccelDownloadM2MF(PixmapPtr pspix, int x, int y, int w, int h,
 	NVPtr pNv = NVPTR(pScrn);
 	struct nouveau_channel *chan = pNv->chan;
 	struct nouveau_bo *bo = nouveau_pixmap_bo(pspix);
+	struct nouveau_grobj *m2mf = pNv->NvMemFormat;
 	const int cpp = pspix->drawable.bitsPerPixel / 8;
 	const int line_len = w * cpp;
 	const int line_limit = (128 << 10) / line_len;
@@ -46,7 +47,7 @@ NVC0AccelDownloadM2MF(PixmapPtr pspix, int x, int y, int w, int h,
 		src_pitch = exaGetPixmapPitch(pspix);
 		src_offset = (y * src_pitch) + (x * cpp);
 	} else {
-		BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_TILING_MODE_IN, 5);
+		BEGIN_RING(chan, m2mf, NVC0_M2MF_TILING_MODE_IN, 5);
 		OUT_RING  (chan, bo->tile_mode);
 		OUT_RING  (chan, pspix->drawable.width * cpp);
 		OUT_RING  (chan, pspix->drawable.height);
@@ -65,11 +66,11 @@ NVC0AccelDownloadM2MF(PixmapPtr pspix, int x, int y, int w, int h,
 
 		MARK_RING(chan, 16, 4);
 
-		BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
+		BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
 		OUT_RELOCh(chan, pNv->GART, 0, NOUVEAU_BO(GART, GART, WR));
 		OUT_RELOCl(chan, pNv->GART, 0, NOUVEAU_BO(GART, GART, WR));
 
-		BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_IN_HIGH, 6);
+		BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_IN_HIGH, 6);
 		OUT_RELOCh(chan, bo, src_offset, NOUVEAU_BO(VRAM, GART, RD));
 		OUT_RELOCl(chan, bo, src_offset, NOUVEAU_BO(VRAM, GART, RD));
 		OUT_RING  (chan, src_pitch);
@@ -78,13 +79,13 @@ NVC0AccelDownloadM2MF(PixmapPtr pspix, int x, int y, int w, int h,
 		OUT_RING  (chan, line_count);
 
 		if (tiled) {
-			BEGIN_RING(chan, NvSubM2MF,
+			BEGIN_RING(chan, m2mf,
 				   NVC0_M2MF_TILING_POSITION_IN_X, 2);
 			OUT_RING  (chan, x * cpp);
 			OUT_RING  (chan, y);
 		}
 
-		BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_EXEC, 1);
+		BEGIN_RING(chan, m2mf, NVC0_M2MF_EXEC, 1);
 		OUT_RING  (chan, 0x100000 | (tiled << 8));
 
 		if (nouveau_bo_map(pNv->GART, NOUVEAU_BO_RD)) {
@@ -122,6 +123,7 @@ NVC0AccelUploadM2MF(PixmapPtr pdpix, int x, int y, int w, int h,
 	NVPtr pNv = NVPTR(pScrn);
 	struct nouveau_channel *chan = pNv->chan;
 	struct nouveau_bo *bo = nouveau_pixmap_bo(pdpix);
+	struct nouveau_grobj *m2mf = pNv->NvMemFormat;
 	int cpp = pdpix->drawable.bitsPerPixel / 8;
 	int line_len = w * cpp;
 	int line_limit = (128 << 10) / line_len;
@@ -132,7 +134,7 @@ NVC0AccelUploadM2MF(PixmapPtr pdpix, int x, int y, int w, int h,
 		dst_pitch = exaGetPixmapPitch(pdpix);
 		dst_offset = (y * dst_pitch) + (x * cpp);
 	} else {
-		BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_TILING_MODE_OUT, 5);
+		BEGIN_RING(chan, m2mf, NVC0_M2MF_TILING_MODE_OUT, 5);
 		OUT_RING  (chan, bo->tile_mode);
 		OUT_RING  (chan, pdpix->drawable.width * cpp);
 		OUT_RING  (chan, pdpix->drawable.height);
@@ -167,28 +169,28 @@ NVC0AccelUploadM2MF(PixmapPtr pdpix, int x, int y, int w, int h,
 		if (MARK_RING(chan, 16, 4))
 			return FALSE;
 
-		BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_IN_HIGH, 2);
+		BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_IN_HIGH, 2);
 		OUT_RELOCh(chan, pNv->GART, 0, NOUVEAU_BO(GART, GART, RD));
 		OUT_RELOCl(chan, pNv->GART, 0, NOUVEAU_BO(GART, GART, RD));
 
-		BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
+		BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
 		OUT_RELOCh(chan, bo, dst_offset, NOUVEAU_BO(VRAM, GART, WR));
 		OUT_RELOCl(chan, bo, dst_offset, NOUVEAU_BO(VRAM, GART, WR));
 
 		if (tiled) {
-			BEGIN_RING(chan, NvSubM2MF,
+			BEGIN_RING(chan, m2mf,
 				   NVC0_M2MF_TILING_POSITION_OUT_X, 2);
 			OUT_RING  (chan, x * cpp);
 			OUT_RING  (chan, y);
 		}
 
-		BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_PITCH_IN, 4);
+		BEGIN_RING(chan, m2mf, NVC0_M2MF_PITCH_IN, 4);
 		OUT_RING  (chan, line_len);
 		OUT_RING  (chan, dst_pitch);
 		OUT_RING  (chan, line_len);
 		OUT_RING  (chan, line_count);
 
-		BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_EXEC, 1);
+		BEGIN_RING(chan, m2mf, NVC0_M2MF_EXEC, 1);
 		OUT_RING  (chan, 0x100000 | (tiled << 4));
 		FIRE_RING (chan);
 
@@ -218,6 +220,9 @@ static struct nvc0_exa_state exa_state;
 	ScrnInfoPtr pScrn = xf86Screens[(p)->drawable.pScreen->myNum]; \
 	NVPtr pNv = NVPTR(pScrn);                                      \
 	struct nouveau_channel *chan = pNv->chan; (void)chan;          \
+	struct nouveau_grobj *m2mf = pNv->NvMemFormat; (void)m2mf;     \
+	struct nouveau_grobj *eng2d = pNv->Nv2D; (void)eng2d;          \
+	struct nouveau_grobj *fermi = pNv->Nv3D; (void)fermi;          \
 	struct nvc0_exa_state *state = &exa_state; (void)state
 
 #define BF(f) NV50_BLEND_FACTOR_##f
@@ -271,7 +276,7 @@ static void NVC0EXASetClip(PixmapPtr ppix, int x, int y, int w, int h)
 {
 	NVC0EXA_LOCALS(ppix);
 
-	BEGIN_RING(chan, NvSub2D, NV50_2D_CLIP_X, 4);
+	BEGIN_RING(chan, eng2d, NV50_2D_CLIP_X, 4);
 	OUT_RING  (chan, x);
 	OUT_RING  (chan, y);
 	OUT_RING  (chan, w);
@@ -293,13 +298,13 @@ NVC0EXAAcquireSurface2D(PixmapPtr ppix, int is_src)
 	bo_flags |= is_src ? NOUVEAU_BO_RD : NOUVEAU_BO_WR;
 
 	if (!nv50_style_tiled_pixmap(ppix)) {
-		BEGIN_RING(chan, NvSub2D, mthd, 2);
+		BEGIN_RING(chan, eng2d, mthd, 2);
 		OUT_RING  (chan, fmt);
 		OUT_RING  (chan, 1);
-		BEGIN_RING(chan, NvSub2D, mthd + 0x14, 1);
+		BEGIN_RING(chan, eng2d, mthd + 0x14, 1);
 		OUT_RING  (chan, (uint32_t)exaGetPixmapPitch(ppix));
 	} else {
-		BEGIN_RING(chan, NvSub2D, mthd, 5);
+		BEGIN_RING(chan, eng2d, mthd, 5);
 		OUT_RING  (chan, fmt);
 		OUT_RING  (chan, 0);
 		OUT_RING  (chan, bo->tile_mode);
@@ -307,7 +312,7 @@ NVC0EXAAcquireSurface2D(PixmapPtr ppix, int is_src)
 		OUT_RING  (chan, 0);
 	}
 
-	BEGIN_RING(chan, NvSub2D, mthd + 0x18, 4);
+	BEGIN_RING(chan, eng2d, mthd + 0x18, 4);
 	OUT_RING  (chan, ppix->drawable.width);
 	OUT_RING  (chan, ppix->drawable.height);
 	if (OUT_RELOCh(chan, bo, 0, bo_flags) ||
@@ -325,7 +330,7 @@ NVC0EXASetPattern(PixmapPtr pdpix, int col0, int col1, int pat0, int pat1)
 {
 	NVC0EXA_LOCALS(pdpix);
 
-	BEGIN_RING(chan, NvSub2D, NV50_2D_PATTERN_COLOR(0), 4);
+	BEGIN_RING(chan, eng2d, NV50_2D_PATTERN_COLOR(0), 4);
 	OUT_RING  (chan, col0);
 	OUT_RING  (chan, col1);
 	OUT_RING  (chan, pat0);
@@ -343,7 +348,7 @@ NVC0EXASetROP(PixmapPtr pdpix, int alu, Pixel planemask)
 	else
 		rop = NVROP[alu].copy;
 
-	BEGIN_RING(chan, NvSub2D, NV50_2D_OPERATION, 1);
+	BEGIN_RING(chan, eng2d, NV50_2D_OPERATION, 1);
 	if (alu == GXcopy && EXA_PM_IS_SOLID(&pdpix->drawable, planemask)) {
 		OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 		return;
@@ -351,7 +356,7 @@ NVC0EXASetROP(PixmapPtr pdpix, int alu, Pixel planemask)
 		OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY_PREMULT);
 	}
 
-	BEGIN_RING(chan, NvSub2D, NV50_2D_PATTERN_FORMAT, 2);
+	BEGIN_RING(chan, eng2d, NV50_2D_PATTERN_FORMAT, 2);
 	switch (pdpix->drawable.bitsPerPixel) {
 	case  8: OUT_RING  (chan, 3); break;
 	case 15: OUT_RING  (chan, 1); break;
@@ -378,7 +383,7 @@ NVC0EXASetROP(PixmapPtr pdpix, int alu, Pixel planemask)
 	}
 
 	if (pNv->currentRop != alu) {
-		BEGIN_RING(chan, NvSub2D, NV50_2D_ROP, 1);
+		BEGIN_RING(chan, eng2d, NV50_2D_ROP, 1);
 		OUT_RING  (chan, rop);
 		pNv->currentRop = alu;
 	}
@@ -413,7 +418,7 @@ NVC0EXAPrepareSolid(PixmapPtr pdpix, int alu, Pixel planemask, Pixel fg)
 
 	NVC0EXASetROP(pdpix, alu, planemask);
 
-	BEGIN_RING(chan, NvSub2D, NV50_2D_DRAW_SHAPE, 3);
+	BEGIN_RING(chan, eng2d, NV50_2D_DRAW_SHAPE, 3);
 	OUT_RING  (chan, NV50_2D_DRAW_SHAPE_RECTANGLES);
 	OUT_RING  (chan, fmt);
 	OUT_RING  (chan, fg);
@@ -432,7 +437,7 @@ NVC0EXASolid(PixmapPtr pdpix, int x1, int y1, int x2, int y2)
 	NVC0EXA_LOCALS(pdpix);
 
 	WAIT_RING (chan, 5);
-	BEGIN_RING(chan, NvSub2D, NV50_2D_DRAW_POINT32_X(0), 4);
+	BEGIN_RING(chan, eng2d, NV50_2D_DRAW_POINT32_X(0), 4);
 	OUT_RING  (chan, x1);
 	OUT_RING  (chan, y1);
 	OUT_RING  (chan, x2);
@@ -497,11 +502,11 @@ NVC0EXACopy(PixmapPtr pdpix, int srcX , int srcY,
 	NVC0EXA_LOCALS(pdpix);
 
 	WAIT_RING (chan, 17);
-	BEGIN_RING(chan, NvSub2D, NV50_2D_SERIALIZE, 1);
+	BEGIN_RING(chan, eng2d, NV50_2D_SERIALIZE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub2D, 0x088c, 1);
+	BEGIN_RING(chan, eng2d, 0x088c, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub2D, NV50_2D_BLIT_DST_X, 12);
+	BEGIN_RING(chan, eng2d, NV50_2D_BLIT_DST_X, 12);
 	OUT_RING  (chan, dstX);
 	OUT_RING  (chan, dstY);
 	OUT_RING  (chan, width);
@@ -564,12 +569,12 @@ NVC0EXAUploadSIFC(const char *src, int src_pitch,
 	 */
 	NVC0EXASetClip(pdpix, x, y, w, h);
 
-	BEGIN_RING(chan, NvSub2D, NV50_2D_OPERATION, 1);
+	BEGIN_RING(chan, eng2d, NV50_2D_OPERATION, 1);
 	OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
-	BEGIN_RING(chan, NvSub2D, NV50_2D_SIFC_BITMAP_ENABLE, 2);
+	BEGIN_RING(chan, eng2d, NV50_2D_SIFC_BITMAP_ENABLE, 2);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, sifc_fmt);
-	BEGIN_RING(chan, NvSub2D, NV50_2D_SIFC_WIDTH, 10);
+	BEGIN_RING(chan, eng2d, NV50_2D_SIFC_WIDTH, 10);
 	OUT_RING  (chan, (line_dwords * 4) / cpp);
 	OUT_RING  (chan, h);
 	OUT_RING  (chan, 0); /* SIFC_DX,Y_DU,V_FRACT,INT */
@@ -592,7 +597,7 @@ NVC0EXAUploadSIFC(const char *src, int src_pitch,
 			int size = count > 1792 ? 1792 : count;
 
 			WAIT_RING (chan, size + 1);
-			BEGIN_RING_NI(chan, NvSub2D, NV50_2D_SIFC_DATA, size);
+			BEGIN_RING_NI(chan, eng2d, NV50_2D_SIFC_DATA, size);
 			OUT_RINGp (chan, ptr, size);
 
 			ptr += size * 4;
@@ -666,7 +671,7 @@ NVC0EXARenderTarget(PixmapPtr ppix, PicturePtr ppict)
 		NOUVEAU_FALLBACK("invalid picture format\n");
 	}
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_RT_ADDRESS_HIGH(0), 8);
+	BEGIN_RING(chan, fermi, NVC0_3D_RT_ADDRESS_HIGH(0), 8);
 	if (OUT_RELOCh(chan, bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR) ||
 	    OUT_RELOCl(chan, bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR))
 		return FALSE;
@@ -759,24 +764,24 @@ NVC0EXATexture(PixmapPtr ppix, PicturePtr ppict, unsigned unit)
 	if (!nv50_style_tiled_pixmap(ppix))
 		NOUVEAU_FALLBACK("pixmap is scanout buffer\n");
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_TIC_ADDRESS_HIGH, 3);
+	BEGIN_RING(chan, fermi, NVC0_3D_TIC_ADDRESS_HIGH, 3);
 	if (OUT_RELOCh(chan, pNv->tesla_scratch, TIC_OFFSET, tcb_flags) ||
 	    OUT_RELOCl(chan, pNv->tesla_scratch, TIC_OFFSET, tcb_flags))
 		return FALSE;
 	OUT_RING  (chan, 15);
 
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
 	if (OUT_RELOCh(chan, pNv->tesla_scratch,
 		       TIC_OFFSET + unit * 32, tcb_flags) ||
 	    OUT_RELOCl(chan, pNv->tesla_scratch,
 		       TIC_OFFSET + unit * 32, tcb_flags))
 		return FALSE;
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_LINE_LENGTH_IN, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_LINE_LENGTH_IN, 2);
 	OUT_RING  (chan, 8 * 4);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_EXEC, 1);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_EXEC, 1);
 	OUT_RING  (chan, 0x100111);
-	BEGIN_RING_NI(chan, NvSubM2MF, NVC0_M2MF_DATA, 8);
+	BEGIN_RING_NI(chan, m2mf, NVC0_M2MF_DATA, 8);
 
 	switch (ppict->format) {
 	case PICT_a8r8g8b8:
@@ -858,24 +863,24 @@ NVC0EXATexture(PixmapPtr ppix, PicturePtr ppict, unsigned unit)
 	OUT_RING  (chan, 0x03000000);
 	OUT_RING  (chan, 0x00000000);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_TSC_ADDRESS_HIGH, 3);
+	BEGIN_RING(chan, fermi, NVC0_3D_TSC_ADDRESS_HIGH, 3);
 	if (OUT_RELOCh(chan, pNv->tesla_scratch, TSC_OFFSET, tcb_flags) ||
 	    OUT_RELOCl(chan, pNv->tesla_scratch, TSC_OFFSET, tcb_flags))
 		return FALSE;
 	OUT_RING  (chan, 0);
 
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
 	if (OUT_RELOCh(chan, pNv->tesla_scratch,
 		       TSC_OFFSET + unit * 32, tcb_flags) ||
 	    OUT_RELOCl(chan, pNv->tesla_scratch,
 		       TSC_OFFSET + unit * 32, tcb_flags))
 		return FALSE;
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_LINE_LENGTH_IN, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_LINE_LENGTH_IN, 2);
 	OUT_RING  (chan, 8 * 4);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_EXEC, 1);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_EXEC, 1);
 	OUT_RING  (chan, 0x100111);
-	BEGIN_RING_NI(chan, NvSubM2MF, NVC0_M2MF_DATA, 8);
+	BEGIN_RING_NI(chan, m2mf, NVC0_M2MF_DATA, 8);
 
 	if (ppict->repeat) {
 		switch (ppict->repeatType) {
@@ -962,18 +967,18 @@ NVC0EXABlend(PixmapPtr ppix, PicturePtr ppict, int op, int component_alpha)
 	}
 
 	if (sblend == BF(ONE) && dblend == BF(ZERO)) {
-		BEGIN_RING(chan, NvSub3D, NVC0_3D_BLEND_ENABLE(0), 1);
+		BEGIN_RING(chan, fermi, NVC0_3D_BLEND_ENABLE(0), 1);
 		OUT_RING  (chan, 0);
 	} else {
-		BEGIN_RING(chan, NvSub3D, NVC0_3D_BLEND_ENABLE(0), 1);
+		BEGIN_RING(chan, fermi, NVC0_3D_BLEND_ENABLE(0), 1);
 		OUT_RING  (chan, 1);
-		BEGIN_RING(chan, NvSub3D, NVC0_3D_BLEND_EQUATION_RGB, 5);
+		BEGIN_RING(chan, fermi, NVC0_3D_BLEND_EQUATION_RGB, 5);
 		OUT_RING  (chan, NVC0_3D_BLEND_EQUATION_RGB_FUNC_ADD);
 		OUT_RING  (chan, sblend);
 		OUT_RING  (chan, dblend);
 		OUT_RING  (chan, NVC0_3D_BLEND_EQUATION_ALPHA_FUNC_ADD);
 		OUT_RING  (chan, sblend);
-		BEGIN_RING(chan, NvSub3D, NVC0_3D_BLEND_FUNC_DST_ALPHA, 1);
+		BEGIN_RING(chan, fermi, NVC0_3D_BLEND_FUNC_DST_ALPHA, 1);
 		OUT_RING  (chan, dblend);
 	}
 }
@@ -1032,7 +1037,7 @@ NVC0EXAPrepareComposite(int op,
 		NOUVEAU_FALLBACK("comp-alpha");
 	*/
 
-	BEGIN_RING(chan, NvSub2D, NV50_2D_SERIALIZE, 1);
+	BEGIN_RING(chan, eng2d, NV50_2D_SERIALIZE, 1);
 	OUT_RING  (chan, 0);
 
 	if (!NVC0EXARenderTarget(pdpix, pdpict)) {
@@ -1043,7 +1048,7 @@ NVC0EXAPrepareComposite(int op,
 	NVC0EXABlend(pdpix, pdpict, op, pmpict && pmpict->componentAlpha &&
 		     PICT_FORMAT_RGB(pmpict->format));
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_CODE_ADDRESS_HIGH, 2);
+	BEGIN_RING(chan, fermi, NVC0_3D_CODE_ADDRESS_HIGH, 2);
 	if (OUT_RELOCh(chan, pNv->tesla_scratch, CODE_OFFSET, shd_flags) ||
 	    OUT_RELOCl(chan, pNv->tesla_scratch, CODE_OFFSET, shd_flags)) {
 		MARK_UNDO(chan);
@@ -1054,7 +1059,7 @@ NVC0EXAPrepareComposite(int op,
 		MARK_UNDO(chan);
 		NOUVEAU_FALLBACK("src picture invalid\n");
 	}
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_BIND_TIC(4), 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_BIND_TIC(4), 1);
 	OUT_RING  (chan, (0 << 9) | (0 << 1) | NVC0_3D_BIND_TIC_ACTIVE);
 
 	if (pmpict) {
@@ -1064,10 +1069,10 @@ NVC0EXAPrepareComposite(int op,
 		}
 		state->have_mask = TRUE;
 
-		BEGIN_RING(chan, NvSub3D, NVC0_3D_BIND_TIC(4), 1);
+		BEGIN_RING(chan, fermi, NVC0_3D_BIND_TIC(4), 1);
 		OUT_RING  (chan, (1 << 9) | (1 << 1) | NVC0_3D_BIND_TIC_ACTIVE);
 
-		BEGIN_RING(chan, NvSub3D, NVC0_3D_SP_START_ID(5), 1);
+		BEGIN_RING(chan, fermi, NVC0_3D_SP_START_ID(5), 1);
 		if (pdpict->format == PICT_a8) {
 			OUT_RING  (chan, PFP_C_A8);
 		} else {
@@ -1084,21 +1089,21 @@ NVC0EXAPrepareComposite(int op,
 	} else {
 		state->have_mask = FALSE;
 
-		BEGIN_RING(chan, NvSub3D, NVC0_3D_BIND_TIC(4), 1);
+		BEGIN_RING(chan, fermi, NVC0_3D_BIND_TIC(4), 1);
 		OUT_RING  (chan, (1 << 1) | 0);
 
-		BEGIN_RING(chan, NvSub3D, NVC0_3D_SP_START_ID(5), 1);
+		BEGIN_RING(chan, fermi, NVC0_3D_SP_START_ID(5), 1);
 		if (pdpict->format == PICT_a8)
 			OUT_RING  (chan, PFP_S_A8);
 		else
 			OUT_RING  (chan, PFP_S);
 	}
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_TSC_FLUSH, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_TSC_FLUSH, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_TIC_FLUSH, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_TIC_FLUSH, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_TEX_CACHE_CTL, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_TEX_CACHE_CTL, 1);
 	OUT_RING  (chan, 0);
 
 	pNv->alu = op;
@@ -1143,10 +1148,10 @@ NVC0EXAComposite(PixmapPtr pdpix,
 	float sX0, sX1, sX2, sY0, sY1, sY2;
 
 	WAIT_RING (chan, 64);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_SCISSOR_HORIZ(0), 2);
+	BEGIN_RING(chan, fermi, NVC0_3D_SCISSOR_HORIZ(0), 2);
 	OUT_RING  (chan, ((dx + w) << 16) | dx);
 	OUT_RING  (chan, ((dy + h) << 16) | dy);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_VERTEX_BEGIN_GL, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_VERTEX_BEGIN_GL, 1);
 	OUT_RING  (chan, NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
 
 	NVC0EXATransform(state->unit[0].transform, sx, sy + (h * 2),
@@ -1181,7 +1186,7 @@ NVC0EXAComposite(PixmapPtr pdpix,
 		VTX1s(pNv, sX2, sY2, dx + (w * 2), dy);
 	}
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_VERTEX_END_GL, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_VERTEX_END_GL, 1);
 	OUT_RING  (chan, 0);
 }
 
diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c
index 188c4f6..41ec7a8 100644
--- a/src/nvc0_xv.c
+++ b/src/nvc0_xv.c
@@ -38,52 +38,54 @@
 extern Atom xvSyncToVBlank, xvSetDefaults;
 
 void
-nvc0_xv_m2mf(struct nouveau_channel *chan,
+nvc0_xv_m2mf(struct nouveau_grobj *m2mf,
 	     struct nouveau_bo *dst, int uv_offset, int dst_pitch, int nlines,
 	     struct nouveau_bo *src, int line_len)
 {
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_TILING_MODE_OUT, 5);
+	struct nouveau_channel *chan = m2mf->channel;
+
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_TILING_MODE_OUT, 5);
 	OUT_RING  (chan, dst->tile_mode);
 	OUT_RING  (chan, dst_pitch);
 	OUT_RING  (chan, nlines);
 	OUT_RING  (chan, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_TILING_POSITION_OUT_X, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_TILING_POSITION_OUT_X, 2);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
 
 	if (uv_offset) {
-		BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_IN_HIGH, 2);
+		BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_IN_HIGH, 2);
 		OUT_RELOCh(chan, src, line_len * nlines,
 				 NOUVEAU_BO_GART | NOUVEAU_BO_RD);
 		OUT_RELOCl(chan, src, line_len * nlines,
 				 NOUVEAU_BO_GART | NOUVEAU_BO_RD);
-		BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
+		BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
 		OUT_RELOCh(chan, dst, uv_offset,
 				 NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 		OUT_RELOCl(chan, dst, uv_offset,
 				 NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
-		BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_PITCH_IN, 4);
+		BEGIN_RING(chan, m2mf, NVC0_M2MF_PITCH_IN, 4);
 		OUT_RING  (chan, line_len);
 		OUT_RING  (chan, dst_pitch);
 		OUT_RING  (chan, line_len);
 		OUT_RING  (chan, nlines >> 1);
-		BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_EXEC, 1);
+		BEGIN_RING(chan, m2mf, NVC0_M2MF_EXEC, 1);
 		OUT_RING  (chan, 0x00100010);
 	}
 
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_IN_HIGH, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_IN_HIGH, 2);
 	OUT_RELOCh(chan, src, 0, NOUVEAU_BO_GART | NOUVEAU_BO_RD);
 	OUT_RELOCl(chan, src, 0, NOUVEAU_BO_GART | NOUVEAU_BO_RD);
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
 	OUT_RELOCh(chan, dst, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 	OUT_RELOCl(chan, dst, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_PITCH_IN, 4);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_PITCH_IN, 4);
 	OUT_RING  (chan, line_len);
 	OUT_RING  (chan, dst_pitch);
 	OUT_RING  (chan, line_len);
 	OUT_RING  (chan, nlines);
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_EXEC, 1);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_EXEC, 1);
 	OUT_RING  (chan, 0x00100010);
 }
 
@@ -114,6 +116,8 @@ nvc0_xv_state_emit(PixmapPtr ppix, int id, struct nouveau_bo *src,
 	NVPtr pNv = NVPTR(pScrn);
 	struct nouveau_channel *chan = pNv->chan;
 	struct nouveau_bo *bo = nouveau_pixmap_bo(ppix);
+	struct nouveau_grobj *m2mf = pNv->NvMemFormat;
+	struct nouveau_grobj *fermi = pNv->Nv3D;
 	const unsigned shd_flags = NOUVEAU_BO_RD | NOUVEAU_BO_VRAM;
 	const unsigned tcb_flags = NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM;
 	uint32_t mode = 0xd0005000 | (src->tile_mode << 18);
@@ -121,7 +125,7 @@ nvc0_xv_state_emit(PixmapPtr ppix, int id, struct nouveau_bo *src,
 	if (MARK_RING(chan, 256, 18))
 		return FALSE;
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_RT_ADDRESS_HIGH(0), 8);
+	BEGIN_RING(chan, fermi, NVC0_3D_RT_ADDRESS_HIGH(0), 8);
 	if (OUT_RELOCh(chan, bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR) ||
 	    OUT_RELOCl(chan, bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR)) {
 		MARK_UNDO(chan);
@@ -139,10 +143,10 @@ nvc0_xv_state_emit(PixmapPtr ppix, int id, struct nouveau_bo *src,
 	OUT_RING  (chan, 1);
 	OUT_RING  (chan, 0);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_BLEND_ENABLE(0), 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_BLEND_ENABLE(0), 1);
 	OUT_RING  (chan, 0);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_TIC_ADDRESS_HIGH, 3);
+	BEGIN_RING(chan, fermi, NVC0_3D_TIC_ADDRESS_HIGH, 3);
 	if (OUT_RELOCh(chan, pNv->tesla_scratch, TIC_OFFSET, tcb_flags) ||
 	    OUT_RELOCl(chan, pNv->tesla_scratch, TIC_OFFSET, tcb_flags)) {
 		MARK_UNDO(chan);
@@ -150,18 +154,18 @@ nvc0_xv_state_emit(PixmapPtr ppix, int id, struct nouveau_bo *src,
 	}
 	OUT_RING  (chan, 15);
 
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
 	if (OUT_RELOCh(chan, pNv->tesla_scratch, TIC_OFFSET, tcb_flags) ||
 	    OUT_RELOCl(chan, pNv->tesla_scratch, TIC_OFFSET, tcb_flags)) {
 		MARK_UNDO(chan);
 		return FALSE;
 	}
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_LINE_LENGTH_IN, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_LINE_LENGTH_IN, 2);
 	OUT_RING  (chan, 16 * 4);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_EXEC, 1);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_EXEC, 1);
 	OUT_RING  (chan, 0x00100111);
-	BEGIN_RING_NI(chan, NvSubM2MF, NVC0_M2MF_DATA, 16);
+	BEGIN_RING_NI(chan, m2mf, NVC0_M2MF_DATA, 16);
 	if (id == FOURCC_YV12 || id == FOURCC_I420) {
 	OUT_RING  (chan, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
 			 NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
@@ -246,7 +250,7 @@ nvc0_xv_state_emit(PixmapPtr ppix, int id, struct nouveau_bo *src,
 	OUT_RING  (chan, 0x00000000);
 	}
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_TSC_ADDRESS_HIGH, 3);
+	BEGIN_RING(chan, fermi, NVC0_3D_TSC_ADDRESS_HIGH, 3);
 	if (OUT_RELOCh(chan, pNv->tesla_scratch, TSC_OFFSET, tcb_flags) ||
 	    OUT_RELOCl(chan, pNv->tesla_scratch, TSC_OFFSET, tcb_flags)) {
 		MARK_UNDO(chan);
@@ -254,18 +258,18 @@ nvc0_xv_state_emit(PixmapPtr ppix, int id, struct nouveau_bo *src,
 	}
 	OUT_RING  (chan, 0x00000000);
 
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_OFFSET_OUT_HIGH, 2);
 	if (OUT_RELOCh(chan, pNv->tesla_scratch, TSC_OFFSET, tcb_flags) ||
 	    OUT_RELOCl(chan, pNv->tesla_scratch, TSC_OFFSET, tcb_flags)) {
 		MARK_UNDO(chan);
 		return FALSE;
 	}
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_LINE_LENGTH_IN, 2);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_LINE_LENGTH_IN, 2);
 	OUT_RING  (chan, 16 * 4);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSubM2MF, NVC0_M2MF_EXEC, 1);
+	BEGIN_RING(chan, m2mf, NVC0_M2MF_EXEC, 1);
 	OUT_RING  (chan, 0x00100111);
-	BEGIN_RING_NI(chan, NvSubM2MF, NVC0_M2MF_DATA, 16);
+	BEGIN_RING_NI(chan, m2mf, NVC0_M2MF_DATA, 16);
 	OUT_RING  (chan, NV50TSC_1_0_WRAPS_CLAMP_TO_EDGE |
 			 NV50TSC_1_0_WRAPT_CLAMP_TO_EDGE |
 			 NV50TSC_1_0_WRAPR_CLAMP_TO_EDGE);
@@ -291,26 +295,26 @@ nvc0_xv_state_emit(PixmapPtr ppix, int id, struct nouveau_bo *src,
 	OUT_RING  (chan, 0x00000000);
 	OUT_RING  (chan, 0x00000000);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_CODE_ADDRESS_HIGH, 2);
+	BEGIN_RING(chan, fermi, NVC0_3D_CODE_ADDRESS_HIGH, 2);
 	if (OUT_RELOCh(chan, pNv->tesla_scratch, CODE_OFFSET, shd_flags) ||
 	    OUT_RELOCl(chan, pNv->tesla_scratch, CODE_OFFSET, shd_flags)) {
 		MARK_UNDO(chan);
 		return FALSE;
 
 	}
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_SP_START_ID(5), 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_SP_START_ID(5), 1);
 	OUT_RING  (chan, PFP_NV12);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_TSC_FLUSH, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_TSC_FLUSH, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_TIC_FLUSH, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_TIC_FLUSH, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_TEX_CACHE_CTL, 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_TEX_CACHE_CTL, 1);
 	OUT_RING  (chan, 0);
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_BIND_TIC(4), 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_BIND_TIC(4), 1);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_BIND_TIC(4), 1);
+	BEGIN_RING(chan, fermi, NVC0_3D_BIND_TIC(4), 1);
 	OUT_RING  (chan, 0x203);
 
 	return TRUE;
@@ -329,6 +333,7 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
 {
 	NVPtr pNv = NVPTR(pScrn);
 	struct nouveau_channel *chan = pNv->chan;
+	struct nouveau_grobj *fermi = pNv->Nv3D;
 	float X1, X2, Y1, Y2;
 	BoxPtr pbox;
 	int nbox;
@@ -371,16 +376,16 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
 				return BadAlloc;
 		}
 
-		BEGIN_RING(chan, NvSub3D, NVC0_3D_SCISSOR_HORIZ(0), 2);
+		BEGIN_RING(chan, fermi, NVC0_3D_SCISSOR_HORIZ(0), 2);
 		OUT_RING  (chan, sx2 << NVC0_3D_SCISSOR_HORIZ_MAX__SHIFT | sx1);
 		OUT_RING  (chan, sy2 << NVC0_3D_SCISSOR_VERT_MAX__SHIFT | sy1 );
 
-		BEGIN_RING(chan, NvSub3D, NVC0_3D_VERTEX_BEGIN_GL, 1);
+		BEGIN_RING(chan, fermi, NVC0_3D_VERTEX_BEGIN_GL, 1);
 		OUT_RING  (chan, NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
 		VTX2s(pNv, tx1, ty1, tx1, ty1, sx1, sy1);
 		VTX2s(pNv, tx2+(tx2-tx1), ty1, tx2+(tx2-tx1), ty1, sx2+(sx2-sx1), sy1);
 		VTX2s(pNv, tx1, ty2+(ty2-ty1), tx1, ty2+(ty2-ty1), sx1, sy2+(sy2-sy1));
-		BEGIN_RING(chan, NvSub3D, NVC0_3D_VERTEX_END_GL, 1);
+		BEGIN_RING(chan, fermi, NVC0_3D_VERTEX_END_GL, 1);
 		OUT_RING  (chan, 0);
 
 		pbox++;
@@ -395,18 +400,19 @@ nvc0_xv_csc_update(NVPtr pNv, float yco, float *off, float *uco, float *vco)
 {
 	struct nouveau_channel *chan = pNv->chan;
 	struct nouveau_bo *bo = pNv->tesla_scratch;
+	struct nouveau_grobj *fermi = pNv->Nv3D;
 
 	if (MARK_RING(chan, 64, 2))
 		return;
 
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_CB_SIZE, 3);
+	BEGIN_RING(chan, fermi, NVC0_3D_CB_SIZE, 3);
 	OUT_RING  (chan, 256);
 	if (OUT_RELOCh(chan, bo, CB_OFFSET, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR) ||
 	    OUT_RELOCl(chan, bo, CB_OFFSET, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR)) {
 		MARK_UNDO(chan);
 		return;
 	}
-	BEGIN_RING(chan, NvSub3D, NVC0_3D_CB_POS, 11);
+	BEGIN_RING(chan, fermi, NVC0_3D_CB_POS, 11);
 	OUT_RING  (chan, 0);
 	OUT_RINGf (chan, yco);
 	OUT_RINGf (chan, off[0]);