diff options
| -rw-r--r-- | src/nv_bios.c | 4 | ||||
| -rw-r--r-- | src/nv_hw.c | 12 | ||||
| -rw-r--r-- | src/nv_setup.c | 6 | ||||
| -rw-r--r-- | src/nv_type.h | 6 |
4 files changed, 17 insertions, 11 deletions
diff --git a/src/nv_bios.c b/src/nv_bios.c index 8e80766..448ce81 100644 --- a/src/nv_bios.c +++ b/src/nv_bios.c @@ -1118,7 +1118,7 @@ static Bool init_ram_condition2(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, * offset + 1 (8 bit): and mask * offset + 2 (8 bit): cmpval * - * Test if (NV_PEXTDEV_BOOT & and mask) matches cmpval + * Test if (NV_EXTDEV_BOOT & and mask) matches cmpval */ NVPtr pNv = NVPTR(pScrn); CARD32 and = *((CARD32 *) (&bios->data[offset + 1])); @@ -1126,7 +1126,7 @@ static Bool init_ram_condition2(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, CARD32 data; if (iexec->execute) { - data=(pNv->PEXTDEV[NV_PEXTDEV_BOOT/4])∧ + data=(nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT))∧ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n", diff --git a/src/nv_hw.c b/src/nv_hw.c index e3a05aa..ee9d29a 100644 --- a/src/nv_hw.c +++ b/src/nv_hw.c @@ -423,7 +423,7 @@ static void nv4UpdateArbitrationSettings ( sim_data.pix_bpp = (char)pixelDepth; sim_data.enable_video = 0; sim_data.enable_mp = 0; - sim_data.memory_width = (pNv->PEXTDEV[0x0000/4] & 0x10) ? 128 : 64; + sim_data.memory_width = (nvReadEXTDEV(pNv, 0x0000) & 0x10) ? 128 : 64; sim_data.mem_latency = (char)cfg1 & 0x0F; sim_data.mem_aligned = 1; sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); @@ -651,7 +651,7 @@ static void nv10UpdateArbitrationSettings ( sim_data.enable_video = 1; sim_data.enable_mp = 0; sim_data.memory_type = (nvReadFB(pNv, 0x0200) & 0x01) ? 1 : 0; - sim_data.memory_width = (pNv->PEXTDEV[0x0000/4] & 0x10) ? 128 : 64; + sim_data.memory_width = (nvReadEXTDEV(pNv, 0x0000) & 0x10) ? 128 : 64; sim_data.mem_latency = (char)cfg1 & 0x0F; sim_data.mem_aligned = 1; sim_data.mem_page_miss = (char)(((cfg1>>4) &0x0F) + ((cfg1>>31) & 0x01)); @@ -964,11 +964,11 @@ void NVLoadStateExt ( nvWriteMC(pNv, 0x0200, 0xFFFF00FF); nvWriteMC(pNv, 0x0200, 0xFFFFFFFF); - pNv->PTIMER[0x0200] = 0x00000008; - pNv->PTIMER[0x0210] = 0x00000003; + nvWriteTIMER(pNv, 0x0200, 0x00000008); + nvWriteTIMER(pNv, 0x0210, 0x00000003); /*TODO: DRM handle PTIMER interrupts */ - pNv->PTIMER[0x0140] = 0x00000000; - pNv->PTIMER[0x0100] = 0xFFFFFFFF; + nvWriteTIMER(pNv, 0x0140, 0x00000000); + nvWriteTIMER(pNv, 0x0100, 0xFFFFFFFF); /* begin surfaces */ /* it seems those regions are equivalent to the radeon's SURFACEs. needs to go in-kernel just like the SURFACEs */ diff --git a/src/nv_setup.c b/src/nv_setup.c index b34cd3f..e1fb4dd 100644 --- a/src/nv_setup.c +++ b/src/nv_setup.c @@ -279,7 +279,7 @@ static void nv4GetConfig (NVPtr pNv) break; } } - pNv->CrystalFreqKHz = (pNv->PEXTDEV[0x0000/4] & 0x00000040) ? 14318 : 13500; + pNv->CrystalFreqKHz = (nvReadEXTDEV(pNv, 0x0000) & 0x00000040) ? 14318 : 13500; pNv->CURSOR = &(pNv->PRAMIN[0x1E00]); pNv->MinVClockFreqKHz = 12000; pNv->MaxVClockFreqKHz = 350000; @@ -310,11 +310,11 @@ static void nv10GetConfig (NVPtr pNv) if(pNv->RamAmountKBytes > 256*1024) pNv->RamAmountKBytes = 256*1024; - pNv->CrystalFreqKHz = (pNv->PEXTDEV[0x0000/4] & (1 << 6)) ? 14318 : 13500; + pNv->CrystalFreqKHz = (nvReadEXTDEV(pNv, 0x0000) & (1 << 6)) ? 14318 : 13500; if(pNv->twoHeads && (implementation != CHIPSET_NV11)) { - if(pNv->PEXTDEV[0x0000/4] & (1 << 22)) + if(nvReadEXTDEV(pNv, 0x0000) & (1 << 22)) pNv->CrystalFreqKHz = 27000; } diff --git a/src/nv_type.h b/src/nv_type.h index 3ecf28e..766f169 100644 --- a/src/nv_type.h +++ b/src/nv_type.h @@ -258,4 +258,10 @@ typedef struct _NVRec { #define nvReadMC(pNv, reg) MMIO_IN32(pNv->PMC, reg) #define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->PMC, reg, val) +#define nvReadEXTDEV(pNv, reg) MMIO_IN32(pNv->PEXTDEV, reg) +#define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->PEXTDEV, reg, val) + +#define nvReadTIMER(pNv, reg) MMIO_IN32(pNv->PTIMER, reg) +#define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->PTIMER, reg, val) + #endif /* __NV_STRUCT_H__ */ |