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-rw-r--r--src/Makefile.am4
-rw-r--r--src/i2c_vid.h16
-rw-r--r--src/local_xf86Rename.h23
-rw-r--r--src/nv_bios.c90
-rw-r--r--src/nv_crtc.c1439
-rw-r--r--src/nv_cursor.c76
-rw-r--r--src/nv_dac.c425
-rw-r--r--src/nv_driver.c443
-rw-r--r--src/nv_hw.c438
-rw-r--r--src/nv_i2c.c70
-rw-r--r--src/nv_include.h2
-rw-r--r--src/nv_local.h27
-rw-r--r--src/nv_output.c885
-rw-r--r--src/nv_proto.h50
-rw-r--r--src/nv_setup.c139
-rw-r--r--src/nv_type.h103
-rw-r--r--src/nv_xf86Rename.h66
-rw-r--r--src/nvreg.h90
18 files changed, 3173 insertions, 1213 deletions
diff --git a/src/Makefile.am b/src/Makefile.am
index 7e4f5b1..b53ebd9 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -33,7 +33,6 @@ nouveau_drv_la_SOURCES = \
nv_bios.c \
nv_const.h \
nv_cursor.c \
- nv_dac.c \
nv_dma.c \
nv_dma.h \
nv_dri.c \
@@ -54,6 +53,9 @@ nouveau_drv_la_SOURCES = \
nv_type.h \
nv_video.c \
nv_xaa.c \
+ nv_output.c \
+ nv_crtc.c \
+ nv_i2c.c \
nv30_exa.c
#riva128_la_LTLIBRARIES = riva128.la
diff --git a/src/i2c_vid.h b/src/i2c_vid.h
new file mode 100644
index 0000000..87ebe7a
--- /dev/null
+++ b/src/i2c_vid.h
@@ -0,0 +1,16 @@
+/* this needs to go in the server */
+#ifndef I2C_VID_H
+#define I2C_VID_H
+
+typedef struct _NVI2CVidOutputRec {
+ void *(*init)(I2CBusPtr b, I2CSlaveAddr addr);
+ xf86OutputStatus (*detect)(I2CDevPtr d);
+ ModeStatus (*mode_valid)(I2CDevPtr d, DisplayModePtr mode);
+ void (*mode_set)(I2CDevPtr d, DisplayModePtr mode);
+ void (*dpms)(I2CDevPtr d, int mode);
+ void (*dump_regs)(I2CDevPtr d);
+ void (*save)(I2CDevPtr d);
+ void (*restore)(I2CDevPtr d);
+} NVI2CVidOutputRec, *NVI2CVidOutputPtr;
+
+#endif
diff --git a/src/local_xf86Rename.h b/src/local_xf86Rename.h
new file mode 100644
index 0000000..708877f
--- /dev/null
+++ b/src/local_xf86Rename.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright © 2006 Keith Packard
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission. The copyright holders make no representations
+ * about the suitability of this software for any purpose. It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+
+#define XF86NAME(x) nv_##x
diff --git a/src/nv_bios.c b/src/nv_bios.c
index d093100..a5ecf66 100644
--- a/src/nv_bios.c
+++ b/src/nv_bios.c
@@ -31,6 +31,7 @@
* * PLL algorithms.
*/
+#include <byteswap.h>
typedef struct {
Bool execute;
Bool repeat;
@@ -1519,6 +1520,14 @@ static void parse_bit_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int of
}
}
+static unsigned short brs(unsigned char *data, int offset)
+{
+ unsigned short ret;
+
+ ret = (data[offset]) | ((data[offset+1]) << 8);
+ return ret;
+}
+
static void parse_pins_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
{
int pins_version_major=bios->data[offset+5];
@@ -1527,7 +1536,6 @@ static void parse_pins_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int o
int init2 = bios->data[offset + 20] + (bios->data[offset + 21] * 256);
int init_size = bios->data[offset + 22] + (bios->data[offset + 23] * 256) + 1;
int ram_tab;
-
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PINS version %d.%d\n",pins_version_major,pins_version_minor);
#if 0
@@ -1562,6 +1570,77 @@ static unsigned int findstr(bios_t* bios, unsigned char *str, int len)
return 0;
}
+#define G5_FIXED_LOC 0xe2f8
+
+
+static unsigned int nv_find_dcb_table(ScrnInfoPtr pScrn, bios_t *bios)
+{
+ NVPtr pNv = NVPTR(pScrn);
+ CARD16 bufloc;
+ int is_g5 = 0;
+ CARD32 sig;
+ char *table2;
+ unsigned char headerSize, entries;
+ CARD32 header_word;
+ int i;
+ int sig_offsets[2] = { 0x4, 0x6 };
+ int offset = -1;
+
+ /* get the offset from 0x36 */
+
+ bufloc = *(CARD16 *)&bios->data[0x36];
+
+ if (bufloc == 0x0) {
+ if ((pNv->Chipset & 0x0ff0) == CHIPSET_NV43) {
+ is_g5 = 1;
+ bufloc = G5_FIXED_LOC;
+ } else {
+ return 0;
+ }
+ }
+
+ table2 = &bios->data[bufloc];
+
+ /* lets play hunt the signature */
+ for (i = 0; i < sizeof(sig_offsets) / sizeof(int); i++) {
+ sig = *(uint32_t*)(table2 + sig_offsets[i]);
+ if ((sig == 0x4edcbdcb) || (sig == 0xcbbddc4e)) {
+ offset = sig_offsets[i];
+ break;
+ }
+ }
+ if (offset == -1)
+ return 0;
+
+ if (offset == 6) {
+ header_word = *(uint32_t *)table2;
+ if (is_g5) {
+ headerSize = 0x3c;
+ entries = 0xa;
+ } else {
+ headerSize = (header_word >> 8) & 0xff;
+ entries = (header_word >> 16) & 0xff;
+ }
+ } else {
+ entries = 0xa;
+ headerSize = 0x8;
+ }
+
+ ErrorF("DCB size is %02X, entries is %02X\n", headerSize, entries);
+ if (entries >= NV40_NUM_DCB_ENTRIES)
+ entries = NV40_NUM_DCB_ENTRIES;
+
+ for (i = 0; i < entries; i++) {
+ if (is_g5)
+ pNv->dcb_table[i] = __bswap_32(*(uint32_t *)&table2[headerSize + 8 * i]);
+ else
+ pNv->dcb_table[i] = *(uint32_t *)&table2[headerSize + 8 * i];
+ }
+
+ return entries;
+}
+
+
unsigned int NVParseBios(ScrnInfoPtr pScrn)
{
unsigned int bit_offset;
@@ -1591,6 +1670,15 @@ unsigned int NVParseBios(ScrnInfoPtr pScrn)
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No known script signature found.\n");
}
+ /* look for NV40+ DCB table - and make a copy somewhere for output setup code */
+ ret = nv_find_dcb_table(pScrn, &bios);
+ if (ret)
+ {
+ pNv->dcb_entries = ret;
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DCB found %d entries.\n", ret);
+ }
+ else
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No DCB table found\n");
xfree(bios.data);
return 1;
}
diff --git a/src/nv_crtc.c b/src/nv_crtc.c
new file mode 100644
index 0000000..5b646d0
--- /dev/null
+++ b/src/nv_crtc.c
@@ -0,0 +1,1439 @@
+/*
+ * Copyright 2006 Dave Airlie
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECT
+ */
+/*
+ * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
+ * decleration is at the bottom of this file as it is rather ugly
+ */
+
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <assert.h>
+#include "xf86.h"
+#include "os.h"
+#include "mibank.h"
+#include "globals.h"
+#include "xf86.h"
+#include "xf86Priv.h"
+#include "xf86DDC.h"
+#include "mipointer.h"
+#include "windowstr.h"
+#include <randrstr.h>
+#include <X11/extensions/render.h>
+
+#include "xf86Crtc.h"
+#include "nv_include.h"
+
+#include "vgaHW.h"
+
+#define CRTC_INDEX 0x3d4
+#define CRTC_DATA 0x3d5
+#define CRTC_IN_STAT_1 0x3da
+
+#define WHITE_VALUE 0x3F
+#define BLACK_VALUE 0x00
+#define OVERSCAN_VALUE 0x01
+
+static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
+static void nv_crtc_load_state_ext (xf86CrtcPtr crtc, RIVA_HW_STATE *state);
+static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
+static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
+
+static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+
+ NV_WR08(pNv->PVIO, VGA_MISC_OUT_W, value);
+}
+
+static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+
+ return NV_RD08(pNv->PVIO, VGA_MISC_OUT_R);
+}
+
+
+static void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+ volatile CARD8 *pCRTCReg = nv_crtc->crtc ? pNv->PCIO1 : pNv->PCIO0;
+
+ NV_WR08(pCRTCReg, CRTC_INDEX, index);
+ NV_WR08(pCRTCReg, CRTC_DATA, value);
+}
+
+static CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+ volatile CARD8 *pCRTCReg = nv_crtc->crtc ? pNv->PCIO1 : pNv->PCIO0;
+
+ NV_WR08(pCRTCReg, CRTC_INDEX, index);
+ return NV_RD08(pCRTCReg, CRTC_DATA);
+}
+
+static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+
+ NV_WR08(pNv->PVIO, VGA_SEQ_INDEX, index);
+ NV_WR08(pNv->PVIO, VGA_SEQ_DATA, value);
+}
+
+static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+ volatile CARD8 *pVGAReg = pNv->PVIO;
+
+ NV_WR08(pNv->PVIO, VGA_SEQ_INDEX, index);
+ return NV_RD08(pNv->PVIO, VGA_SEQ_DATA);
+}
+
+static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+
+ NV_WR08(pNv->PVIO, VGA_GRAPH_INDEX, index);
+ NV_WR08(pNv->PVIO, VGA_GRAPH_DATA, value);
+}
+
+static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+ volatile CARD8 *pVGAReg = pNv->PVIO;
+
+ NV_WR08(pVGAReg, VGA_GRAPH_INDEX, index);
+ return NV_RD08(pVGAReg, VGA_GRAPH_DATA);
+}
+
+
+static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+ volatile CARD8 *pCRTCReg = nv_crtc->crtc ? pNv->PCIO1 : pNv->PCIO0;
+
+ NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
+ if (nv_crtc->paletteEnabled)
+ index &= ~0x20;
+ else
+ index |= 0x20;
+ NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
+ NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
+}
+
+static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+ volatile CARD8 *pCRTCReg = nv_crtc->crtc ? pNv->PCIO1 : pNv->PCIO0;
+
+ NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
+ if (nv_crtc->paletteEnabled)
+ index &= ~0x20;
+ else
+ index |= 0x20;
+ NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
+ return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
+}
+
+void NVCrtcSetOwner(xf86CrtcPtr crtc)
+{
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ /*TODO beos double writes this on nv11 */
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_OWNER, nv_crtc->crtc * 0x3);
+}
+
+static void
+NVEnablePalette(xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+ volatile CARD8 *pCRTCReg = nv_crtc->crtc ? pNv->PCIO1 : pNv->PCIO0;
+
+ NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
+ NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
+ nv_crtc->paletteEnabled = TRUE;
+}
+
+static void
+NVDisablePalette(xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+ volatile CARD8 *pCRTCReg = nv_crtc->crtc ? pNv->PCIO1 : pNv->PCIO0;
+
+ NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
+ NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
+ nv_crtc->paletteEnabled = FALSE;
+}
+
+static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+ volatile CARD8 *pCRTCReg = nv_crtc->crtc ? pNv->PCIO1 : pNv->PCIO0;
+
+ NV_WR08(pCRTCReg, reg, value);
+}
+
+/* perform a sequencer reset */
+static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
+{
+ if (start)
+ NVWriteVgaSeq(crtc, 0x00, 0x1);
+ else
+ NVWriteVgaSeq(crtc, 0x00, 0x3);
+
+}
+static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
+{
+ CARD8 tmp;
+
+ if (on) {
+ tmp = NVReadVgaSeq(crtc, 0x1);
+ NVVgaSeqReset(crtc, TRUE);
+ NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
+
+ NVEnablePalette(crtc);
+ } else {
+ /*
+ * Reenable sequencer, then turn on screen.
+ */
+ tmp = NVReadVgaSeq(crtc, 0x1);
+ NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
+ NVVgaSeqReset(crtc, FALSE);
+
+ NVDisablePalette(crtc);
+ }
+}
+
+void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
+{
+ CARD8 cr11;
+
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
+ cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
+ if (Lock) cr11 |= 0x80;
+ else cr11 &= ~0x80;
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
+}
+/*
+ * Calculate the Video Clock parameters for the PLL.
+ */
+static void CalcVClock (
+ int clockIn,
+ int *clockOut,
+ CARD32 *pllOut,
+ NVPtr pNv
+)
+{
+ unsigned lowM, highM;
+ unsigned DeltaNew, DeltaOld;
+ unsigned VClk, Freq;
+ unsigned M, N, P;
+
+ DeltaOld = 0xFFFFFFFF;
+
+ VClk = (unsigned)clockIn;
+
+ if (pNv->CrystalFreqKHz == 13500) {
+ lowM = 7;
+ highM = 13;
+ } else {
+ lowM = 8;
+ highM = 14;
+ }
+
+ for (P = 0; P <= 4; P++) {
+ Freq = VClk << P;
+ if ((Freq >= 128000) && (Freq <= 350000)) {
+ for (M = lowM; M <= highM; M++) {
+ N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
+ if(N <= 255) {
+ Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
+ if (Freq > VClk)
+ DeltaNew = Freq - VClk;
+ else
+ DeltaNew = VClk - Freq;
+ if (DeltaNew < DeltaOld) {
+ *pllOut = (P << 16) | (N << 8) | M;
+ *clockOut = Freq;
+ DeltaOld = DeltaNew;
+ }
+ }
+ }
+ }
+ }
+}
+
+static void CalcVClock2Stage (
+ int clockIn,
+ int *clockOut,
+ CARD32 *pllOut,
+ CARD32 *pllBOut,
+ NVPtr pNv
+)
+{
+ unsigned DeltaNew, DeltaOld;
+ unsigned VClk, Freq;
+ unsigned M, N, P;
+
+ DeltaOld = 0xFFFFFFFF;
+
+ *pllBOut = 0x80000401; /* fixed at x4 for now */
+
+ VClk = (unsigned)clockIn;
+
+ for (P = 0; P <= 6; P++) {
+ Freq = VClk << P;
+ if ((Freq >= 400000) && (Freq <= 1000000)) {
+ for (M = 1; M <= 13; M++) {
+ N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
+ if((N >= 5) && (N <= 255)) {
+ Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
+ if (Freq > VClk)
+ DeltaNew = Freq - VClk;
+ else
+ DeltaNew = VClk - Freq;
+ if (DeltaNew < DeltaOld) {
+ *pllOut = (P << 16) | (N << 8) | M;
+ *clockOut = Freq;
+ DeltaOld = DeltaNew;
+ }
+ }
+ }
+ }
+ }
+}
+
+static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
+{
+ state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
+ if(pNv->twoHeads)
+ state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
+ if(pNv->twoStagePLL) {
+ state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
+ state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
+ }
+ state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
+}
+
+
+static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
+{
+ nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
+
+ ErrorF("writting vpll %08X\n", state->vpll);
+ ErrorF("writting vpll2 %08X\n", state->vpll2);
+ nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
+ if(pNv->twoHeads)
+ nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
+ if(pNv->twoStagePLL) {
+ nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
+ nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
+ }
+}
+
+/*
+ * Calculate extended mode parameters (SVGA) and save in a
+ * mode state structure.
+ */
+void nv_crtc_calc_state_ext(
+ xf86CrtcPtr crtc,
+ int bpp,
+ int width,
+ int hDisplaySize,
+ int height,
+ int dotClock,
+ int flags
+)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ int pixelDepth, VClk;
+ CARD32 CursorStart;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ NVCrtcRegPtr regp;
+ NVPtr pNv = NVPTR(pScrn);
+ RIVA_HW_STATE *state;
+ int num_crtc_enabled, i;
+
+ state = &pNv->ModeReg;
+
+ regp = &pNv->ModeReg.crtc_reg[nv_crtc->crtc];
+
+ /*
+ * Extended RIVA registers.
+ */
+ pixelDepth = (bpp + 1)/8;
+ if(pNv->twoStagePLL)
+ CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
+ else
+ CalcVClock(dotClock, &VClk, &state->pll, pNv);
+
+ switch (pNv->Architecture)
+ {
+ case NV_ARCH_04:
+ nv4UpdateArbitrationSettings(VClk,
+ pixelDepth * 8,
+ &(state->arbitration0),
+ &(state->arbitration1),
+ pNv);
+ regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
+ regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
+ if (flags & V_DBLSCAN)
+ regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
+ regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
+ state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
+ state->config = 0x00001114;
+ regp->CRTC[NV_VGA_CRTCX_REPAINT1] = hDisplaySize < 1280 ? 0x04 : 0x00;
+ break;
+ case NV_ARCH_10:
+ case NV_ARCH_20:
+ case NV_ARCH_30:
+ default:
+ if(((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
+ ((pNv->Chipset & 0xfff0) == CHIPSET_C512))
+ {
+ state->arbitration0 = 128;
+ state->arbitration1 = 0x0480;
+ } else
+ if(((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
+ ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2))
+ {
+ nForceUpdateArbitrationSettings(VClk,
+ pixelDepth * 8,
+ &(state->arbitration0),
+ &(state->arbitration1),
+ pNv);
+ } else if(pNv->Architecture < NV_ARCH_30) {
+ nv10UpdateArbitrationSettings(VClk,
+ pixelDepth * 8,
+ &(state->arbitration0),
+ &(state->arbitration1),
+ pNv);
+ } else {
+ nv30UpdateArbitrationSettings(pNv,
+ &(state->arbitration0),
+ &(state->arbitration1));
+ }
+
+
+ CursorStart = pNv->Cursor->offset;
+
+ regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
+ regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
+ regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
+
+ if (flags & V_DBLSCAN)
+ regp->CRTC[NV_VGA_CRTCX_CURCTL1]|= 2;
+
+
+ state->config = nvReadFB(pNv, NV_PFB_CFG0);
+ regp->CRTC[NV_VGA_CRTCX_REPAINT1] = hDisplaySize < 1280 ? 0x04 : 0x00;
+ break;
+ }
+
+ /* okay do we have 2 CRTCs running ? */
+ num_crtc_enabled = 0;
+ for (i = 0; i < xf86_config->num_crtc; i++) {
+ if (xf86_config->crtc[i]->enabled)
+ num_crtc_enabled++;
+ }
+
+ if (num_crtc_enabled > 1) {
+ if (nv_crtc->crtc == 1) {
+ state->vpll2 = state->pll;
+ state->vpll2B = state->pllB;
+ state->pllsel |= (1<<29) | (1<<11);
+ } else {
+ state->vpll = state->pll;
+ state->vpllB = state->pllB;
+ state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
+ state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
+ }
+ } else {
+ state->vpll = state->pll;
+ state->vpllB = state->pllB;
+ state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
+ state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
+ }
+
+
+ regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
+ regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
+ if (pNv->Architecture >= NV_ARCH_30) {
+ regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
+ }
+
+
+ regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((width / 8) * pixelDepth) & 0x700) >> 3;
+ regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
+}
+
+
+static void
+nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
+{
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ unsigned char seq1 = 0, crtc17 = 0;
+ unsigned char crtc1A;
+ int ret;
+
+ NVCrtcSetOwner(crtc);
+
+ crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
+ switch(mode) {
+ case DPMSModeStandby:
+ /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
+ seq1 = 0x20;
+ crtc17 = 0x80;
+ crtc1A |= 0x80;
+ break;
+ case DPMSModeSuspend:
+ /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
+ seq1 = 0x20;
+ crtc17 = 0x80;
+ crtc1A |= 0x40;
+ break;
+ case DPMSModeOff:
+ /* Screen: Off; HSync: Off, VSync: Off */
+ seq1 = 0x20;
+ crtc17 = 0x00;
+ crtc1A |= 0xC0;
+ break;
+ case DPMSModeOn:
+ default:
+ /* Screen: On; HSync: On, VSync: On */
+ seq1 = 0x00;
+ crtc17 = 0x80;
+ break;
+ }
+
+ NVWriteVgaSeq(crtc, 0x00, 0x1);
+ seq1 = NVReadVgaSeq(crtc, 0x01) & ~0x20;
+ NVWriteVgaSeq(crtc, 0x1, seq1);
+ crtc17 |= NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80;
+ usleep(10000);
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
+ NVWriteVgaSeq(crtc, 0x0, 0x3);
+
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
+
+}
+
+static Bool
+nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
+ DisplayModePtr adjusted_mode)
+{
+ return TRUE;
+}
+
+static void
+nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVCrtcRegPtr regp;
+ NVPtr pNv = NVPTR(pScrn);
+ int depth = pScrn->depth;
+ unsigned int i;
+
+ regp = &pNv->ModeReg.crtc_reg[nv_crtc->crtc];
+
+
+ /*
+ * compute correct Hsync & Vsync polarity
+ */
+ if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
+ && (mode->Flags & (V_PVSYNC | V_NVSYNC)))
+ {
+ regp->MiscOutReg = 0x23;
+ if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
+ if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
+ }
+ else
+ {
+ int VDisplay = mode->VDisplay;
+ if (mode->Flags & V_DBLSCAN)
+ VDisplay *= 2;
+ if (mode->VScan > 1)
+ VDisplay *= mode->VScan;
+ if (VDisplay < 400)
+ regp->MiscOutReg = 0xA3; /* +hsync -vsync */
+ else if (VDisplay < 480)
+ regp->MiscOutReg = 0x63; /* -hsync +vsync */
+ else if (VDisplay < 768)
+ regp->MiscOutReg = 0xE3; /* -hsync -vsync */
+ else
+ regp->MiscOutReg = 0x23; /* +hsync +vsync */
+ }
+
+ regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
+
+ /*
+ * Time Sequencer
+ */
+ if (depth == 4)
+ regp->Sequencer[0] = 0x02;
+ else
+ regp->Sequencer[0] = 0x00;
+ if (mode->Flags & V_CLKDIV2)
+ regp->Sequencer[1] = 0x09;
+ else
+ regp->Sequencer[1] = 0x01;
+ if (depth == 1)
+ regp->Sequencer[2] = 1 << BIT_PLANE;
+ else
+ regp->Sequencer[2] = 0x0F;
+ regp->Sequencer[3] = 0x00; /* Font select */
+ if (depth < 8)
+ regp->Sequencer[4] = 0x06; /* Misc */
+ else
+ regp->Sequencer[4] = 0x0E; /* Misc */
+
+ /*
+ * CRTC Controller
+ */
+ regp->CRTC[0] = (mode->CrtcHTotal >> 3) - 5;
+ regp->CRTC[1] = (mode->CrtcHDisplay >> 3) - 1;
+ regp->CRTC[2] = (mode->CrtcHBlankStart >> 3) - 1;
+ regp->CRTC[3] = (((mode->CrtcHBlankEnd >> 3) - 1) & 0x1F) | 0x80;
+ i = (((mode->CrtcHSkew << 2) + 0x10) & ~0x1F);
+ if (i < 0x80)
+ regp->CRTC[3] |= i;
+ regp->CRTC[4] = (mode->CrtcHSyncStart >> 3);
+ regp->CRTC[5] = ((((mode->CrtcHBlankEnd >> 3) - 1) & 0x20) << 2)
+ | (((mode->CrtcHSyncEnd >> 3)) & 0x1F);
+ regp->CRTC[6] = (mode->CrtcVTotal - 2) & 0xFF;
+ regp->CRTC[7] = (((mode->CrtcVTotal - 2) & 0x100) >> 8)
+ | (((mode->CrtcVDisplay - 1) & 0x100) >> 7)
+ | ((mode->CrtcVSyncStart & 0x100) >> 6)
+ | (((mode->CrtcVBlankStart - 1) & 0x100) >> 5)
+ | 0x10
+ | (((mode->CrtcVTotal - 2) & 0x200) >> 4)
+ | (((mode->CrtcVDisplay - 1) & 0x200) >> 3)
+ | ((mode->CrtcVSyncStart & 0x200) >> 2);
+ regp->CRTC[8] = 0x00;
+ regp->CRTC[9] = (((mode->CrtcVBlankStart - 1) & 0x200) >> 4) | 0x40;
+ if (mode->Flags & V_DBLSCAN)
+ regp->CRTC[9] |= 0x80;
+ if (mode->VScan >= 32)
+ regp->CRTC[9] |= 0x1F;
+ else if (mode->VScan > 1)
+ regp->CRTC[9] |= mode->VScan - 1;
+ regp->CRTC[10] = 0x00;
+ regp->CRTC[11] = 0x00;
+ regp->CRTC[12] = 0x00;
+ regp->CRTC[13] = 0x00;
+ regp->CRTC[14] = 0x00;
+ regp->CRTC[15] = 0x00;
+ regp->CRTC[16] = mode->CrtcVSyncStart & 0xFF;
+ regp->CRTC[17] = (mode->CrtcVSyncEnd & 0x0F) | 0x20;
+ regp->CRTC[18] = (mode->CrtcVDisplay - 1) & 0xFF;
+ regp->CRTC[19] = mode->CrtcHDisplay >> 4; /* just a guess */
+ regp->CRTC[20] = 0x00;
+ regp->CRTC[21] = (mode->CrtcVBlankStart - 1) & 0xFF;
+ regp->CRTC[22] = (mode->CrtcVBlankEnd - 1) & 0xFF;
+ if (depth < 8)
+ regp->CRTC[23] = 0xE3;
+ else
+ regp->CRTC[23] = 0xC3;
+ regp->CRTC[24] = 0xFF;
+
+ /*
+ * Theory resumes here....
+ */
+
+ /*
+ * Graphics Display Controller
+ */
+ regp->Graphics[0] = 0x00;
+ regp->Graphics[1] = 0x00;
+ regp->Graphics[2] = 0x00;
+ regp->Graphics[3] = 0x00;
+ if (depth == 1) {
+ regp->Graphics[4] = BIT_PLANE;
+ regp->Graphics[5] = 0x00;
+ } else {
+ regp->Graphics[4] = 0x00;
+ if (depth == 4)
+ regp->Graphics[5] = 0x02;
+ else
+ regp->Graphics[5] = 0x40;
+ }
+ regp->Graphics[6] = 0x05; /* only map 64k VGA memory !!!! */
+ regp->Graphics[7] = 0x0F;
+ regp->Graphics[8] = 0xFF;
+
+ if (depth == 1) {
+ /* Initialise the Mono map according to which bit-plane gets used */
+
+ Bool flipPixels = xf86GetFlipPixels();
+
+ for (i=0; i<16; i++)
+ if (((i & (1 << BIT_PLANE)) != 0) != flipPixels)
+ regp->Attribute[i] = WHITE_VALUE;
+ else
+ regp->Attribute[i] = BLACK_VALUE;
+
+ } else {
+ regp->Attribute[0] = 0x00; /* standard colormap translation */
+ regp->Attribute[1] = 0x01;
+ regp->Attribute[2] = 0x02;
+ regp->Attribute[3] = 0x03;
+ regp->Attribute[4] = 0x04;
+ regp->Attribute[5] = 0x05;
+ regp->Attribute[6] = 0x06;
+ regp->Attribute[7] = 0x07;
+ regp->Attribute[8] = 0x08;
+ regp->Attribute[9] = 0x09;
+ regp->Attribute[10] = 0x0A;
+ regp->Attribute[11] = 0x0B;
+ regp->Attribute[12] = 0x0C;
+ regp->Attribute[13] = 0x0D;
+ regp->Attribute[14] = 0x0E;
+ regp->Attribute[15] = 0x0F;
+ if (depth == 4)
+ regp->Attribute[16] = 0x81; /* wrong for the ET4000 */
+ else
+ regp->Attribute[16] = 0x41; /* wrong for the ET4000 */
+ if (depth > 4)
+ regp->Attribute[17] = 0xff;
+ /* Attribute[17] (overscan) initialised in vgaHWGetHWRec() */
+ }
+ regp->Attribute[18] = 0x0F;
+ regp->Attribute[19] = 0x00;
+ regp->Attribute[20] = 0x00;
+
+}
+
+
+
+/**
+ * Sets up registers for the given mode/adjusted_mode pair.
+ *
+ * The clocks, CRTCs and outputs attached to this CRTC must be off.
+ *
+ * This shouldn't enable any clocks, CRTCs, or outputs, but they should
+ * be easily turned on/off after this.
+ */
+static void
+nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+ NVRegPtr state = &pNv->ModeReg;
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVFBLayout *pLayout = &pNv->CurrentLayout;
+ NVCrtcRegPtr regp, savep;
+ unsigned int i;
+ int horizDisplay = (mode->CrtcHDisplay/8) - 1;
+ int horizStart = (mode->CrtcHSyncStart/8) - 1;
+ int horizEnd = (mode->CrtcHSyncEnd/8) - 1;
+ int horizTotal = (mode->CrtcHTotal/8) - 5;
+ int horizBlankStart = (mode->CrtcHDisplay/8) - 1;
+ int horizBlankEnd = (mode->CrtcHTotal/8) - 1;
+ int vertDisplay = mode->CrtcVDisplay - 1;
+ int vertStart = mode->CrtcVSyncStart - 1;
+ int vertEnd = mode->CrtcVSyncEnd - 1;
+ int vertTotal = mode->CrtcVTotal - 2;
+ int vertBlankStart = mode->CrtcVDisplay - 1;
+ int vertBlankEnd = mode->CrtcVTotal - 1;
+ Bool is_fp = FALSE;
+
+ for (i = 0; i < xf86_config->num_output; i++) {
+ xf86OutputPtr output = xf86_config->output[i];
+ NVOutputPrivatePtr nv_output = output->driver_private;
+
+ if (output->crtc == crtc)
+ if ((nv_output->type == OUTPUT_PANEL) ||
+ (nv_output->type == OUTPUT_DIGITAL))
+ is_fp = TRUE;
+
+ }
+
+ regp = &pNv->ModeReg.crtc_reg[nv_crtc->crtc];
+ savep = &pNv->SavedReg.crtc_reg[nv_crtc->crtc];
+
+ if(mode->Flags & V_INTERLACE)
+ vertTotal |= 1;
+
+ regp->CRTC[NV_VGA_CRTCX_HTOTAL] = Set8Bits(horizTotal);
+ regp->CRTC[NV_VGA_CRTCX_HDISPE] = Set8Bits(horizDisplay);
+ regp->CRTC[NV_VGA_CRTCX_HBLANKS] = Set8Bits(horizBlankStart);
+ regp->CRTC[NV_VGA_CRTCX_HBLANKE] = SetBitField(horizBlankEnd,4:0,4:0)
+ | SetBit(7);
+ regp->CRTC[NV_VGA_CRTCX_HSYNCS] = Set8Bits(horizStart);
+ regp->CRTC[NV_VGA_CRTCX_HSYNCE] = SetBitField(horizBlankEnd,5:5,7:7)
+ | SetBitField(horizEnd,4:0,4:0);
+ regp->CRTC[NV_VGA_CRTCX_VTOTAL] = SetBitField(vertTotal,7:0,7:0);
+ regp->CRTC[NV_VGA_CRTCX_OVERFLOW] = SetBitField(vertTotal,8:8,0:0)
+ | SetBitField(vertDisplay,8:8,1:1)
+ | SetBitField(vertStart,8:8,2:2)
+ | SetBitField(vertBlankStart,8:8,3:3)
+ | SetBit(4)
+ | SetBitField(vertTotal,9:9,5:5)
+ | SetBitField(vertDisplay,9:9,6:6)
+ | SetBitField(vertStart,9:9,7:7);
+ regp->CRTC[NV_VGA_CRTCX_MAXSCLIN] = SetBitField(vertBlankStart,9:9,5:5)
+ | SetBit(6)
+ | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
+ regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
+ regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
+ regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
+ regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pLayout->displayWidth/8)*(pLayout->bitsPerPixel/8));
+ regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
+ regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
+
+ regp->Attribute[0x10] = 0x01;
+
+ if(pNv->Television)
+ regp->Attribute[0x11] = 0x00;
+
+ regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
+ | SetBitField(vertBlankStart,10:10,3:3)
+ | SetBitField(vertStart,10:10,2:2)
+ | SetBitField(vertDisplay,10:10,1:1)
+ | SetBitField(vertTotal,10:10,0:0);
+
+ regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
+ | SetBitField(horizDisplay,8:8,1:1)
+ | SetBitField(horizBlankStart,8:8,2:2)
+ | SetBitField(horizStart,8:8,3:3);
+
+ regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
+ | SetBitField(vertDisplay,11:11,2:2)
+ | SetBitField(vertStart,11:11,4:4)
+ | SetBitField(vertBlankStart,11:11,6:6);
+
+ if(mode->Flags & V_INTERLACE) {
+ horizTotal = (horizTotal >> 1) & ~1;
+ regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
+ regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
+ } else {
+ regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff; /* interlace off */
+ }
+
+ regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
+
+ if (is_fp) {
+ regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD] | 1;
+ /* this turns on the DFP on nv28 outputs */
+ regp->CRTC[NV_VGA_CRTCX_59] = savep->CRTC[NV_VGA_CRTCX_59] | 1;
+ } else {
+ regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD] & ~1;
+ }
+
+ /*
+ * Initialize DAC palette.
+ */
+ if(pLayout->bitsPerPixel != 8 )
+ {
+ for (i = 0; i < 256; i++)
+ {
+ regp->DAC[i*3] = i;
+ regp->DAC[(i*3)+1] = i;
+ regp->DAC[(i*3)+2] = i;
+ }
+ }
+
+ /*
+ * Calculate the extended registers.
+ */
+
+ if(pLayout->depth < 24)
+ i = pLayout->depth;
+ else i = 32;
+
+ if(pNv->Architecture >= NV_ARCH_10)
+ pNv->CURSOR = (CARD32 *)pNv->Cursor->map;
+
+ ErrorF("crtc %d %d %d\n", nv_crtc->crtc, mode->CrtcHDisplay, pLayout->displayWidth);
+ nv_crtc_calc_state_ext(crtc,
+ i,
+ pLayout->displayWidth,
+ mode->CrtcHDisplay,
+ mode->CrtcVDisplay,
+ mode->Clock,
+ mode->Flags);
+
+ if (is_fp)
+ regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
+
+ regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
+
+ if(nv_crtc->crtc) {
+ if (is_fp) {
+ regp->head &= ~NV_CRTC_FSEL_FPP2;
+ regp->head |= NV_CRTC_FSEL_FPP1;
+ } else {
+ regp->head &= ~NV_CRTC_FSEL_FPP1;
+ regp->head |= NV_CRTC_FSEL_FPP2;
+ }
+
+ regp->crtcOwner = 3;
+ /* only enable secondary pllsel if CRTC 1 is selected on */
+
+ } else {
+ if(pNv->twoHeads) {
+ regp->head = savep->head | 0x00001000;
+ if (is_fp) {
+ regp->head &= ~NV_CRTC_FSEL_FPP2;
+ regp->head |= NV_CRTC_FSEL_FPP1;
+ } else {
+ regp->head &= ~NV_CRTC_FSEL_FPP1;
+ regp->head |= NV_CRTC_FSEL_FPP2;
+ }
+
+ regp->crtcOwner = 0;
+ }
+ }
+
+ regp->cursorConfig = 0x00000100;
+ if(mode->Flags & V_DBLSCAN)
+ regp->cursorConfig |= (1 << 4);
+ if(pNv->alphaCursor) {
+ if((pNv->Chipset & 0x0ff0) != CHIPSET_NV11)
+ regp->cursorConfig |= 0x04011000;
+ else
+ regp->cursorConfig |= 0x14011000;
+ } else
+ regp->cursorConfig |= 0x02000000;
+
+ regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
+ regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
+
+ regp->unk830 = mode->CrtcVDisplay - 3;
+ regp->unk834 = mode->CrtcVDisplay - 1;
+}
+
+/**
+ * Sets up registers for the given mode/adjusted_mode pair.
+ *
+ * The clocks, CRTCs and outputs attached to this CRTC must be off.
+ *
+ * This shouldn't enable any clocks, CRTCs, or outputs, but they should
+ * be easily turned on/off after this.
+ */
+static void
+nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
+ DisplayModePtr adjusted_mode,
+ int x, int y)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->crtc);
+ xf86PrintModeline(pScrn->scrnIndex, mode);
+ NVCrtcSetOwner(crtc);
+
+ nv_crtc_mode_set_vga(crtc, mode);
+ nv_crtc_mode_set_regs(crtc, mode);
+
+
+ NVVgaProtect(crtc, TRUE);
+ nv_crtc_load_state_ext(crtc, &pNv->ModeReg);
+ nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
+ nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
+
+ NVVgaProtect(crtc, FALSE);
+ // NVCrtcLockUnlock(crtc, 1);
+
+ NVCrtcSetBase(crtc, x, y);
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ /* turn on LFB swapping */
+ {
+ unsigned char tmp;
+
+ tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
+ tmp |= (1 << 7);
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
+ }
+#endif
+
+}
+
+void nv_crtc_save(xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+
+ NVCrtcSetOwner(crtc);
+ nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
+ nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
+ nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
+
+}
+
+void nv_crtc_restore(xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+
+ NVCrtcSetOwner(crtc);
+ nv_crtc_load_state_ext(crtc, &pNv->SavedReg);
+ nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
+ nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
+ nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
+
+}
+
+void nv_crtc_prepare(xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+ /* Sync the engine before adjust mode */
+if (pNv->AccelInfoRec && pNv->AccelInfoRec->NeedToSync) {
+ (*pNv->AccelInfoRec->Sync)(pScrn);
+ pNv->AccelInfoRec->NeedToSync = FALSE;
+}
+
+}
+
+void nv_crtc_commit(xf86CrtcPtr crtc)
+{
+
+
+}
+
+static Bool nv_crtc_lock(xf86CrtcPtr crtc)
+{
+ return FALSE;
+}
+
+static void nv_crtc_unlock(xf86CrtcPtr crtc)
+{
+
+}
+
+static const xf86CrtcFuncsRec nv_crtc_funcs = {
+ .dpms = nv_crtc_dpms,
+ .save = nv_crtc_save, /* XXX */
+ .restore = nv_crtc_restore, /* XXX */
+ .mode_fixup = nv_crtc_mode_fixup,
+ .mode_set = nv_crtc_mode_set,
+ .prepare = nv_crtc_prepare,
+ .commit = nv_crtc_commit,
+ .destroy = NULL, /* XXX */
+ .lock = nv_crtc_lock,
+ .unlock = nv_crtc_unlock,
+};
+
+void
+nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
+{
+ NVPtr pNv = NVPTR(pScrn);
+ xf86CrtcPtr crtc;
+ NVCrtcPrivatePtr nv_crtc;
+
+ crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
+ if (crtc == NULL)
+ return;
+
+ nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
+ nv_crtc->crtc = crtc_num;
+
+ crtc->driver_private = nv_crtc;
+
+ NVCrtcLockUnlock(crtc, 0);
+
+}
+
+static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ int i, j;
+ CARD32 temp;
+ NVCrtcRegPtr regp;
+
+ regp = &state->crtc_reg[nv_crtc->crtc];
+
+ NVWriteMiscOut(crtc, regp->MiscOutReg);
+
+ for (i = 1; i < 5; i++)
+ NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
+
+ /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
+ NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
+
+ for (i = 0; i < 25; i++)
+ NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
+
+ for (i = 0; i < 9; i++)
+ NVWriteVgaGr(crtc, i, regp->Graphics[i]);
+
+ NVEnablePalette(crtc);
+ for (i = 0; i < 21; i++)
+ NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
+ NVDisablePalette(crtc);
+
+}
+
+static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
+{
+ /* TODO - implement this properly */
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+
+ if(pNv->Architecture == NV_ARCH_40) { /* HW bug */
+ volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
+ nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
+ }
+
+}
+static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ int i, j;
+ CARD32 temp;
+ NVCrtcRegPtr regp;
+
+ regp = &state->crtc_reg[nv_crtc->crtc];
+
+ if (!pNv->IRQ)
+ nvWriteMC(pNv, 0x140, 0);
+
+ if(pNv->Architecture >= NV_ARCH_10) {
+ if(pNv->twoHeads) {
+ nvWriteCRTC(pNv, nv_crtc->crtc, NV_CRTC_FSEL, regp->head);
+ }
+ nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
+ nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
+ nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
+ nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
+ nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
+ nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
+ nvWriteMC(pNv, 0x1588, 0);
+
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, 0xff);
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
+ nvWriteCRTC(pNv, nv_crtc->crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
+ nvWriteCRTC(pNv, nv_crtc->crtc, NV_CRTC_0830, regp->unk830);
+ nvWriteCRTC(pNv, nv_crtc->crtc, NV_CRTC_0834, regp->unk834);
+
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
+
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
+ }
+
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
+ if(pNv->Architecture >= NV_ARCH_30) {
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
+ }
+
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
+ nv_crtc_fix_nv40_hw_cursor(crtc);
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
+
+ nvWriteCRTC(pNv, nv_crtc->crtc, NV_CRTC_INTR_EN_0, 0);
+ nvWriteCRTC(pNv, nv_crtc->crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
+
+ pNv->CurrentState = state;
+}
+
+static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ int i;
+ NVCrtcRegPtr regp;
+
+ regp = &state->crtc_reg[nv_crtc->crtc];
+
+ regp->MiscOutReg = NVReadMiscOut(crtc);
+
+ for (i = 0; i < 25; i++)
+ regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
+
+ NVEnablePalette(crtc);
+ for (i = 0; i < 21; i++)
+ regp->Attribute[i] = NVReadVgaAttr(crtc, i);
+ NVDisablePalette(crtc);
+
+ for (i = 0; i < 9; i++)
+ regp->Graphics[i] = NVReadVgaGr(crtc, i);
+
+ for (i = 1; i < 5; i++)
+ regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
+
+}
+
+static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVCrtcRegPtr regp;
+ int i;
+
+ regp = &state->crtc_reg[nv_crtc->crtc];
+
+ regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
+ regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
+ regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
+ regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
+ regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
+ regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
+ regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
+ regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
+
+ regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
+ regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
+ if(pNv->Architecture >= NV_ARCH_30) {
+ regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
+ }
+ regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
+ regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
+ regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
+ regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
+
+ regp->unk830 = nvReadCRTC(pNv, nv_crtc->crtc, NV_CRTC_0830);
+ regp->unk834 = nvReadCRTC(pNv, nv_crtc->crtc, NV_CRTC_0834);
+
+ if(pNv->Architecture >= NV_ARCH_10) {
+ if(pNv->twoHeads) {
+ regp->head = nvReadCRTC(pNv, nv_crtc->crtc, NV_CRTC_FSEL);
+ regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
+ }
+ regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
+
+ regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->crtc, NV_CRTC_CURSOR_CONFIG);
+
+ regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
+ regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
+ regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
+ }
+}
+
+void
+NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVFBLayout *pLayout = &pNv->CurrentLayout;
+ CARD32 start = 0;
+
+ start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
+ start += pNv->FB->offset;
+
+ nvWriteCRTC(pNv, nv_crtc->crtc, NV_CRTC_START, start);
+
+ crtc->x = x;
+ crtc->y = y;
+}
+
+void NVCrtcSetCursor(xf86CrtcPtr crtc, Bool state)
+{
+ int current = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
+
+ if(state)
+ current |= 1;
+ else
+ current &= ~1;
+
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, current);
+}
+
+static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+ volatile CARD8 *pDACReg = nv_crtc->crtc ? pNv->PDIO1 : pNv->PDIO0;
+
+ NV_WR08(pDACReg, VGA_DAC_MASK, value);
+}
+
+static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+ volatile CARD8 *pDACReg = nv_crtc->crtc ? pNv->PDIO1 : pNv->PDIO0;
+
+ return NV_RD08(pDACReg, VGA_DAC_MASK);
+}
+
+static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+ volatile CARD8 *pDACReg = nv_crtc->crtc ? pNv->PDIO1 : pNv->PDIO0;
+
+ NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
+}
+
+static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+ volatile CARD8 *pDACReg = nv_crtc->crtc ? pNv->PDIO1 : pNv->PDIO0;
+
+ NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
+}
+
+static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+ volatile CARD8 *pDACReg = nv_crtc->crtc ? pNv->PDIO1 : pNv->PDIO0;
+
+ NV_WR08(pDACReg, VGA_DAC_DATA, value);
+}
+
+static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVPtr pNv = NVPTR(pScrn);
+ volatile CARD8 *pDACReg = nv_crtc->crtc ? pNv->PDIO1 : pNv->PDIO0;
+
+ return NV_RD08(pDACReg, VGA_DAC_DATA);
+}
+
+void NVCrtcLoadPalette(xf86CrtcPtr crtc)
+{
+ int i;
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVCrtcRegPtr regp;
+ ScrnInfoPtr pScrn = crtc->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+
+ regp = &pNv->ModeReg.crtc_reg[nv_crtc->crtc];
+
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_OWNER, nv_crtc->crtc * 0x3);
+ NVCrtcWriteDacMask(crtc, 0xff);
+ NVCrtcWriteDacWriteAddr(crtc, 0x00);
+
+ for (i = 0; i<768; i++) {
+ NVCrtcWriteDacData(crtc, regp->DAC[i]);
+ }
+ NVDisablePalette(crtc);
+}
+
+void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
+{
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ unsigned char scrn;
+
+ NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_OWNER, nv_crtc->crtc * 0x3);
+
+ scrn = NVReadVgaSeq(crtc, 0x01);
+ if (on) {
+ scrn &= ~0x20;
+ } else {
+ scrn |= 0x20;
+ }
+
+ NVVgaSeqReset(crtc, TRUE);
+ NVWriteVgaSeq(crtc, 0x01, scrn);
+ NVVgaSeqReset(crtc, FALSE);
+}
+
+/*************************************************************************** \
+|* *|
+|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
+|* *|
+|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
+|* international laws. Users and possessors of this source code are *|
+|* hereby granted a nonexclusive, royalty-free copyright license to *|
+|* use this code in individual and commercial software. *|
+|* *|
+|* Any use of this source code must include, in the user documenta- *|
+|* tion and internal comments to the code, notices to the end user *|
+|* as follows: *|
+|* *|
+|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
+|* *|
+|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
+|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
+|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
+|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
+|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
+|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
+|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
+|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
+|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
+|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
+|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
+|* *|
+|* U.S. Government End Users. This source code is a "commercial *|
+|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
+|* consisting of "commercial computer software" and "commercial *|
+|* computer software documentation," as such terms are used in *|
+|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
+|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
+|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
+|* all U.S. Government End Users acquire the source code with only *|
+|* those rights set forth herein. *|
+|* *|
+ \***************************************************************************/
diff --git a/src/nv_cursor.c b/src/nv_cursor.c
index 88f1874..4be0b4e 100644
--- a/src/nv_cursor.c
+++ b/src/nv_cursor.c
@@ -49,6 +49,13 @@
* *
\****************************************************************************/
+#define NV_CURSOR_X 64
+#define NV_CURSOR_Y 64
+
+#define CURSOR_X_SHIFT 0
+#define CURSOR_Y_SHIFT 16
+#define CURSOR_POS_MASK 0xffff
+
#define TRANSPARENT_PIXEL 0
#define ConvertToRGB555(c) (((c & 0xf80000) >> 9 ) | /* Blue */ \
@@ -166,12 +173,55 @@ NVLoadCursorImage( ScrnInfoPtr pScrn, unsigned char *src )
TransformCursor(pNv);
}
+
static void
NVSetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
{
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
NVPtr pNv = NVPTR(pScrn);
-
- nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, (x & 0xFFFF) | (y << 16));
+ xf86CrtcPtr crtc;
+ NVCrtcPrivatePtr nv_crtc;
+ DisplayModePtr mode;
+ int thisx;
+ int thisy;
+ int o;
+ Bool inrange;
+ CARD32 temp;
+
+ for (o = 0; o < xf86_config->num_output; o++)
+ {
+ xf86OutputPtr output = xf86_config->output[o];
+
+ if (!output->crtc)
+ continue;
+
+ if (!output->crtc->enabled)
+ continue;
+
+ crtc = output->crtc;
+ mode = &crtc->mode;
+ thisx = x - crtc->x;
+ thisy = y - crtc->y;
+
+ inrange = TRUE;
+ if (thisx >= mode->HDisplay ||
+ thisy >= mode->VDisplay ||
+ thisx <= -NV_CURSOR_X || thisy <= -NV_CURSOR_Y)
+ {
+ inrange = FALSE;
+ thisx = 0;
+ thisy = 0;
+ }
+
+ temp = 0;
+ temp |= ((thisx & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
+ temp |= ((thisy & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
+
+ nv_crtc = output->crtc->driver_private;
+
+ nvWriteRAMDAC(pNv, nv_crtc->crtc, NV_RAMDAC_CURSOR_POS, temp);
+
+ }
}
static void
@@ -209,20 +259,28 @@ NVSetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
}
-static void
+static void
NVShowCursor(ScrnInfoPtr pScrn)
{
- NVPtr pNv = NVPTR(pScrn);
- /* Enable cursor - X-Windows mode */
- NVShowHideCursor(pNv, 1);
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ NVPtr pNv = NVPTR(pScrn);
+ int c;
+
+ pNv->cursorOn = TRUE;
+ for (c= 0; c < xf86_config->num_crtc; c++)
+ NVCrtcSetCursor (xf86_config->crtc[c], TRUE);
}
static void
NVHideCursor(ScrnInfoPtr pScrn)
{
- NVPtr pNv = NVPTR(pScrn);
- /* Disable cursor */
- NVShowHideCursor(pNv, 0);
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ NVPtr pNv = NVPTR(pScrn);
+ int c;
+
+ pNv->cursorOn = FALSE;
+ for (c = 0; c < xf86_config->num_crtc; c++)
+ NVCrtcSetCursor (xf86_config->crtc[c], TRUE);
}
static Bool
diff --git a/src/nv_dac.c b/src/nv_dac.c
deleted file mode 100644
index f6cbd28..0000000
--- a/src/nv_dac.c
+++ /dev/null
@@ -1,425 +0,0 @@
- /***************************************************************************\
-|* *|
-|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
-|* *|
-|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
-|* international laws. Users and possessors of this source code are *|
-|* hereby granted a nonexclusive, royalty-free copyright license to *|
-|* use this code in individual and commercial software. *|
-|* *|
-|* Any use of this source code must include, in the user documenta- *|
-|* tion and internal comments to the code, notices to the end user *|
-|* as follows: *|
-|* *|
-|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
-|* *|
-|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
-|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
-|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
-|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
-|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
-|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
-|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
-|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
-|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
-|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
-|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
-|* *|
-|* U.S. Government End Users. This source code is a "commercial *|
-|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
-|* consisting of "commercial computer software" and "commercial *|
-|* computer software documentation," as such terms are used in *|
-|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
-|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
-|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
-|* all U.S. Government End Users acquire the source code with only *|
-|* those rights set forth herein. *|
-|* *|
- \***************************************************************************/
-
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_dac.c,v 1.45 2005/07/09 00:53:00 mvojkovi Exp $ */
-
-#include "nv_include.h"
-
-static int
-NVDACPanelTweaks(NVPtr pNv, NVRegPtr state)
-{
- int tweak = 0;
-
- if(pNv->usePanelTweak) {
- tweak = pNv->PanelTweak;
- } else {
- /* begin flat panel hacks */
- /* This is unfortunate, but some chips need this register
- tweaked or else you get artifacts where adjacent pixels are
- swapped. There are no hard rules for what to set here so all
- we can do is experiment and apply hacks. */
-
- if(((pNv->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
- /* At least one NV34 laptop needs this workaround. */
- tweak = -1;
- }
-
- if((pNv->Chipset & 0xfff0) == CHIPSET_NV31) {
- tweak = 1;
- }
- /* end flat panel hacks */
- }
-
- return tweak;
-}
-
-Bool
-NVDACInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
-{
- int i;
- int horizDisplay = (mode->CrtcHDisplay/8) - 1;
- int horizStart = (mode->CrtcHSyncStart/8) - 1;
- int horizEnd = (mode->CrtcHSyncEnd/8) - 1;
- int horizTotal = (mode->CrtcHTotal/8) - 5;
- int horizBlankStart = (mode->CrtcHDisplay/8) - 1;
- int horizBlankEnd = (mode->CrtcHTotal/8) - 1;
- int vertDisplay = mode->CrtcVDisplay - 1;
- int vertStart = mode->CrtcVSyncStart - 1;
- int vertEnd = mode->CrtcVSyncEnd - 1;
- int vertTotal = mode->CrtcVTotal - 2;
- int vertBlankStart = mode->CrtcVDisplay - 1;
- int vertBlankEnd = mode->CrtcVTotal - 1;
-
- NVPtr pNv = NVPTR(pScrn);
- NVRegPtr nvReg = &pNv->ModeReg;
- NVFBLayout *pLayout = &pNv->CurrentLayout;
- vgaRegPtr pVga;
-
- /*
- * Initialize all of the generic VGA registers. Don't bother with
- * VGA_FIX_SYNC_PULSES, given the relevant CRTC settings are overridden
- * below. Ditto for the KGA workaround.
- */
- if (!vgaHWInit(pScrn, mode))
- return(FALSE);
-
- pVga = &VGAHWPTR(pScrn)->ModeReg;
-
- /*
- * Set all CRTC values.
- */
-
- if(mode->Flags & V_INTERLACE)
- vertTotal |= 1;
-
- if(pNv->FlatPanel == 1) {
- vertStart = vertTotal - 3;
- vertEnd = vertTotal - 2;
- vertBlankStart = vertStart;
- horizStart = horizTotal - 5;
- horizEnd = horizTotal - 2;
- horizBlankEnd = horizTotal + 4;
- }
-
- pVga->CRTC[0x0] = Set8Bits(horizTotal);
- pVga->CRTC[0x1] = Set8Bits(horizDisplay);
- pVga->CRTC[0x2] = Set8Bits(horizBlankStart);
- pVga->CRTC[0x3] = SetBitField(horizBlankEnd,4:0,4:0)
- | SetBit(7);
- pVga->CRTC[0x4] = Set8Bits(horizStart);
- pVga->CRTC[0x5] = SetBitField(horizBlankEnd,5:5,7:7)
- | SetBitField(horizEnd,4:0,4:0);
- pVga->CRTC[0x6] = SetBitField(vertTotal,7:0,7:0);
- pVga->CRTC[0x7] = SetBitField(vertTotal,8:8,0:0)
- | SetBitField(vertDisplay,8:8,1:1)
- | SetBitField(vertStart,8:8,2:2)
- | SetBitField(vertBlankStart,8:8,3:3)
- | SetBit(4)
- | SetBitField(vertTotal,9:9,5:5)
- | SetBitField(vertDisplay,9:9,6:6)
- | SetBitField(vertStart,9:9,7:7);
- pVga->CRTC[0x9] = SetBitField(vertBlankStart,9:9,5:5)
- | SetBit(6)
- | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
- pVga->CRTC[0x10] = Set8Bits(vertStart);
- pVga->CRTC[0x11] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
- pVga->CRTC[0x12] = Set8Bits(vertDisplay);
- pVga->CRTC[0x13] = ((pLayout->displayWidth/8)*(pLayout->bitsPerPixel/8));
- pVga->CRTC[0x15] = Set8Bits(vertBlankStart);
- pVga->CRTC[0x16] = Set8Bits(vertBlankEnd);
-
- pVga->Attribute[0x10] = 0x01;
-
- if(pNv->Television)
- pVga->Attribute[0x11] = 0x00;
-
- nvReg->screen = SetBitField(horizBlankEnd,6:6,4:4)
- | SetBitField(vertBlankStart,10:10,3:3)
- | SetBitField(vertStart,10:10,2:2)
- | SetBitField(vertDisplay,10:10,1:1)
- | SetBitField(vertTotal,10:10,0:0);
-
- nvReg->horiz = SetBitField(horizTotal,8:8,0:0)
- | SetBitField(horizDisplay,8:8,1:1)
- | SetBitField(horizBlankStart,8:8,2:2)
- | SetBitField(horizStart,8:8,3:3);
-
- nvReg->extra = SetBitField(vertTotal,11:11,0:0)
- | SetBitField(vertDisplay,11:11,2:2)
- | SetBitField(vertStart,11:11,4:4)
- | SetBitField(vertBlankStart,11:11,6:6);
-
- if(mode->Flags & V_INTERLACE) {
- horizTotal = (horizTotal >> 1) & ~1;
- nvReg->interlace = Set8Bits(horizTotal);
- nvReg->horiz |= SetBitField(horizTotal,8:8,4:4);
- } else {
- nvReg->interlace = 0xff; /* interlace off */
- }
-
-
- /*
- * Initialize DAC palette.
- */
- if(pLayout->bitsPerPixel != 8 )
- {
- for (i = 0; i < 256; i++)
- {
- pVga->DAC[i*3] = i;
- pVga->DAC[(i*3)+1] = i;
- pVga->DAC[(i*3)+2] = i;
- }
- }
-
- /*
- * Calculate the extended registers.
- */
-
- if(pLayout->depth < 24)
- i = pLayout->depth;
- else i = 32;
-
- if(pNv->Architecture >= NV_ARCH_10)
- pNv->CURSOR = (CARD32 *)pNv->Cursor->map;
-
- NVCalcStateExt(pNv,
- nvReg,
- i,
- pLayout->displayWidth,
- mode->CrtcHDisplay,
- pScrn->virtualY,
- mode->Clock,
- mode->Flags);
-
- nvReg->scale = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_CONTROL) & 0xfff000ff;
- if(pNv->FlatPanel == 1) {
- nvReg->pixel |= (1 << 7);
- if(!pNv->fpScaler || (pNv->fpWidth <= mode->HDisplay)
- || (pNv->fpHeight <= mode->VDisplay))
- {
- nvReg->scale |= (1 << 8) ;
- }
- nvReg->crtcSync = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_HCRTC);
- nvReg->crtcSync += NVDACPanelTweaks(pNv, nvReg);
- }
-
- nvReg->vpll = nvReg->pll;
- nvReg->vpll2 = nvReg->pll;
- nvReg->vpllB = nvReg->pllB;
- nvReg->vpll2B = nvReg->pllB;
-
- nvReg->fifo = nvReadVGA(pNv, 0x1c) & ~(1<<5);
-
- if(pNv->CRTCnumber) {
- nvReg->head = nvReadCRTC(pNv, 0, NV_CRTC_HEAD_CONFIG) & ~0x00001000;
- nvReg->head2 = nvReadCRTC(pNv, 1, NV_CRTC_HEAD_CONFIG) | 0x00001000;
- nvReg->crtcOwner = 3;
- nvReg->pllsel |= 0x20000800;
- nvReg->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
- if(pNv->twoStagePLL)
- nvReg->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
- } else
- if(pNv->twoHeads) {
- nvReg->head = nvReadCRTC(pNv, 0, NV_CRTC_HEAD_CONFIG) | 0x00001000;
- nvReg->head2 = nvReadCRTC(pNv, 1, NV_CRTC_HEAD_CONFIG) & ~0x00001000;
- nvReg->crtcOwner = 0;
- nvReg->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
- if(pNv->twoStagePLL)
- nvReg->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
- }
-
- nvReg->cursorConfig = 0x00000100;
- if(mode->Flags & V_DBLSCAN)
- nvReg->cursorConfig |= (1 << 4);
- if(pNv->alphaCursor) {
- if((pNv->Chipset & 0x0ff0) != CHIPSET_NV11)
- nvReg->cursorConfig |= 0x04011000;
- else
- nvReg->cursorConfig |= 0x14011000;
- nvReg->general |= (1 << 29);
- } else
- nvReg->cursorConfig |= 0x02000000;
-
- if(pNv->twoHeads) {
- if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
- nvReg->dither = nvReadCurRAMDAC(pNv, NV_RAMDAC_DITHER_NV11) & ~0x00010000;
- if(pNv->FPDither)
- nvReg->dither |= 0x00010000;
- } else {
- nvReg->dither = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_DITHER) & ~1;
- if(pNv->FPDither)
- nvReg->dither |= 1;
- }
- }
-
- nvReg->timingH = 0;
- nvReg->timingV = 0;
- nvReg->displayV = mode->CrtcVDisplay;
-
- return (TRUE);
-}
-
-void
-NVDACRestore(ScrnInfoPtr pScrn, vgaRegPtr vgaReg, NVRegPtr nvReg,
- Bool primary)
-{
- NVPtr pNv = NVPTR(pScrn);
- int restore = VGA_SR_MODE;
-
- if(primary) restore |= VGA_SR_CMAP | VGA_SR_FONTS;
- NVLoadStateExt(pScrn, nvReg);
-#if defined(__powerpc__)
- restore &= ~VGA_SR_FONTS;
-#endif
- vgaHWRestore(pScrn, vgaReg, restore);
-}
-
-/*
- * NVDACSave
- *
- * This function saves the video state.
- */
-void
-NVDACSave(ScrnInfoPtr pScrn, vgaRegPtr vgaReg, NVRegPtr nvReg,
- Bool saveFonts)
-{
- NVPtr pNv = NVPTR(pScrn);
-
-#if defined(__powerpc__)
- saveFonts = FALSE;
-#endif
-
- vgaHWSave(pScrn, vgaReg, VGA_SR_CMAP | VGA_SR_MODE |
- (saveFonts? VGA_SR_FONTS : 0));
- NVUnloadStateExt(pNv, nvReg);
-
- /* can't read this reliably on NV11 */
- if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11)
- nvReg->crtcOwner = pNv->CRTCnumber;
-}
-
-#define DEPTH_SHIFT(val, w) ((val << (8 - w)) | (val >> ((w << 1) - 8)))
-#define MAKE_INDEX(in, w) (DEPTH_SHIFT(in, w) * 3)
-
-void
-NVDACLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices, LOCO *colors,
- VisualPtr pVisual )
-{
- int i, index;
- NVPtr pNv = NVPTR(pScrn);
- vgaRegPtr pVga;
-
- pVga = &VGAHWPTR(pScrn)->ModeReg;
-
- switch(pNv->CurrentLayout.depth) {
- case 15:
- for(i = 0; i < numColors; i++) {
- index = indices[i];
- pVga->DAC[MAKE_INDEX(index, 5) + 0] = colors[index].red;
- pVga->DAC[MAKE_INDEX(index, 5) + 1] = colors[index].green;
- pVga->DAC[MAKE_INDEX(index, 5) + 2] = colors[index].blue;
- }
- break;
- case 16:
- for(i = 0; i < numColors; i++) {
- index = indices[i];
- pVga->DAC[MAKE_INDEX(index, 6) + 1] = colors[index].green;
- if(index < 32) {
- pVga->DAC[MAKE_INDEX(index, 5) + 0] = colors[index].red;
- pVga->DAC[MAKE_INDEX(index, 5) + 2] = colors[index].blue;
- }
- }
- break;
- default:
- for(i = 0; i < numColors; i++) {
- index = indices[i];
- pVga->DAC[index*3] = colors[index].red;
- pVga->DAC[(index*3)+1] = colors[index].green;
- pVga->DAC[(index*3)+2] = colors[index].blue;
- }
- break;
- }
- vgaHWRestore(pScrn, pVga, VGA_SR_CMAP);
-}
-
-/*
- * DDC1 support only requires DDC_SDA_MASK,
- * DDC2 support requires DDC_SDA_MASK and DDC_SCL_MASK
- */
-#define DDC_SDA_READ_MASK (1 << 3)
-#define DDC_SCL_READ_MASK (1 << 2)
-#define DDC_SDA_WRITE_MASK (1 << 4)
-#define DDC_SCL_WRITE_MASK (1 << 5)
-
-static void
-NV_I2CGetBits(I2CBusPtr b, int *clock, int *data)
-{
- NVPtr pNv = NVPTR(xf86Screens[b->scrnIndex]);
- unsigned char val;
-
- /* Get the result. */
- val = nvReadVGA(pNv, pNv->DDCBase);
-
- *clock = (val & DDC_SCL_READ_MASK) != 0;
- *data = (val & DDC_SDA_READ_MASK) != 0;
-}
-
-static void
-NV_I2CPutBits(I2CBusPtr b, int clock, int data)
-{
- NVPtr pNv = NVPTR(xf86Screens[b->scrnIndex]);
- unsigned char val;
-
- val = nvReadVGA(pNv, pNv->DDCBase + 1) & 0xf0;
- if (clock)
- val |= DDC_SCL_WRITE_MASK;
- else
- val &= ~DDC_SCL_WRITE_MASK;
-
- if (data)
- val |= DDC_SDA_WRITE_MASK;
- else
- val &= ~DDC_SDA_WRITE_MASK;
-
- nvWriteVGA(pNv, pNv->DDCBase + 1, val | 0x1);
-}
-
-Bool
-NVDACi2cInit(ScrnInfoPtr pScrn)
-{
- NVPtr pNv = NVPTR(pScrn);
- I2CBusPtr I2CPtr;
-
- I2CPtr = xf86CreateI2CBusRec();
- if(!I2CPtr) return FALSE;
-
- pNv->I2C = I2CPtr;
-
- I2CPtr->BusName = "DDC";
- I2CPtr->scrnIndex = pScrn->scrnIndex;
- I2CPtr->I2CPutBits = NV_I2CPutBits;
- I2CPtr->I2CGetBits = NV_I2CGetBits;
- I2CPtr->AcknTimeout = 5;
-
- if (!xf86I2CBusInit(I2CPtr)) {
- return FALSE;
- }
- return TRUE;
-}
-
diff --git a/src/nv_driver.c b/src/nv_driver.c
index f437bee..ef9efc6 100644
--- a/src/nv_driver.c
+++ b/src/nv_driver.c
@@ -542,7 +542,6 @@ NVFreeRec(ScrnInfoPtr pScrn)
pScrn->driverPrivate = NULL;
}
-
static pointer
nouveauSetup(pointer module, pointer opts, int *errmaj, int *errmin)
{
@@ -815,7 +814,20 @@ NVProbe(DriverPtr drv, int flags)
Bool
NVSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
{
- return NVModeInit(xf86Screens[scrnIndex], mode);
+ ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
+ NVPtr pNv = NVPTR(pScrn);
+ Bool ret = TRUE;
+
+ NVFBLayout *pLayout = &pNv->CurrentLayout;
+
+ if (pLayout->mode != mode) {
+ if (!NVSetMode(pScrn, mode, RR_Rotate_0))
+ ret = FALSE;
+ }
+
+ pLayout->mode = mode;
+
+ return ret;
}
/*
@@ -827,13 +839,38 @@ void
NVAdjustFrame(int scrnIndex, int x, int y, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
+ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
int startAddr;
NVPtr pNv = NVPTR(pScrn);
NVFBLayout *pLayout = &pNv->CurrentLayout;
+ xf86CrtcPtr crtc = config->output[config->compat_output]->crtc;
+
+ if (crtc && crtc->enabled) {
+ NVCrtcSetBase(crtc, x, y);
+ }
+}
+
+void
+NVResetCrtcConfig(ScrnInfoPtr pScrn, int set)
+{
+ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
+ NVPtr pNv = NVPTR(pScrn);
+ int i;
+ CARD32 val = 0;
+
+ for (i = 0; i < config->num_crtc; i++) {
+ xf86CrtcPtr crtc = config->crtc[i];
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+
+ if (set) {
+ NVCrtcRegPtr regp;
- startAddr = (((y*pLayout->displayWidth)+x)*(pLayout->bitsPerPixel/8));
- startAddr += pNv->FB->offset;
- NVSetStartAddress(pNv, startAddr);
+ regp = &pNv->ModeReg.crtc_reg[nv_crtc->crtc];
+ val = regp->head;
+ }
+
+ nvWriteCRTC(pNv, nv_crtc->crtc, NV_CRTC_FSEL, val);
+ }
}
@@ -849,12 +886,24 @@ static Bool
NVEnterVT(int scrnIndex, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
NVPtr pNv = NVPTR(pScrn);
+ int i;
- if (!NVModeInit(pScrn, pScrn->currentMode))
- return FALSE;
- NVAdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
-
+ /* Save the current state */
+ if (pNv->SaveGeneration != serverGeneration) {
+ pNv->SaveGeneration = serverGeneration;
+ NVSave(pScrn);
+ }
+
+ pScrn->vtSema = TRUE;
+
+ NVResetCrtcConfig(pScrn, 0);
+ if (!xf86SetDesiredModes(pScrn))
+ return FALSE;
+ NVResetCrtcConfig(pScrn, 1);
+ pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
+
if(pNv->overlayAdaptor)
NVResetVideo(pScrn);
return TRUE;
@@ -876,7 +925,6 @@ NVLeaveVT(int scrnIndex, int flags)
NVSync(pScrn);
NVRestore(pScrn);
- NVLockUnlock(pNv, 1);
}
@@ -924,7 +972,6 @@ NVCloseScreen(int scrnIndex, ScreenPtr pScreen)
pScrn->vtSema = FALSE;
NVSync(pScrn);
NVRestore(pScrn);
- NVLockUnlock(pNv, 1);
}
NVUnmapMem(pScrn);
@@ -999,7 +1046,7 @@ Bool NVI2CInit(ScrnInfoPtr pScrn)
mod = "ddc";
if(xf86LoadSubModule(pScrn, mod)) {
xf86LoaderReqSymLists(ddcSymbols, NULL);
- return NVDACi2cInit(pScrn);
+ return TRUE;
}
}
@@ -1029,16 +1076,29 @@ static Bool NVPreInitDRI(ScrnInfoPtr pScrn)
return TRUE;
}
+static Bool
+nv_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
+{
+ scrn->virtualX = width;
+ scrn->virtualY = height;
+ return TRUE;
+}
+
+static const xf86CrtcConfigFuncsRec nv_xf86crtc_config_funcs = {
+ nv_xf86crtc_resize
+};
+
/* Mandatory */
Bool
NVPreInit(ScrnInfoPtr pScrn, int flags)
{
+ xf86CrtcConfigPtr xf86_config;
NVPtr pNv;
MessageType from;
int i, max_width, max_height;
ClockRangePtr clockRanges;
const char *s;
- int config_mon_rates;
+ int num_crtc;
if (flags & PROBE_DETECT) {
EntityInfoPtr pEnt = xf86GetEntityInfo(pScrn->entityList[0]);
@@ -1355,7 +1415,7 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "forcing %s usage\n",
pNv->FlatPanel ? "DFP" : "CRTC");
} else {
- pNv->FlatPanel = -1; /* autodetect later */
+ pNv->FlatPanel = -1; /* autodetect later */
}
pNv->FPDither = FALSE;
@@ -1496,18 +1556,46 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
pNv->alphaCursor = (pNv->Architecture >= NV_ARCH_10) &&
((pNv->Chipset & 0x0ff0) != CHIPSET_NV10);
+
+ /* Allocate an xf86CrtcConfig */
+ xf86CrtcConfigInit (pScrn, &nv_xf86crtc_config_funcs);
+ xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+
+ max_width = 16384;
+ xf86CrtcSetSizeRange (pScrn, 320, 200, max_width, 2048);
+
if (NVPreInitDRI(pScrn) == FALSE) {
xf86FreeInt10(pNv->pInt);
return FALSE;
}
- if ((pScrn->monitor->nHsync == 0) &&
- (pScrn->monitor->nVrefresh == 0))
- config_mon_rates = FALSE;
- else
- config_mon_rates = TRUE;
-
NVCommonSetup(pScrn);
+ NVI2CInit(pScrn);
+
+ num_crtc = pNv->twoHeads ? 2 : 1;
+ for (i = 0; i < num_crtc; i++) {
+ nv_crtc_init(pScrn, i);
+ }
+
+ NvSetupOutputs(pScrn);
+
+#if 0
+ /* Do an initial detection of the outputs while none are configured on yet.
+ * This will give us some likely legitimate response for later if both
+ * pipes are already allocated and we're asked to do a detect.
+ */
+ for (i = 0; i < xf86_config->num_output; i++) {
+ xf86OutputPtr output = xf86_config->output[i];
+
+ output->status = (*output->funcs->detect) (output);
+ }
+#endif
+
+ if (!xf86InitialConfiguration (pScrn, FALSE)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes.\n");
+ return FALSE;
+ }
+
pScrn->videoRam = pNv->RamAmountKBytes;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "VideoRAM: %d kBytes\n",
@@ -1564,36 +1652,6 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
max_height = 4096;
}
- /* If DFP, add a modeline corresponding to its panel size */
- if (pNv->FlatPanel && !pNv->Television && pNv->fpWidth && pNv->fpHeight) {
- DisplayModePtr Mode;
-
- Mode = xnfcalloc(1, sizeof(DisplayModeRec));
- Mode = xf86CVTMode(pNv->fpWidth, pNv->fpHeight, 60.00, TRUE, FALSE);
- Mode->type = M_T_DRIVER;
- pScrn->monitor->Modes = xf86ModesAdd(pScrn->monitor->Modes, Mode);
-
- if (!config_mon_rates) {
- if (!Mode->HSync)
- Mode->HSync = ((float) Mode->Clock ) / ((float) Mode->HTotal);
- if (!Mode->VRefresh)
- Mode->VRefresh = (1000.0 * ((float) Mode->Clock)) /
- ((float) (Mode->HTotal * Mode->VTotal));
-
- if (Mode->HSync < pScrn->monitor->hsync[0].lo)
- pScrn->monitor->hsync[0].lo = Mode->HSync;
- if (Mode->HSync > pScrn->monitor->hsync[0].hi)
- pScrn->monitor->hsync[0].hi = Mode->HSync;
- if (Mode->VRefresh < pScrn->monitor->vrefresh[0].lo)
- pScrn->monitor->vrefresh[0].lo = Mode->VRefresh;
- if (Mode->VRefresh > pScrn->monitor->vrefresh[0].hi)
- pScrn->monitor->vrefresh[0].hi = Mode->VRefresh;
-
- pScrn->monitor->nHsync = 1;
- pScrn->monitor->nVrefresh = 1;
- }
- }
-
/*
* xf86ValidateModes will check that the mode HTotal and VTotal values
* don't exceed the chipset's limit if pScrn->maxHValue and
@@ -1696,6 +1754,14 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
pNv->CurrentLayout.weight.blue = pScrn->weight.blue;
pNv->CurrentLayout.mode = pScrn->currentMode;
+ if (pScrn->modes == NULL) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n");
+ PreInitCleanup(pScrn);
+ return FALSE;
+ }
+
+ pScrn->currentMode = pScrn->modes;
+
xf86FreeInt10(pNv->pInt);
pNv->pInt = NULL;
@@ -1759,6 +1825,10 @@ NVMapMem(ScrnInfoPtr pScrn)
ErrorF("Failed to allocate memory for hardware cursor\n");
return FALSE;
}
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Allocated %dKiB VRAM for cursor\n",
+ pNv->Cursor->size >> 10
+ );
pNv->ScratchBuffer = NVAllocateMemory(pNv, NOUVEAU_MEM_FB,
pNv->Architecture <NV_ARCH_10 ? 8192 : 16384);
@@ -1791,56 +1861,6 @@ NVUnmapMem(ScrnInfoPtr pScrn)
* Initialise a new mode.
*/
-static Bool
-NVModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
-{
- vgaHWPtr hwp = VGAHWPTR(pScrn);
- vgaRegPtr vgaReg;
- NVPtr pNv = NVPTR(pScrn);
- NVRegPtr nvReg;
-
- /* Initialise the ModeReg values */
- if (!vgaHWInit(pScrn, mode))
- return FALSE;
- pScrn->vtSema = TRUE;
-
- vgaReg = &hwp->ModeReg;
- nvReg = &pNv->ModeReg;
-
- if(!NVDACInit(pScrn, mode))
- return FALSE;
-
- NVLockUnlock(pNv, 0);
- if(pNv->twoHeads) {
- nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, nvReg->crtcOwner);
- NVLockUnlock(pNv, 0);
- }
-
- /* Program the registers */
- vgaHWProtect(pScrn, TRUE);
-
- NVDACRestore(pScrn, vgaReg, nvReg, FALSE);
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* turn on LFB swapping */
- {
- unsigned char tmp;
-
- tmp = nvReadVGA(pNv, NV_VGA_CRTCX_SWAPPING);
- tmp |= (1 << 7);
- nvWriteVGA(pNv, NV_VGA_CRTCX_SWAPPING, tmp);
- }
-#endif
-
- NVResetGraphics(pScrn);
-
- vgaHWProtect(pScrn, FALSE);
-
- pNv->CurrentLayout.mode = mode;
-
- return TRUE;
-}
-
/*
* Restore the initial (text) mode.
*/
@@ -1850,119 +1870,90 @@ NVRestore(ScrnInfoPtr pScrn)
vgaHWPtr hwp = VGAHWPTR(pScrn);
vgaRegPtr vgaReg = &hwp->SavedReg;
NVPtr pNv = NVPTR(pScrn);
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
NVRegPtr nvReg = &pNv->SavedReg;
+ int i;
+ int vgaflags = VGA_SR_CMAP | VGA_SR_MODE;
- NVLockUnlock(pNv, 0);
+ NVCrtcLockUnlock(xf86_config->crtc[0], 0);
+ NVCrtcLockUnlock(xf86_config->crtc[1], 0);
- if(pNv->twoHeads) {
- nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->CRTCnumber * 0x3);
- NVLockUnlock(pNv, 0);
+ for (i = 0; i < xf86_config->num_crtc; i++) {
+ xf86_config->crtc[i]->funcs->restore(xf86_config->crtc[i]);
}
- /* Only restore text mode fonts/text for the primary card */
- vgaHWProtect(pScrn, TRUE);
- NVDACRestore(pScrn, vgaReg, nvReg, pNv->Primary);
- if(pNv->twoHeads) {
- nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
+ for (i = 0; i< xf86_config->num_output; i++) {
+ xf86_config->output[i]->funcs->restore(xf86_config->output[i]);
}
- vgaHWProtect(pScrn, FALSE);
-}
-static void NVBacklightEnable(NVPtr pNv, Bool on)
-{
- /* This is done differently on each laptop. Here we
- define the ones we know for sure. */
-#if defined(__powerpc__)
- if((pNv->Chipset == 0x10DE0179) ||
- (pNv->Chipset == 0x10DE0189) ||
- (pNv->Chipset == 0x10DE0329))
- {
- /* NV17,18,34 Apple iMac, iBook, PowerBook */
- CARD32 tmp_pmc, tmp_pcrt;
- tmp_pmc = nvReadMC(pNv, 0x10F0) & 0x7FFFFFFF;
- tmp_pcrt = nvReadCRTC0(pNv, NV_CRTC_081C) & 0xFFFFFFFC;
- if(on) {
- tmp_pmc |= (1 << 31);
- tmp_pcrt |= 0x1;
- }
- nvWriteMC(pNv, 0x10F0, tmp_pmc);
- nvWriteCRTC0(pNv, NV_CRTC_081C, tmp_pcrt);
- }
+#ifndef __powerpc__
+ vgaflags |= VGA_SR_FONTS;
#endif
-
- if(pNv->LVDS) {
- if(pNv->twoHeads && ((pNv->Chipset & 0x0ff0) != CHIPSET_NV11)) {
- nvWriteMC(pNv, 0x130C, on ? 3 : 7);
- }
- } else {
- CARD32 fpcontrol;
+ vgaHWRestore(pScrn, vgaReg, vgaflags);
- fpcontrol = nvReadCurRAMDAC(pNv, 0x848) & 0xCfffffCC;
+ vgaHWLock(hwp);
+ NVCrtcLockUnlock(xf86_config->crtc[0], 1);
+ NVCrtcLockUnlock(xf86_config->crtc[1], 1);
- /* cut the TMDS output */
- if(on) fpcontrol |= pNv->fpSyncs;
- else fpcontrol |= 0x20000022;
- nvWriteCurRAMDAC(pNv, 0x0848, fpcontrol);
- }
}
+#define DEPTH_SHIFT(val, w) ((val << (8 - w)) | (val >> ((w << 1) - 8)))
+#define MAKE_INDEX(in, w) (DEPTH_SHIFT(in, w) * 3)
+
static void
-NVDPMSSetLCD(ScrnInfoPtr pScrn, int PowerManagementMode, int flags)
+NVLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices,
+ LOCO * colors, VisualPtr pVisual)
{
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ int c;
NVPtr pNv = NVPTR(pScrn);
+ int i, index;
- if (!pScrn->vtSema) return;
-
- vgaHWDPMSSet(pScrn, PowerManagementMode, flags);
-
- switch (PowerManagementMode) {
- case DPMSModeStandby: /* HSync: Off, VSync: On */
- case DPMSModeSuspend: /* HSync: On, VSync: Off */
- case DPMSModeOff: /* HSync: Off, VSync: Off */
- NVBacklightEnable(pNv, 0);
- break;
- case DPMSModeOn: /* HSync: On, VSync: On */
- NVBacklightEnable(pNv, 1);
- default:
- break;
- }
-}
+ for (c = 0; c < xf86_config->num_crtc; c++){
+ xf86CrtcPtr crtc = xf86_config->crtc[c];
+ NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
+ NVCrtcRegPtr regp;
+ regp = &pNv->ModeReg.crtc_reg[nv_crtc->crtc];
+
+ if (crtc->enabled == 0)
+ continue;
+
+ switch(pNv->CurrentLayout.depth) {
+ case 15:
+ for(i = 0; i < numColors; i++) {
+ index = indices[i];
+ regp->DAC[MAKE_INDEX(index, 5) + 0] = colors[index].red;
+ regp->DAC[MAKE_INDEX(index, 5) + 1] = colors[index].green;
+ regp->DAC[MAKE_INDEX(index, 5) + 2] = colors[index].blue;
+ }
+ break;
+ case 16:
+ for(i = 0; i < numColors; i++) {
+ index = indices[i];
+ regp->DAC[MAKE_INDEX(index, 6) + 1] = colors[index].green;
+ if(index < 32) {
+ regp->DAC[MAKE_INDEX(index, 5) + 0] = colors[index].red;
+ regp->DAC[MAKE_INDEX(index, 5) + 2] = colors[index].blue;
+ }
+ }
+ break;
+ default:
+ for(i = 0; i < numColors; i++) {
+ index = indices[i];
+ regp->DAC[index*3] = colors[index].red;
+ regp->DAC[(index*3)+1] = colors[index].green;
+ regp->DAC[(index*3)+2] = colors[index].blue;
+ }
+ break;
+ }
-static void
-NVDPMSSet(ScrnInfoPtr pScrn, int PowerManagementMode, int flags)
-{
- unsigned char crtc1A;
- vgaHWPtr hwp = VGAHWPTR(pScrn);
-
- if (!pScrn->vtSema) return;
-
- crtc1A = hwp->readCrtc(hwp, 0x1A) & ~0xC0;
-
- switch (PowerManagementMode) {
- case DPMSModeStandby: /* HSync: Off, VSync: On */
- crtc1A |= 0x80;
- break;
- case DPMSModeSuspend: /* HSync: On, VSync: Off */
- crtc1A |= 0x40;
- break;
- case DPMSModeOff: /* HSync: Off, VSync: Off */
- crtc1A |= 0xC0;
- break;
- case DPMSModeOn: /* HSync: On, VSync: On */
- default:
- break;
+ NVCrtcLoadPalette(crtc);
}
-
- /* vgaHWDPMSSet will merely cut the dac output */
- vgaHWDPMSSet(pScrn, PowerManagementMode, flags);
-
- hwp->writeCrtc(hwp, 0x1A, crtc1A);
}
-
/* Mandatory */
/* This gets called at the start of each server generation */
@@ -2010,16 +2001,15 @@ NVScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
if (!NVAccelCommonInit(pScrn))
return FALSE;
- /* Save the current state */
- NVSave(pScrn);
- /* Initialise the first mode */
- if (!NVModeInit(pScrn, pScrn->currentMode)) {
- return FALSE;
- }
+ pScrn->memPhysBase = pNv->VRAMPhysical;
+ pScrn->fbOffset = 0;
+
+ if (!NVEnterVT(scrnIndex, 0))
+ return FALSE;
/* Darken the screen for aesthetic reasons and set the viewport */
- NVSaveScreen(pScreen, SCREEN_SAVER_ON);
- pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
+ // NVSaveScreen(pScreen, SCREEN_SAVER_ON);
+ // pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
/*
* The next step is to setup the screen's visuals, and initialise the
@@ -2163,10 +2153,19 @@ NVScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
/* Initialize colormap layer.
Must follow initialization of the default colormap */
- if(!xf86HandleColormaps(pScreen, 256, 8, NVDACLoadPalette,
+ if(!xf86HandleColormaps(pScreen, 256, 8, NVLoadPalette,
NULL, CMAP_RELOAD_ON_MODE_SWITCH | CMAP_PALETTED_TRUECOLOR))
return FALSE;
+
+ xf86DPMSInit(pScreen, xf86DPMSSet, 0);
+
+ if (!xf86CrtcScreenInit (pScreen))
+ return FALSE;
+
+ pNv->PointerMoved = pScrn->PointerMoved;
+ pScrn->PointerMoved = NVPointerMoved;
+
if(pNv->ShadowFB) {
RefreshAreaFuncPtr refreshArea = NVRefreshArea;
@@ -2190,11 +2189,6 @@ NVScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
ShadowFBInit(pScreen, refreshArea);
}
- if(pNv->FlatPanel)
- xf86DPMSInit(pScreen, NVDPMSSetLCD, 0);
- else
- xf86DPMSInit(pScreen, NVDPMSSet, 0);
-
pScrn->memPhysBase = pNv->VRAMPhysical;
pScrn->fbOffset = 0;
@@ -2210,7 +2204,7 @@ NVScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
pNv->BlockHandler = pScreen->BlockHandler;
pScreen->BlockHandler = NVBlockHandler;
-#ifdef RANDR
+#if 0 //def RANDR
/* Install our DriverFunc. We have to do it this way instead of using the
* HaveDriverFuncs argument to xf86AddDriver, because InitOutput clobbers
* pScrn->DriverFunc */
@@ -2227,7 +2221,23 @@ NVScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
static Bool
NVSaveScreen(ScreenPtr pScreen, int mode)
{
- return vgaHWSaveScreen(pScreen, mode);
+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ NVPtr pNv = NVPTR(pScrn);
+ int i;
+ Bool on = xf86IsUnblank(mode);
+
+ if (pScrn->vtSema) {
+ for (i = 0; i < xf86_config->num_crtc; i++) {
+
+ if (xf86_config->crtc[i]->enabled) {
+ NVCrtcBlankScreen(xf86_config->crtc[i], on);
+ }
+ }
+
+ }
+ return TRUE;
+
}
static void
@@ -2237,14 +2247,24 @@ NVSave(ScrnInfoPtr pScrn)
NVRegPtr nvReg = &pNv->SavedReg;
vgaHWPtr pVga = VGAHWPTR(pScrn);
vgaRegPtr vgaReg = &pVga->SavedReg;
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ int i;
+ int vgaflags = VGA_SR_CMAP | VGA_SR_MODE;
+
+ for (i = 0; i < xf86_config->num_crtc; i++) {
+ xf86_config->crtc[i]->funcs->save(xf86_config->crtc[i]);
+ }
+
- NVLockUnlock(pNv, 0);
- if(pNv->twoHeads) {
- nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->CRTCnumber * 0x3);
- NVLockUnlock(pNv, 0);
+ for (i = 0; i< xf86_config->num_output; i++) {
+ xf86_config->output[i]->funcs->save(xf86_config->output[i]);
}
- NVDACSave(pScrn, vgaReg, nvReg, pNv->Primary);
+ vgaHWUnlock(pVga);
+#ifndef __powerpc__
+ vgaflags |= VGA_SR_FONTS;
+#endif
+ vgaHWSave(pScrn, vgaReg, vgaflags);
}
#ifdef RANDR
@@ -2308,3 +2328,4 @@ NVDriverFunc(ScrnInfoPtr pScrn, xorgDriverFuncOp op, pointer data)
return FALSE;
}
#endif
+
diff --git a/src/nv_hw.c b/src/nv_hw.c
index 0dc78a1..2cfb741 100644
--- a/src/nv_hw.c
+++ b/src/nv_hw.c
@@ -65,7 +65,7 @@ CARD32 nvReadRAMDAC(NVPtr pNv, uint8_t head, uint32_t ramdac_reg)
void nvWriteRAMDAC(NVPtr pNv, uint8_t head, uint32_t ramdac_reg, CARD32 val)
{
volatile const void *ptr = head ? pNv->PRAMDAC1 : pNv->PRAMDAC0;
- MMIO_OUT32(ptr, ramdac_reg, val);
+ NV_WR32(ptr, ramdac_reg, val);
}
CARD32 nvReadCRTC(NVPtr pNv, uint8_t head, uint32_t reg)
@@ -77,42 +77,7 @@ CARD32 nvReadCRTC(NVPtr pNv, uint8_t head, uint32_t reg)
void nvWriteCRTC(NVPtr pNv, uint8_t head, uint32_t reg, CARD32 val)
{
volatile const void *ptr = head ? pNv->PCRTC1 : pNv->PCRTC0;
- MMIO_OUT32(ptr, reg, val);
-}
-
-void NVLockUnlock (
- NVPtr pNv,
- Bool Lock
-)
-{
- CARD8 cr11;
-
- nvWriteVGA(pNv, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57 );
-
- cr11 = nvReadVGA(pNv, NV_VGA_CRTCX_VSYNCE);
- if(Lock) cr11 |= 0x80;
- else cr11 &= ~0x80;
- nvWriteVGA(pNv, NV_VGA_CRTCX_VSYNCE, cr11);
-}
-
-int NVShowHideCursor (
- NVPtr pNv,
- int ShowHide
-)
-{
- int current = pNv->CurrentState->cursor1;
-
- pNv->CurrentState->cursor1 = (pNv->CurrentState->cursor1 & 0xFE) |
- (ShowHide & 0x01);
-
- nvWriteVGA(pNv, NV_VGA_CRTCX_CURCTL1, pNv->CurrentState->cursor1);
-
- if(pNv->Architecture == NV_ARCH_40) { /* HW bug */
- volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
- nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
- }
-
- return (current & 0x01);
+ NV_WR32(ptr, reg, val);
}
/****************************************************************************\
@@ -277,7 +242,7 @@ static void nvGetClocks(NVPtr pNv, unsigned int *MClk, unsigned int *NVClk)
}
-static void nv4CalcArbitration (
+void nv4CalcArbitration (
nv4_fifo_info *fifo,
nv4_sim_state *arb
)
@@ -416,7 +381,7 @@ static void nv4CalcArbitration (
}
}
-static void nv4UpdateArbitrationSettings (
+void nv4UpdateArbitrationSettings (
unsigned VClk,
unsigned pixelDepth,
unsigned *burst,
@@ -452,7 +417,7 @@ static void nv4UpdateArbitrationSettings (
}
}
-static void nv10CalcArbitration (
+void nv10CalcArbitration (
nv10_fifo_info *fifo,
nv10_sim_state *arb
)
@@ -643,7 +608,7 @@ static void nv10CalcArbitration (
}
}
-static void nv10UpdateArbitrationSettings (
+void nv10UpdateArbitrationSettings (
unsigned VClk,
unsigned pixelDepth,
unsigned *burst,
@@ -680,11 +645,9 @@ static void nv10UpdateArbitrationSettings (
}
-static void nv30UpdateArbitrationSettings (
- NVPtr pNv,
- unsigned *burst,
- unsigned *lwm
-)
+void nv30UpdateArbitrationSettings (NVPtr pNv,
+ unsigned *burst,
+ unsigned *lwm)
{
unsigned int MClk, NVClk;
unsigned int fifo_size, burst_size, graphics_lwm;
@@ -701,12 +664,11 @@ static void nv30UpdateArbitrationSettings (
*lwm = graphics_lwm >> 3;
}
-static void nForceUpdateArbitrationSettings (
- unsigned VClk,
- unsigned pixelDepth,
- unsigned *burst,
- unsigned *lwm,
- NVPtr pNv
+void nForceUpdateArbitrationSettings (unsigned VClk,
+ unsigned pixelDepth,
+ unsigned *burst,
+ unsigned *lwm,
+ NVPtr pNv
)
{
nv10_fifo_info fifo_data;
@@ -765,375 +727,3 @@ static void nForceUpdateArbitrationSettings (
}
-/****************************************************************************\
-* *
-* RIVA Mode State Routines *
-* *
-\****************************************************************************/
-
-/*
- * Calculate the Video Clock parameters for the PLL.
- */
-static void CalcVClock (
- int clockIn,
- int *clockOut,
- CARD32 *pllOut,
- NVPtr pNv
-)
-{
- unsigned lowM, highM;
- unsigned DeltaNew, DeltaOld;
- unsigned VClk, Freq;
- unsigned M, N, P;
-
- DeltaOld = 0xFFFFFFFF;
-
- VClk = (unsigned)clockIn;
-
- if (pNv->CrystalFreqKHz == 13500) {
- lowM = 7;
- highM = 13;
- } else {
- lowM = 8;
- highM = 14;
- }
-
- for (P = 0; P <= 4; P++) {
- Freq = VClk << P;
- if ((Freq >= 128000) && (Freq <= 350000)) {
- for (M = lowM; M <= highM; M++) {
- N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
- if(N <= 255) {
- Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
- if (Freq > VClk)
- DeltaNew = Freq - VClk;
- else
- DeltaNew = VClk - Freq;
- if (DeltaNew < DeltaOld) {
- *pllOut = (P << 16) | (N << 8) | M;
- *clockOut = Freq;
- DeltaOld = DeltaNew;
- }
- }
- }
- }
- }
-}
-
-static void CalcVClock2Stage (
- int clockIn,
- int *clockOut,
- CARD32 *pllOut,
- CARD32 *pllBOut,
- NVPtr pNv
-)
-{
- unsigned DeltaNew, DeltaOld;
- unsigned VClk, Freq;
- unsigned M, N, P;
-
- DeltaOld = 0xFFFFFFFF;
-
- *pllBOut = 0x80000401; /* fixed at x4 for now */
-
- VClk = (unsigned)clockIn;
-
- for (P = 0; P <= 6; P++) {
- Freq = VClk << P;
- if ((Freq >= 400000) && (Freq <= 1000000)) {
- for (M = 1; M <= 13; M++) {
- N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
- if((N >= 5) && (N <= 255)) {
- Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
- if (Freq > VClk)
- DeltaNew = Freq - VClk;
- else
- DeltaNew = VClk - Freq;
- if (DeltaNew < DeltaOld) {
- *pllOut = (P << 16) | (N << 8) | M;
- *clockOut = Freq;
- DeltaOld = DeltaNew;
- }
- }
- }
- }
- }
-}
-
-/*
- * Calculate extended mode parameters (SVGA) and save in a
- * mode state structure.
- */
-void NVCalcStateExt (
- NVPtr pNv,
- RIVA_HW_STATE *state,
- int bpp,
- int width,
- int hDisplaySize,
- int height,
- int dotClock,
- int flags
-)
-{
- int pixelDepth, VClk;
- CARD32 CursorStart;
-
- /*
- * Save mode parameters.
- */
- state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
- state->width = width;
- state->height = height;
- /*
- * Extended RIVA registers.
- */
- pixelDepth = (bpp + 1)/8;
- if(pNv->twoStagePLL)
- CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
- else
- CalcVClock(dotClock, &VClk, &state->pll, pNv);
-
- switch (pNv->Architecture)
- {
- case NV_ARCH_04:
- nv4UpdateArbitrationSettings(VClk,
- pixelDepth * 8,
- &(state->arbitration0),
- &(state->arbitration1),
- pNv);
- state->cursor0 = 0x00;
- state->cursor1 = 0xbC;
- if (flags & V_DBLSCAN)
- state->cursor1 |= 2;
- state->cursor2 = 0x00000000;
- state->pllsel = 0x10000700;
- state->config = 0x00001114;
- state->general = bpp == 16 ? 0x00101100 : 0x00100100;
- state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
- break;
- case NV_ARCH_10:
- case NV_ARCH_20:
- case NV_ARCH_30:
- default:
- if(((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
- ((pNv->Chipset & 0xfff0) == CHIPSET_C512))
- {
- state->arbitration0 = 128;
- state->arbitration1 = 0x0480;
- } else
- if(((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
- ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2))
- {
- nForceUpdateArbitrationSettings(VClk,
- pixelDepth * 8,
- &(state->arbitration0),
- &(state->arbitration1),
- pNv);
- } else if(pNv->Architecture < NV_ARCH_30) {
- nv10UpdateArbitrationSettings(VClk,
- pixelDepth * 8,
- &(state->arbitration0),
- &(state->arbitration1),
- pNv);
- } else {
- nv30UpdateArbitrationSettings(pNv,
- &(state->arbitration0),
- &(state->arbitration1));
- }
- CursorStart = pNv->Cursor->offset;
- state->cursor0 = 0x80 | (CursorStart >> 17);
- state->cursor1 = (CursorStart >> 11) << 2;
- state->cursor2 = CursorStart >> 24;
- if (flags & V_DBLSCAN)
- state->cursor1 |= 2;
- state->pllsel = 0x10000700;
- state->config = nvReadFB(pNv, NV_PFB_CFG0);
- state->general = bpp == 16 ? 0x00101100 : 0x00100100;
- state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
- break;
- }
-
- if(bpp != 8) /* DirectColor */
- state->general |= 0x00000030;
-
- state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3;
- state->pixel = (pixelDepth > 2) ? 3 : pixelDepth;
-}
-
-
-void NVLoadStateExt (
- ScrnInfoPtr pScrn,
- RIVA_HW_STATE *state
-)
-{
- NVPtr pNv = NVPTR(pScrn);
- int i, j;
- CARD32 temp;
-
- if(pNv->Architecture >= NV_ARCH_40) {
- switch(pNv->Chipset & 0xfff0) {
- case CHIPSET_NV44:
- case CHIPSET_NV44A:
- case CHIPSET_C51:
- case CHIPSET_G70:
- case CHIPSET_G71:
- case CHIPSET_G72:
- case CHIPSET_G73:
- case CHIPSET_C512:
- temp = nvReadCurRAMDAC(pNv, NV_RAMDAC_TEST_CONTROL);
- nvWriteCurRAMDAC(pNv, NV_RAMDAC_TEST_CONTROL, temp | 0x00100000);
- break;
- default:
- break;
- };
- }
-
- if(pNv->Architecture >= NV_ARCH_10) {
- if(pNv->twoHeads) {
- nvWriteCRTC(pNv, 0, NV_CRTC_HEAD_CONFIG, state->head);
- nvWriteCRTC(pNv, 1, NV_CRTC_HEAD_CONFIG, state->head2);
- }
- temp = nvReadCurRAMDAC(pNv, NV_RAMDAC_0404);
- nvWriteCurRAMDAC(pNv, NV_RAMDAC_0404, temp | (1 << 25));
-
- nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
- nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
- nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
- nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
- nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
- nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
- nvWriteMC(pNv, 0x1588, 0);
-
- nvWriteCurCRTC(pNv, NV_CRTC_CURSOR_CONFIG, state->cursorConfig);
- nvWriteCurCRTC(pNv, NV_CRTC_0830, state->displayV - 3);
- nvWriteCurCRTC(pNv, NV_CRTC_0834, state->displayV - 1);
-
- if(pNv->FlatPanel) {
- if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
- nvWriteCurRAMDAC(pNv, NV_RAMDAC_DITHER_NV11, state->dither);
- } else
- if(pNv->twoHeads) {
- nvWriteCurRAMDAC(pNv, NV_RAMDAC_FP_DITHER, state->dither);
- }
-
- nvWriteVGA(pNv, NV_VGA_CRTCX_FP_HTIMING, state->timingH);
- nvWriteVGA(pNv, NV_VGA_CRTCX_FP_VTIMING, state->timingV);
- nvWriteVGA(pNv, NV_VGA_CRTCX_BUFFER, 0xfa);
- }
-
- nvWriteVGA(pNv, NV_VGA_CRTCX_EXTRA, state->extra);
- }
-
- nvWriteVGA(pNv, NV_VGA_CRTCX_REPAINT0, state->repaint0);
- nvWriteVGA(pNv, NV_VGA_CRTCX_REPAINT1, state->repaint1);
- nvWriteVGA(pNv, NV_VGA_CRTCX_LSR, state->screen);
- nvWriteVGA(pNv, NV_VGA_CRTCX_PIXEL, state->pixel);
- nvWriteVGA(pNv, NV_VGA_CRTCX_HEB, state->horiz);
- nvWriteVGA(pNv, NV_VGA_CRTCX_FIFO1, state->fifo);
- nvWriteVGA(pNv, NV_VGA_CRTCX_FIFO0, state->arbitration0);
- nvWriteVGA(pNv, NV_VGA_CRTCX_FIFO_LWM, state->arbitration1);
- if(pNv->Architecture >= NV_ARCH_30) {
- nvWriteVGA(pNv, NV_VGA_CRTCX_FIFO_LWM_NV30, state->arbitration1 >> 8);
- }
-
- nvWriteVGA(pNv, NV_VGA_CRTCX_CURCTL0, state->cursor0);
- nvWriteVGA(pNv, NV_VGA_CRTCX_CURCTL1, state->cursor1);
- if(pNv->Architecture == NV_ARCH_40) { /* HW bug */
- volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
- nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
- }
- nvWriteVGA(pNv, NV_VGA_CRTCX_CURCTL2, state->cursor2);
- nvWriteVGA(pNv, NV_VGA_CRTCX_INTERLACE, state->interlace);
-
- if(!pNv->FlatPanel) {
- nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
- nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
- if(pNv->twoHeads)
- nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
- if(pNv->twoStagePLL) {
- nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
- nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
- }
- } else {
- nvWriteCurRAMDAC(pNv, NV_RAMDAC_FP_CONTROL, state->scale);
- nvWriteCurRAMDAC(pNv, NV_RAMDAC_FP_HCRTC, state->crtcSync);
- }
- nvWriteCurRAMDAC(pNv, NV_RAMDAC_GENERAL_CONTROL, state->general);
-
- nvWriteCurCRTC(pNv, NV_CRTC_INTR_EN_0, 0);
- nvWriteCurCRTC(pNv, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
-
- pNv->CurrentState = state;
-}
-
-void NVUnloadStateExt
-(
- NVPtr pNv,
- RIVA_HW_STATE *state
-)
-{
- state->repaint0 = nvReadVGA(pNv, NV_VGA_CRTCX_REPAINT0);
- state->repaint1 = nvReadVGA(pNv, NV_VGA_CRTCX_REPAINT1);
- state->screen = nvReadVGA(pNv, NV_VGA_CRTCX_LSR);
- state->pixel = nvReadVGA(pNv, NV_VGA_CRTCX_PIXEL);
- state->horiz = nvReadVGA(pNv, NV_VGA_CRTCX_HEB);
- state->fifo = nvReadVGA(pNv, NV_VGA_CRTCX_FIFO1);
- state->arbitration0 = nvReadVGA(pNv, NV_VGA_CRTCX_FIFO0);
- state->arbitration1 = nvReadVGA(pNv, NV_VGA_CRTCX_FIFO_LWM);
- if(pNv->Architecture >= NV_ARCH_30) {
- state->arbitration1 |= (nvReadVGA(pNv, NV_VGA_CRTCX_FIFO_LWM_NV30) & 1) << 8;
- }
- state->cursor0 = nvReadVGA(pNv, NV_VGA_CRTCX_CURCTL0);
- state->cursor1 = nvReadVGA(pNv, NV_VGA_CRTCX_CURCTL1);
- state->cursor2 = nvReadVGA(pNv, NV_VGA_CRTCX_CURCTL2);
- state->interlace = nvReadVGA(pNv, NV_VGA_CRTCX_INTERLACE);
-
- state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
- if(pNv->twoHeads)
- state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
- if(pNv->twoStagePLL) {
- state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
- state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
- }
- state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
- state->general = nvReadCurRAMDAC(pNv, NV_RAMDAC_GENERAL_CONTROL);
- state->scale = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_CONTROL);
- state->config = nvReadFB(pNv, NV_PFB_CFG0);
-
- if(pNv->Architecture >= NV_ARCH_10) {
- if(pNv->twoHeads) {
- state->head = nvReadCRTC(pNv, 0, NV_CRTC_HEAD_CONFIG);
- state->head2 = nvReadCRTC(pNv, 1, NV_CRTC_HEAD_CONFIG);
- state->crtcOwner = nvReadVGA(pNv, NV_VGA_CRTCX_OWNER);
- }
- state->extra = nvReadVGA(pNv, NV_VGA_CRTCX_EXTRA);
-
- state->cursorConfig = nvReadCurCRTC(pNv, NV_CRTC_CURSOR_CONFIG);
-
- if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
- state->dither = nvReadCurRAMDAC(pNv, NV_RAMDAC_DITHER_NV11);
- } else
- if(pNv->twoHeads) {
- state->dither = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_DITHER);
- }
-
- if(pNv->FlatPanel) {
- state->timingH = nvReadVGA(pNv, NV_VGA_CRTCX_FP_HTIMING);
- state->timingV = nvReadVGA(pNv, NV_VGA_CRTCX_FP_VTIMING);
- }
- }
-
- if(pNv->FlatPanel) {
- state->crtcSync = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_HCRTC);
- }
-}
-
-void NVSetStartAddress (
- NVPtr pNv,
- CARD32 start
-)
-{
- nvWriteCurCRTC(pNv, NV_CRTC_START, start);
-}
-
-
diff --git a/src/nv_i2c.c b/src/nv_i2c.c
new file mode 100644
index 0000000..93bef4f
--- /dev/null
+++ b/src/nv_i2c.c
@@ -0,0 +1,70 @@
+
+#include "nv_include.h"
+
+/*
+ * DDC1 support only requires DDC_SDA_MASK,
+ * DDC2 support requires DDC_SDA_MASK and DDC_SCL_MASK
+ */
+#define DDC_SDA_READ_MASK (1 << 3)
+#define DDC_SCL_READ_MASK (1 << 2)
+#define DDC_SDA_WRITE_MASK (1 << 4)
+#define DDC_SCL_WRITE_MASK (1 << 5)
+
+static void
+NVI2CGetBits(I2CBusPtr b, int *clock, int *data)
+{
+ NVPtr pNv = NVPTR(xf86Screens[b->scrnIndex]);
+ unsigned char val;
+
+ /* Get the result. */
+ val = nvReadVGA(pNv, b->DriverPrivate.uval);
+
+ *clock = (val & DDC_SCL_READ_MASK) != 0;
+ *data = (val & DDC_SDA_READ_MASK) != 0;
+}
+
+static void
+NVI2CPutBits(I2CBusPtr b, int clock, int data)
+{
+ NVPtr pNv = NVPTR(xf86Screens[b->scrnIndex]);
+ unsigned char val;
+
+ val = nvReadVGA(pNv, b->DriverPrivate.uval + 1) & 0xf0;
+ if (clock)
+ val |= DDC_SCL_WRITE_MASK;
+ else
+ val &= ~DDC_SCL_WRITE_MASK;
+
+ if (data)
+ val |= DDC_SDA_WRITE_MASK;
+ else
+ val &= ~DDC_SDA_WRITE_MASK;
+
+ nvWriteVGA(pNv, b->DriverPrivate.uval + 1, val | 0x1);
+}
+
+Bool
+NV_I2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg, char *name)
+{
+ I2CBusPtr pI2CBus;
+
+ pI2CBus = xf86CreateI2CBusRec();
+ if(!pI2CBus)
+ return FALSE;
+
+ pI2CBus->BusName = name;
+ pI2CBus->scrnIndex = pScrn->scrnIndex;
+ pI2CBus->I2CPutBits = NVI2CPutBits;
+ pI2CBus->I2CGetBits = NVI2CGetBits;
+ pI2CBus->AcknTimeout = 5;
+
+ pI2CBus->DriverPrivate.uval = i2c_reg;
+
+ if (!xf86I2CBusInit(pI2CBus)) {
+ return FALSE;
+ }
+
+ *bus_ptr = pI2CBus;
+ return TRUE;
+}
+
diff --git a/src/nv_include.h b/src/nv_include.h
index 2d9ec3c..eaa5090 100644
--- a/src/nv_include.h
+++ b/src/nv_include.h
@@ -74,4 +74,6 @@
#include "nouveau_reg.h"
#include "nvreg.h"
+#include "xf86Crtc.h"
+
#endif /* __NV_INCLUDE_H__ */
diff --git a/src/nv_local.h b/src/nv_local.h
index 5a74ee2..f539a2c 100644
--- a/src/nv_local.h
+++ b/src/nv_local.h
@@ -49,14 +49,37 @@
#include "compiler.h"
#include "xf86_OSproc.h"
+//#define DAVE_DEBUG
+#ifdef DAVE_DEBUG
+
+extern CARD32 debug_offset;
+static inline void nv_wr08(void *p, int i, CARD8 d, char *fname)
+{
+ static int last_vga = 0;
+
+ if (i == 0x3d4)
+ last_vga = d;
+
+ if (strcmp(fname, "nvReadVGA") && last_vga != 0x3f && last_vga != 0x37)
+ ErrorF("wr08: %08X %08X, %02X\t%s\n", p-debug_offset, i, d, fname);
+ MMIO_OUT8((pointer)(p), (i), (d));
+}
+
+
+#define NV_WR08(p,i,d) nv_wr08(p, i, d, __FUNCTION__)
+#define NV_WR32(p,i,d) do { ErrorF("wr32: %08X, %08X\t%s\n", p -debug_offset + i, d, __FUNCTION__); MMIO_OUT32((pointer)(p), (i), (d)); } while(0)
+#else
+#define NV_WR08(p,i,d) MMIO_OUT8((pointer)(p), (i), (d))
+#define NV_WR32(p,i,d) MMIO_OUT32((pointer)(p), (i), (d))
+#endif
+
+
/*
* HW access macros. These assume memory-mapped I/O, and not normal I/O space.
*/
-#define NV_WR08(p,i,d) MMIO_OUT8((pointer)(p), (i), (d))
#define NV_RD08(p,i) MMIO_IN8((pointer)(p), (i))
#define NV_WR16(p,i,d) MMIO_OUT16((pointer)(p), (i), (d))
#define NV_RD16(p,i) MMIO_IN16((pointer)(p), (i))
-#define NV_WR32(p,i,d) MMIO_OUT32((pointer)(p), (i), (d))
#define NV_RD32(p,i) MMIO_IN32((pointer)(p), (i))
/* VGA I/O is now always done through MMIO */
diff --git a/src/nv_output.c b/src/nv_output.c
new file mode 100644
index 0000000..9f72fd3
--- /dev/null
+++ b/src/nv_output.c
@@ -0,0 +1,885 @@
+/*
+ * Copyright 2006 Dave Airlie
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Dave Airlie
+ */
+/*
+ * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
+ * decleration is at the bottom of this file as it is rather ugly
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "xf86.h"
+#include "os.h"
+#include "mibank.h"
+#include "globals.h"
+#include "xf86.h"
+#include "xf86Priv.h"
+#include "xf86DDC.h"
+#include "mipointer.h"
+#include "windowstr.h"
+#include <randrstr.h>
+#include <X11/extensions/render.h>
+
+#include "xf86Crtc.h"
+#include "nv_include.h"
+
+const char *OutputType[] = {
+ "None",
+ "VGA",
+ "DVI",
+ "LVDS",
+ "S-video",
+ "Composite",
+};
+
+const char *MonTypeName[7] = {
+ "AUTO",
+ "NONE",
+ "CRT",
+ "LVDS",
+ "TMDS",
+ "CTV",
+ "STV"
+};
+
+void NVOutputWriteRAMDAC(xf86OutputPtr output, CARD32 ramdac_reg, CARD32 val)
+{
+ NVOutputPrivatePtr nv_output = output->driver_private;
+ ScrnInfoPtr pScrn = output->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+
+ nvWriteRAMDAC(pNv, nv_output->ramdac, ramdac_reg, val);
+}
+
+CARD32 NVOutputReadRAMDAC(xf86OutputPtr output, CARD32 ramdac_reg)
+{
+ NVOutputPrivatePtr nv_output = output->driver_private;
+ ScrnInfoPtr pScrn = output->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+
+ return nvReadRAMDAC(pNv, nv_output->ramdac, ramdac_reg);
+}
+
+static void nv_output_backlight_enable(xf86OutputPtr output, Bool on)
+{
+ ScrnInfoPtr pScrn = output->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+
+ /* This is done differently on each laptop. Here we
+ define the ones we know for sure. */
+
+#if defined(__powerpc__)
+ if((pNv->Chipset == 0x10DE0179) ||
+ (pNv->Chipset == 0x10DE0189) ||
+ (pNv->Chipset == 0x10DE0329))
+ {
+ /* NV17,18,34 Apple iMac, iBook, PowerBook */
+ CARD32 tmp_pmc, tmp_pcrt;
+ tmp_pmc = nvReadMC(pNv, 0x10F0) & 0x7FFFFFFF;
+ tmp_pcrt = nvReadCRTC0(pNv, NV_CRTC_081C) & 0xFFFFFFFC;
+ if(on) {
+ tmp_pmc |= (1 << 31);
+ tmp_pcrt |= 0x1;
+ }
+ nvWriteMC(pNv, 0x10F0, tmp_pmc);
+ nvWriteCRTC0(pNv, NV_CRTC_081C, tmp_pcrt);
+ }
+#endif
+
+ if(pNv->twoHeads && ((pNv->Chipset & 0x0ff0) != CHIPSET_NV11))
+ nvWriteMC(pNv, 0x130C, on ? 3 : 7);
+}
+
+static void
+nv_panel_output_dpms(xf86OutputPtr output, int mode)
+{
+
+ switch(mode) {
+ case DPMSModeStandby:
+ case DPMSModeSuspend:
+ case DPMSModeOff:
+ nv_output_backlight_enable(output, 0);
+ break;
+ case DPMSModeOn:
+ nv_output_backlight_enable(output, 1);
+ default:
+ break;
+ }
+}
+
+static void
+nv_analog_output_dpms(xf86OutputPtr output, int mode)
+{
+
+}
+
+static void
+nv_digital_output_dpms(xf86OutputPtr output, int mode)
+{
+ NVOutputPrivatePtr nv_output = output->driver_private;
+ xf86CrtcPtr crtc = output->crtc;
+ ScrnInfoPtr pScrn = output->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+ NVCrtcPrivatePtr nv_crtc;
+
+ CARD32 fpcontrol;
+
+ if (crtc) {
+ nv_crtc = crtc->driver_private;
+
+ fpcontrol = nvReadRAMDAC(pNv, nv_crtc->crtc, NV_RAMDAC_FP_CONTROL) & 0xCfffffCC;
+ switch(mode) {
+ case DPMSModeStandby:
+ case DPMSModeSuspend:
+ case DPMSModeOff:
+ /* cut the TMDS output */
+ fpcontrol |= 0x20000022;
+ break;
+ case DPMSModeOn:
+ fpcontrol |= nv_output->fpSyncs;
+ }
+
+ nvWriteRAMDAC(pNv, nv_crtc->crtc, NV_RAMDAC_FP_CONTROL, fpcontrol);
+ }
+}
+
+void nv_output_save_state_ext(xf86OutputPtr output, RIVA_HW_STATE *state)
+{
+ NVOutputPrivatePtr nv_output = output->driver_private;
+ ScrnInfoPtr pScrn = output->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+ NVOutputRegPtr regp;
+
+ regp = &state->dac_reg[nv_output->ramdac];
+ regp->general = NVOutputReadRAMDAC(output, NV_RAMDAC_GENERAL_CONTROL);
+ regp->fp_control = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_CONTROL);
+ regp->debug_0 = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_DEBUG_0);
+ state->config = nvReadFB(pNv, NV_PFB_CFG0);
+
+ regp->output = NVOutputReadRAMDAC(output, NV_RAMDAC_OUTPUT);
+
+ if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
+ regp->dither = NVOutputReadRAMDAC(output, NV_RAMDAC_DITHER_NV11);
+ } else if(pNv->twoHeads) {
+ regp->dither = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_DITHER);
+ }
+ // regp->crtcSync = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_HCRTC);
+ regp->nv10_cursync = NVOutputReadRAMDAC(output, NV_RAMDAC_NV10_CURSYNC);
+
+ if (nv_output->type == OUTPUT_DIGITAL) {
+ int i;
+
+ for (i = 0; i < 7; i++) {
+ uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
+
+ regp->fp_horiz_regs[i] = NVOutputReadRAMDAC(output, ramdac_reg);
+ }
+
+ for (i = 0; i < 7; i++) {
+ uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
+
+ regp->fp_vert_regs[i] = NVOutputReadRAMDAC(output, ramdac_reg);
+ }
+ }
+
+}
+
+void nv_output_load_state_ext(xf86OutputPtr output, RIVA_HW_STATE *state)
+{
+ NVOutputPrivatePtr nv_output = output->driver_private;
+ ScrnInfoPtr pScrn = output->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+ NVOutputRegPtr regp;
+
+ regp = &state->dac_reg[nv_output->ramdac];
+
+ NVOutputWriteRAMDAC(output, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
+ NVOutputWriteRAMDAC(output, NV_RAMDAC_OUTPUT, regp->output);
+ NVOutputWriteRAMDAC(output, NV_RAMDAC_FP_CONTROL, regp->fp_control);
+ // NVOutputWriteRAMDAC(output, NV_RAMDAC_FP_HCRTC, regp->crtcSync);
+
+
+ if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
+ NVOutputWriteRAMDAC(output, NV_RAMDAC_DITHER_NV11, regp->dither);
+ } else if(pNv->twoHeads) {
+ NVOutputWriteRAMDAC(output, NV_RAMDAC_FP_DITHER, regp->dither);
+ }
+
+ NVOutputWriteRAMDAC(output, NV_RAMDAC_GENERAL_CONTROL, regp->general);
+ NVOutputWriteRAMDAC(output, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
+
+ if (nv_output->type == OUTPUT_DIGITAL) {
+ int i;
+
+ for (i = 0; i < 7; i++) {
+ uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
+ NVOutputWriteRAMDAC(output, ramdac_reg, regp->fp_horiz_regs[i]);
+ }
+
+ for (i = 0; i < 7; i++) {
+ uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
+
+ NVOutputWriteRAMDAC(output, ramdac_reg, regp->fp_vert_regs[i]);
+ }
+ }
+
+}
+
+
+static void
+nv_output_save (xf86OutputPtr output)
+{
+ ScrnInfoPtr pScrn = output->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+ RIVA_HW_STATE *state;
+
+ state = &pNv->SavedReg;
+
+ nv_output_save_state_ext(output, state);
+
+}
+
+static void
+nv_output_restore (xf86OutputPtr output)
+{
+ ScrnInfoPtr pScrn = output->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+ RIVA_HW_STATE *state;
+
+ state = &pNv->SavedReg;
+
+ nv_output_load_state_ext(output, state);
+}
+
+static int
+nv_output_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
+{
+ if (pMode->Flags & V_DBLSCAN)
+ return MODE_NO_DBLESCAN;
+
+ if (pMode->Clock > 400000 || pMode->Clock < 25000)
+ return MODE_CLOCK_RANGE;
+
+ return MODE_OK;
+}
+
+
+static Bool
+nv_output_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
+ DisplayModePtr adjusted_mode)
+{
+ return TRUE;
+}
+
+static int
+nv_output_tweak_panel(xf86OutputPtr output, NVRegPtr state)
+{
+ NVOutputPrivatePtr nv_output = output->driver_private;
+ ScrnInfoPtr pScrn = output->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+ NVOutputRegPtr regp;
+ int tweak = 0;
+
+ regp = &state->dac_reg[nv_output->ramdac];
+ if (pNv->usePanelTweak) {
+ tweak = pNv->PanelTweak;
+ } else {
+ /* begin flat panel hacks */
+ /* This is unfortunate, but some chips need this register
+ tweaked or else you get artifacts where adjacent pixels are
+ swapped. There are no hard rules for what to set here so all
+ we can do is experiment and apply hacks. */
+
+ if(((pNv->Chipset & 0xffff) == 0x0328) && (regp->bpp == 32)) {
+ /* At least one NV34 laptop needs this workaround. */
+ tweak = -1;
+ }
+
+ if((pNv->Chipset & 0xfff0) == CHIPSET_NV31) {
+ tweak = 1;
+ }
+ /* end flat panel hacks */
+ }
+ return tweak;
+}
+
+static void
+nv_output_mode_set_regs(xf86OutputPtr output, DisplayModePtr mode)
+{
+ NVOutputPrivatePtr nv_output = output->driver_private;
+ ScrnInfoPtr pScrn = output->scrn;
+ int bpp;
+ NVPtr pNv = NVPTR(pScrn);
+ NVFBLayout *pLayout = &pNv->CurrentLayout;
+ RIVA_HW_STATE *state, *sv_state;
+ Bool is_fp = FALSE;
+ NVOutputRegPtr regp, savep;
+ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
+ int i;
+
+ state = &pNv->ModeReg;
+ regp = &state->dac_reg[nv_output->ramdac];
+
+ sv_state = &pNv->SavedReg;
+ savep = &sv_state->dac_reg[nv_output->ramdac];
+
+ if ((nv_output->type == OUTPUT_PANEL) || (nv_output->type == OUTPUT_DIGITAL))
+ {
+ is_fp = TRUE;
+
+ for (i = 0; i < 7; i++) {
+ regp->fp_horiz_regs[i] = savep->fp_horiz_regs[i];
+ regp->fp_vert_regs[i] = savep->fp_vert_regs[i];
+ }
+
+ regp->fp_horiz_regs[REG_DISP_END] = mode->CrtcHDisplay - 1;
+ regp->fp_horiz_regs[REG_DISP_TOTAL] = mode->CrtcHTotal - 1;
+ regp->fp_horiz_regs[REG_DISP_CRTC] = mode->CrtcHDisplay;
+ regp->fp_horiz_regs[REG_DISP_SYNC_START] = mode->CrtcHSyncStart - 1;
+ regp->fp_horiz_regs[REG_DISP_SYNC_END] = mode->CrtcHSyncEnd - 1;
+ regp->fp_horiz_regs[REG_DISP_VALID_START] = mode->CrtcHSkew;
+ regp->fp_horiz_regs[REG_DISP_VALID_END] = mode->CrtcHDisplay - 1;
+
+ regp->fp_vert_regs[REG_DISP_END] = mode->CrtcVDisplay - 1;
+ regp->fp_vert_regs[REG_DISP_TOTAL] = mode->CrtcVTotal - 1;
+ regp->fp_vert_regs[REG_DISP_CRTC] = mode->CrtcVDisplay;
+ regp->fp_vert_regs[REG_DISP_SYNC_START] = mode->CrtcVSyncStart - 1;
+ regp->fp_vert_regs[REG_DISP_SYNC_END] = mode->CrtcVSyncEnd - 1;
+ regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
+ regp->fp_vert_regs[REG_DISP_VALID_END] = mode->CrtcVDisplay - 1;
+
+ }
+
+ if (pNv->Architecture >= NV_ARCH_10)
+ regp->nv10_cursync = savep->nv10_cursync | (1<<25);
+
+ regp->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
+
+ regp->debug_0 = savep->debug_0;
+ regp->fp_control = savep->fp_control & 0xfff000ff;
+ if(is_fp == 1) {
+ if(!pNv->fpScaler || (nv_output->fpWidth <= mode->HDisplay)
+ || (nv_output->fpHeight <= mode->VDisplay))
+ {
+ regp->fp_control |= (1 << 8) ;
+ }
+ regp->crtcSync = savep->crtcSync;
+ regp->crtcSync += nv_output_tweak_panel(output, state);
+
+ regp->debug_0 &= ~NV_RAMDAC_FP_DEBUG_0_PWRDOWN_BOTH;
+ }
+ else
+ regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_BOTH;
+
+ ErrorF("output %d debug_0 %08X\n", nv_output->ramdac, regp->debug_0);
+
+ if(pNv->twoHeads) {
+ if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
+ regp->dither = savep->dither & ~0x00010000;
+ if(pNv->FPDither)
+ regp->dither |= 0x00010000;
+ } else {
+ ErrorF("savep->dither %08X\n", savep->dither);
+ regp->dither = savep->dither & ~1;
+ if(pNv->FPDither)
+ regp->dither |= 1;
+ }
+ }
+
+ if(pLayout->depth < 24)
+ bpp = pLayout->depth;
+ else bpp = 32;
+
+ regp->general = bpp == 16 ? 0x00101100 : 0x00100100;
+
+ if (pNv->alphaCursor)
+ regp->general |= (1<<29);
+
+ if(bpp != 8) /* DirectColor */
+ regp->general |= 0x00000030;
+
+ if (output->crtc) {
+ NVCrtcPrivatePtr nv_crtc = output->crtc->driver_private;
+ int two_crt = FALSE;
+ int two_mon = FALSE;
+
+ for (i = 0; i < config->num_output; i++) {
+ NVOutputPrivatePtr nv_output2 = config->output[i]->driver_private;
+
+ /* is it this output ?? */
+ if (config->output[i] == output)
+ continue;
+
+ /* it the output connected */
+ if (config->output[i]->crtc == NULL)
+ continue;
+
+ two_mon = TRUE;
+ if ((nv_output2->type == OUTPUT_ANALOG) && (nv_output->type == OUTPUT_ANALOG))
+ two_crt = TRUE;
+ }
+
+ if (is_fp == TRUE)
+ regp->output = 0x0;
+ else
+ regp->output = NV_RAMDAC_OUTPUT_DAC_ENABLE;
+
+ if (nv_crtc->crtc == 1 && two_mon)
+ regp->output |= NV_RAMDAC_OUTPUT_SELECT_CRTC2;
+
+ ErrorF("%d: crtc %d output%d: %04X: twocrt %d twomon %d\n", is_fp, nv_crtc->crtc, nv_output->ramdac, regp->output, two_crt, two_mon);
+ }
+}
+
+static void
+nv_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
+ DisplayModePtr adjusted_mode)
+{
+ ScrnInfoPtr pScrn = output->scrn;
+ NVPtr pNv = NVPTR(pScrn);
+ RIVA_HW_STATE *state;
+
+ state = &pNv->ModeReg;
+
+ nv_output_mode_set_regs(output, mode);
+ nv_output_load_state_ext(output, state);
+}
+
+static Bool
+nv_ddc_detect(xf86OutputPtr output)
+{
+ /* no use for shared DDC output */
+ NVOutputPrivatePtr nv_output = output->driver_private;
+ xf86MonPtr ddc_mon;
+
+ ddc_mon = xf86OutputGetEDID(output, nv_output->pDDCBus);
+ if (!ddc_mon)
+ return 0;
+
+ if (ddc_mon->features.input_type && (nv_output->type == OUTPUT_ANALOG))
+ return 0;
+
+ if ((!ddc_mon->features.input_type) && (nv_output->type == OUTPUT_DIGITAL))
+ return 0;
+
+ return 1;
+}
+
+static Bool
+nv_crt_load_detect(xf86OutputPtr output)
+{
+ ScrnInfoPtr pScrn = output->scrn;
+ CARD32 reg_output, reg_test_ctrl, temp;
+ int present = FALSE;
+
+ reg_output = NVOutputReadRAMDAC(output, NV_RAMDAC_OUTPUT);
+ reg_test_ctrl = NVOutputReadRAMDAC(output, NV_RAMDAC_TEST_CONTROL);
+
+ NVOutputWriteRAMDAC(output, NV_RAMDAC_TEST_CONTROL, (reg_test_ctrl & ~0x00010000));
+
+ NVOutputWriteRAMDAC(output, NV_RAMDAC_OUTPUT, (reg_output & 0x0000FEEE));
+ usleep(1000);
+
+ temp = NVOutputReadRAMDAC(output, NV_RAMDAC_OUTPUT);
+ NVOutputWriteRAMDAC(output, NV_RAMDAC_OUTPUT, temp | 1);
+
+ NVOutputWriteRAMDAC(output, NV_RAMDAC_TEST_DATA, 0x94050140);
+ temp = NVOutputReadRAMDAC(output, NV_RAMDAC_TEST_CONTROL);
+ NVOutputWriteRAMDAC(output, NV_RAMDAC_TEST_CONTROL, temp | 0x1000);
+
+ usleep(1000);
+
+ present = (NVOutputReadRAMDAC(output, NV_RAMDAC_TEST_CONTROL) & (1 << 28)) ? TRUE : FALSE;
+
+ temp = NVOutputReadRAMDAC(output, NV_RAMDAC_TEST_CONTROL);
+ NVOutputWriteRAMDAC(output, NV_RAMDAC_TEST_CONTROL, temp & 0x000EFFF);
+
+ NVOutputWriteRAMDAC(output, NV_RAMDAC_OUTPUT, reg_output);
+ NVOutputWriteRAMDAC(output, NV_RAMDAC_TEST_CONTROL, reg_test_ctrl);
+
+ xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "CRT detect returned %d\n",
+ present);
+
+ return present;
+
+}
+
+static xf86OutputStatus
+nv_digital_output_detect(xf86OutputPtr output)
+{
+ NVOutputPrivatePtr nv_output = output->driver_private;
+
+ if (nv_ddc_detect(output))
+ return XF86OutputStatusConnected;
+
+ return XF86OutputStatusDisconnected;
+}
+
+
+static xf86OutputStatus
+nv_analog_output_detect(xf86OutputPtr output)
+{
+ NVOutputPrivatePtr nv_output = output->driver_private;
+
+ if (nv_ddc_detect(output))
+ return XF86OutputStatusConnected;
+
+ /* seems a bit flaky on ramdac 1 */
+ if ((nv_output->ramdac==0) && nv_crt_load_detect(output))
+ return XF86OutputStatusConnected;
+
+ return XF86OutputStatusDisconnected;
+}
+
+static DisplayModePtr
+nv_output_get_modes(xf86OutputPtr output)
+{
+ ScrnInfoPtr pScrn = output->scrn;
+ NVOutputPrivatePtr nv_output = output->driver_private;
+ xf86MonPtr ddc_mon;
+ DisplayModePtr ddc_modes, mode;
+ int i;
+
+
+ ddc_mon = xf86OutputGetEDID(output, nv_output->pDDCBus);
+
+ if (ddc_mon == NULL) {
+ xf86OutputSetEDID(output, ddc_mon);
+ return NULL;
+ }
+
+ if (ddc_mon->features.input_type && (nv_output->type == OUTPUT_ANALOG)) {
+ xf86OutputSetEDID(output, NULL);
+ return NULL;
+ }
+
+ if ((!ddc_mon->features.input_type) && (nv_output->type == OUTPUT_DIGITAL)) {
+ xf86OutputSetEDID(output, NULL);
+ return NULL;
+ }
+
+ xf86OutputSetEDID(output, ddc_mon);
+
+ ddc_modes = xf86OutputGetEDIDModes (output);
+ return ddc_modes;
+
+}
+
+static void
+nv_output_destroy (xf86OutputPtr output)
+{
+ if (output->driver_private)
+ xfree (output->driver_private);
+
+}
+
+static void
+nv_output_prepare(xf86OutputPtr output)
+{
+
+}
+
+static void
+nv_output_commit(xf86OutputPtr output)
+{
+
+
+}
+
+static const xf86OutputFuncsRec nv_analog_output_funcs = {
+ .dpms = nv_analog_output_dpms,
+ .save = nv_output_save,
+ .restore = nv_output_restore,
+ .mode_valid = nv_output_mode_valid,
+ .mode_fixup = nv_output_mode_fixup,
+ .mode_set = nv_output_mode_set,
+ .detect = nv_analog_output_detect,
+ .get_modes = nv_output_get_modes,
+ .destroy = nv_output_destroy,
+ .prepare = nv_output_prepare,
+ .commit = nv_output_commit,
+};
+
+static const xf86OutputFuncsRec nv_digital_output_funcs = {
+ .dpms = nv_digital_output_dpms,
+ .save = nv_output_save,
+ .restore = nv_output_restore,
+ .mode_valid = nv_output_mode_valid,
+ .mode_fixup = nv_output_mode_fixup,
+ .mode_set = nv_output_mode_set,
+ .detect = nv_digital_output_detect,
+ .get_modes = nv_output_get_modes,
+ .destroy = nv_output_destroy,
+ .prepare = nv_output_prepare,
+ .commit = nv_output_commit,
+};
+
+static xf86OutputStatus
+nv_output_lvds_detect(xf86OutputPtr output)
+{
+ return XF86OutputStatusUnknown;
+}
+
+static DisplayModePtr
+nv_output_lvds_get_modes(xf86OutputPtr output)
+{
+ ScrnInfoPtr pScrn = output->scrn;
+ NVOutputPrivatePtr nv_output = output->driver_private;
+
+ // nv_output->fpWidth = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_HDISP_END) + 1;
+ // nv_output->fpHeight = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_VDISP_END) + 1;
+ nv_output->fpSyncs = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_CONTROL) & 0x30000033;
+ // xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Panel size is %i x %i\n",
+ // nv_output->fpWidth, nv_output->fpHeight);
+
+ return NULL;
+
+}
+
+static const xf86OutputFuncsRec nv_lvds_output_funcs = {
+ .dpms = nv_panel_output_dpms,
+ .save = nv_output_save,
+ .restore = nv_output_restore,
+ .mode_valid = nv_output_mode_valid,
+ .mode_fixup = nv_output_mode_fixup,
+ .mode_set = nv_output_mode_set,
+ .detect = nv_output_lvds_detect,
+ .get_modes = nv_output_lvds_get_modes,
+ .destroy = nv_output_destroy,
+ .prepare = nv_output_prepare,
+ .commit = nv_output_commit,
+};
+
+
+static void nv_add_analog_output(ScrnInfoPtr pScrn, int i2c_index)
+{
+ NVPtr pNv = NVPTR(pScrn);
+ xf86OutputPtr output;
+ NVOutputPrivatePtr nv_output;
+ char outputname[20];
+ int crtc_mask = (1<<0) | (1<<1);
+
+ sprintf(outputname, "Analog-%d", pNv->analog_count);
+ output = xf86OutputCreate (pScrn, &nv_analog_output_funcs, outputname);
+ if (!output)
+ return;
+ nv_output = xnfcalloc (sizeof (NVOutputPrivateRec), 1);
+ if (!nv_output)
+ {
+ xf86OutputDestroy (output);
+ return;
+ }
+
+ output->driver_private = nv_output;
+ nv_output->type = OUTPUT_ANALOG;
+
+ nv_output->ramdac = pNv->analog_count;
+
+ nv_output->pDDCBus = pNv->pI2CBus[i2c_index];
+
+ output->possible_crtcs = crtc_mask;
+ xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Adding output %s\n", outputname);
+
+ pNv->analog_count++;
+}
+
+
+static void nv_add_digital_output(ScrnInfoPtr pScrn, int i2c_index)
+{
+ NVPtr pNv = NVPTR(pScrn);
+ xf86OutputPtr output;
+ NVOutputPrivatePtr nv_output;
+ char outputname[20];
+ int crtc_mask = (1<<0) | (1<<1);
+
+ sprintf(outputname, "Digital-%d", pNv->digital_count);
+ output = xf86OutputCreate (pScrn, &nv_digital_output_funcs, outputname);
+ if (!output)
+ return;
+ nv_output = xnfcalloc (sizeof (NVOutputPrivateRec), 1);
+ if (!nv_output)
+ {
+ xf86OutputDestroy (output);
+ return;
+ }
+
+ output->driver_private = nv_output;
+ nv_output->type = OUTPUT_DIGITAL;
+
+ nv_output->ramdac = pNv->digital_count;
+
+ nv_output->pDDCBus = pNv->pI2CBus[i2c_index];
+
+ output->possible_crtcs = crtc_mask;
+ xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Adding output %s\n", outputname);
+
+ pNv->digital_count++;
+}
+/**
+ * Set up the outputs according to what type of chip we are.
+ *
+ * Some outputs may not initialize, due to allocation failure or because a
+ * controller chip isn't found.
+ */
+
+void Nv20SetupOutputs(ScrnInfoPtr pScrn)
+{
+ NVPtr pNv = NVPTR(pScrn);
+ xf86OutputPtr output;
+ NVOutputPrivatePtr nv_output;
+ int i;
+ int num_analog_outputs = pNv->twoHeads ? 2 : 1;
+ int num_digital_outputs = 1;
+
+ for (i = 0 ; i < num_analog_outputs; i++) {
+ nv_add_analog_output(pScrn, i);
+ }
+
+ for (i = 0 ; i < num_digital_outputs; i++) {
+ nv_add_digital_output(pScrn, i);
+ }
+}
+
+void NvDCBSetupOutputs(ScrnInfoPtr pScrn)
+{
+ unsigned char type, port, or;
+ NVPtr pNv = NVPTR(pScrn);
+ int i;
+
+ /* we setup the outputs up from the BIOS table */
+ if (pNv->dcb_entries) {
+ for (i = 0 ; i < pNv->dcb_entries; i++) {
+ type = pNv->dcb_table[i] & 0xf;
+ port = (pNv->dcb_table[i] >> 4) & 0xf;
+ or = ffs((pNv->dcb_table[i] >> 24) & 0xf) - 1;
+
+ if (type < 4)
+ xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "DCB entry: %d: %08X type: %d, port %d:, or %d\n", i, pNv->dcb_table[i], type, port, or);
+ if (type < 4 && port != 0xf) {
+ switch(type) {
+ case 0: /* analog */
+ nv_add_analog_output(pScrn, port);
+ break;
+ case 2:
+ nv_add_digital_output(pScrn, port);
+ default:
+ break;
+ }
+ }
+ }
+ } else
+ Nv20SetupOutputs(pScrn);
+
+}
+
+struct nv_i2c_struct {
+ int reg;
+ char *name;
+} nv_i2c_buses[] = {
+ { 0x3e, "DDC1" },
+ { 0x36, "DDC2" },
+ { 0x50, "TV" },
+};
+
+
+void NvSetupOutputs(ScrnInfoPtr pScrn)
+{
+ int i;
+ NVPtr pNv = NVPTR(pScrn);
+ xf86OutputPtr output;
+ NVOutputPrivatePtr nv_output;
+
+ int num_outputs = pNv->twoHeads ? 2 : 1;
+ char outputname[20];
+ pNv->Television = FALSE;
+
+ /* add the 3 I2C buses */
+ for (i = 0; i < NV_I2C_BUSES; i++) {
+ NV_I2CInit(pScrn, &pNv->pI2CBus[i], nv_i2c_buses[i].reg, nv_i2c_buses[i].name);
+ }
+
+ NvDCBSetupOutputs(pScrn);
+
+#if 0
+ if (pNv->Mobile) {
+ output = xf86OutputCreate(pScrn, &nv_output_funcs, OutputType[OUTPUT_LVDS]);
+ if (!output)
+ return;
+
+ nv_output = xnfcalloc(sizeof(NVOutputPrivateRec), 1);
+ if (!nv_output) {
+ xf86OutputDestroy(output);
+ return;
+ }
+
+ output->driver_private = nv_output;
+ nv_output->type = output_type;
+
+ output->possible_crtcs = i ? 1 : crtc_mask;
+ }
+#endif
+}
+
+
+/*************************************************************************** \
+|* *|
+|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
+|* *|
+|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
+|* international laws. Users and possessors of this source code are *|
+|* hereby granted a nonexclusive, royalty-free copyright license to *|
+|* use this code in individual and commercial software. *|
+|* *|
+|* Any use of this source code must include, in the user documenta- *|
+|* tion and internal comments to the code, notices to the end user *|
+|* as follows: *|
+|* *|
+|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
+|* *|
+|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
+|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
+|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
+|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
+|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
+|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
+|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
+|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
+|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
+|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
+|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
+|* *|
+|* U.S. Government End Users. This source code is a "commercial *|
+|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
+|* consisting of "commercial computer software" and "commercial *|
+|* computer software documentation," as such terms are used in *|
+|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
+|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
+|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
+|* all U.S. Government End Users acquire the source code with only *|
+|* those rights set forth herein. *|
+|* *|
+ \***************************************************************************/
diff --git a/src/nv_proto.h b/src/nv_proto.h
index 83748c4..d1075b2 100644
--- a/src/nv_proto.h
+++ b/src/nv_proto.h
@@ -37,17 +37,6 @@ Bool NVDRIFinishScreenInit(ScrnInfoPtr pScrn);
extern const char *drmSymbols[], *driSymbols[];
Bool NVDRIGetVersion(ScrnInfoPtr pScrn);
-/* in nv_dac.c */
-Bool NVDACInit(ScrnInfoPtr pScrn, DisplayModePtr mode);
-void NVDACSave(ScrnInfoPtr pScrn, vgaRegPtr vgaReg,
- NVRegPtr nvReg, Bool saveFonts);
-void NVDACRestore(ScrnInfoPtr pScrn, vgaRegPtr vgaReg,
- NVRegPtr nvReg, Bool restoreFonts);
-void NVDACLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices,
- LOCO *colors, VisualPtr pVisual );
-Bool NVDACi2cInit(ScrnInfoPtr pScrn);
-
-
/* in nv_video.c */
void NVInitVideo(ScreenPtr);
void NVResetVideo (ScrnInfoPtr pScrnInfo);
@@ -81,8 +70,6 @@ void NVCalcStateExt(NVPtr,struct _riva_hw_state *,int,int,int,int,int,int);
void NVLoadStateExt(ScrnInfoPtr pScrn,struct _riva_hw_state *);
void NVUnloadStateExt(NVPtr,struct _riva_hw_state *);
void NVSetStartAddress(NVPtr,CARD32);
-int NVShowHideCursor(NVPtr,int);
-void NVLockUnlock(NVPtr,int);
uint8_t nvReadVGA(NVPtr pNv, uint8_t index);
void nvWriteVGA(NVPtr pNv, uint8_t index, uint8_t data);
void nvWriteRAMDAC(NVPtr pNv, uint8_t head, uint32_t ramdac_reg, CARD32 val);
@@ -100,6 +87,43 @@ void NVPointerMoved(int index, int x, int y);
/* in nv_bios.c */
unsigned int NVParseBios(ScrnInfoPtr pScrn);
+void nForceUpdateArbitrationSettings (unsigned VClk, unsigned pixelDepth,
+ unsigned *burst, unsigned *lwm,
+ NVPtr pNv);
+
+
+/* nv_crtc.c */
+Bool NVSetMode(ScrnInfoPtr pScrn, DisplayModePtr pMode, Rotation rotation);
+Bool NVCrtcSetMode(xf86CrtcPtr crtc, DisplayModePtr pMode, Rotation rotation, int x, int y);
+DisplayModePtr NVCrtcFindClosestMode(xf86CrtcPtr crtc, DisplayModePtr pMode);
+void NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y);
+void NVCrtcLoadPalette(xf86CrtcPtr crtc);
+void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on);
+
+/* nv_hw.c */
+void nForceUpdateArbitrationSettings (unsigned VClk, unsigned pixelDepth,
+ unsigned *burst, unsigned *lwm,
+ NVPtr pNv);
+void nv30UpdateArbitrationSettings (NVPtr pNv,
+ unsigned *burst,
+ unsigned *lwm);
+void nv10UpdateArbitrationSettings (unsigned VClk,
+ unsigned pixelDepth,
+ unsigned *burst,
+ unsigned *lwm,
+ NVPtr pNv);
+void nv4UpdateArbitrationSettings (unsigned VClk,
+ unsigned pixelDepth,
+ unsigned *burst,
+ unsigned *lwm,
+ NVPtr pNv);
+
+void NVInitSurface(ScrnInfoPtr pScrn, RIVA_HW_STATE *state);
+void NVInitGraphContext(ScrnInfoPtr pScrn);
+
+/* nv_i2c.c */
+Bool NV_I2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg, char *name);
+
/* in nv30_exa.c */
Bool NVAccelInitNV40TCL(ScrnInfoPtr pScrn);
Bool NV30EXACheckComposite(int, PicturePtr, PicturePtr, PicturePtr);
diff --git a/src/nv_setup.c b/src/nv_setup.c
index 8af34c1..310f46f 100644
--- a/src/nv_setup.c
+++ b/src/nv_setup.c
@@ -42,6 +42,8 @@
#include "nv_include.h"
#include "nvreg.h"
+CARD32 debug_offset;
+
/*
* Override VGA I/O routines.
*/
@@ -178,50 +180,6 @@ static CARD8 NVReadDacData(vgaHWPtr pVga)
return (VGA_RD08(ptr, VGA_DAC_DATA));
}
-static Bool
-NVIsConnected (ScrnInfoPtr pScrn, int output)
-{
- NVPtr pNv = NVPTR(pScrn);
- CARD32 reg52C, reg608, temp;
- Bool present;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Probing for analog device on output %s...\n",
- output ? "B" : "A");
-
- reg52C = nvReadRAMDAC(pNv, output, NV_RAMDAC_052C);
- reg608 = nvReadRAMDAC(pNv, output, NV_RAMDAC_TEST_CONTROL);
-
- nvWriteRAMDAC(pNv, output, NV_RAMDAC_TEST_CONTROL, (reg608 & ~0x00010000));
-
- nvWriteRAMDAC(pNv, output, NV_RAMDAC_052C, (reg52C & 0x0000FEEE));
- usleep(1000);
-
- temp = nvReadRAMDAC(pNv, output, NV_RAMDAC_052C);
- nvWriteRAMDAC(pNv, output, NV_RAMDAC_052C, temp | 1);
-
- nvWriteRAMDAC(pNv, output, NV_RAMDAC_TEST_DATA, 0x94050140);
- temp = nvReadRAMDAC(pNv, output, NV_RAMDAC_TEST_CONTROL);
- nvWriteRAMDAC(pNv, output, NV_RAMDAC_TEST_CONTROL, temp | 0x1000);
-
- usleep(1000);
-
- present = (nvReadRAMDAC(pNv, output, NV_RAMDAC_TEST_CONTROL) & (1 << 28)) ? TRUE : FALSE;
-
- if(present)
- xf86DrvMsg(pScrn->scrnIndex, X_PROBED, " ...found one\n");
- else
- xf86DrvMsg(pScrn->scrnIndex, X_PROBED, " ...can't find one\n");
-
- temp = nvReadRAMDAC(pNv, output, NV_RAMDAC_TEST_CONTROL);
- nvWriteRAMDAC(pNv, output, NV_RAMDAC_TEST_CONTROL, temp & 0x000EFFF);
-
- nvWriteRAMDAC(pNv, output, NV_RAMDAC_052C, reg52C);
- nvWriteRAMDAC(pNv, output, NV_RAMDAC_TEST_CONTROL, reg608);
-
- return present;
-}
-
static void
NVSelectHeadRegisters(ScrnInfoPtr pScrn, int head)
{
@@ -230,32 +188,6 @@ NVSelectHeadRegisters(ScrnInfoPtr pScrn, int head)
pNv->cur_head = head;
}
-static xf86MonPtr
-NVProbeDDC (ScrnInfoPtr pScrn, int bus)
-{
- NVPtr pNv = NVPTR(pScrn);
- xf86MonPtr MonInfo = NULL;
-
- if(!pNv->I2C) return NULL;
-
- pNv->DDCBase = bus ? 0x36 : 0x3e;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Probing for EDID on I2C bus %s...\n", bus ? "B" : "A");
-
- if ((MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, pNv->I2C))) {
- xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
- "DDC detected a %s:\n", MonInfo->features.input_type ?
- "DFP" : "CRT");
- xf86PrintEDID( MonInfo );
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " ... none found\n");
- }
-
- return MonInfo;
-}
-
static void nv3GetConfig (NVPtr pNv)
{
CARD32 reg_FB0 = nvReadFB(pNv, 0x0);
@@ -352,12 +284,6 @@ NVCommonSetup(ScrnInfoPtr pScrn)
NVPtr pNv = NVPTR(pScrn);
vgaHWPtr pVga = VGAHWPTR(pScrn);
CARD16 implementation = pNv->Chipset & 0x0ff0;
- xf86MonPtr monitorA, monitorB;
- Bool mobile = FALSE;
- Bool tvA = FALSE;
- Bool tvB = FALSE;
- int FlatPanel = -1; /* really means the CRTC is slaved */
- Bool Television = FALSE;
/*
* Override VGA I/O routines.
@@ -390,7 +316,8 @@ NVCommonSetup(ScrnInfoPtr pScrn)
pNv->REGS = xf86MapPciMem(pScrn->scrnIndex,
VIDMEM_MMIO | VIDMEM_READSIDEEFFECT,
pNv->PciTag, pNv->IOAddress, 0x01000000);
-
+
+ debug_offset = pNv->REGS;
pNv->PRAMIN = pNv->REGS + (NV_PRAMIN_OFFSET/4);
pNv->PCRTC0 = pNv->REGS + (NV_PCRTC0_OFFSET/4);
pNv->PRAMDAC0 = pNv->REGS + (NV_PRAMDAC0_OFFSET/4);
@@ -430,6 +357,28 @@ NVCommonSetup(ScrnInfoPtr pScrn)
pNv->BlendingPossible = ((pNv->Chipset & 0xffff) > CHIPSET_NV04);
+
+
+ /* Parse the bios to initialize the card */
+ NVSelectHeadRegisters(pScrn, 0);
+ NVParseBios(pScrn);
+ /* reset PFIFO and PGRAPH, then power up all the card units */
+ nvWriteMC(pNv, 0x200, 0x17110013);
+ usleep(1000);
+ nvWriteMC(pNv, 0x200, 0x17111113);
+
+ if(pNv->Architecture == NV_ARCH_03)
+ nv3GetConfig(pNv);
+ else if(pNv->Architecture == NV_ARCH_04)
+ nv4GetConfig(pNv);
+ else
+ nv10GetConfig(pNv);
+
+ NVSelectHeadRegisters(pScrn, 0);
+
+ pNv->vtOWNER = nvReadVGA(pNv, NV_VGA_CRTCX_OWNER);
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vtowner is %d\n", pNv->vtOWNER);
/* look for known laptop chips */
/* FIXME we could add some ids here (0x0164,0x0167,0x0168,0x01D6,0x01D7,0x01D8,0x0298,0x0299,0x0398) */
switch(pNv->Chipset & 0xffff) {
@@ -479,34 +428,27 @@ NVCommonSetup(ScrnInfoPtr pScrn)
case 0x0148:
case 0x0098:
case 0x0099:
- mobile = TRUE;
+ pNv->Mobile = TRUE;
break;
default:
break;
}
- /* Parse the bios to initialize the card */
- NVSelectHeadRegisters(pScrn, 0);
- NVParseBios(pScrn);
- /* reset PFIFO and PGRAPH, then power up all the card units */
- nvWriteMC(pNv, 0x200, 0x17110013);
- usleep(1000);
- nvWriteMC(pNv, 0x200, 0x17111113);
-
- if(pNv->Architecture == NV_ARCH_03)
- nv3GetConfig(pNv);
- else if(pNv->Architecture == NV_ARCH_04)
- nv4GetConfig(pNv);
- else
- nv10GetConfig(pNv);
-
- NVSelectHeadRegisters(pScrn, 0);
-
- NVLockUnlock(pNv, 0);
+ pNv->Television = FALSE;
- NVI2CInit(pScrn);
+}
- pNv->Television = FALSE;
+#if 0
+void NVPreInitOldCode(ScrnInfoPtr pScrn)
+{
+ NVPtr pNv = NVPTR(pScrn);
+ xf86MonPtr monitorA, monitorB;
+ Bool mobile = pNv->Mobile;
+ Bool tvA = FALSE;
+ Bool tvB = FALSE;
+ int FlatPanel = -1; /* really means the CRTC is slaved */
+ Bool Television = FALSE;
+ CARD16 implementation = pNv->Chipset & 0x0ff0;
if(!pNv->twoHeads) {
pNv->CRTCnumber = 0;
@@ -736,3 +678,4 @@ NVCommonSetup(ScrnInfoPtr pScrn)
}
}
+#endif
diff --git a/src/nv_type.h b/src/nv_type.h
index 774300a..3be97ad 100644
--- a/src/nv_type.h
+++ b/src/nv_type.h
@@ -15,6 +15,7 @@
#include "dri.h"
#include <stdint.h>
#include "nouveau_drm.h"
+#include "xf86Crtc.h"
#else
#error "This driver requires a DRI-enabled X server"
#endif
@@ -69,6 +70,18 @@
#define SetBit(n) (1<<(n))
#define Set8Bits(value) ((value)&0xff)
+#define NV_I2C_BUSES 3
+#define NV40_NUM_DCB_ENTRIES 10
+
+typedef enum
+{
+ OUTPUT_NONE,
+ OUTPUT_ANALOG,
+ OUTPUT_DIGITAL,
+ OUTPUT_PANEL,
+ OUTPUT_TV,
+} NVOutputType;
+
typedef struct {
int bitsPerPixel;
int depth;
@@ -77,21 +90,37 @@ typedef struct {
DisplayModePtr mode;
} NVFBLayout;
-typedef struct _riva_hw_state
+typedef struct _nv_crtc_reg
{
- CARD32 bpp;
- CARD32 width;
- CARD32 height;
- CARD32 interlace;
- CARD32 repaint0;
- CARD32 repaint1;
- CARD32 screen;
- CARD32 scale;
+ unsigned char MiscOutReg; /* */
+ CARD8 CRTC[90];
+ CARD8 Sequencer[5];
+ CARD8 Graphics[9];
+ CARD8 Attribute[21];
+ unsigned char DAC[768]; /* Internal Colorlookuptable */
+ CARD32 cursorConfig;
+ CARD32 crtcOwner;
+ CARD32 unk830;
+ CARD32 unk834;
+ CARD32 head;
+} NVCrtcRegRec, *NVCrtcRegPtr;
+
+typedef struct _nv_output_reg
+{
+ CARD32 fp_control;
+ CARD32 crtcSync;
CARD32 dither;
- CARD32 extra;
- CARD32 fifo;
- CARD32 pixel;
- CARD32 horiz;
+ CARD32 general;
+ CARD32 bpp;
+ CARD32 nv10_cursync;
+ CARD32 output;
+ CARD32 debug_0;
+ CARD32 fp_horiz_regs[7];
+ CARD32 fp_vert_regs[7];
+} NVOutputRegRec, *NVOutputRegPtr;
+
+typedef struct _riva_hw_state
+{
CARD32 arbitration0;
CARD32 arbitration1;
CARD32 pll;
@@ -101,19 +130,12 @@ typedef struct _riva_hw_state
CARD32 vpllB;
CARD32 vpll2B;
CARD32 pllsel;
- CARD32 general;
- CARD32 crtcOwner;
- CARD32 head;
- CARD32 head2;
CARD32 config;
- CARD32 cursorConfig;
- CARD32 cursor0;
- CARD32 cursor1;
- CARD32 cursor2;
+
CARD32 timingH;
CARD32 timingV;
- CARD32 displayV;
- CARD32 crtcSync;
+ NVCrtcRegRec crtc_reg[2];
+ NVOutputRegRec dac_reg[2];
} RIVA_HW_STATE, *NVRegPtr;
typedef struct {
@@ -123,6 +145,25 @@ typedef struct {
void *map;
} NVAllocRec;
+typedef struct _NVCrtcPrivateRec {
+ int crtc;
+ Bool paletteEnabled;
+} NVCrtcPrivateRec, *NVCrtcPrivatePtr;
+
+#define NVCrtcPrivate(c) ((NVCrtcPrivatePtr)(c)->driver_private)
+
+typedef struct _NVOutputPrivateRec {
+ int ramdac;
+ I2CBusPtr pDDCBus;
+ NVOutputType type;
+ CARD32 fpSyncs;
+ CARD32 fpWidth;
+ CARD32 fpHeight;
+ Bool fpdither;
+} NVOutputPrivateRec, *NVOutputPrivatePtr;
+
+#define NVOutputPrivate(o) ((NVOutputPrivatePtr (o)->driver_private)
+
typedef struct _NVRec *NVPtr;
typedef struct _NVRec {
RIVA_HW_STATE SavedReg;
@@ -136,6 +177,7 @@ typedef struct _NVRec {
int ChipRev;
Bool Primary;
CARD32 IOAddress;
+ Bool cursorOn;
/* VRAM physical address */
unsigned long VRAMPhysical;
@@ -152,6 +194,7 @@ typedef struct _NVRec {
NVAllocRec * Cursor;
NVAllocRec * ScratchBuffer;
NVAllocRec * AGPScratch;
+
Bool NoAccel;
Bool HWCursor;
Bool FpScale;
@@ -191,6 +234,7 @@ typedef struct _NVRec {
volatile CARD32 *RAMHT;
CARD32 pramin_free;
+ unsigned int SaveGeneration;
uint8_t cur_head;
XAAInfoRecPtr AccelInfoRec;
ExaDriverPtr EXADriverPtr;
@@ -205,7 +249,7 @@ typedef struct _NVRec {
CARD32 curFg, curBg;
CARD32 curImage[256];
/* I2C / DDC */
- I2CBusPtr I2C;
+ int ddc2;
xf86Int10InfoPtr pInt;
void (*VideoTimerCallback)(ScrnInfoPtr, Time);
void (*DMAKickoffCallback)(NVPtr pNv);
@@ -214,6 +258,7 @@ typedef struct _NVRec {
int videoKey;
int FlatPanel;
Bool FPDither;
+ int Mobile;
Bool Television;
int CRTCnumber;
int vtOWNER;
@@ -252,6 +297,16 @@ typedef struct _NVRec {
DRIInfoPtr pDRIInfo;
drmVersionPtr pLibDRMVersion;
drmVersionPtr pKernelDRMVersion;
+
+ CreateScreenResourcesProcPtr CreateScreenResources;
+
+ /* we know about 3 i2c buses */
+ I2CBusPtr pI2CBus[3];
+ int dcb_entries;
+
+ int analog_count;
+ int digital_count;
+ CARD32 dcb_table[NV40_NUM_DCB_ENTRIES]; /* 10 is a good limit */
} NVRec;
#define NVPTR(p) ((NVPtr)((p)->driverPrivate))
diff --git a/src/nv_xf86Rename.h b/src/nv_xf86Rename.h
new file mode 100644
index 0000000..cf8de62
--- /dev/null
+++ b/src/nv_xf86Rename.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright © 2006 Keith Packard
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission. The copyright holders make no representations
+ * about the suitability of this software for any purpose. It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+
+#ifndef _XF86RENAME_H_
+#define _XF86RENAME_H_
+
+#include "local_xf86Rename.h"
+
+#define xf86CrtcConfigInit XF86NAME(xf86CrtcConfigInit)
+#define xf86CrtcConfigPrivateIndex XF86NAME(xf86CrtcConfigPrivateIndex)
+#define xf86CrtcCreate XF86NAME(xf86CrtcCreate)
+#define xf86CrtcDestroy XF86NAME(xf86CrtcDestroy)
+#define xf86CrtcInUse XF86NAME(xf86CrtcInUse)
+#define xf86CrtcRotate XF86NAME(xf86CrtcRotate)
+#define xf86CrtcSetMode XF86NAME(xf86CrtcSetMode)
+#define xf86CrtcSetSizeRange XF86NAME(xf86CrtcSetSizeRange)
+#define xf86CVTMode XF86NAME(xf86CVTMode)
+#define xf86DisableUnusedFunctions XF86NAME(xf86DisableUnusedFunctions)
+#define xf86DPMSSet XF86NAME(xf86DPMSSet)
+#define xf86DuplicateMode XF86NAME(xf86DuplicateMode)
+#define xf86DuplicateModes XF86NAME(xf86DuplicateModes)
+#define xf86GetDefaultModes XF86NAME(xf86GetDefaultModes)
+#define xf86GetMonitorModes XF86NAME(xf86GetMonitorModes)
+#define xf86InitialConfiguration XF86NAME(xf86InitialConfiguration)
+#define xf86ModeHSync XF86NAME(xf86ModeHSync)
+#define xf86ModesAdd XF86NAME(xf86ModesAdd)
+#define xf86ModesEqual XF86NAME(xf86ModesEqual)
+#define xf86ModeVRefresh XF86NAME(xf86ModeVRefresh)
+#define xf86OutputCreate XF86NAME(xf86OutputCreate)
+#define xf86OutputDestroy XF86NAME(xf86OutputDestroy)
+#define xf86OutputGetEDID XF86NAME(xf86OutputGetEDID)
+#define xf86OutputGetEDIDModes XF86NAME(xf86OutputGetEDIDModes)
+#define xf86OutputRename XF86NAME(xf86OutputRename)
+#define xf86OutputSetEDID XF86NAME(xf86OutputSetEDID)
+#define xf86PrintModeline XF86NAME(xf86PrintModeline)
+#define xf86ProbeOutputModes XF86NAME(xf86ProbeOutputModes)
+#define xf86PruneInvalidModes XF86NAME(xf86PruneInvalidModes)
+#define xf86SetModeCrtc XF86NAME(xf86SetModeCrtc)
+#define xf86SetModeDefaultName XF86NAME(xf86SetModeDefaultName)
+#define xf86SetScrnInfoModes XF86NAME(xf86SetScrnInfoModes)
+#define xf86ValidateModesClocks XF86NAME(xf86ValidateModesClocks)
+#define xf86ValidateModesFlags XF86NAME(xf86ValidateModesFlags)
+#define xf86ValidateModesSize XF86NAME(xf86ValidateModesSize)
+#define xf86ValidateModesSync XF86NAME(xf86ValidateModesSync)
+#define xf86ValidateModesUserConfig XF86NAME(xf86ValidateModesUserConfig)
+
+#endif /* _XF86RENAME_H_ */
diff --git a/src/nvreg.h b/src/nvreg.h
index 0cbe930..ca0f850 100644
--- a/src/nvreg.h
+++ b/src/nvreg.h
@@ -120,6 +120,7 @@
#define NV_VGA_CRTCX_FIFO_LWM_NV30 0x47
#define NV_VGA_CRTCX_FP_HTIMING 0x53
#define NV_VGA_CRTCX_FP_VTIMING 0x54
+#define NV_VGA_CRTCX_59 0x59
#define NV_PGRAPH_STATUS (0x00000700)
#define NV_PFIFO_RAMHT (0x00000210)
@@ -131,7 +132,7 @@
#define NV_RAMDAC_CURSOR_DATA_LO 0x324
#define NV_RAMDAC_CURSOR_DATA_HI 0x328
-#define NV_RAMDAC_0404 0x404
+#define NV_RAMDAC_NV10_CURSYNC 0x404
#define NV_RAMDAC_NVPLL 0x500
#define NV_RAMDAC_MPLL 0x504
@@ -141,9 +142,37 @@
#define NV_RAMDAC_VPLL 0x508
#define NV_RAMDAC_PLL_SELECT 0x50c
+#define NV_RAMDAC_PLL_SELECT_DLL_BYPASS (1<<4)
+#define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_DEFAULT (0<<8)
+#define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL (1<<8)
+#define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL (2<<8)
+#define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL (4<<8)
+#define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL (7<<8)
+#define NV_RAMDAC_PLL_SELECT_MPLL_BYPASS_FALSE (0<<12)
+#define NV_RAMDAC_PLL_SELECT_MPLL_BYPASS_TRUE (1<<12)
+#define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_NONE (0<<16)
+#define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_VSCLK (1<<16)
+#define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_PCLK (2<<16)
+#define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_BOTH (3<<16)
+
+#define NV_RAMDAC_PLL_SELECT_TVCLK_SOURCE_EXT (0<<20)
+#define NV_RAMDAC_PLL_SELECT_TVCLK_SOURCE_VIP (1<<20)
+
+#define NV_RAMDAC_PLL_SELECT_TVCLK_RATIO_DB1 (0<<24)
+#define NV_RAMDAC_PLL_SELECT_TVCLK_RATIO_DB2 (1<<24)
+#define NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB1 (0<<28)
+#define NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 (1<<28)
+
+
+#define NV_RAMDAC_PLL_SETUP_CONTROL 0x510
+#define NV_RAMDAC_PLL_TEST_COUNTER 0x514
+#define NV_RAMDAC_PALETTE_TEST 0x518
#define NV_RAMDAC_VPLL2 0x520
+#define NV_RAMDAC_SEL_CLK 0x524
#define NV_RAMDAC_DITHER_NV11 0x528
-#define NV_RAMDAC_052C 0x52c
+#define NV_RAMDAC_OUTPUT 0x52c
+#define NV_RAMDAC_OUTPUT_DAC_ENABLE (1<<0)
+#define NV_RAMDAC_OUTPUT_SELECT_CRTC2 (1<<8)
#define NV_RAMDAC_NVPLL_B 0x570
#define NV_RAMDAC_MPLL_B 0x574
@@ -154,14 +183,59 @@
#define NV_RAMDAC_TEST_CONTROL 0x608
#define NV_RAMDAC_TEST_DATA 0x610
+#define NV_RAMDAC_TV_SETUP 0x700
+#define NV_RAMDAC_TV_VBLANK_START 0x704
+#define NV_RAMDAC_TV_VBLANK_END 0x708
+#define NV_RAMDAC_TV_HBLANK_START 0x70c
+#define NV_RAMDAC_TV_HBLANK_END 0x710
+#define NV_RAMDAC_TV_BLANK_COLOR 0x714
+#define NV_RAMDAC_TV_VTOTAL 0x720
+#define NV_RAMDAC_TV_VSYNC_START 0x724
+#define NV_RAMDAC_TV_VSYNC_END 0x728
+#define NV_RAMDAC_TV_HTOTAL 0x72c
+#define NV_RAMDAC_TV_HSYNC_START 0x730
+#define NV_RAMDAC_TV_HSYNC_END 0x734
+#define NV_RAMDAC_TV_SYNC_DELAY 0x738
+
+#define REG_DISP_END 0
+#define REG_DISP_TOTAL 1
+#define REG_DISP_CRTC 2
+#define REG_DISP_SYNC_START 3
+#define REG_DISP_SYNC_END 4
+#define REG_DISP_VALID_START 5
+#define REG_DISP_VALID_END 6
+
#define NV_RAMDAC_FP_VDISP_END 0x800
+#define NV_RAMDAC_FP_VTOTAL 0x804
+#define NV_RAMDAC_FP_VCRTC 0x808
+#define NV_RAMDAC_FP_VSYNC_START 0x80c
+#define NV_RAMDAC_FP_VSYNC_END 0x810
+#define NV_RAMDAC_FP_VVALID_START 0x814
+#define NV_RAMDAC_FP_VVALID_END 0x818
#define NV_RAMDAC_FP_HDISP_END 0x820
+#define NV_RAMDAC_FP_HTOTAL 0x824
#define NV_RAMDAC_FP_HCRTC 0x828
+#define NV_RAMDAC_FP_HSYNC_START 0x82c
+#define NV_RAMDAC_FP_HSYNC_END 0x830
+#define NV_RAMDAC_FP_HVALID_START 0x834
+#define NV_RAMDAC_FP_HVALID_END 0x838
+
#define NV_RAMDAC_FP_DITHER 0x83c
+#define NV_RAMDAC_FP_CHECKSUM 0x840
+#define NV_RAMDAC_FP_TEST_CONTROL 0x844
#define NV_RAMDAC_FP_CONTROL 0x848
+#define NV_RAMDAC_FP_CONTROL_ENABLE (1<<28) // toggling this bit turns things on/off
+
+#define NV_RAMDAC_FP_DEBUG_0 0x880
+#define NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK (1<<28)
+#define NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL (2<<28)
+#define NV_RAMDAC_FP_DEBUG_0_PWRDOWN_BOTH (3<<28)
-#define NV_RAMDAC_FP_TMDS_DATA 0x8b0
-#define NV_RAMDAC_FP_TMDS_LVDS 0x8b4
+#define NV_RAMDAC_FP_TMDS_CONTROL 0x8b0
+/* 0xff - address mask */
+#define NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE (1<<16)
+#define NV_RAMDAC_FP_TMDS_DATA 0x8b4
+/* 0xff - data mask */
#define NV_CRTC_INTR_0 0x100
# define NV_CRTC_INTR_VBLANK 1
@@ -171,7 +245,13 @@
#define NV_CRTC_081C 0x81c
#define NV_CRTC_0830 0x830
#define NV_CRTC_0834 0x834
-#define NV_CRTC_HEAD_CONFIG 0x860
+#define NV_CRTC_FSEL 0x860
+#define NV_CRTC_FSEL_I2C (1<<4)
+#define NV_CRTC_FSEL_TVOUT1 (1<<8)
+#define NV_CRTC_FSEL_TVOUT2 (2<<8)
+#define NV_CRTC_FSEL_OVERLAY (1<<12)
+#define NV_CRTC_FSEL_FPP2 (1<<16)
+#define NV_CRTC_FSEL_FPP1 (2<<16)
#define NV_PFB_CFG0 0x200
#define NV_PFB_CFG1 0x204
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