diff options
-rw-r--r-- | src/nouveau_xv.c | 43 | ||||
-rw-r--r-- | src/nv04_accel.h | 6 | ||||
-rw-r--r-- | src/nv30_exa.c | 11 | ||||
-rw-r--r-- | src/nv30_shaders.c | 7 | ||||
-rw-r--r-- | src/nv30_xv_tex.c | 79 | ||||
-rw-r--r-- | src/nv40_exa.c | 12 | ||||
-rw-r--r-- | src/nv40_xv_tex.c | 81 | ||||
-rw-r--r-- | src/nv50_accel.c | 62 | ||||
-rw-r--r-- | src/nv50_accel.h | 2 | ||||
-rw-r--r-- | src/nv50_exa.c | 10 | ||||
-rw-r--r-- | src/nv50_xv.c | 16 | ||||
-rw-r--r-- | src/nv_accel_common.c | 14 | ||||
-rw-r--r-- | src/nv_proto.h | 1 | ||||
-rw-r--r-- | src/nv_type.h | 4 | ||||
-rw-r--r-- | src/nvc0_accel.c | 22 | ||||
-rw-r--r-- | src/nvc0_exa.c | 6 | ||||
-rw-r--r-- | src/nvc0_shader.h | 2 | ||||
-rw-r--r-- | src/nvc0_xv.c | 12 |
18 files changed, 129 insertions, 261 deletions
diff --git a/src/nouveau_xv.c b/src/nouveau_xv.c index 9ada296..aea6c39 100644 --- a/src/nouveau_xv.c +++ b/src/nouveau_xv.c @@ -2141,7 +2141,6 @@ NVTakedownVideo(ScrnInfoPtr pScrn) { NVPtr pNv = NVPTR(pScrn); - nouveau_bo_ref(NULL, &pNv->xv_filtertable_mem); if (pNv->blitAdaptor) NVFreePortMemory(pScrn, GET_BLIT_PRIVATE(pNv)); if (pNv->textureAdaptor[0]) { @@ -2154,3 +2153,45 @@ NVTakedownVideo(ScrnInfoPtr pScrn) } } +/* The filtering function used for video scaling. We use a cubic filter as + * defined in "Reconstruction Filters in Computer Graphics" Mitchell & + * Netravali in SIGGRAPH '88 + */ +static float filter_func(float x) +{ + const double B=0.75; + const double C=(1.0-B)/2.0; + double x1=fabs(x); + double x2=fabs(x)*x1; + double x3=fabs(x)*x2; + + if (fabs(x)<1.0) + return ( (12.0-9.0*B-6.0*C)*x3+(-18.0+12.0*B+6.0*C)*x2+(6.0-2.0*B) )/6.0; + else + return ( (-B-6.0*C)*x3+(6.0*B+30.0*C)*x2+(-12.0*B-48.0*C)*x1+(8.0*B+24.0*C) )/6.0; +} + +static int8_t f32tosb8(float v) +{ + return (int8_t)(v*127.0); +} + +void +NVXVComputeBicubicFilter(struct nouveau_bo *bo, unsigned offset, unsigned size) +{ + int8_t *t = (int8_t *)(bo->map + offset); + int i; + + for(i = 0; i < size; i++) { + float x = (i + 0.5) / size; + float w0 = filter_func(x+1.0); + float w1 = filter_func(x); + float w2 = filter_func(x-1.0); + float w3 = filter_func(x-2.0); + + t[4*i+2]=f32tosb8(1.0+x-w1/(w0+w1)); + t[4*i+1]=f32tosb8(1.0-x+w3/(w2+w3)); + t[4*i+0]=f32tosb8(w0+w1); + t[4*i+3]=f32tosb8(0.0); + } +} diff --git a/src/nv04_accel.h b/src/nv04_accel.h index d9d0822..e1b4d8f 100644 --- a/src/nv04_accel.h +++ b/src/nv04_accel.h @@ -1,6 +1,12 @@ #ifndef __NV04_ACCEL_H__ #define __NV04_ACCEL_H__ +#define XV_TABLE_SIZE 512 + +/* scratch buffer offsets */ +#define FRAGPROG 0x00000000 +#define XV_TABLE 0x00001000 + /* subchannel assignments */ #define SUBC_M2MF(mthd) 0, (mthd) #define NV03_M2MF(mthd) SUBC_M2MF(NV03_M2MF_##mthd) diff --git a/src/nv30_exa.c b/src/nv30_exa.c index 725a66a..7ac318c 100644 --- a/src/nv30_exa.c +++ b/src/nv30_exa.c @@ -629,10 +629,11 @@ NVAccelInitNV30TCL(ScrnInfoPtr pScrn) struct nouveau_pushbuf *push = pNv->pushbuf; struct nv04_fifo *fifo = pNv->channel->data; uint32_t class = 0, chipset; - int next_hw_offset = 0, i; + int next_hw_offset = FRAGPROG, i; if (!nv40_fp_map_a8[0]) NV30EXAHackupA8Shaders(pScrn); + NVXVComputeBicubicFilter(pNv->scratch, XV_TABLE, XV_TABLE_SIZE); #define NV30TCL_CHIPSET_3X_MASK 0x00000003 #define NV35TCL_CHIPSET_3X_MASK 0x000001e0 @@ -658,14 +659,6 @@ NVAccelInitNV30TCL(ScrnInfoPtr pScrn) if (nouveau_object_new(pNv->channel, Nv3D, class, NULL, 0, &pNv->Nv3D)) return FALSE; - if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_MAP, - 0, 0x1000, NULL, &pNv->shader_mem)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Couldn't alloc fragprog buffer!\n"); - nouveau_object_del(&pNv->Nv3D); - return FALSE; - } - if (!PUSH_SPACE(push, 256)) return FALSE; diff --git a/src/nv30_shaders.c b/src/nv30_shaders.c index baa70d7..6a72d8d 100644 --- a/src/nv30_shaders.c +++ b/src/nv30_shaders.c @@ -33,8 +33,7 @@ void NV30_UploadFragProg(NVPtr pNv, nv_shader_t *shader, int *hw_offset) shader->hw_id = *hw_offset; - nouveau_bo_map(pNv->shader_mem, NOUVEAU_BO_WR, pNv->client); - map = pNv->shader_mem->map + *hw_offset; + map = pNv->scratch->map + *hw_offset; for (i = 0; i < shader->size; i++) { data = shader->data[i]; #if (X_BYTE_ORDER != X_LITTLE_ENDIAN) @@ -73,7 +72,7 @@ NV30_LoadFragProg(ScrnInfoPtr pScrn, nv_shader_t *shader) struct nouveau_pushbuf *push = pNv->pushbuf; BEGIN_NV04(push, NV30_3D(FP_ACTIVE_PROGRAM), 1); - PUSH_MTHD (push, NV30_3D(FP_ACTIVE_PROGRAM), pNv->shader_mem, + PUSH_MTHD (push, NV30_3D(FP_ACTIVE_PROGRAM), pNv->scratch, shader->hw_id, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_LOW | NOUVEAU_BO_OR, NV30_3D_FP_ACTIVE_PROGRAM_DMA0, @@ -108,7 +107,7 @@ NV40_LoadFragProg(ScrnInfoPtr pScrn, nv_shader_t *shader) struct nouveau_pushbuf *push = pNv->pushbuf; BEGIN_NV04(push, NV30_3D(FP_ACTIVE_PROGRAM), 1); - PUSH_MTHD (push, NV30_3D(FP_ACTIVE_PROGRAM), pNv->shader_mem, + PUSH_MTHD (push, NV30_3D(FP_ACTIVE_PROGRAM), pNv->scratch, shader->hw_id, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW | NOUVEAU_BO_OR, NV30_3D_FP_ACTIVE_PROGRAM_DMA0, diff --git a/src/nv30_xv_tex.c b/src/nv30_xv_tex.c index 59d60b6..88fed3e 100644 --- a/src/nv30_xv_tex.c +++ b/src/nv30_xv_tex.c @@ -43,79 +43,6 @@ extern Atom xvSyncToVBlank, xvSetDefaults; -/* - * The filtering function used for video scaling. We use a cubic filter as defined in - * "Reconstruction Filters in Computer Graphics" - * Mitchell & Netravali in SIGGRAPH '88 - */ -static float filter_func(float x) -{ - const double B=0.75; - const double C=(1.0-B)/2.0; - double x1=fabs(x); - double x2=fabs(x)*x1; - double x3=fabs(x)*x2; - - if (fabs(x)<1.0) - return ( (12.0-9.0*B-6.0*C)*x3+(-18.0+12.0*B+6.0*C)*x2+(6.0-2.0*B) )/6.0; - else - return ( (-B-6.0*C)*x3+(6.0*B+30.0*C)*x2+(-12.0*B-48.0*C)*x1+(8.0*B+24.0*C) )/6.0; -} - -static int8_t f32tosb8(float v) -{ - return (int8_t)(v*127.0); -} - -/* - * 512 means 2048 bytes of VRAM - */ -#define TABLE_SIZE 512 -static void compute_filter_table(int8_t *t) { - int i; - float x; - for(i=0;i<TABLE_SIZE;i++) { - x=(i+0.5)/TABLE_SIZE; - - float w0=filter_func(x+1.0); - float w1=filter_func(x); - float w2=filter_func(x-1.0); - float w3=filter_func(x-2.0); - - t[4*i+2]=f32tosb8(1.0+x-w1/(w0+w1)); - t[4*i+1]=f32tosb8(1.0-x+w3/(w2+w3)); - t[4*i+0]=f32tosb8(w0+w1); - t[4*i+3]=f32tosb8(0.0); - } -} - -static void -NV30_LoadFilterTable(ScrnInfoPtr pScrn) -{ - NVPtr pNv = NVPTR(pScrn); - - if (!pNv->xv_filtertable_mem) { - if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | - NOUVEAU_BO_MAP, 0, - TABLE_SIZE * sizeof(float) * 4, NULL, - &pNv->xv_filtertable_mem)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Couldn't alloc filter table!\n"); - return; - } - - if (nouveau_bo_map(pNv->xv_filtertable_mem, NOUVEAU_BO_RDWR, - pNv->client)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Couldn't map filter table!\n"); - return; - } - - int8_t *t=pNv->xv_filtertable_mem->map; - compute_filter_table(t); - } -} - #define SWIZZLE(ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w) \ ( \ NV30_3D_TEX_SWIZZLE_S0_X_##ts0x | NV30_3D_TEX_SWIZZLE_S0_Y_##ts0y | \ @@ -307,14 +234,12 @@ NV30PutTextureImage(ScrnInfoPtr pScrn, struct nouveau_bo *src, int src_offset, PUSH_DATA (push, (y<<16)|x); } - NV30_LoadFilterTable(pScrn); - BEGIN_NV04(push, NV30_3D(TEX_UNITS_ENABLE), 1); PUSH_DATA (push, NV30_3D_TEX_UNITS_ENABLE_TX0 | NV30_3D_TEX_UNITS_ENABLE_TX1); - if (!NV30VideoTexture(pScrn, pNv->xv_filtertable_mem, 0, TABLE_SIZE, - 1, 0 , 0) || + if (!NV30VideoTexture(pScrn, pNv->scratch, XV_TABLE, XV_TABLE_SIZE, + 1, 0, 0) || !NV30VideoTexture(pScrn, src, src_offset, src_w, src_h, src_pitch, 1)) return BadImplementation; diff --git a/src/nv40_exa.c b/src/nv40_exa.c index bbf15aa..42fc428 100644 --- a/src/nv40_exa.c +++ b/src/nv40_exa.c @@ -580,10 +580,11 @@ NVAccelInitNV40TCL(ScrnInfoPtr pScrn) struct nouveau_pushbuf *push = pNv->pushbuf; struct nv04_fifo *fifo = pNv->channel->data; uint32_t class = 0, chipset; - int next_hw_id = 0, next_hw_offset = 0, i; + int next_hw_id = 0, next_hw_offset = FRAGPROG, i; if (!nv40_fp_map_a8[0]) NV40EXAHackupA8Shaders(pScrn); + NVXVComputeBicubicFilter(pNv->scratch, XV_TABLE, XV_TABLE_SIZE); chipset = pNv->dev->chipset; if ((chipset & 0xf0) == NV_ARCH_40) { @@ -605,15 +606,6 @@ NVAccelInitNV40TCL(ScrnInfoPtr pScrn) if (nouveau_object_new(pNv->channel, Nv3D, class, NULL, 0, &pNv->Nv3D)) return FALSE; - if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | - NOUVEAU_BO_MAP, 0, 0x1000, NULL, - &pNv->shader_mem)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Couldn't alloc fragprog buffer!\n"); - nouveau_object_del(&pNv->Nv3D); - return FALSE; - } - if (!PUSH_SPACE(push, 256)) return FALSE; diff --git a/src/nv40_xv_tex.c b/src/nv40_xv_tex.c index f0f7105..78dd0d6 100644 --- a/src/nv40_xv_tex.c +++ b/src/nv40_xv_tex.c @@ -43,81 +43,6 @@ extern Atom xvSyncToVBlank, xvSetDefaults; -/* - * The filtering function used for video scaling. We use a cubic filter as defined in - * "Reconstruction Filters in Computer Graphics" - * Mitchell & Netravali in SIGGRAPH '88 - */ -static float filter_func(float x) -{ - const double B=0.75; - const double C=(1.0-B)/2.0; - double x1=fabs(x); - double x2=fabs(x)*x1; - double x3=fabs(x)*x2; - - if (fabs(x)<1.0) - return ( (12.0-9.0*B-6.0*C)*x3+(-18.0+12.0*B+6.0*C)*x2+(6.0-2.0*B) )/6.0; - else - return ( (-B-6.0*C)*x3+(6.0*B+30.0*C)*x2+(-12.0*B-48.0*C)*x1+(8.0*B+24.0*C) )/6.0; -} - -static int8_t f32tosb8(float v) -{ - return (int8_t)(v*127.0); -} - -/* - * Implements the filtering as described in - * "Fast Third-Order Texture Filtering" - * Sigg & Hardwiger in GPU Gems 2 - */ -#define TABLE_SIZE 512 -static void compute_filter_table(int8_t *t) { - int i; - float x; - for(i=0;i<TABLE_SIZE;i++) { - x=(i+0.5)/TABLE_SIZE; - - float w0=filter_func(x+1.0); - float w1=filter_func(x); - float w2=filter_func(x-1.0); - float w3=filter_func(x-2.0); - - t[4*i+2]=f32tosb8(1.0+x-w1/(w0+w1)); - t[4*i+1]=f32tosb8(1.0-x+w3/(w2+w3)); - t[4*i+0]=f32tosb8(w0+w1); - t[4*i+3]=f32tosb8(0.0); - } -} - -static void -NV40_LoadFilterTable(ScrnInfoPtr pScrn) -{ - NVPtr pNv = NVPTR(pScrn); - - if (!pNv->xv_filtertable_mem) { - if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | - NOUVEAU_BO_MAP, 0, - TABLE_SIZE * sizeof(float) * 4, NULL, - &pNv->xv_filtertable_mem)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Couldn't alloc filter table!\n"); - return; - } - - if (nouveau_bo_map(pNv->xv_filtertable_mem, NOUVEAU_BO_RDWR, - pNv->client)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Couldn't map filter table!\n"); - return; - } - - int8_t *t=pNv->xv_filtertable_mem->map; - compute_filter_table(t); - } -} - #define SWIZZLE(ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w) ( \ NV30_3D_TEX_SWIZZLE_S0_X_##ts0x | NV30_3D_TEX_SWIZZLE_S0_Y_##ts0y | \ NV30_3D_TEX_SWIZZLE_S0_Z_##ts0z | NV30_3D_TEX_SWIZZLE_S0_W_##ts0w | \ @@ -294,10 +219,8 @@ NV40PutTextureImage(ScrnInfoPtr pScrn, PUSH_MTHDl(push, NV30_3D(COLOR0_OFFSET), bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - NV40_LoadFilterTable(pScrn); - - if (!NV40VideoTexture(pScrn, pNv->xv_filtertable_mem, 0, TABLE_SIZE, - 1, 0 , 0) || + if (!NV40VideoTexture(pScrn, pNv->scratch, XV_TABLE, XV_TABLE_SIZE, + 1, 0, 0) || !NV40VideoTexture(pScrn, src, src_offset, src_w, src_h, src_pitch, 1)) { PUSH_RESET(push); diff --git a/src/nv50_accel.c b/src/nv50_accel.c index 4a76e23..443e5c4 100644 --- a/src/nv50_accel.c +++ b/src/nv50_accel.c @@ -124,7 +124,6 @@ NVAccelInitNV50TCL(ScrnInfoPtr pScrn) struct nv04_fifo *fifo = pNv->channel->data; struct nouveau_pushbuf *push = pNv->pushbuf; struct nv04_notify ntfy = { .length = 32 }; - struct nouveau_bo *bo; unsigned class; int i; @@ -170,19 +169,10 @@ NVAccelInitNV50TCL(ScrnInfoPtr pScrn) return FALSE; } - if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM, 0, 65536, - NULL, &pNv->tesla_scratch)) { - nouveau_object_del(&pNv->vblank_sem); - nouveau_object_del(&pNv->NvSW); - nouveau_object_del(&pNv->Nv3D); - return FALSE; - } - bo = pNv->tesla_scratch; - if (nouveau_pushbuf_space(push, 512, 0, 0) || nouveau_pushbuf_refn (push, &(struct nouveau_pushbuf_refn) { - bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR - }, 1)) + pNv->scratch, NOUVEAU_BO_VRAM | + NOUVEAU_BO_WR }, 1)) return FALSE; BEGIN_NV04(push, NV01_SUBC(NVSW, OBJECT), 1); @@ -213,12 +203,12 @@ NVAccelInitNV50TCL(ScrnInfoPtr pScrn) PUSH_DATA (push, 1); BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3); - PUSH_DATA (push, (bo->offset + TIC_OFFSET) >> 32); - PUSH_DATA (push, (bo->offset + TIC_OFFSET)); + PUSH_DATA (push, (pNv->scratch->offset + TIC_OFFSET) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + TIC_OFFSET)); PUSH_DATA (push, 0x00000800); BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3); - PUSH_DATA (push, (bo->offset + TSC_OFFSET) >> 32); - PUSH_DATA (push, (bo->offset + TSC_OFFSET)); + PUSH_DATA (push, (pNv->scratch->offset + TSC_OFFSET) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + TSC_OFFSET)); PUSH_DATA (push, 0x00000000); BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1); PUSH_DATA (push, 1); @@ -226,8 +216,8 @@ NVAccelInitNV50TCL(ScrnInfoPtr pScrn) PUSH_DATA (push, 0x54); BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); - PUSH_DATA (push, (bo->offset + PVP_OFFSET) >> 32); - PUSH_DATA (push, (bo->offset + PVP_OFFSET)); + PUSH_DATA (push, (pNv->scratch->offset + PVP_OFFSET) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + PVP_OFFSET)); PUSH_DATA (push, 0x00004000); BEGIN_NV04(push, NV50_3D(CB_ADDR), 1); PUSH_DATA (push, 0); @@ -260,14 +250,14 @@ NVAccelInitNV50TCL(ScrnInfoPtr pScrn) PUSH_DATA (push, 8); } BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2); - PUSH_DATA (push, (bo->offset + PVP_OFFSET) >> 32); - PUSH_DATA (push, (bo->offset + PVP_OFFSET)); + PUSH_DATA (push, (pNv->scratch->offset + PVP_OFFSET) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + PVP_OFFSET)); BEGIN_NV04(push, NV50_3D(VP_START_ID), 1); PUSH_DATA (push, 0); BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); - PUSH_DATA (push, (bo->offset + PFP_OFFSET + PFP_S) >> 32); - PUSH_DATA (push, (bo->offset + PFP_OFFSET + PFP_S)); + PUSH_DATA (push, (pNv->scratch->offset + PFP_OFFSET + PFP_S) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + PFP_OFFSET + PFP_S)); PUSH_DATA (push, (0 << NV50_3D_CB_DEF_SET_BUFFER__SHIFT) | 0x4000); BEGIN_NV04(push, NV50_3D(CB_ADDR), 1); PUSH_DATA (push, 0); @@ -279,8 +269,8 @@ NVAccelInitNV50TCL(ScrnInfoPtr pScrn) PUSH_DATA (push, 0xf6400001); PUSH_DATA (push, 0x0000c785); BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); - PUSH_DATA (push, (bo->offset + PFP_OFFSET + PFP_C) >> 32); - PUSH_DATA (push, (bo->offset + PFP_OFFSET + PFP_C)); + PUSH_DATA (push, (pNv->scratch->offset + PFP_OFFSET + PFP_C) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + PFP_OFFSET + PFP_C)); PUSH_DATA (push, (0 << NV50_3D_CB_DEF_SET_BUFFER__SHIFT) | 0x4000); BEGIN_NV04(push, NV50_3D(CB_ADDR), 1); PUSH_DATA (push, 0); @@ -302,8 +292,8 @@ NVAccelInitNV50TCL(ScrnInfoPtr pScrn) PUSH_DATA (push, 0xc004060d); PUSH_DATA (push, 0x00000781); BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); - PUSH_DATA (push, (bo->offset + PFP_OFFSET + PFP_CCA) >> 32); - PUSH_DATA (push, (bo->offset + PFP_OFFSET + PFP_CCA)); + PUSH_DATA (push, (pNv->scratch->offset + PFP_OFFSET + PFP_CCA) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + PFP_OFFSET + PFP_CCA)); PUSH_DATA (push, (0 << NV50_3D_CB_DEF_SET_BUFFER__SHIFT) | 0x4000); BEGIN_NV04(push, NV50_3D(CB_ADDR), 1); PUSH_DATA (push, 0); @@ -325,8 +315,8 @@ NVAccelInitNV50TCL(ScrnInfoPtr pScrn) PUSH_DATA (push, 0xc007060d); PUSH_DATA (push, 0x00000781); BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); - PUSH_DATA (push, (bo->offset + PFP_OFFSET + PFP_CCASA) >> 32); - PUSH_DATA (push, (bo->offset + PFP_OFFSET + PFP_CCASA)); + PUSH_DATA (push, (pNv->scratch->offset + PFP_OFFSET + PFP_CCASA) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + PFP_OFFSET + PFP_CCASA)); PUSH_DATA (push, (0 << NV50_3D_CB_DEF_SET_BUFFER__SHIFT) | 0x4000); BEGIN_NV04(push, NV50_3D(CB_ADDR), 1); PUSH_DATA (push, 0); @@ -348,8 +338,8 @@ NVAccelInitNV50TCL(ScrnInfoPtr pScrn) PUSH_DATA (push, 0xc004060d); PUSH_DATA (push, 0x00000781); BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); - PUSH_DATA (push, (bo->offset + PFP_OFFSET + PFP_S_A8) >> 32); - PUSH_DATA (push, (bo->offset + PFP_OFFSET + PFP_S_A8)); + PUSH_DATA (push, (pNv->scratch->offset + PFP_OFFSET + PFP_S_A8) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + PFP_OFFSET + PFP_S_A8)); PUSH_DATA (push, (0 << NV50_3D_CB_DEF_SET_BUFFER__SHIFT) | 0x4000); BEGIN_NV04(push, NV50_3D(CB_ADDR), 1); PUSH_DATA (push, 0); @@ -365,8 +355,8 @@ NVAccelInitNV50TCL(ScrnInfoPtr pScrn) PUSH_DATA (push, 0x1000000d); PUSH_DATA (push, 0x0403c781); BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); - PUSH_DATA (push, (bo->offset + PFP_OFFSET + PFP_C_A8) >> 32); - PUSH_DATA (push, (bo->offset + PFP_OFFSET + PFP_C_A8)); + PUSH_DATA (push, (pNv->scratch->offset + PFP_OFFSET + PFP_C_A8) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + PFP_OFFSET + PFP_C_A8)); PUSH_DATA (push, (0 << NV50_3D_CB_DEF_SET_BUFFER__SHIFT) | 0x4000); BEGIN_NV04(push, NV50_3D(CB_ADDR), 1); PUSH_DATA (push, 0); @@ -388,8 +378,8 @@ NVAccelInitNV50TCL(ScrnInfoPtr pScrn) PUSH_DATA (push, 0x10000609); PUSH_DATA (push, 0x0403c781); BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); - PUSH_DATA (push, (bo->offset + PFP_OFFSET + PFP_NV12) >> 32); - PUSH_DATA (push, (bo->offset + PFP_OFFSET + PFP_NV12)); + PUSH_DATA (push, (pNv->scratch->offset + PFP_OFFSET + PFP_NV12) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + PFP_OFFSET + PFP_NV12)); PUSH_DATA (push, (0 << NV50_3D_CB_DEF_SET_BUFFER__SHIFT) | 0x4000); BEGIN_NV04(push, NV50_3D(CB_ADDR), 1); PUSH_DATA (push, 0); @@ -429,8 +419,8 @@ NVAccelInitNV50TCL(ScrnInfoPtr pScrn) PUSH_DATA (push, 0x08040404); PUSH_DATA (push, 0x00000008); /* NV50_3D_FP_REG_ALLOC_TEMP */ BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2); - PUSH_DATA (push, (bo->offset + PFP_OFFSET) >> 32); - PUSH_DATA (push, (bo->offset + PFP_OFFSET)); + PUSH_DATA (push, (pNv->scratch->offset + PFP_OFFSET) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + PFP_OFFSET)); BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 1); PUSH_DATA (push, 1); diff --git a/src/nv50_accel.h b/src/nv50_accel.h index b8d837f..606fe74 100644 --- a/src/nv50_accel.h +++ b/src/nv50_accel.h @@ -20,7 +20,7 @@ #define SUBC_3D(mthd) 7, (mthd) #define NV50_3D(mthd) SUBC_3D(NV50_3D_##mthd) -/* "Tesla scratch buffer" offsets */ +/* scratch buffer offsets */ #define PVP_OFFSET 0x00000000 /* Vertex program */ #define PFP_OFFSET 0x00001000 /* Fragment program */ #define TIC_OFFSET 0x00002000 /* Texture Image Control */ diff --git a/src/nv50_exa.c b/src/nv50_exa.c index 6f87df9..d75e8c0 100644 --- a/src/nv50_exa.c +++ b/src/nv50_exa.c @@ -546,8 +546,8 @@ NV50EXATexture(PixmapPtr ppix, PicturePtr ppict, unsigned unit) NOUVEAU_FALLBACK("pixmap is scanout buffer\n"); BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); - PUSH_DATA (push, (pNv->tesla_scratch->offset + TIC_OFFSET) >> 32); - PUSH_DATA (push, (pNv->tesla_scratch->offset + TIC_OFFSET)); + PUSH_DATA (push, (pNv->scratch->offset + TIC_OFFSET) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + TIC_OFFSET)); PUSH_DATA (push, (CB_TIC << NV50_3D_CB_DEF_SET_BUFFER__SHIFT) | 0x4000); BEGIN_NV04(push, NV50_3D(CB_ADDR), 1); PUSH_DATA (push, CB_TIC | ((unit * 8) << NV50_3D_CB_ADDR_ID__SHIFT)); @@ -632,8 +632,8 @@ NV50EXATexture(PixmapPtr ppix, PicturePtr ppict, unsigned unit) PUSH_DATA (push, 0x00000000); BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); - PUSH_DATA (push, (pNv->tesla_scratch->offset + TSC_OFFSET) >> 32); - PUSH_DATA (push, (pNv->tesla_scratch->offset + TSC_OFFSET)); + PUSH_DATA (push, (pNv->scratch->offset + TSC_OFFSET) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + TSC_OFFSET)); PUSH_DATA (push, (CB_TSC << NV50_3D_CB_DEF_SET_BUFFER__SHIFT) | 0x4000); BEGIN_NV04(push, NV50_3D(CB_ADDR), 1); PUSH_DATA (push, CB_TSC | ((unit * 8) << NV50_3D_CB_ADDR_ID__SHIFT)); @@ -825,7 +825,7 @@ NV50EXAPrepareComposite(int op, PUSH_DATA (push, 0x203); PUSH_RESET(push); - PUSH_REFN (push, pNv->tesla_scratch, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); + PUSH_REFN (push, pNv->scratch, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); PUSH_REFN (push, src, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); PUSH_REFN (push, dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); if (pmpict) diff --git a/src/nv50_xv.c b/src/nv50_xv.c index a5a7c51..3522dde 100644 --- a/src/nv50_xv.c +++ b/src/nv50_xv.c @@ -73,7 +73,7 @@ nv50_xv_image_put(ScrnInfoPtr pScrn, struct nouveau_bo *dst = nouveau_pixmap_bo(ppix); struct nouveau_pushbuf *push = pNv->pushbuf; struct nouveau_pushbuf_refn refs[] = { - { pNv->tesla_scratch, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR }, + { pNv->scratch, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR }, { src, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD }, { dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR }, }; @@ -109,8 +109,8 @@ nv50_xv_image_put(ScrnInfoPtr pScrn, PUSH_DATA (push, 0); BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); - PUSH_DATA (push, (pNv->tesla_scratch->offset + TIC_OFFSET) >> 32); - PUSH_DATA (push, (pNv->tesla_scratch->offset + TIC_OFFSET)); + PUSH_DATA (push, (pNv->scratch->offset + TIC_OFFSET) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + TIC_OFFSET)); PUSH_DATA (push, (CB_TIC << NV50_3D_CB_DEF_SET_BUFFER__SHIFT) | 0x4000); BEGIN_NV04(push, NV50_3D(CB_ADDR), 1); PUSH_DATA (push, CB_TIC); @@ -184,8 +184,8 @@ nv50_xv_image_put(ScrnInfoPtr pScrn, } BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); - PUSH_DATA (push, (pNv->tesla_scratch->offset + TSC_OFFSET) >> 32); - PUSH_DATA (push, (pNv->tesla_scratch->offset + TSC_OFFSET)); + PUSH_DATA (push, (pNv->scratch->offset + TSC_OFFSET) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + TSC_OFFSET)); PUSH_DATA (push, (CB_TSC << NV50_3D_CB_DEF_SET_BUFFER__SHIFT) | 0x4000); BEGIN_NV04(push, NV50_3D(CB_ADDR), 1); PUSH_DATA (push, CB_TSC); @@ -338,13 +338,13 @@ nv50_xv_csc_update(ScrnInfoPtr pScrn, NVPortPrivPtr pPriv) if (nouveau_pushbuf_space(push, 64, 0, 0) || nouveau_pushbuf_refn (push, &(struct nouveau_pushbuf_refn) { - pNv->tesla_scratch, NOUVEAU_BO_WR | + pNv->scratch, NOUVEAU_BO_WR | NOUVEAU_BO_VRAM }, 1)) return; BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); - PUSH_DATA (push, (pNv->tesla_scratch->offset + PFP_DATA) >> 32); - PUSH_DATA (push, (pNv->tesla_scratch->offset + PFP_DATA)); + PUSH_DATA (push, (pNv->scratch->offset + PFP_DATA) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + PFP_DATA)); PUSH_DATA (push, (CB_PFP << NV50_3D_CB_DEF_SET_BUFFER__SHIFT) | 0x00004000); BEGIN_NV04(push, NV50_3D(CB_ADDR), 1); diff --git a/src/nv_accel_common.c b/src/nv_accel_common.c index 32cae49..4516e97 100644 --- a/src/nv_accel_common.c +++ b/src/nv_accel_common.c @@ -592,6 +592,17 @@ NVAccelCommonInit(ScrnInfoPtr pScrn) if (pNv->NoAccel) return TRUE; + /* Scratch buffer */ + ret = nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_MAP, + 128 * 1024, 128 * 1024, NULL, &pNv->scratch); + if (!ret) + ret = nouveau_bo_map(pNv->scratch, 0, pNv->client); + if (ret) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Failed to allocate scratch buffer: %d\n", ret); + return FALSE; + } + /* General engine objects */ if (pNv->Architecture < NV_ARCH_C0) { INIT_CONTEXT_OBJECT(DmaNotifier0); @@ -679,6 +690,5 @@ void NVAccelFree(ScrnInfoPtr pScrn) nouveau_object_del(&pNv->NvSW); nouveau_object_del(&pNv->Nv3D); - nouveau_bo_ref(NULL, &pNv->tesla_scratch); - nouveau_bo_ref(NULL, &pNv->shader_mem); + nouveau_bo_ref(NULL, &pNv->scratch); } diff --git a/src/nv_proto.h b/src/nv_proto.h index f3aa3be..28db773 100644 --- a/src/nv_proto.h +++ b/src/nv_proto.h @@ -36,6 +36,7 @@ void nouveau_dri2_fini(ScreenPtr pScreen); void NVInitVideo(ScreenPtr); void NVTakedownVideo(ScrnInfoPtr); void NVSetPortDefaults (ScrnInfoPtr pScrn, NVPortPrivPtr pPriv); +void NVXVComputeBicubicFilter(struct nouveau_bo *, unsigned, unsigned); unsigned int nv_window_belongs_to_crtc(ScrnInfoPtr, int, int, int, int); /* in nv_dma.c */ diff --git a/src/nv_type.h b/src/nv_type.h index 1ba3e4e..bd00df3 100644 --- a/src/nv_type.h +++ b/src/nv_type.h @@ -102,9 +102,7 @@ typedef struct _NVRec { struct nouveau_object *Nv2D; struct nouveau_object *Nv3D; struct nouveau_object *NvSW; - struct nouveau_bo *tesla_scratch; - struct nouveau_bo *shader_mem; - struct nouveau_bo *xv_filtertable_mem; + struct nouveau_bo *scratch; /* Acceleration context */ PixmapPtr pspix, pmpix, pdpix; diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c index ad34554..d0f6770 100644 --- a/src/nvc0_accel.c +++ b/src/nvc0_accel.c @@ -32,11 +32,6 @@ NVAccelInitM2MF_NVC0(ScrnInfoPtr pScrn) struct nouveau_pushbuf *push = pNv->pushbuf; int ret; - ret = nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM, 128 * 1024, 0x20000, - NULL, &pNv->tesla_scratch); - if (ret) - return FALSE; - ret = nouveau_object_new(pNv->channel, 0x00009039, 0x9039, NULL, 0, &pNv->NvMemFormat); if (ret) @@ -45,8 +40,8 @@ NVAccelInitM2MF_NVC0(ScrnInfoPtr pScrn) BEGIN_NVC0(push, NV01_SUBC(M2MF, OBJECT), 1); PUSH_DATA (push, pNv->NvMemFormat->handle); BEGIN_NVC0(push, NVC0_M2MF(QUERY_ADDRESS_HIGH), 3); - PUSH_DATA (push, (pNv->tesla_scratch->offset + NTFY_OFFSET) >> 32); - PUSH_DATA (push, (pNv->tesla_scratch->offset + NTFY_OFFSET)); + PUSH_DATA (push, (pNv->scratch->offset + NTFY_OFFSET) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + NTFY_OFFSET)); PUSH_DATA (push, 0); return TRUE; @@ -59,11 +54,6 @@ NVAccelInitP2MF_NVE0(ScrnInfoPtr pScrn) struct nouveau_pushbuf *push = pNv->pushbuf; int ret; - ret = nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM, 128 * 1024, 0x20000, - NULL, &pNv->tesla_scratch); - if (ret) - return FALSE; - ret = nouveau_object_new(pNv->channel, 0x0000a040, 0xa040, NULL, 0, &pNv->NvMemFormat); if (ret) @@ -128,7 +118,7 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn) { NVPtr pNv = NVPTR(pScrn); struct nouveau_pushbuf *push = pNv->pushbuf; - struct nouveau_bo *bo = pNv->tesla_scratch; + struct nouveau_bo *bo = pNv->scratch; uint32_t class; int ret; @@ -144,7 +134,7 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn) if (nouveau_pushbuf_space(push, 512, 0, 0) || nouveau_pushbuf_refn (push, &(struct nouveau_pushbuf_refn) { - pNv->tesla_scratch, NOUVEAU_BO_VRAM | + pNv->scratch, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR }, 1)) return FALSE; @@ -153,8 +143,8 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn) BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1); PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS); BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 3); - PUSH_DATA (push, (pNv->tesla_scratch->offset + NTFY_OFFSET) >> 32); - PUSH_DATA (push, (pNv->tesla_scratch->offset + NTFY_OFFSET)); + PUSH_DATA (push, (pNv->scratch->offset + NTFY_OFFSET) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + NTFY_OFFSET)); PUSH_DATA (push, 0); BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1); PUSH_DATA (push, 0); diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c index 8b6d51e..7ec45b3 100644 --- a/src/nvc0_exa.c +++ b/src/nvc0_exa.c @@ -546,7 +546,7 @@ NVC0EXATexture(PixmapPtr ppix, PicturePtr ppict, unsigned unit) if (!nv50_style_tiled_pixmap(ppix)) NOUVEAU_FALLBACK("pixmap is scanout buffer\n"); - PUSH_DATAu(push, pNv->tesla_scratch, TIC_OFFSET + (unit * 32), 8); + PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32), 8); switch (ppict->format) { case PICT_a8r8g8b8: PUSH_DATA (push, _(B_C0, G_C1, R_C2, A_C3, 8_8_8_8)); @@ -626,7 +626,7 @@ NVC0EXATexture(PixmapPtr ppix, PicturePtr ppict, unsigned unit) PUSH_DATA (push, 0x03000000); PUSH_DATA (push, 0x00000000); - PUSH_DATAu(push, pNv->tesla_scratch, TSC_OFFSET + (unit * 32), 8); + PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8); if (ppict->repeat) { switch (ppict->repeatType) { case RepeatPad: @@ -817,7 +817,7 @@ NVC0EXAPrepareComposite(int op, PUSH_DATA (push, 0); PUSH_RESET(push); - PUSH_REFN (push, pNv->tesla_scratch, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); + PUSH_REFN (push, pNv->scratch, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); PUSH_REFN (push, src, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); PUSH_REFN (push, dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); if (pmpict) diff --git a/src/nvc0_shader.h b/src/nvc0_shader.h index 2084a6d..73727fc 100644 --- a/src/nvc0_shader.h +++ b/src/nvc0_shader.h @@ -3,7 +3,7 @@ #define NVC0PushProgram(pNv,addr,code) do { \ const unsigned size = sizeof(code) / sizeof(code[0]); \ - PUSH_DATAu((pNv)->pushbuf, (pNv)->tesla_scratch, (addr), size); \ + PUSH_DATAu((pNv)->pushbuf, (pNv)->scratch, (addr), size); \ PUSH_DATAp((pNv)->pushbuf, (code), size); \ } while(0) diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c index 3c08a7f..74ac7dc 100644 --- a/src/nvc0_xv.c +++ b/src/nvc0_xv.c @@ -69,7 +69,7 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn, NVPtr pNv = NVPTR(pScrn); struct nouveau_bo *dst = nouveau_pixmap_bo(ppix); struct nouveau_pushbuf_refn refs[] = { - { pNv->tesla_scratch, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR }, + { pNv->scratch, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR }, { src, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD }, { dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR }, }; @@ -103,7 +103,7 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn, BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE(0)), 1); PUSH_DATA (push, 0); - PUSH_DATAu(push, pNv->tesla_scratch, TIC_OFFSET, 16); + PUSH_DATAu(push, pNv->scratch, TIC_OFFSET, 16); if (id == FOURCC_YV12 || id == FOURCC_I420) { PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM | NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM | @@ -172,7 +172,7 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn, PUSH_DATA (push, 0x00000000); } - PUSH_DATAu(push, pNv->tesla_scratch, TSC_OFFSET, 16); + PUSH_DATAu(push, pNv->scratch, TSC_OFFSET, 16); PUSH_DATA (push, NV50TSC_1_0_WRAPS_CLAMP_TO_EDGE | NV50TSC_1_0_WRAPT_CLAMP_TO_EDGE | NV50TSC_1_0_WRAPR_CLAMP_TO_EDGE); @@ -265,14 +265,14 @@ nvc0_xv_csc_update(NVPtr pNv, float yco, float *off, float *uco, float *vco) if (nouveau_pushbuf_space(push, 64, 0, 0) || nouveau_pushbuf_refn (push, &(struct nouveau_pushbuf_refn) { - pNv->tesla_scratch, NOUVEAU_BO_WR | + pNv->scratch, NOUVEAU_BO_WR | NOUVEAU_BO_VRAM }, 1)) return; BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); PUSH_DATA (push, 256); - PUSH_DATA (push, (pNv->tesla_scratch->offset + CB_OFFSET) >> 32); - PUSH_DATA (push, (pNv->tesla_scratch->offset + CB_OFFSET)); + PUSH_DATA (push, (pNv->scratch->offset + CB_OFFSET) >> 32); + PUSH_DATA (push, (pNv->scratch->offset + CB_OFFSET)); BEGIN_NVC0(push, NVC0_3D(CB_POS), 11); PUSH_DATA (push, 0); PUSH_DATAf(push, yco); |