Update AVX and FMA to latest Intel specification (Dec 2008).

- Removed VPERMIL2 opcodes (VPERMIL2PS, VPERMIL2PD).
- Replaced 4-operand FMA instructions with completely new set of opcodes.

Contributed by: Mark Charney, Intel Corporation <mark.charney@intel.com>

svn path=/trunk/yasm/; revision=2170

8 files changed, 1717 insertions, 928 deletions

diff --git a/modules/arch/x86/gen_x86_insn.py b/modules/arch/x86/gen_x86_insn.py
index 9dcae4ba..60f27eb4 100755
--- a/modules/arch/x86/gen_x86_insn.py
+++ b/modules/arch/x86/gen_x86_insn.py
@@ -6283,225 +6283,123 @@ add_group("vpermil",
 add_insn("vpermilpd", "vpermil", modifiers=[0x05])
 add_insn("vpermilps", "vpermil", modifiers=[0x04])
 
-add_group("vpermil2",
-    cpu=["AVX"],
-    modifiers=["Op2Add"],
-    vex=128,
-    vexw=0,
-    prefix=0x66,
-    opcode=[0x0F, 0x3A, 0x00],
-    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDReg", size=128, dest="VEX"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
-              Operand(type="SIMDReg", size=128, dest="VEXImmSrc"),
-              Operand(type="Imm", dest="VEXImm")])
-add_group("vpermil2",
-    cpu=["AVX"],
-    modifiers=["Op2Add"],
-    vex=128,
-    vexw=1,
-    prefix=0x66,
-    opcode=[0x0F, 0x3A, 0x00],
-    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDReg", size=128, dest="VEX"),
-              Operand(type="SIMDReg", size=128, dest="VEXImmSrc"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
-              Operand(type="Imm", dest="VEXImm")])
-add_group("vpermil2",
-    cpu=["AVX"],
-    modifiers=["Op2Add"],
-    vex=256,
-    vexw=0,
-    prefix=0x66,
-    opcode=[0x0F, 0x3A, 0x00],
-    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
-              Operand(type="SIMDReg", size=256, dest="VEX"),
-              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
-              Operand(type="SIMDReg", size=256, dest="VEXImmSrc"),
-              Operand(type="Imm", dest="VEXImm")])
-add_group("vpermil2",
+add_group("vperm2f128",
     cpu=["AVX"],
-    modifiers=["Op2Add"],
     vex=256,
-    vexw=1,
     prefix=0x66,
-    opcode=[0x0F, 0x3A, 0x00],
+    opcode=[0x0F, 0x3A, 0x06],
     operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
               Operand(type="SIMDReg", size=256, dest="VEX"),
-              Operand(type="SIMDReg", size=256, dest="VEXImmSrc"),
               Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
-              Operand(type="Imm", dest="VEXImm")])
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 
-add_insn("vpermil2pd", "vpermil2", modifiers=[0x49])
-add_insn("vpermil2ps", "vpermil2", modifiers=[0x48])
+add_insn("vperm2f128", "vperm2f128")
 
-# Immediate aliases for the above
-add_group("vpermil2_fixed",
-    cpu=["AVX"],
-    modifiers=["Op2Add", "Imm8"],
-    vex=128,
-    vexw=0,
-    prefix=0x66,
-    opcode=[0x0F, 0x3A, 0x00],
-    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDReg", size=128, dest="VEX"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
-              Operand(type="SIMDReg", size=128, dest="VEXImmSrc")])
-add_group("vpermil2_fixed",
-    cpu=["AVX"],
-    modifiers=["Op2Add", "Imm8"],
+#####################################################################
+# Intel FMA instructions
+#####################################################################
+
+### 128/256b FMA PS
+add_group("vfma_ps",
+    cpu=["FMA"],
+    modifiers=["Op2Add"],
     vex=128,
-    vexw=1,
+    vexw=0, # single precision
     prefix=0x66,
-    opcode=[0x0F, 0x3A, 0x00],
+    opcode=[0x0F, 0x38, 0x00],
     operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="SIMDReg", size=128, dest="VEX"),
-              Operand(type="SIMDReg", size=128, dest="VEXImmSrc"),
               Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
-add_group("vpermil2_fixed",
-    cpu=["AVX"],
-    modifiers=["Op2Add", "Imm8"],
-    vex=256,
-    vexw=0,
-    prefix=0x66,
-    opcode=[0x0F, 0x3A, 0x00],
-    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
-              Operand(type="SIMDReg", size=256, dest="VEX"),
-              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
-              Operand(type="SIMDReg", size=256, dest="VEXImmSrc")])
-add_group("vpermil2_fixed",
-    cpu=["AVX"],
-    modifiers=["Op2Add", "Imm8"],
+add_group("vfma_ps",
+    cpu=["FMA"],
+    modifiers=["Op2Add"],
     vex=256,
-    vexw=1,
+    vexw=0, # single precision
     prefix=0x66,
-    opcode=[0x0F, 0x3A, 0x00],
+    opcode=[0x0F, 0x38, 0x00],
     operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
               Operand(type="SIMDReg", size=256, dest="VEX"),
-              Operand(type="SIMDReg", size=256, dest="VEXImmSrc"),
               Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
 
-for ib, cc in [(0, "td"), (2, "mo"), (3, "mz")]:
-    add_insn("vpermil"+cc+"2pd", "vpermil2_fixed", modifiers=[0x49, ib])
-    add_insn("vpermil"+cc+"2ps", "vpermil2_fixed", modifiers=[0x48, ib])
-
-add_group("vperm2f128",
-    cpu=["AVX"],
+### 128/256b FMA PD(W=1) 
+add_group("vfma_pd",
+    cpu=["FMA"],
+    modifiers=["Op2Add"],
+    vex=128,
+    vexw=1, # double precision
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+add_group("vfma_pd",
+    cpu=["FMA"],
+    modifiers=["Op2Add"],
     vex=256,
+    vexw=1, # double precision
     prefix=0x66,
-    opcode=[0x0F, 0x3A, 0x06],
+    opcode=[0x0F, 0x38, 0x00],
     operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
               Operand(type="SIMDReg", size=256, dest="VEX"),
-              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
-              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-
-add_insn("vperm2f128", "vperm2f128")
-
-#####################################################################
-# Intel FMA instructions
-#####################################################################
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
 
-add_group("fma_128_256",
+add_group("vfma_ss",
     cpu=["FMA"],
     modifiers=["Op2Add"],
     vex=128,
     vexw=0,
     prefix=0x66,
-    opcode=[0x0F, 0x3A, 0x00],
+    opcode=[0x0F, 0x38, 0x00],
     operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDReg", size=128, dest="VEXImmSrc"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
-              Operand(type="SIMDReg", size=128, dest="VEX")])
-add_group("fma_128_256",
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDReg", size=128, dest="EA")])
+
+add_group("vfma_ss",
     cpu=["FMA"],
     modifiers=["Op2Add"],
     vex=128,
-    vexw=1,
+    vexw=0,
     prefix=0x66,
-    opcode=[0x0F, 0x3A, 0x00],
+    opcode=[0x0F, 0x38, 0x00],
     operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDReg", size=128, dest="VEXImmSrc"),
               Operand(type="SIMDReg", size=128, dest="VEX"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
-add_group("fma_128_256",
+              Operand(type="Mem", size=32, relaxed=True, dest="EA")])
+
+add_group("vfma_sd",
     cpu=["FMA"],
     modifiers=["Op2Add"],
-    vex=256,
-    vexw=0,
+    vex=128,
+    vexw=1,
     prefix=0x66,
-    opcode=[0x0F, 0x3A, 0x00],
-    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
-              Operand(type="SIMDReg", size=256, dest="VEXImmSrc"),
-              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
-              Operand(type="SIMDReg", size=256, dest="VEX")])
-add_group("fma_128_256",
+    opcode=[0x0F, 0x38, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDReg", size=128, dest="EA")])
+
+add_group("vfma_sd",
     cpu=["FMA"],
     modifiers=["Op2Add"],
-    vex=256,
+    vex=128,
     vexw=1,
     prefix=0x66,
-    opcode=[0x0F, 0x3A, 0x00],
-    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
-              Operand(type="SIMDReg", size=256, dest="VEXImmSrc"),
-              Operand(type="SIMDReg", size=256, dest="VEX"),
-              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
-
-add_insn("vfmaddpd", "fma_128_256", modifiers=[0x69])
-add_insn("vfmaddps", "fma_128_256", modifiers=[0x68])
-add_insn("vfmaddsubpd", "fma_128_256", modifiers=[0x5D])
-add_insn("vfmaddsubps", "fma_128_256", modifiers=[0x5C])
-add_insn("vfmsubaddpd", "fma_128_256", modifiers=[0x5F])
-add_insn("vfmsubaddps", "fma_128_256", modifiers=[0x5E])
-add_insn("vfmsubpd", "fma_128_256", modifiers=[0x6D])
-add_insn("vfmsubps", "fma_128_256", modifiers=[0x6C])
-add_insn("vfnmaddpd", "fma_128_256", modifiers=[0x79])
-add_insn("vfnmaddps", "fma_128_256", modifiers=[0x78])
-add_insn("vfnmsubpd", "fma_128_256", modifiers=[0x7D])
-add_insn("vfnmsubps", "fma_128_256", modifiers=[0x7C])
-
-for sz in [32, 64]:
-    add_group("fma_128_m%d" % sz,
-        cpu=["FMA"],
-        modifiers=["Op2Add"],
-        vex=128,
-        vexw=0,
-        prefix=0x66,
-        opcode=[0x0F, 0x3A, 0x00],
-        operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
-                  Operand(type="SIMDReg", size=128, dest="VEXImmSrc"),
-                  Operand(type="SIMDReg", size=128, dest="EA"),
-                  Operand(type="SIMDReg", size=128, dest="VEX")])
-    add_group("fma_128_m%d" % sz,
-        cpu=["FMA"],
-        modifiers=["Op2Add"],
-        vex=128,
-        vexw=0,
-        prefix=0x66,
-        opcode=[0x0F, 0x3A, 0x00],
-        operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
-                  Operand(type="SIMDReg", size=128, dest="VEXImmSrc"),
-                  Operand(type="Mem", size=sz, relaxed=True, dest="EA"),
-                  Operand(type="SIMDReg", size=128, dest="VEX")])
-    add_group("fma_128_m%d" % sz,
-        cpu=["FMA"],
-        modifiers=["Op2Add"],
-        vex=128,
-        vexw=1,
-        prefix=0x66,
-        opcode=[0x0F, 0x3A, 0x00],
-        operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
-                  Operand(type="SIMDReg", size=128, dest="VEXImmSrc"),
-                  Operand(type="SIMDReg", size=128, dest="VEX"),
-                  Operand(type="Mem", size=sz, relaxed=True, dest="EA")])
+    opcode=[0x0F, 0x38, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="Mem", size=64, relaxed=True, dest="EA")])
 
-add_insn("vfmaddsd", "fma_128_m64", modifiers=[0x6B])
-add_insn("vfmaddss", "fma_128_m32", modifiers=[0x6A])
-add_insn("vfmsubsd", "fma_128_m64", modifiers=[0x6F])
-add_insn("vfmsubss", "fma_128_m32", modifiers=[0x6E])
-add_insn("vfnmaddsd", "fma_128_m64", modifiers=[0x7B])
-add_insn("vfnmaddss", "fma_128_m32", modifiers=[0x7A])
-add_insn("vfnmsubsd", "fma_128_m64", modifiers=[0x7F])
-add_insn("vfnmsubss", "fma_128_m32", modifiers=[0x7E])
+for orderval, order in enumerate(["132", "213", "231"]):
+    ov = orderval << 4
+    for combval, comb in enumerate(["ps", "pd", "ss", "sd"]):
+        cv = combval >> 1
+        add_insn("vfmadd"+order+comb, "vfma_"+comb, modifiers=[0x98+ov+cv])
+        add_insn("vfmsub"+order+comb, "vfma_"+comb, modifiers=[0x9A+ov+cv])
+        add_insn("vfnmsub"+order+comb, "vfma_"+comb, modifiers=[0x9E+ov+cv])
+        add_insn("vfnmadd"+order+comb, "vfma_"+comb, modifiers=[0x9C+ov+cv])
+
+    # no ss/sd for these
+    for comb in ["ps", "pd"]:
+        add_insn("vfmaddsub"+order+comb, "vfma_"+comb, modifiers=[0x96+ov])
+        add_insn("vfmsubadd"+order+comb, "vfma_"+comb, modifiers=[0x97+ov])
 
 #####################################################################
 # Intel AES instructions
diff --git a/modules/arch/x86/tests/Makefile.inc b/modules/arch/x86/tests/Makefile.inc
index 687fb31a..bbe26ed2 100644
--- a/modules/arch/x86/tests/Makefile.inc
+++ b/modules/arch/x86/tests/Makefile.inc
@@ -3,6 +3,7 @@
 TESTS += modules/arch/x86/tests/x86_test.sh
 
 EXTRA_DIST += modules/arch/x86/tests/x86_test.sh
+EXTRA_DIST += modules/arch/x86/tests/gen-fma-test.py
 EXTRA_DIST += modules/arch/x86/tests/addbyte.asm
 EXTRA_DIST += modules/arch/x86/tests/addbyte.errwarn
 EXTRA_DIST += modules/arch/x86/tests/addbyte.hex
@@ -212,8 +213,6 @@ EXTRA_DIST += modules/arch/x86/tests/vmx.asm
 EXTRA_DIST += modules/arch/x86/tests/vmx.hex
 EXTRA_DIST += modules/arch/x86/tests/vmx-err.asm
 EXTRA_DIST += modules/arch/x86/tests/vmx-err.errwarn
-EXTRA_DIST += modules/arch/x86/tests/vpermil2.asm
-EXTRA_DIST += modules/arch/x86/tests/vpermil2.hex
 EXTRA_DIST += modules/arch/x86/tests/x86label.asm
 EXTRA_DIST += modules/arch/x86/tests/x86label.hex
 EXTRA_DIST += modules/arch/x86/tests/xchg64.asm
diff --git a/modules/arch/x86/tests/avx.asm b/modules/arch/x86/tests/avx.asm
index 6461ea05..eff8cc97 100644
--- a/modules/arch/x86/tests/avx.asm
+++ b/modules/arch/x86/tests/avx.asm
@@ -1432,17 +1432,6 @@ vpermilpd xmm1, dqword [rax], 5
 vpermilpd ymm1, [rax], byte 5
 vpermilpd ymm1, yword [rax], 5
 
-vpermil2pd xmm1, xmm2, xmm3, xmm4, 5
-vpermil2pd xmm1, xmm2, [rax], xmm4, 5
-vpermil2pd xmm1, xmm2, dqword [rax], xmm4, 5
-vpermil2pd xmm1, xmm2, xmm3, [rax], 5
-vpermil2pd xmm1, xmm2, xmm3, dqword [rax], 5
-vpermil2pd ymm1, ymm2, ymm3, ymm4, 5
-vpermil2pd ymm1, ymm2, [rax], ymm4, 5
-vpermil2pd ymm1, ymm2, yword [rax], ymm4, 5
-vpermil2pd ymm1, ymm2, ymm3, [rax], 5
-vpermil2pd ymm1, ymm2, ymm3, yword [rax], 5
-
 vpermilps xmm1, xmm2, xmm3
 vpermilps xmm1, xmm2, [rax]
 vpermilps xmm1, xmm2, dqword [rax]
@@ -1454,17 +1443,6 @@ vpermilps xmm1, dqword [rax], 5
 vpermilps ymm1, [rax], byte 5
 vpermilps ymm1, yword [rax], 5
 
-vpermil2ps xmm1, xmm2, xmm3, xmm4, 5
-vpermil2ps xmm1, xmm2, [rax], xmm4, 5
-vpermil2ps xmm1, xmm2, dqword [rax], xmm4, 5
-vpermil2ps xmm1, xmm2, xmm3, [rax], 5
-vpermil2ps xmm1, xmm2, xmm3, dqword [rax], 5
-vpermil2ps ymm1, ymm2, ymm3, ymm4, 5
-vpermil2ps ymm1, ymm2, [rax], ymm4, 5
-vpermil2ps ymm1, ymm2, yword [rax], ymm4, 5
-vpermil2ps ymm1, ymm2, ymm3, [rax], 5
-vpermil2ps ymm1, ymm2, ymm3, yword [rax], 5
-
 vperm2f128 ymm1, ymm2, ymm3, 5
 vperm2f128 ymm1, ymm2, [rax], byte 5
 vperm2f128 ymm1, ymm2, yword [rax], 5
diff --git a/modules/arch/x86/tests/avx.hex b/modules/arch/x86/tests/avx.hex
index c9ada3e1..4bc11def 100644
--- a/modules/arch/x86/tests/avx.hex
+++ b/modules/arch/x86/tests/avx.hex
@@ -5463,66 +5463,6 @@ e3
 08 
 05 
 c4 
-e3 
-69 
-49 
-cb 
-45 
-c4 
-e3 
-69 
-49 
-08 
-45 
-c4 
-e3 
-69 
-49 
-08 
-45 
-c4 
-e3 
-e9 
-49 
-08 
-35 
-c4 
-e3 
-e9 
-49 
-08 
-35 
-c4 
-e3 
-6d 
-49 
-cb 
-45 
-c4 
-e3 
-6d 
-49 
-08 
-45 
-c4 
-e3 
-6d 
-49 
-08 
-45 
-c4 
-e3 
-ed 
-49 
-08 
-35 
-c4 
-e3 
-ed 
-49 
-08 
-35 
-c4 
 e2 
 69 
 0c 
@@ -5578,66 +5518,6 @@ e3
 05 
 c4 
 e3 
-69 
-48 
-cb 
-45 
-c4 
-e3 
-69 
-48 
-08 
-45 
-c4 
-e3 
-69 
-48 
-08 
-45 
-c4 
-e3 
-e9 
-48 
-08 
-35 
-c4 
-e3 
-e9 
-48 
-08 
-35 
-c4 
-e3 
-6d 
-48 
-cb 
-45 
-c4 
-e3 
-6d 
-48 
-08 
-45 
-c4 
-e3 
-6d 
-48 
-08 
-45 
-c4 
-e3 
-ed 
-48 
-08 
-35 
-c4 
-e3 
-ed 
-48 
-08 
-35 
-c4 
-e3 
 6d 
 06 
 cb 
diff --git a/modules/arch/x86/tests/fma.asm b/modules/arch/x86/tests/fma.asm
index 25fdc50d..9bfb512b 100644
--- a/modules/arch/x86/tests/fma.asm
+++ b/modules/arch/x86/tests/fma.asm
@@ -1,109 +1,289 @@
 [bits 64]
-vfmaddpd xmm0, xmm1, xmm2, xmm3
-vfmaddpd xmm0, xmm1, [rax], xmm3
-vfmaddpd xmm0, xmm1, dqword [rax], xmm3
-vfmaddpd xmm0, xmm1, xmm2, [rax]
-vfmaddpd xmm0, xmm1, xmm2, dqword [rax]
-vfmaddpd ymm0, ymm1, ymm2, ymm3
-vfmaddpd ymm0, ymm1, [rax], ymm3
-vfmaddpd ymm0, ymm1, yword [rax], ymm3
-vfmaddpd ymm0, ymm1, ymm2, [rax]
-vfmaddpd ymm0, ymm1, ymm2, yword [rax]
-
-vfmaddps xmm0, xmm1, xmm2, xmm3
-vfmaddps xmm0, xmm1, dqword [rax], xmm3
-vfmaddps xmm0, xmm1, xmm2, dqword [rax]
-vfmaddps ymm0, ymm1, ymm2, ymm3
-vfmaddps ymm0, ymm1, yword [rax], ymm3
-vfmaddps ymm0, ymm1, ymm2, yword [rax]
-
-vfmaddsd xmm0, xmm1, xmm2, xmm3
-vfmaddsd xmm0, xmm1, [rax], xmm3
-vfmaddsd xmm0, xmm1, qword [rax], xmm3
-vfmaddsd xmm0, xmm1, xmm2, [rax]
-vfmaddsd xmm0, xmm1, xmm2, qword [rax]
-
-vfmaddss xmm0, xmm1, xmm2, xmm3
-vfmaddss xmm0, xmm1, dword [rax], xmm3
-vfmaddss xmm0, xmm1, xmm2, dword [rax]
-
-vfmaddsubpd xmm0, xmm1, xmm2, xmm3
-vfmaddsubpd xmm0, xmm1, dqword [rax], xmm3
-vfmaddsubpd xmm0, xmm1, xmm2, dqword [rax]
-vfmaddsubpd ymm0, ymm1, ymm2, ymm3
-vfmaddsubpd ymm0, ymm1, yword [rax], ymm3
-vfmaddsubpd ymm0, ymm1, ymm2, yword [rax]
-
-vfmaddsubps xmm0, xmm1, xmm2, xmm3
-vfmaddsubps xmm0, xmm1, dqword [rax], xmm3
-vfmaddsubps xmm0, xmm1, xmm2, dqword [rax]
-vfmaddsubps ymm0, ymm1, ymm2, ymm3
-vfmaddsubps ymm0, ymm1, yword [rax], ymm3
-vfmaddsubps ymm0, ymm1, ymm2, yword [rax]
-
-vfmsubpd xmm0, xmm1, xmm2, xmm3
-vfmsubpd xmm0, xmm1, dqword [rax], xmm3
-vfmsubpd xmm0, xmm1, xmm2, dqword [rax]
-vfmsubpd ymm0, ymm1, ymm2, ymm3
-vfmsubpd ymm0, ymm1, yword [rax], ymm3
-vfmsubpd ymm0, ymm1, ymm2, yword [rax]
-
-vfmsubps xmm0, xmm1, xmm2, xmm3
-vfmsubps xmm0, xmm1, dqword [rax], xmm3
-vfmsubps xmm0, xmm1, xmm2, dqword [rax]
-vfmsubps ymm0, ymm1, ymm2, ymm3
-vfmsubps ymm0, ymm1, yword [rax], ymm3
-vfmsubps ymm0, ymm1, ymm2, yword [rax]
-
-vfmsubsd xmm0, xmm1, xmm2, xmm3
-vfmsubsd xmm0, xmm1, qword [rax], xmm3
-vfmsubsd xmm0, xmm1, xmm2, qword [rax]
-
-vfmsubss xmm0, xmm1, xmm2, xmm3
-vfmsubss xmm0, xmm1, dword [rax], xmm3
-vfmsubss xmm0, xmm1, xmm2, dword [rax]
-
-vfnmaddpd xmm0, xmm1, xmm2, xmm3
-vfnmaddpd xmm0, xmm1, dqword [rax], xmm3
-vfnmaddpd xmm0, xmm1, xmm2, dqword [rax]
-vfnmaddpd ymm0, ymm1, ymm2, ymm3
-vfnmaddpd ymm0, ymm1, yword [rax], ymm3
-vfnmaddpd ymm0, ymm1, ymm2, yword [rax]
-
-vfnmaddps xmm0, xmm1, xmm2, xmm3
-vfnmaddps xmm0, xmm1, dqword [rax], xmm3
-vfnmaddps xmm0, xmm1, xmm2, dqword [rax]
-vfnmaddps ymm0, ymm1, ymm2, ymm3
-vfnmaddps ymm0, ymm1, yword [rax], ymm3
-vfnmaddps ymm0, ymm1, ymm2, yword [rax]
-
-vfnmaddsd xmm0, xmm1, xmm2, xmm3
-vfnmaddsd xmm0, xmm1, qword [rax], xmm3
-vfnmaddsd xmm0, xmm1, xmm2, qword [rax]
-
-vfnmaddss xmm0, xmm1, xmm2, xmm3
-vfnmaddss xmm0, xmm1, dword [rax], xmm3
-vfnmaddss xmm0, xmm1, xmm2, dword [rax]
-
-vfnmsubpd xmm0, xmm1, xmm2, xmm3
-vfnmsubpd xmm0, xmm1, dqword [rax], xmm3
-vfnmsubpd xmm0, xmm1, xmm2, dqword [rax]
-vfnmsubpd ymm0, ymm1, ymm2, ymm3
-vfnmsubpd ymm0, ymm1, yword [rax], ymm3
-vfnmsubpd ymm0, ymm1, ymm2, yword [rax]
-
-vfnmsubps xmm0, xmm1, xmm2, xmm3
-vfnmsubps xmm0, xmm1, dqword [rax], xmm3
-vfnmsubps xmm0, xmm1, xmm2, dqword [rax]
-vfnmsubps ymm0, ymm1, ymm2, ymm3
-vfnmsubps ymm0, ymm1, yword [rax], ymm3
-vfnmsubps ymm0, ymm1, ymm2, yword [rax]
-
-vfnmsubsd xmm0, xmm1, xmm2, xmm3
-vfnmsubsd xmm0, xmm1, qword [rax], xmm3
-vfnmsubsd xmm0, xmm1, xmm2, qword [rax]
-
-vfnmsubss xmm0, xmm1, xmm2, xmm3
-vfnmsubss xmm0, xmm1, dword [rax], xmm3
-vfnmsubss xmm0, xmm1, xmm2, dword [rax]
-
+vfmadd132ss xmm1, xmm2, xmm3
+vfmadd132ss xmm1, xmm2, dword [rax]
+vfmadd132ss xmm1, xmm2, [rax]
+vfmadd231ss xmm1, xmm2, xmm3
+vfmadd231ss xmm1, xmm2, dword [rax]
+vfmadd231ss xmm1, xmm2, [rax]
+vfmadd213ss xmm1, xmm2, xmm3
+vfmadd213ss xmm1, xmm2, dword [rax]
+vfmadd213ss xmm1, xmm2, [rax]
+vfmadd132sd xmm1, xmm2, xmm3
+vfmadd132sd xmm1, xmm2, qword [rax]
+vfmadd132sd xmm1, xmm2, [rax]
+vfmadd231sd xmm1, xmm2, xmm3
+vfmadd231sd xmm1, xmm2, qword [rax]
+vfmadd231sd xmm1, xmm2, [rax]
+vfmadd213sd xmm1, xmm2, xmm3
+vfmadd213sd xmm1, xmm2, qword [rax]
+vfmadd213sd xmm1, xmm2, [rax]
+vfmadd132ps xmm1, xmm2, xmm3
+vfmadd132ps xmm1, xmm2, xmm3
+vfmadd132ps xmm1, xmm2, [rax]
+vfmadd231ps xmm1, xmm2, xmm3
+vfmadd231ps xmm1, xmm2, xmm3
+vfmadd231ps xmm1, xmm2, [rax]
+vfmadd213ps xmm1, xmm2, xmm3
+vfmadd213ps xmm1, xmm2, xmm3
+vfmadd213ps xmm1, xmm2, [rax]
+vfmadd132ps ymm1, ymm2, ymm3
+vfmadd132ps ymm1, ymm2, yword [rax]
+vfmadd132ps ymm1, ymm2, [rax]
+vfmadd231ps ymm1, ymm2, ymm3
+vfmadd231ps ymm1, ymm2, yword [rax]
+vfmadd231ps ymm1, ymm2, [rax]
+vfmadd213ps ymm1, ymm2, ymm3
+vfmadd213ps ymm1, ymm2, yword [rax]
+vfmadd213ps ymm1, ymm2, [rax]
+vfmadd132pd xmm1, xmm2, xmm3
+vfmadd132pd xmm1, xmm2, dqword [rax]
+vfmadd132pd xmm1, xmm2, [rax]
+vfmadd231pd xmm1, xmm2, xmm3
+vfmadd231pd xmm1, xmm2, dqword [rax]
+vfmadd231pd xmm1, xmm2, [rax]
+vfmadd213pd xmm1, xmm2, xmm3
+vfmadd213pd xmm1, xmm2, dqword [rax]
+vfmadd213pd xmm1, xmm2, [rax]
+vfmadd132pd ymm1, ymm2, ymm3
+vfmadd132pd ymm1, ymm2, yword [rax]
+vfmadd132pd ymm1, ymm2, [rax]
+vfmadd231pd ymm1, ymm2, ymm3
+vfmadd231pd ymm1, ymm2, yword [rax]
+vfmadd231pd ymm1, ymm2, [rax]
+vfmadd213pd ymm1, ymm2, ymm3
+vfmadd213pd ymm1, ymm2, yword [rax]
+vfmadd213pd ymm1, ymm2, [rax]
+vfmsub132ss xmm1, xmm2, xmm3
+vfmsub132ss xmm1, xmm2, dword [rax]
+vfmsub132ss xmm1, xmm2, [rax]
+vfmsub231ss xmm1, xmm2, xmm3
+vfmsub231ss xmm1, xmm2, dword [rax]
+vfmsub231ss xmm1, xmm2, [rax]
+vfmsub213ss xmm1, xmm2, xmm3
+vfmsub213ss xmm1, xmm2, dword [rax]
+vfmsub213ss xmm1, xmm2, [rax]
+vfmsub132sd xmm1, xmm2, xmm3
+vfmsub132sd xmm1, xmm2, qword [rax]
+vfmsub132sd xmm1, xmm2, [rax]
+vfmsub231sd xmm1, xmm2, xmm3
+vfmsub231sd xmm1, xmm2, qword [rax]
+vfmsub231sd xmm1, xmm2, [rax]
+vfmsub213sd xmm1, xmm2, xmm3
+vfmsub213sd xmm1, xmm2, qword [rax]
+vfmsub213sd xmm1, xmm2, [rax]
+vfmsub132ps xmm1, xmm2, xmm3
+vfmsub132ps xmm1, xmm2, xmm3
+vfmsub132ps xmm1, xmm2, [rax]
+vfmsub231ps xmm1, xmm2, xmm3
+vfmsub231ps xmm1, xmm2, xmm3
+vfmsub231ps xmm1, xmm2, [rax]
+vfmsub213ps xmm1, xmm2, xmm3
+vfmsub213ps xmm1, xmm2, xmm3
+vfmsub213ps xmm1, xmm2, [rax]
+vfmsub132ps ymm1, ymm2, ymm3
+vfmsub132ps ymm1, ymm2, yword [rax]
+vfmsub132ps ymm1, ymm2, [rax]
+vfmsub231ps ymm1, ymm2, ymm3
+vfmsub231ps ymm1, ymm2, yword [rax]
+vfmsub231ps ymm1, ymm2, [rax]
+vfmsub213ps ymm1, ymm2, ymm3
+vfmsub213ps ymm1, ymm2, yword [rax]
+vfmsub213ps ymm1, ymm2, [rax]
+vfmsub132pd xmm1, xmm2, xmm3
+vfmsub132pd xmm1, xmm2, dqword [rax]
+vfmsub132pd xmm1, xmm2, [rax]
+vfmsub231pd xmm1, xmm2, xmm3
+vfmsub231pd xmm1, xmm2, dqword [rax]
+vfmsub231pd xmm1, xmm2, [rax]
+vfmsub213pd xmm1, xmm2, xmm3
+vfmsub213pd xmm1, xmm2, dqword [rax]
+vfmsub213pd xmm1, xmm2, [rax]
+vfmsub132pd ymm1, ymm2, ymm3
+vfmsub132pd ymm1, ymm2, yword [rax]
+vfmsub132pd ymm1, ymm2, [rax]
+vfmsub231pd ymm1, ymm2, ymm3
+vfmsub231pd ymm1, ymm2, yword [rax]
+vfmsub231pd ymm1, ymm2, [rax]
+vfmsub213pd ymm1, ymm2, ymm3
+vfmsub213pd ymm1, ymm2, yword [rax]
+vfmsub213pd ymm1, ymm2, [rax]
+vfnmadd132ss xmm1, xmm2, xmm3
+vfnmadd132ss xmm1, xmm2, dword [rax]
+vfnmadd132ss xmm1, xmm2, [rax]
+vfnmadd231ss xmm1, xmm2, xmm3
+vfnmadd231ss xmm1, xmm2, dword [rax]
+vfnmadd231ss xmm1, xmm2, [rax]
+vfnmadd213ss xmm1, xmm2, xmm3
+vfnmadd213ss xmm1, xmm2, dword [rax]
+vfnmadd213ss xmm1, xmm2, [rax]
+vfnmadd132sd xmm1, xmm2, xmm3
+vfnmadd132sd xmm1, xmm2, qword [rax]
+vfnmadd132sd xmm1, xmm2, [rax]
+vfnmadd231sd xmm1, xmm2, xmm3
+vfnmadd231sd xmm1, xmm2, qword [rax]
+vfnmadd231sd xmm1, xmm2, [rax]
+vfnmadd213sd xmm1, xmm2, xmm3
+vfnmadd213sd xmm1, xmm2, qword [rax]
+vfnmadd213sd xmm1, xmm2, [rax]
+vfnmadd132ps xmm1, xmm2, xmm3
+vfnmadd132ps xmm1, xmm2, xmm3
+vfnmadd132ps xmm1, xmm2, [rax]
+vfnmadd231ps xmm1, xmm2, xmm3
+vfnmadd231ps xmm1, xmm2, xmm3
+vfnmadd231ps xmm1, xmm2, [rax]
+vfnmadd213ps xmm1, xmm2, xmm3
+vfnmadd213ps xmm1, xmm2, xmm3
+vfnmadd213ps xmm1, xmm2, [rax]
+vfnmadd132ps ymm1, ymm2, ymm3
+vfnmadd132ps ymm1, ymm2, yword [rax]
+vfnmadd132ps ymm1, ymm2, [rax]
+vfnmadd231ps ymm1, ymm2, ymm3
+vfnmadd231ps ymm1, ymm2, yword [rax]
+vfnmadd231ps ymm1, ymm2, [rax]
+vfnmadd213ps ymm1, ymm2, ymm3
+vfnmadd213ps ymm1, ymm2, yword [rax]
+vfnmadd213ps ymm1, ymm2, [rax]
+vfnmadd132pd xmm1, xmm2, xmm3
+vfnmadd132pd xmm1, xmm2, dqword [rax]
+vfnmadd132pd xmm1, xmm2, [rax]
+vfnmadd231pd xmm1, xmm2, xmm3
+vfnmadd231pd xmm1, xmm2, dqword [rax]
+vfnmadd231pd xmm1, xmm2, [rax]
+vfnmadd213pd xmm1, xmm2, xmm3
+vfnmadd213pd xmm1, xmm2, dqword [rax]
+vfnmadd213pd xmm1, xmm2, [rax]
+vfnmadd132pd ymm1, ymm2, ymm3
+vfnmadd132pd ymm1, ymm2, yword [rax]
+vfnmadd132pd ymm1, ymm2, [rax]
+vfnmadd231pd ymm1, ymm2, ymm3
+vfnmadd231pd ymm1, ymm2, yword [rax]
+vfnmadd231pd ymm1, ymm2, [rax]
+vfnmadd213pd ymm1, ymm2, ymm3
+vfnmadd213pd ymm1, ymm2, yword [rax]
+vfnmadd213pd ymm1, ymm2, [rax]
+vfnmsub132ss xmm1, xmm2, xmm3
+vfnmsub132ss xmm1, xmm2, dword [rax]
+vfnmsub132ss xmm1, xmm2, [rax]
+vfnmsub231ss xmm1, xmm2, xmm3
+vfnmsub231ss xmm1, xmm2, dword [rax]
+vfnmsub231ss xmm1, xmm2, [rax]
+vfnmsub213ss xmm1, xmm2, xmm3
+vfnmsub213ss xmm1, xmm2, dword [rax]
+vfnmsub213ss xmm1, xmm2, [rax]
+vfnmsub132sd xmm1, xmm2, xmm3
+vfnmsub132sd xmm1, xmm2, qword [rax]
+vfnmsub132sd xmm1, xmm2, [rax]
+vfnmsub231sd xmm1, xmm2, xmm3
+vfnmsub231sd xmm1, xmm2, qword [rax]
+vfnmsub231sd xmm1, xmm2, [rax]
+vfnmsub213sd xmm1, xmm2, xmm3
+vfnmsub213sd xmm1, xmm2, qword [rax]
+vfnmsub213sd xmm1, xmm2, [rax]
+vfnmsub132ps xmm1, xmm2, xmm3
+vfnmsub132ps xmm1, xmm2, xmm3
+vfnmsub132ps xmm1, xmm2, [rax]
+vfnmsub231ps xmm1, xmm2, xmm3
+vfnmsub231ps xmm1, xmm2, xmm3
+vfnmsub231ps xmm1, xmm2, [rax]
+vfnmsub213ps xmm1, xmm2, xmm3
+vfnmsub213ps xmm1, xmm2, xmm3
+vfnmsub213ps xmm1, xmm2, [rax]
+vfnmsub132ps ymm1, ymm2, ymm3
+vfnmsub132ps ymm1, ymm2, yword [rax]
+vfnmsub132ps ymm1, ymm2, [rax]
+vfnmsub231ps ymm1, ymm2, ymm3
+vfnmsub231ps ymm1, ymm2, yword [rax]
+vfnmsub231ps ymm1, ymm2, [rax]
+vfnmsub213ps ymm1, ymm2, ymm3
+vfnmsub213ps ymm1, ymm2, yword [rax]
+vfnmsub213ps ymm1, ymm2, [rax]
+vfnmsub132pd xmm1, xmm2, xmm3
+vfnmsub132pd xmm1, xmm2, dqword [rax]
+vfnmsub132pd xmm1, xmm2, [rax]
+vfnmsub231pd xmm1, xmm2, xmm3
+vfnmsub231pd xmm1, xmm2, dqword [rax]
+vfnmsub231pd xmm1, xmm2, [rax]
+vfnmsub213pd xmm1, xmm2, xmm3
+vfnmsub213pd xmm1, xmm2, dqword [rax]
+vfnmsub213pd xmm1, xmm2, [rax]
+vfnmsub132pd ymm1, ymm2, ymm3
+vfnmsub132pd ymm1, ymm2, yword [rax]
+vfnmsub132pd ymm1, ymm2, [rax]
+vfnmsub231pd ymm1, ymm2, ymm3
+vfnmsub231pd ymm1, ymm2, yword [rax]
+vfnmsub231pd ymm1, ymm2, [rax]
+vfnmsub213pd ymm1, ymm2, ymm3
+vfnmsub213pd ymm1, ymm2, yword [rax]
+vfnmsub213pd ymm1, ymm2, [rax]
+vfmaddsub132ps xmm1, xmm2, xmm3
+vfmaddsub132ps xmm1, xmm2, xmm3
+vfmaddsub132ps xmm1, xmm2, [rax]
+vfmaddsub231ps xmm1, xmm2, xmm3
+vfmaddsub231ps xmm1, xmm2, xmm3
+vfmaddsub231ps xmm1, xmm2, [rax]
+vfmaddsub213ps xmm1, xmm2, xmm3
+vfmaddsub213ps xmm1, xmm2, xmm3
+vfmaddsub213ps xmm1, xmm2, [rax]
+vfmaddsub132ps ymm1, ymm2, ymm3
+vfmaddsub132ps ymm1, ymm2, yword [rax]
+vfmaddsub132ps ymm1, ymm2, [rax]
+vfmaddsub231ps ymm1, ymm2, ymm3
+vfmaddsub231ps ymm1, ymm2, yword [rax]
+vfmaddsub231ps ymm1, ymm2, [rax]
+vfmaddsub213ps ymm1, ymm2, ymm3
+vfmaddsub213ps ymm1, ymm2, yword [rax]
+vfmaddsub213ps ymm1, ymm2, [rax]
+vfmaddsub132pd xmm1, xmm2, xmm3
+vfmaddsub132pd xmm1, xmm2, dqword [rax]
+vfmaddsub132pd xmm1, xmm2, [rax]
+vfmaddsub231pd xmm1, xmm2, xmm3
+vfmaddsub231pd xmm1, xmm2, dqword [rax]
+vfmaddsub231pd xmm1, xmm2, [rax]
+vfmaddsub213pd xmm1, xmm2, xmm3
+vfmaddsub213pd xmm1, xmm2, dqword [rax]
+vfmaddsub213pd xmm1, xmm2, [rax]
+vfmaddsub132pd ymm1, ymm2, ymm3
+vfmaddsub132pd ymm1, ymm2, yword [rax]
+vfmaddsub132pd ymm1, ymm2, [rax]
+vfmaddsub231pd ymm1, ymm2, ymm3
+vfmaddsub231pd ymm1, ymm2, yword [rax]
+vfmaddsub231pd ymm1, ymm2, [rax]
+vfmaddsub213pd ymm1, ymm2, ymm3
+vfmaddsub213pd ymm1, ymm2, yword [rax]
+vfmaddsub213pd ymm1, ymm2, [rax]
+vfmsubadd132ps xmm1, xmm2, xmm3
+vfmsubadd132ps xmm1, xmm2, xmm3
+vfmsubadd132ps xmm1, xmm2, [rax]
+vfmsubadd231ps xmm1, xmm2, xmm3
+vfmsubadd231ps xmm1, xmm2, xmm3
+vfmsubadd231ps xmm1, xmm2, [rax]
+vfmsubadd213ps xmm1, xmm2, xmm3
+vfmsubadd213ps xmm1, xmm2, xmm3
+vfmsubadd213ps xmm1, xmm2, [rax]
+vfmsubadd132ps ymm1, ymm2, ymm3
+vfmsubadd132ps ymm1, ymm2, yword [rax]
+vfmsubadd132ps ymm1, ymm2, [rax]
+vfmsubadd231ps ymm1, ymm2, ymm3
+vfmsubadd231ps ymm1, ymm2, yword [rax]
+vfmsubadd231ps ymm1, ymm2, [rax]
+vfmsubadd213ps ymm1, ymm2, ymm3
+vfmsubadd213ps ymm1, ymm2, yword [rax]
+vfmsubadd213ps ymm1, ymm2, [rax]
+vfmsubadd132pd xmm1, xmm2, xmm3
+vfmsubadd132pd xmm1, xmm2, dqword [rax]
+vfmsubadd132pd xmm1, xmm2, [rax]
+vfmsubadd231pd xmm1, xmm2, xmm3
+vfmsubadd231pd xmm1, xmm2, dqword [rax]
+vfmsubadd231pd xmm1, xmm2, [rax]
+vfmsubadd213pd xmm1, xmm2, xmm3
+vfmsubadd213pd xmm1, xmm2, dqword [rax]
+vfmsubadd213pd xmm1, xmm2, [rax]
+vfmsubadd132pd ymm1, ymm2, ymm3
+vfmsubadd132pd ymm1, ymm2, yword [rax]
+vfmsubadd132pd ymm1, ymm2, [rax]
+vfmsubadd231pd ymm1, ymm2, ymm3
+vfmsubadd231pd ymm1, ymm2, yword [rax]
+vfmsubadd231pd ymm1, ymm2, [rax]
+vfmsubadd213pd ymm1, ymm2, ymm3
+vfmsubadd213pd ymm1, ymm2, yword [rax]
+vfmsubadd213pd ymm1, ymm2, [rax]
diff --git a/modules/arch/x86/tests/fma.hex b/modules/arch/x86/tests/fma.hex
index 7f51092a..161933f9 100644
--- a/modules/arch/x86/tests/fma.hex
+++ b/modules/arch/x86/tests/fma.hex
@@ -1,540 +1,1440 @@
 c4 
-e3 
-61 
+e2 
 69 
-c2 
-10 
+99 
+cb 
 c4 
-e3 
-61 
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 69 
-00 
-10 
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 c4 
-e3 
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 69 
-00 
-10 
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 c4 
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 69 
-00 
-10 
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 c4 
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 e9 
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 69 
-00 
-10 
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 c4 
-e3 
-65 
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 69 
-c2 
-10 
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 c4 
-e3 
-65 
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 69 
-00 
-10 
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 c4 
-e3 
-65 
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 69 
-00 
-10 
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 c4 
-e3 
-ed 
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 69 
-00 
-10 
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 c4 
-e3 
-ed 
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 69 
-00 
-10 
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diff --git a/modules/arch/x86/tests/vpermil2.asm b/modules/arch/x86/tests/vpermil2.asm
deleted file mode 100644
index cc774c1b..00000000
--- a/modules/arch/x86/tests/vpermil2.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-[bits 64]
-vpermiltd2pd xmm1, xmm2, xmm3, xmm4	; 0
-;vpermiltd2pd xmm1, xmm2, xmm3, xmm4	; 1
-vpermilmo2pd xmm1, xmm2, xmm3, xmm4	; 2
-vpermilmz2pd xmm1, xmm2, xmm3, xmm4	; 3
-
-vpermiltd2ps xmm1, xmm2, xmm3, xmm4	; 0
-;vpermiltd2ps xmm1, xmm2, xmm3, xmm4	; 1
-vpermilmo2ps xmm1, xmm2, xmm3, xmm4	; 2
-vpermilmz2ps xmm1, xmm2, xmm3, xmm4	; 3
diff --git a/modules/arch/x86/tests/vpermil2.hex b/modules/arch/x86/tests/vpermil2.hex
deleted file mode 100644
index 29d1af0a..00000000
--- a/modules/arch/x86/tests/vpermil2.hex
+++ /dev/null
@@ -1,36 +0,0 @@
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