Add support for VEX-encoded pclmul*qdq instructions per the latest AVX spec.

To stay consist with handling of other VEX instructions, also add yasm
extensions to support combining the first two operands for direct translation
from non-VEX to VEX-encoded by simply adding a "v" prefix to the opcode.

Contributed by: Mark Charney, Intel Corporation <Mark.Charney@intel.com>
Yasm extensions by: Peter Johnson

svn path=/trunk/yasm/; revision=2173

3 files changed, 175 insertions, 6 deletions

diff --git a/modules/arch/x86/gen_x86_insn.py b/modules/arch/x86/gen_x86_insn.py
index 60f27eb4..271d3ffa 100755
--- a/modules/arch/x86/gen_x86_insn.py
+++ b/modules/arch/x86/gen_x86_insn.py
@@ -6462,20 +6462,49 @@ add_insn("vaeskeygenassist", "aes_imm", modifiers=[0x3A, 0xDF, VEXL0],
 # Intel PCLMULQDQ instruction
 #####################################################################
 
-add_insn("pclmulqdq", "aes_imm", modifiers=[0x3A, 0x44], cpu=["CLMUL"])
+add_group("pclmulqdq",
+    cpu=["CLMUL"],
+    modifiers=["Op1Add", "Op2Add", "SetVEX"],
+    prefix=0x66,
+    opcode=[0x0F, 0x00, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+add_group("pclmulqdq",
+    cpu=["CLMUL", "AVX"],
+    modifiers=["Op1Add", "Op2Add"],
+    vex=128,
+    prefix=0x66,
+    opcode=[0x0F, 0x00, 0x00],
+    operands=[Operand(type="SIMDReg", size=128,               dest="Spare"),
+              Operand(type="SIMDReg", size=128,               dest="VEX"),
+              Operand(type="SIMDRM",  size=128, relaxed=True, dest="EA"),
+              Operand(type="Imm",     size=8,   relaxed=True, dest="Imm")])
+
+add_insn("pclmulqdq", "pclmulqdq", modifiers=[0x3A, 0x44])
+add_insn("vpclmulqdq", "pclmulqdq", modifiers=[0x3A, 0x44, VEXL0], avx=True)
 
 add_group("pclmulqdq_fixed",
     cpu=["CLMUL"],
+    modifiers=["Imm8", "SetVEX"],
+    prefix=0x66,
+    opcode=[0x0F, 0x3A, 0x44],
+    operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+add_group("pclmulqdq_fixed",
+    cpu=["CLMUL", "AVX"],
     modifiers=["Imm8"],
+    vex=128,
     prefix=0x66,
     opcode=[0x0F, 0x3A, 0x44],
     operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDRM",  size=128, relaxed=True, dest="EA")])
 
-add_insn("pclmullqlqdq", "pclmulqdq_fixed", modifiers=[0x00])
-add_insn("pclmulhqlqdq", "pclmulqdq_fixed", modifiers=[0x01])
-add_insn("pclmullqhqdq", "pclmulqdq_fixed", modifiers=[0x10])
-add_insn("pclmulhqhqdq", "pclmulqdq_fixed", modifiers=[0x11])
+for comb, combval in zip(["lql","hql","lqh","hqh"], [0x00,0x01,0x10,0x11]):
+    add_insn("pclmul"+comb+"qdq", "pclmulqdq_fixed", modifiers=[combval])
+    add_insn("vpclmul"+comb+"qdq", "pclmulqdq_fixed",
+             modifiers=[combval, VEXL0], avx=True)
 
 #####################################################################
 # AMD SSE4a instructions
diff --git a/modules/arch/x86/tests/clmul.asm b/modules/arch/x86/tests/clmul.asm
index 053bc449..92e168ef 100644
--- a/modules/arch/x86/tests/clmul.asm
+++ b/modules/arch/x86/tests/clmul.asm
@@ -3,20 +3,40 @@
 pclmulqdq xmm1, xmm2, 5
 pclmulqdq xmm1, [rax], byte 5
 pclmulqdq xmm1, dqword [rax], 5
+vpclmulqdq xmm1, xmm2, 0x10
+vpclmulqdq xmm1, dqword [rbx], 0x10
+vpclmulqdq xmm0, xmm1, xmm2, 0x10
+vpclmulqdq xmm0, xmm1, dqword [rbx], 0x10
 
 pclmullqlqdq xmm1, xmm2
 pclmullqlqdq xmm1, [rax]
 pclmullqlqdq xmm1, dqword [rax]
+vpclmullqlqdq xmm1, xmm2
+vpclmullqlqdq xmm1, dqword[rbx]
+vpclmullqlqdq xmm0, xmm1, xmm2
+vpclmullqlqdq xmm0, xmm1, dqword[rbx]
 
 pclmulhqlqdq xmm1, xmm2
 pclmulhqlqdq xmm1, [rax]
 pclmulhqlqdq xmm1, dqword [rax]
+vpclmulhqlqdq xmm1, xmm2
+vpclmulhqlqdq xmm1, dqword[rbx]
+vpclmulhqlqdq xmm0, xmm1, xmm2
+vpclmulhqlqdq xmm0, xmm1, dqword[rbx]
 
 pclmullqhqdq xmm1, xmm2
 pclmullqhqdq xmm1, [rax]
 pclmullqhqdq xmm1, dqword [rax]
+vpclmullqhqdq xmm1, xmm2
+vpclmullqhqdq xmm1, dqword[rbx]
+vpclmullqhqdq xmm0, xmm1, xmm2
+vpclmullqhqdq xmm0, xmm1, dqword[rbx]
 
 pclmulhqhqdq xmm1, xmm2
 pclmulhqhqdq xmm1, [rax]
 pclmulhqhqdq xmm1, dqword [rax]
+vpclmulhqhqdq xmm1, xmm2
+vpclmulhqhqdq xmm1, dqword[rbx]
+vpclmulhqhqdq xmm0, xmm1, xmm2
+vpclmulhqhqdq xmm0, xmm1, dqword[rbx]
 
diff --git a/modules/arch/x86/tests/clmul.hex b/modules/arch/x86/tests/clmul.hex
index cd7a0242..6aad748a 100644
--- a/modules/arch/x86/tests/clmul.hex
+++ b/modules/arch/x86/tests/clmul.hex
@@ -16,6 +16,30 @@ ca
 44 
 08 
 05 
+c4 
+e3 
+71 
+44 
+ca 
+10 
+c4 
+e3 
+71 
+44 
+0b 
+10 
+c4 
+e3 
+71 
+44 
+c2 
+10 
+c4 
+e3 
+71 
+44 
+03 
+10 
 66 
 0f 
 3a 
@@ -34,6 +58,30 @@ ca
 44 
 08 
 00 
+c4 
+e3 
+71 
+44 
+ca 
+00 
+c4 
+e3 
+71 
+44 
+0b 
+00 
+c4 
+e3 
+71 
+44 
+c2 
+00 
+c4 
+e3 
+71 
+44 
+03 
+00 
 66 
 0f 
 3a 
@@ -52,6 +100,30 @@ ca
 44 
 08 
 01 
+c4 
+e3 
+71 
+44 
+ca 
+01 
+c4 
+e3 
+71 
+44 
+0b 
+01 
+c4 
+e3 
+71 
+44 
+c2 
+01 
+c4 
+e3 
+71 
+44 
+03 
+01 
 66 
 0f 
 3a 
@@ -70,6 +142,30 @@ ca
 44 
 08 
 10 
+c4 
+e3 
+71 
+44 
+ca 
+10 
+c4 
+e3 
+71 
+44 
+0b 
+10 
+c4 
+e3 
+71 
+44 
+c2 
+10 
+c4 
+e3 
+71 
+44 
+03 
+10 
 66 
 0f 
 3a 
@@ -88,3 +184,27 @@ ca
 44 
 08 
 11 
+c4 
+e3 
+71 
+44 
+ca 
+11 
+c4 
+e3 
+71 
+44 
+0b 
+11 
+c4 
+e3 
+71 
+44 
+c2 
+11 
+c4 
+e3 
+71 
+44 
+03 
+11