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| author | Edward Cragg <edward.cragg@codethink.co.uk> | 2015-05-29 17:20:30 +0100 |
|---|---|---|
| committer | Edward Cragg <edward.cragg@codethink.co.uk> | 2015-06-01 15:55:58 +0100 |
| commit | 3d419f4c3e4515e5725ceb0717d66550e6490a10 (patch) | |
| tree | 10b8c104ba0950cd4b199a9e0e7dabee003a7ab7 /example/constrain_clocks.sdc | |
| download | bsp-support-3d419f4c3e4515e5725ceb0717d66550e6490a10.tar.gz | |
SoCFPGA: Add example Quartus files
These files can be used to re-create the Quartus project
needed to generate the headers required to build the
SPL preloader
Change-Id: Ic5fc0b9e629244e8687305fbcb2207c029d64527
Diffstat (limited to 'example/constrain_clocks.sdc')
| -rw-r--r-- | example/constrain_clocks.sdc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/example/constrain_clocks.sdc b/example/constrain_clocks.sdc new file mode 100644 index 0000000..840b227 --- /dev/null +++ b/example/constrain_clocks.sdc @@ -0,0 +1,3 @@ +create_clock -name "clk_50mhz" -period 20.000ns clk_clk +derive_pll_clocks -create_base_clocks +derive_clock_uncertainty
\ No newline at end of file |