Remove lib/igb and kmod/igb folder as part of restructuring

Removed lib/igb and kmod/igb and created as separate repos under AVnu.
lib/igb is again added as submodule to lib/igb_avb/lib as there is build
dependency for lib/common.

12 files changed, 1 insertions, 6326 deletions

diff --git a/lib/common/Makefile b/lib/common/Makefile
index 5b50f708..7685056a 100644
--- a/lib/common/Makefile
+++ b/lib/common/Makefile
@@ -15,7 +15,7 @@ ALL_OBJS = avb_avtp.o avb_gptp.o $(AVB_IGB_OBJ)
 
 all: $(ALL_OBJS)
 
-avb_igb.o: CPPFLAGS = -I../igb
+avb_igb.o: CPPFLAGS = -I../igb_avb/lib
 avb_igb.o: avb_igb.c avb_igb.h
 avb_avtp.o: avb_avtp.c avb_avtp.h
 avb_gptp.o: avb_gptp.c avb_gptp.h
diff --git a/lib/igb/LICENSE b/lib/igb/LICENSE
deleted file mode 100644
index d4256c47..00000000
--- a/lib/igb/LICENSE
+++ /dev/null
@@ -1,29 +0,0 @@
-  Copyright (c) 2012-2015, Intel Corporation
-  All rights reserved.
-
-  Redistribution and use in source and binary forms, with or without
-  modification, are permitted provided that the following conditions are met:
-
-   1. Redistributions of source code must retain the above copyright notice,
-      this list of conditions and the following disclaimer.
-
-   2. Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-
-   3. Neither the name of the Intel Corporation nor the names of its
-      contributors may be used to endorse or promote products derived from
-      this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE.
-
diff --git a/lib/igb/Makefile b/lib/igb/Makefile
deleted file mode 100644
index 8a0c4151..00000000
--- a/lib/igb/Makefile
+++ /dev/null
@@ -1,22 +0,0 @@
-OBJS=igb
-INCL=e1000_82575.h e1000_defines.h e1000_hw.h e1000_osdep.h e1000_regs.h igb.h
-AVBLIB=libigb.a
-#CFLAGS=-ggdb
-
-CC?=gcc
-RANLIB?=ranlib
-
-all: $(AVBLIB)
-
-$(AVBLIB): $(addsuffix .o,$(OBJS))
-	$(RM) $@
-	$(AR) rcs $@ $^
-	$(RANLIB) $@
-
-igb.o: igb.c $(INCL)
-	$(CC) -c $(INCFLAGS) $(CFLAGS) igb.c
-
-clean:
-	$(RM) `find . -name "*~" -o -name "*.[oa]" -o -name "\#*\#" -o -name TAGS -o -name core -o -name "*.orig"`
-
-
diff --git a/lib/igb/e1000_82575.h b/lib/igb/e1000_82575.h
deleted file mode 100644
index bac114ea..00000000
--- a/lib/igb/e1000_82575.h
+++ /dev/null
@@ -1,511 +0,0 @@
-/******************************************************************************
-
-  Copyright (c) 2001-2012, Intel Corporation
-  All rights reserved.
-
-  Redistribution and use in source and binary forms, with or without
-  modification, are permitted provided that the following conditions are met:
-
-   1. Redistributions of source code must retain the above copyright notice,
-      this list of conditions and the following disclaimer.
-
-   2. Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-
-   3. Neither the name of the Intel Corporation nor the names of its
-      contributors may be used to endorse or promote products derived from
-      this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE.
-
-******************************************************************************/
-/*$FreeBSD$*/
-
-#ifndef _E1000_82575_H_
-#define _E1000_82575_H_
-
-#define ID_LED_DEFAULT_82575_SERDES	((ID_LED_DEF1_DEF2 << 12) | \
-					 (ID_LED_DEF1_DEF2 <<  8) | \
-					 (ID_LED_DEF1_DEF2 <<  4) | \
-					 (ID_LED_OFF1_ON2))
-/*
- * Receive Address Register Count
- * Number of high/low register pairs in the RAR.  The RAR (Receive Address
- * Registers) holds the directed and multicast addresses that we monitor.
- * These entries are also used for MAC-based filtering.
- */
-/*
- * For 82576, there are an additional set of RARs that begin at an offset
- * separate from the first set of RARs.
- */
-#define E1000_RAR_ENTRIES_82575	16
-#define E1000_RAR_ENTRIES_82576	24
-#define E1000_RAR_ENTRIES_82580	24
-#define E1000_RAR_ENTRIES_I350	32
-#define E1000_SW_SYNCH_MB	0x00000100
-#define E1000_STAT_DEV_RST_SET	0x00100000
-#define E1000_CTRL_DEV_RST	0x20000000
-
-#ifdef E1000_BIT_FIELDS
-struct e1000_adv_data_desc {
-	__le64 buffer_addr;    /* Address of the descriptor's data buffer */
-	union {
-		u32 data;
-		struct {
-			u32 datalen:16; /* Data buffer length */
-			u32 rsvd:4;
-			u32 dtyp:4;  /* Descriptor type */
-			u32 dcmd:8;  /* Descriptor command */
-		} config;
-	} lower;
-	union {
-		u32 data;
-		struct {
-			u32 status:4;  /* Descriptor status */
-			u32 idx:4;
-			u32 popts:6;  /* Packet Options */
-			u32 paylen:18; /* Payload length */
-		} options;
-	} upper;
-};
-
-#define E1000_TXD_DTYP_ADV_C	0x2  /* Advanced Context Descriptor */
-#define E1000_TXD_DTYP_ADV_D	0x3  /* Advanced Data Descriptor */
-#define E1000_ADV_TXD_CMD_DEXT	0x20 /* Descriptor extension (0 = legacy) */
-#define E1000_ADV_TUCMD_IPV4	0x2  /* IP Packet Type: 1=IPv4 */
-#define E1000_ADV_TUCMD_IPV6	0x0  /* IP Packet Type: 0=IPv6 */
-#define E1000_ADV_TUCMD_L4T_UDP	0x0  /* L4 Packet TYPE of UDP */
-#define E1000_ADV_TUCMD_L4T_TCP	0x4  /* L4 Packet TYPE of TCP */
-#define E1000_ADV_TUCMD_MKRREQ	0x10 /* Indicates markers are required */
-#define E1000_ADV_DCMD_EOP	0x1  /* End of Packet */
-#define E1000_ADV_DCMD_IFCS	0x2  /* Insert FCS (Ethernet CRC) */
-#define E1000_ADV_DCMD_RS	0x8  /* Report Status */
-#define E1000_ADV_DCMD_VLE	0x40 /* Add VLAN tag */
-#define E1000_ADV_DCMD_TSE	0x80 /* TCP Seg enable */
-/* Extended Device Control */
-#define E1000_CTRL_EXT_NSICR	0x00000001 /* Disable Intr Clear all on read */
-
-struct e1000_adv_context_desc {
-	union {
-		u32 ip_config;
-		struct {
-			u32 iplen:9;
-			u32 maclen:7;
-			u32 vlan_tag:16;
-		} fields;
-	} ip_setup;
-	u32 seq_num;
-	union {
-		u64 l4_config;
-		struct {
-			u32 mkrloc:9;
-			u32 tucmd:11;
-			u32 dtyp:4;
-			u32 adv:8;
-			u32 rsvd:4;
-			u32 idx:4;
-			u32 l4len:8;
-			u32 mss:16;
-		} fields;
-	} l4_setup;
-};
-#endif
-
-/* SRRCTL bit definitions */
-#define E1000_SRRCTL_BSIZEPKT_SHIFT		10 /* Shift _right_ */
-#define E1000_SRRCTL_BSIZEHDRSIZE_MASK		0x00000F00
-#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT		2  /* Shift _left_ */
-#define E1000_SRRCTL_DESCTYPE_LEGACY		0x00000000
-#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF	0x02000000
-#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT		0x04000000
-#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS	0x0A000000
-#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION	0x06000000
-#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
-#define E1000_SRRCTL_DESCTYPE_MASK		0x0E000000
-#define E1000_SRRCTL_TIMESTAMP			0x40000000
-#define E1000_SRRCTL_DROP_EN			0x80000000
-
-#define E1000_SRRCTL_BSIZEPKT_MASK		0x0000007F
-#define E1000_SRRCTL_BSIZEHDR_MASK		0x00003F00
-
-#define E1000_TX_HEAD_WB_ENABLE		0x1
-#define E1000_TX_SEQNUM_WB_ENABLE	0x2
-
-#define E1000_MRQC_ENABLE_RSS_4Q		0x00000002
-#define E1000_MRQC_ENABLE_VMDQ			0x00000003
-#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q		0x00000005
-#define E1000_MRQC_RSS_FIELD_IPV4_UDP		0x00400000
-#define E1000_MRQC_RSS_FIELD_IPV6_UDP		0x00800000
-#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX	0x01000000
-#define E1000_MRQC_ENABLE_RSS_8Q		0x00000002
-
-#define E1000_VMRCTL_MIRROR_PORT_SHIFT		8
-#define E1000_VMRCTL_MIRROR_DSTPORT_MASK	(7 << \
-						 E1000_VMRCTL_MIRROR_PORT_SHIFT)
-#define E1000_VMRCTL_POOL_MIRROR_ENABLE		(1 << 0)
-#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE	(1 << 1)
-#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE	(1 << 2)
-
-#define E1000_EICR_TX_QUEUE ( \
-	E1000_EICR_TX_QUEUE0 |    \
-	E1000_EICR_TX_QUEUE1 |    \
-	E1000_EICR_TX_QUEUE2 |    \
-	E1000_EICR_TX_QUEUE3)
-
-#define E1000_EICR_RX_QUEUE ( \
-	E1000_EICR_RX_QUEUE0 |    \
-	E1000_EICR_RX_QUEUE1 |    \
-	E1000_EICR_RX_QUEUE2 |    \
-	E1000_EICR_RX_QUEUE3)
-
-#define E1000_EIMS_RX_QUEUE	E1000_EICR_RX_QUEUE
-#define E1000_EIMS_TX_QUEUE	E1000_EICR_TX_QUEUE
-
-#define EIMS_ENABLE_MASK ( \
-	E1000_EIMS_RX_QUEUE  | \
-	E1000_EIMS_TX_QUEUE  | \
-	E1000_EIMS_TCP_TIMER | \
-	E1000_EIMS_OTHER)
-
-/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
-#define E1000_IMIR_PORT_IM_EN	0x00010000  /* TCP port enable */
-#define E1000_IMIR_PORT_BP	0x00020000  /* TCP port check bypass */
-#define E1000_IMIREXT_SIZE_BP	0x00001000  /* Packet size bypass */
-#define E1000_IMIREXT_CTRL_URG	0x00002000  /* Check URG bit in header */
-#define E1000_IMIREXT_CTRL_ACK	0x00004000  /* Check ACK bit in header */
-#define E1000_IMIREXT_CTRL_PSH	0x00008000  /* Check PSH bit in header */
-#define E1000_IMIREXT_CTRL_RST	0x00010000  /* Check RST bit in header */
-#define E1000_IMIREXT_CTRL_SYN	0x00020000  /* Check SYN bit in header */
-#define E1000_IMIREXT_CTRL_FIN	0x00040000  /* Check FIN bit in header */
-#define E1000_IMIREXT_CTRL_BP	0x00080000  /* Bypass check of ctrl bits */
-
-/* Receive Descriptor - Advanced */
-union e1000_adv_rx_desc {
-	struct {
-		__le64 pkt_addr; /* Packet buffer address */
-		__le64 hdr_addr; /* Header buffer address */
-	} read;
-	struct {
-		struct {
-			union {
-				__le32 data;
-				struct {
-					__le16 pkt_info; /*RSS type, Pkt type*/
-					/* Split Header, header buffer len */
-					__le16 hdr_info;
-				} hs_rss;
-			} lo_dword;
-			union {
-				__le32 rss; /* RSS Hash */
-				struct {
-					__le16 ip_id; /* IP id */
-					__le16 csum; /* Packet Checksum */
-				} csum_ip;
-			} hi_dword;
-		} lower;
-		struct {
-			__le32 status_error; /* ext status/error */
-			__le16 length; /* Packet length */
-			__le16 vlan; /* VLAN tag */
-		} upper;
-	} wb;  /* writeback */
-};
-
-#define E1000_RXDADV_RSSTYPE_MASK	0x0000000F
-#define E1000_RXDADV_RSSTYPE_SHIFT	12
-#define E1000_RXDADV_HDRBUFLEN_MASK	0x7FE0
-#define E1000_RXDADV_HDRBUFLEN_SHIFT	5
-#define E1000_RXDADV_SPLITHEADER_EN	0x00001000
-#define E1000_RXDADV_SPH		0x8000
-#define E1000_RXDADV_STAT_TS		0x10000 /* Pkt was time stamped */
-#define E1000_RXDADV_STAT_TSIP		0x08000 /* timestamp in packet */
-#define E1000_RXDADV_ERR_HBO		0x00800000
-
-/* RSS Hash results */
-#define E1000_RXDADV_RSSTYPE_NONE	0x00000000
-#define E1000_RXDADV_RSSTYPE_IPV4_TCP	0x00000001
-#define E1000_RXDADV_RSSTYPE_IPV4	0x00000002
-#define E1000_RXDADV_RSSTYPE_IPV6_TCP	0x00000003
-#define E1000_RXDADV_RSSTYPE_IPV6_EX	0x00000004
-#define E1000_RXDADV_RSSTYPE_IPV6	0x00000005
-#define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
-#define E1000_RXDADV_RSSTYPE_IPV4_UDP	0x00000007
-#define E1000_RXDADV_RSSTYPE_IPV6_UDP	0x00000008
-#define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
-
-/* RSS Packet Types as indicated in the receive descriptor */
-#define E1000_RXDADV_PKTTYPE_NONE	0x00000000
-#define E1000_RXDADV_PKTTYPE_IPV4	0x00000010 /* IPV4 hdr present */
-#define E1000_RXDADV_PKTTYPE_IPV4_EX	0x00000020 /* IPV4 hdr + extensions */
-#define E1000_RXDADV_PKTTYPE_IPV6	0x00000040 /* IPV6 hdr present */
-#define E1000_RXDADV_PKTTYPE_IPV6_EX	0x00000080 /* IPV6 hdr + extensions */
-#define E1000_RXDADV_PKTTYPE_TCP	0x00000100 /* TCP hdr present */
-#define E1000_RXDADV_PKTTYPE_UDP	0x00000200 /* UDP hdr present */
-#define E1000_RXDADV_PKTTYPE_SCTP	0x00000400 /* SCTP hdr present */
-#define E1000_RXDADV_PKTTYPE_NFS	0x00000800 /* NFS hdr present */
-
-#define E1000_RXDADV_PKTTYPE_IPSEC_ESP	0x00001000 /* IPSec ESP */
-#define E1000_RXDADV_PKTTYPE_IPSEC_AH	0x00002000 /* IPSec AH */
-#define E1000_RXDADV_PKTTYPE_LINKSEC	0x00004000 /* LinkSec Encap */
-#define E1000_RXDADV_PKTTYPE_ETQF	0x00008000 /* PKTTYPE is ETQF index */
-#define E1000_RXDADV_PKTTYPE_ETQF_MASK	0x00000070 /* ETQF has 8 indices */
-#define E1000_RXDADV_PKTTYPE_ETQF_SHIFT	4 /* Right-shift 4 bits */
-
-/* LinkSec results */
-/* Security Processing bit Indication */
-#define E1000_RXDADV_LNKSEC_STATUS_SECP		0x00020000
-#define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK	0x18000000
-#define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH	0x08000000
-#define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR	0x10000000
-#define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG	0x18000000
-
-#define E1000_RXDADV_IPSEC_STATUS_SECP			0x00020000
-#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK		0x18000000
-#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL	0x08000000
-#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH		0x10000000
-#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED	0x18000000
-
-/* Transmit Descriptor - Advanced */
-union e1000_adv_tx_desc {
-	struct {
-		__le64 buffer_addr;    /* Address of descriptor's data buf */
-		__le32 cmd_type_len;
-		__le32 olinfo_status;
-	} read;
-	struct {
-		__le64 rsvd;       /* Reserved */
-		__le32 nxtseq_seed;
-		__le32 status;
-	} wb;
-};
-
-/* Adv Transmit Descriptor Config Masks */
-#define E1000_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
-#define E1000_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
-#define E1000_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
-#define E1000_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
-#define E1000_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
-#define E1000_ADVTXD_DCMD_DDTYP_ISCSI	0x10000000 /* DDP hdr type or iSCSI */
-#define E1000_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
-#define E1000_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
-#define E1000_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
-#define E1000_ADVTXD_MAC_LINKSEC	0x00040000 /* Apply LinkSec on pkt */
-#define E1000_ADVTXD_MAC_TSTAMP		0x00080000 /* IEEE1588 Timestamp pkt */
-#define E1000_ADVTXD_STAT_SN_CRC	0x00000002 /* NXTSEQ/SEED prsnt in WB */
-#define E1000_ADVTXD_IDX_SHIFT		4  /* Adv desc Index shift */
-#define E1000_ADVTXD_POPTS_ISCO_1ST	0x00000000 /* 1st TSO of iSCSI PDU */
-#define E1000_ADVTXD_POPTS_ISCO_MDL	0x00000800 /* Middle TSO of iSCSI PDU */
-#define E1000_ADVTXD_POPTS_ISCO_LAST	0x00001000 /* Last TSO of iSCSI PDU */
-/* 1st & Last TSO-full iSCSI PDU*/
-#define E1000_ADVTXD_POPTS_ISCO_FULL	0x00001800
-#define E1000_ADVTXD_POPTS_IPSEC	0x00000400 /* IPSec offload request */
-#define E1000_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */
-
-/* Context descriptors */
-struct e1000_adv_tx_context_desc {
-	__le32 vlan_macip_lens;
-	__le32 seqnum_seed;
-	__le32 type_tucmd_mlhl;
-	__le32 mss_l4len_idx;
-};
-
-#define E1000_ADVTXD_MACLEN_SHIFT	9  /* Adv ctxt desc mac len shift */
-#define E1000_ADVTXD_VLAN_SHIFT		16  /* Adv ctxt vlan tag shift */
-#define E1000_ADVTXD_TUCMD_IPV4		0x00000400  /* IP Packet Type: 1=IPv4 */
-#define E1000_ADVTXD_TUCMD_IPV6		0x00000000  /* IP Packet Type: 0=IPv6 */
-#define E1000_ADVTXD_TUCMD_L4T_UDP	0x00000000  /* L4 Packet TYPE of UDP */
-#define E1000_ADVTXD_TUCMD_L4T_TCP	0x00000800  /* L4 Packet TYPE of TCP */
-#define E1000_ADVTXD_TUCMD_L4T_SCTP	0x00001000  /* L4 Packet TYPE of SCTP */
-#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP	0x00002000 /* IPSec Type ESP */
-/* IPSec Encrypt Enable for ESP */
-#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN	0x00004000
-/* Req requires Markers and CRC */
-#define E1000_ADVTXD_TUCMD_MKRREQ	0x00002000
-#define E1000_ADVTXD_L4LEN_SHIFT	8  /* Adv ctxt L4LEN shift */
-#define E1000_ADVTXD_MSS_SHIFT		16  /* Adv ctxt MSS shift */
-/* Adv ctxt IPSec SA IDX mask */
-#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK	0x000000FF
-/* Adv ctxt IPSec ESP len mask */
-#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK		0x000000FF
-
-/* Additional Transmit Descriptor Control definitions */
-#define E1000_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
-#define E1000_TXDCTL_SWFLSH		0x04000000 /* Tx Desc. wbk flushing */
-/* Tx Queue Arbitration Priority 0=low, 1=high */
-#define E1000_TXDCTL_PRIORITY		0x08000000
-
-/* Additional Receive Descriptor Control definitions */
-#define E1000_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
-#define E1000_RXDCTL_SWFLSH		0x04000000 /* Rx Desc. wbk flushing */
-
-/* Direct Cache Access (DCA) definitions */
-#define E1000_DCA_CTRL_DCA_ENABLE	0x00000000 /* DCA Enable */
-#define E1000_DCA_CTRL_DCA_DISABLE	0x00000001 /* DCA Disable */
-
-#define E1000_DCA_CTRL_DCA_MODE_CB1	0x00 /* DCA Mode CB1 */
-#define E1000_DCA_CTRL_DCA_MODE_CB2	0x02 /* DCA Mode CB2 */
-
-#define E1000_DCA_RXCTRL_CPUID_MASK	0x0000001F /* Rx CPUID Mask */
-#define E1000_DCA_RXCTRL_DESC_DCA_EN	(1 << 5) /* DCA Rx Desc enable */
-#define E1000_DCA_RXCTRL_HEAD_DCA_EN	(1 << 6) /* DCA Rx Desc header ena */
-#define E1000_DCA_RXCTRL_DATA_DCA_EN	(1 << 7) /* DCA Rx Desc payload ena */
-
-#define E1000_DCA_TXCTRL_CPUID_MASK	0x0000001F /* Tx CPUID Mask */
-#define E1000_DCA_TXCTRL_DESC_DCA_EN	(1 << 5) /* DCA Tx Desc enable */
-#define E1000_DCA_TXCTRL_TX_WB_RO_EN	(1 << 11) /* Tx Desc writeback RO bit */
-
-#define E1000_DCA_TXCTRL_CPUID_MASK_82576	0xFF000000 /* Tx CPUID Mask */
-#define E1000_DCA_RXCTRL_CPUID_MASK_82576	0xFF000000 /* Rx CPUID Mask */
-#define E1000_DCA_TXCTRL_CPUID_SHIFT_82576	24 /* Tx CPUID */
-#define E1000_DCA_RXCTRL_CPUID_SHIFT_82576	24 /* Rx CPUID */
-
-/* Additional interrupt register bit definitions */
-#define E1000_ICR_LSECPNS	0x00000020 /* PN threshold - server */
-#define E1000_IMS_LSECPNS	E1000_ICR_LSECPNS /* PN threshold - server */
-#define E1000_ICS_LSECPNS	E1000_ICR_LSECPNS /* PN threshold - server */
-
-/* ETQF register bit definitions */
-#define E1000_ETQF_FILTER_ENABLE	(1 << 26)
-#define E1000_ETQF_IMM_INT		(1 << 29)
-#define E1000_ETQF_1588			(1 << 30)
-#define E1000_ETQF_QUEUE_ENABLE		(1 << 31)
-/*
- * ETQF filter list: one static filter per filter consumer. This is
- *                   to avoid filter collisions later. Add new filters
- *                   here!!
- *
- * Current filters:
- *    EAPOL 802.1x (0x888e): Filter 0
- */
-#define E1000_ETQF_FILTER_EAPOL		0
-
-#define E1000_FTQF_VF_BP		0x00008000
-#define E1000_FTQF_1588_TIME_STAMP	0x08000000
-#define E1000_FTQF_MASK			0xF0000000
-#define E1000_FTQF_MASK_PROTO_BP	0x10000000
-#define E1000_FTQF_MASK_SOURCE_ADDR_BP	0x20000000
-#define E1000_FTQF_MASK_DEST_ADDR_BP	0x40000000
-#define E1000_FTQF_MASK_SOURCE_PORT_BP	0x80000000
-
-#define E1000_NVM_APME_82575		0x0400
-#define MAX_NUM_VFS			7
-
-#define E1000_DTXSWC_MAC_SPOOF_MASK	0x000000FF /* Per VF MAC spoof cntrl */
-#define E1000_DTXSWC_VLAN_SPOOF_MASK	0x0000FF00 /* Per VF VLAN spoof cntrl */
-#define E1000_DTXSWC_LLE_MASK		0x00FF0000 /* Per VF Local LB enables */
-#define E1000_DTXSWC_VLAN_SPOOF_SHIFT	8
-#define E1000_DTXSWC_LLE_SHIFT		16
-#define E1000_DTXSWC_VMDQ_LOOPBACK_EN	(1 << 31)  /* global VF LB enable */
-
-/* Easy defines for setting default pool, would normally be left a zero */
-#define E1000_VT_CTL_DEFAULT_POOL_SHIFT	7
-#define E1000_VT_CTL_DEFAULT_POOL_MASK	(0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
-
-/* Other useful VMD_CTL register defines */
-#define E1000_VT_CTL_IGNORE_MAC		(1 << 28)
-#define E1000_VT_CTL_DISABLE_DEF_POOL	(1 << 29)
-#define E1000_VT_CTL_VM_REPL_EN		(1 << 30)
-
-/* Per VM Offload register setup */
-#define E1000_VMOLR_RLPML_MASK	0x00003FFF /* Long Packet Maximum Length mask */
-#define E1000_VMOLR_LPE		0x00010000 /* Accept Long packet */
-#define E1000_VMOLR_RSSE	0x00020000 /* Enable RSS */
-#define E1000_VMOLR_AUPE	0x01000000 /* Accept untagged packets */
-#define E1000_VMOLR_ROMPE	0x02000000 /* Accept overflow multicast */
-#define E1000_VMOLR_ROPE	0x04000000 /* Accept overflow unicast */
-#define E1000_VMOLR_BAM		0x08000000 /* Accept Broadcast packets */
-#define E1000_VMOLR_MPME	0x10000000 /* Multicast promiscuous mode */
-#define E1000_VMOLR_STRVLAN	0x40000000 /* Vlan stripping enable */
-#define E1000_VMOLR_STRCRC	0x80000000 /* CRC stripping enable */
-
-#define E1000_VMOLR_VPE		0x00800000 /* VLAN promiscuous enable */
-#define E1000_VMOLR_UPE		0x20000000 /* Unicast promisuous enable */
-#define E1000_DVMOLR_HIDVLAN	0x20000000 /* Vlan hiding enable */
-#define E1000_DVMOLR_STRVLAN	0x40000000 /* Vlan stripping enable */
-#define E1000_DVMOLR_STRCRC	0x80000000 /* CRC stripping enable */
-
-#define E1000_PBRWAC_WALPB	0x00000007 /* Wrap around event on LAN Rx PB */
-#define E1000_PBRWAC_PBE	0x00000008 /* Rx packet buffer empty */
-
-#define E1000_VLVF_ARRAY_SIZE		32
-#define E1000_VLVF_VLANID_MASK		0x00000FFF
-#define E1000_VLVF_POOLSEL_SHIFT	12
-#define E1000_VLVF_POOLSEL_MASK		(0xFF << E1000_VLVF_POOLSEL_SHIFT)
-#define E1000_VLVF_LVLAN		0x00100000
-#define E1000_VLVF_VLANID_ENABLE	0x80000000
-
-#define E1000_VMVIR_VLANA_DEFAULT	0x40000000 /* Always use default VLAN */
-#define E1000_VMVIR_VLANA_NEVER		0x80000000 /* Never insert VLAN tag */
-
-#define E1000_VF_INIT_TIMEOUT	200 /* Number of retries to clear RSTI */
-
-#define E1000_IOVCTL		0x05BBC
-#define E1000_IOVCTL_REUSE_VFQ	0x00000001
-
-#define E1000_RPLOLR_STRVLAN	0x40000000
-#define E1000_RPLOLR_STRCRC	0x80000000
-
-#define E1000_TCTL_EXT_COLD	0x000FFC00
-#define E1000_TCTL_EXT_COLD_SHIFT	10
-
-#define E1000_DTXCTL_8023LL	0x0004
-#define E1000_DTXCTL_VLAN_ADDED	0x0008
-#define E1000_DTXCTL_OOS_ENABLE	0x0010
-#define E1000_DTXCTL_MDP_EN	0x0020
-#define E1000_DTXCTL_SPOOF_INT	0x0040
-
-#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT	(1 << 14)
-
-#define ALL_QUEUES		0xFFFF
-
-/* Rx packet buffer size defines */
-#define E1000_RXPBS_SIZE_MASK_82576	0x0000007F
-void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
-void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf);
-void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
-s32 e1000_init_nvm_params_82575(struct e1000_hw *hw);
-
-enum e1000_promisc_type {
-	e1000_promisc_disabled = 0,   /* all promisc modes disabled */
-	e1000_promisc_unicast = 1,    /* unicast promiscuous enabled */
-	e1000_promisc_multicast = 2,  /* multicast promiscuous enabled */
-	e1000_promisc_enabled = 3,    /* both uni and multicast promisc */
-	e1000_num_promisc_types
-};
-
-void e1000_vfta_set_vf(struct e1000_hw *, u16, bool);
-void e1000_rlpml_set_vf(struct e1000_hw *, u16);
-s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type type);
-u16 e1000_rxpbs_adjust_82580(u32 data);
-s32 e1000_set_eee_i350(struct e1000_hw *);
-
-/* I2C SDA and SCL timing parameters for standard mode */
-#define E1000_I2C_T_HD_STA	4
-#define E1000_I2C_T_LOW		5
-#define E1000_I2C_T_HIGH	4
-#define E1000_I2C_T_SU_STA	5
-#define E1000_I2C_T_HD_DATA	5
-#define E1000_I2C_T_SU_DATA	1
-#define E1000_I2C_T_RISE	1
-#define E1000_I2C_T_FALL	1
-#define E1000_I2C_T_SU_STO	4
-#define E1000_I2C_T_BUF		5
-
-s32 e1000_set_i2c_bb(struct e1000_hw *hw);
-s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
-				u8 dev_addr, u8 *data);
-s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
-				 u8 dev_addr, u8 data);
-void e1000_i2c_bus_clear(struct e1000_hw *hw);
-#endif /* _E1000_82575_H_ */
diff --git a/lib/igb/e1000_defines.h b/lib/igb/e1000_defines.h
deleted file mode 100644
index d08162bb..00000000
--- a/lib/igb/e1000_defines.h
+++ /dev/null
@@ -1,1811 +0,0 @@
-/******************************************************************************
-
-  Copyright (c) 2001-2016, Intel Corporation
-  All rights reserved.
-
-  Redistribution and use in source and binary forms, with or without
-  modification, are permitted provided that the following conditions are met:
-
-   1. Redistributions of source code must retain the above copyright notice,
-      this list of conditions and the following disclaimer.
-
-   2. Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-
-   3. Neither the name of the Intel Corporation nor the names of its
-      contributors may be used to endorse or promote products derived from
-      this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE.
-
-******************************************************************************/
-/*$FreeBSD$*/
-
-#ifndef _E1000_DEFINES_H_
-#define _E1000_DEFINES_H_
-
-/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
-#define REQ_TX_DESCRIPTOR_MULTIPLE  8
-#define REQ_RX_DESCRIPTOR_MULTIPLE  8
-
-/* Definitions for power management and wakeup registers */
-/* Wake Up Control */
-#define E1000_WUC_APME		0x00000001 /* APM Enable */
-#define E1000_WUC_PME_EN	0x00000002 /* PME Enable */
-#define E1000_WUC_PME_STATUS	0x00000004 /* PME Status */
-#define E1000_WUC_APMPME	0x00000008 /* Assert PME on APM Wakeup */
-#define E1000_WUC_LSCWE		0x00000010 /* Link Status wake up enable */
-#define E1000_WUC_PPROXYE	0x00000010 /* Protocol Proxy Enable */
-#define E1000_WUC_LSCWO		0x00000020 /* Link Status wake up override */
-#define E1000_WUC_SPM		0x80000000 /* Enable SPM */
-#define E1000_WUC_PHY_WAKE	0x00000100 /* if PHY supports wakeup */
-
-/* Wake Up Filter Control */
-#define E1000_WUFC_LNKC	0x00000001 /* Link Status Change Wakeup Enable */
-#define E1000_WUFC_MAG	0x00000002 /* Magic Packet Wakeup Enable */
-#define E1000_WUFC_EX	0x00000004 /* Directed Exact Wakeup Enable */
-#define E1000_WUFC_MC	0x00000008 /* Directed Multicast Wakeup Enable */
-#define E1000_WUFC_BC	0x00000010 /* Broadcast Wakeup Enable */
-#define E1000_WUFC_ARP	0x00000020 /* ARP Request Packet Wakeup Enable */
-#define E1000_WUFC_IPV4	0x00000040 /* Directed IPv4 Packet Wakeup Enable */
-#define E1000_WUFC_IPV6	0x00000080 /* Directed IPv6 Packet Wakeup Enable */
-#define E1000_WUFC_FLEX_HQ	0x00004000 /* Flex Filters Host Queuing  (AVB) */
-#define E1000_WUFC_IGNORE_TCO	0x00008000 /* Ignore WakeOn TCO packets */
-#define E1000_WUFC_FLX0		0x00010000 /* Flexible Filter 0 Enable */
-#define E1000_WUFC_FLX1		0x00020000 /* Flexible Filter 1 Enable */
-#define E1000_WUFC_FLX2		0x00040000 /* Flexible Filter 2 Enable */
-#define E1000_WUFC_FLX3		0x00080000 /* Flexible Filter 3 Enable */
-#define E1000_WUFC_FW_RST	0x80000000 /* Wake on FW Reset Enable */
-#define E1000_WUFC_ALL_FILTERS		0x000F00FF /* all wakeup filters mask */
-#define E1000_WUFC_FLX_OFFSET		16 /* Flexible Filters bits offset */
-#define E1000_WUFC_FLX_FILTERS		0x000F0000 /* 4 flexible filters mask */
-/*
- * For 82576 to utilize Extended filter masks in addition to
- * existing (filter) masks
- */
-#define E1000_WUFC_EXT_FLX_FILTERS	0x00300000 /* Ext. FLX filter mask */
-
-/* Wake Up Status */
-#define E1000_WUS_LNKC		E1000_WUFC_LNKC
-#define E1000_WUS_MAG		E1000_WUFC_MAG
-#define E1000_WUS_EX		E1000_WUFC_EX
-#define E1000_WUS_MC		E1000_WUFC_MC
-#define E1000_WUS_BC		E1000_WUFC_BC
-#define E1000_WUS_ARP		E1000_WUFC_ARP
-#define E1000_WUS_IPV4		E1000_WUFC_IPV4
-#define E1000_WUS_IPV6		E1000_WUFC_IPV6
-#define E1000_WUS_FLX0		E1000_WUFC_FLX0
-#define E1000_WUS_FLX1		E1000_WUFC_FLX1
-#define E1000_WUS_FLX2		E1000_WUFC_FLX2
-#define E1000_WUS_FLX3		E1000_WUFC_FLX3
-#define E1000_WUS_FLX_FILTERS	E1000_WUFC_FLX_FILTERS
-
-/* Wake Up Packet Length */
-#define E1000_WUPL_LENGTH_MASK	0x0FFF   /* Only the lower 12 bits are valid */
-
-/* Four Flexible Filters are supported */
-#define E1000_FLEXIBLE_FILTER_COUNT_MAX		4
-/* Two Extended Flexible Filters are supported (82576) */
-#define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX	2
-#define E1000_FHFT_LENGTH_OFFSET	0xFC /* Length byte in FHFT */
-#define E1000_FHFT_LENGTH_MASK		0x0FF /* Length in lower byte */
-
-/* Each Flexible Filter is at most 128 (0x80) bytes in length */
-#define E1000_FLEXIBLE_FILTER_SIZE_MAX	128
-
-#define E1000_FFLT_SIZE		E1000_FLEXIBLE_FILTER_COUNT_MAX
-#define E1000_FFMT_SIZE		E1000_FLEXIBLE_FILTER_SIZE_MAX
-#define E1000_FFVT_SIZE		E1000_FLEXIBLE_FILTER_SIZE_MAX
-
-/* Extended Device Control */
-#define E1000_CTRL_EXT_GPI0_EN		0x00000001 /* Maps SDP4 to GPI0 */
-#define E1000_CTRL_EXT_GPI1_EN		0x00000002 /* Maps SDP5 to GPI1 */
-#define E1000_CTRL_EXT_PHYINT_EN	E1000_CTRL_EXT_GPI1_EN
-#define E1000_CTRL_EXT_GPI2_EN		0x00000004 /* Maps SDP6 to GPI2 */
-#define E1000_CTRL_EXT_GPI3_EN		0x00000008 /* Maps SDP7 to GPI3 */
-/* Reserved (bits 4,5) in >= 82575 */
-#define E1000_CTRL_EXT_SDP4_DATA	0x00000010 /* SW Definable Pin 4 data */
-#define E1000_CTRL_EXT_SDP5_DATA	0x00000020 /* SW Definable Pin 5 data */
-#define E1000_CTRL_EXT_PHY_INT		E1000_CTRL_EXT_SDP5_DATA
-#define E1000_CTRL_EXT_SDP6_DATA	0x00000040 /* SW Definable Pin 6 data */
-#define E1000_CTRL_EXT_SDP3_DATA	0x00000080 /* SW Definable Pin 3 data */
-/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
-#define E1000_CTRL_EXT_SDP4_DIR	0x00000100 /* Direction of SDP4 0=in 1=out */
-#define E1000_CTRL_EXT_SDP5_DIR	0x00000200 /* Direction of SDP5 0=in 1=out */
-#define E1000_CTRL_EXT_SDP6_DIR	0x00000400 /* Direction of SDP6 0=in 1=out */
-#define E1000_CTRL_EXT_SDP3_DIR	0x00000800 /* Direction of SDP3 0=in 1=out */
-#define E1000_CTRL_EXT_ASDCHK	0x00001000 /* Initiate an ASD sequence */
-#define E1000_CTRL_EXT_EE_RST	0x00002000 /* Reinitialize from EEPROM */
-#define E1000_CTRL_EXT_IPS	0x00004000 /* Invert Power State */
-/* Physical Func Reset Done Indication */
-#define E1000_CTRL_EXT_PFRSTD	0x00004000
-#define E1000_CTRL_EXT_SPD_BYPS	0x00008000 /* Speed Select Bypass */
-#define E1000_CTRL_EXT_RO_DIS	0x00020000 /* Relaxed Ordering disable */
-#define E1000_CTRL_EXT_DMA_DYN_CLK_EN	0x00080000 /* DMA Dynamic Clk Gating */
-#define E1000_CTRL_EXT_LINK_MODE_MASK	0x00C00000
-/* Offset of the link mode field in Ctrl Ext register */
-#define E1000_CTRL_EXT_LINK_MODE_OFFSET	22
-#define E1000_CTRL_EXT_LINK_MODE_82580_MASK	0x01C00000 /*82580 bit 24:22*/
-#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX	0x00400000
-#define E1000_CTRL_EXT_LINK_MODE_GMII	0x00000000
-#define E1000_CTRL_EXT_LINK_MODE_TBI	0x00C00000
-#define E1000_CTRL_EXT_LINK_MODE_KMRN	0x00000000
-#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES	0x00C00000
-#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES	0x00800000
-#define E1000_CTRL_EXT_LINK_MODE_SGMII	0x00800000
-#define E1000_CTRL_EXT_EIAME		0x01000000
-#define E1000_CTRL_EXT_IRCA		0x00000001
-#define E1000_CTRL_EXT_WR_WMARK_MASK	0x03000000
-#define E1000_CTRL_EXT_WR_WMARK_256	0x00000000
-#define E1000_CTRL_EXT_WR_WMARK_320	0x01000000
-#define E1000_CTRL_EXT_WR_WMARK_384	0x02000000
-#define E1000_CTRL_EXT_WR_WMARK_448	0x03000000
-#define E1000_CTRL_EXT_CANC		0x04000000 /* Int delay cancellation */
-#define E1000_CTRL_EXT_DRV_LOAD		0x10000000 /* Drv loaded bit for FW */
-/* IAME enable bit (27) was removed in >= 82575 */
-#define E1000_CTRL_EXT_IAME		0x08000000 /* Int ACK Auto-mask */
-/* packet buffer parity error detection enabled */
-#define E1000_CRTL_EXT_PB_PAREN		0x01000000
-/* descriptor FIFO parity error detection enable */
-#define E1000_CTRL_EXT_DF_PAREN		0x02000000
-#define E1000_CTRL_EXT_GHOST_PAREN	0x40000000
-#define E1000_CTRL_EXT_PBA_CLR		0x80000000 /* PBA Clear */
-#define E1000_I2CCMD_REG_ADDR_SHIFT	16
-#define E1000_I2CCMD_REG_ADDR		0x00FF0000
-#define E1000_I2CCMD_PHY_ADDR_SHIFT	24
-#define E1000_I2CCMD_PHY_ADDR		0x07000000
-#define E1000_I2CCMD_OPCODE_READ	0x08000000
-#define E1000_I2CCMD_OPCODE_WRITE	0x00000000
-#define E1000_I2CCMD_RESET		0x10000000
-#define E1000_I2CCMD_READY		0x20000000
-#define E1000_I2CCMD_INTERRUPT_ENA	0x40000000
-#define E1000_I2CCMD_ERROR		0x80000000
-#define E1000_I2CCMD_SFP_DATA_ADDR(a)	(0x0000 + (a))
-#define E1000_I2CCMD_SFP_DIAG_ADDR(a)	(0x0100 + (a))
-#define E1000_MAX_SGMII_PHY_REG_ADDR	255
-#define E1000_I2CCMD_PHY_TIMEOUT	200
-#define E1000_IVAR_VALID	0x80
-#define E1000_GPIE_NSICR	0x00000001
-#define E1000_GPIE_MSIX_MODE	0x00000010
-#define E1000_GPIE_EIAME	0x40000000
-#define E1000_GPIE_PBA		0x80000000
-
-/* Receive Descriptor bit definitions */
-#define E1000_RXD_STAT_DD	0x01    /* Descriptor Done */
-#define E1000_RXD_STAT_EOP	0x02    /* End of Packet */
-#define E1000_RXD_STAT_IXSM	0x04    /* Ignore checksum */
-#define E1000_RXD_STAT_VP	0x08    /* IEEE VLAN Packet */
-#define E1000_RXD_STAT_UDPCS	0x10    /* UDP xsum calculated */
-#define E1000_RXD_STAT_TCPCS	0x20    /* TCP xsum calculated */
-#define E1000_RXD_STAT_IPCS	0x40    /* IP xsum calculated */
-#define E1000_RXD_STAT_PIF	0x80    /* passed in-exact filter */
-#define E1000_RXD_STAT_CRCV	0x100   /* Speculative CRC Valid */
-#define E1000_RXD_STAT_IPIDV	0x200   /* IP identification valid */
-#define E1000_RXD_STAT_UDPV	0x400   /* Valid UDP checksum */
-#define E1000_RXD_STAT_DYNINT	0x800   /* Pkt caused INT via DYNINT */
-#define E1000_RXD_STAT_ACK	0x8000  /* ACK Packet indication */
-#define E1000_RXD_ERR_CE	0x01    /* CRC Error */
-#define E1000_RXD_ERR_SE	0x02    /* Symbol Error */
-#define E1000_RXD_ERR_SEQ	0x04    /* Sequence Error */
-#define E1000_RXD_ERR_CXE	0x10    /* Carrier Extension Error */
-#define E1000_RXD_ERR_TCPE	0x20    /* TCP/UDP Checksum Error */
-#define E1000_RXD_ERR_IPE	0x40    /* IP Checksum Error */
-#define E1000_RXD_ERR_RXE	0x80    /* Rx Data Error */
-#define E1000_RXD_SPC_VLAN_MASK	0x0FFF  /* VLAN ID is in lower 12 bits */
-#define E1000_RXD_SPC_PRI_MASK	0xE000  /* Priority is in upper 3 bits */
-#define E1000_RXD_SPC_PRI_SHIFT	13
-#define E1000_RXD_SPC_CFI_MASK	0x1000  /* CFI is bit 12 */
-#define E1000_RXD_SPC_CFI_SHIFT	12
-
-#define E1000_RXDEXT_STATERR_LB		0x00040000
-#define E1000_RXDEXT_STATERR_CE		0x01000000
-#define E1000_RXDEXT_STATERR_SE		0x02000000
-#define E1000_RXDEXT_STATERR_SEQ	0x04000000
-#define E1000_RXDEXT_STATERR_CXE	0x10000000
-#define E1000_RXDEXT_STATERR_TCPE	0x20000000
-#define E1000_RXDEXT_STATERR_IPE	0x40000000
-#define E1000_RXDEXT_STATERR_RXE	0x80000000
-
-/* mask to determine if packets should be dropped due to frame errors */
-#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
-	E1000_RXD_ERR_CE  |		\
-	E1000_RXD_ERR_SE  |		\
-	E1000_RXD_ERR_SEQ |		\
-	E1000_RXD_ERR_CXE |		\
-	E1000_RXD_ERR_RXE)
-
-/* Same mask, but for extended and packet split descriptors */
-#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
-	E1000_RXDEXT_STATERR_CE  |	\
-	E1000_RXDEXT_STATERR_SE  |	\
-	E1000_RXDEXT_STATERR_SEQ |	\
-	E1000_RXDEXT_STATERR_CXE |	\
-	E1000_RXDEXT_STATERR_RXE)
-
-#define E1000_MRQC_ENABLE_MASK			0x00000007
-#define E1000_MRQC_ENABLE_RSS_2Q		0x00000001
-#define E1000_MRQC_ENABLE_RSS_INT		0x00000004
-#define E1000_MRQC_RSS_FIELD_MASK		0xFFFF0000
-#define E1000_MRQC_RSS_FIELD_IPV4_TCP		0x00010000
-#define E1000_MRQC_RSS_FIELD_IPV4		0x00020000
-#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX	0x00040000
-#define E1000_MRQC_RSS_FIELD_IPV6_EX		0x00080000
-#define E1000_MRQC_RSS_FIELD_IPV6		0x00100000
-#define E1000_MRQC_RSS_FIELD_IPV6_TCP		0x00200000
-
-#define E1000_RXDPS_HDRSTAT_HDRSP		0x00008000
-#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK		0x000003FF
-
-/* Management Control */
-#define E1000_MANC_SMBUS_EN	0x00000001 /* SMBus Enabled - RO */
-#define E1000_MANC_ASF_EN	0x00000002 /* ASF Enabled - RO */
-#define E1000_MANC_R_ON_FORCE	0x00000004 /* Reset on Force TCO - RO */
-#define E1000_MANC_RMCP_EN	0x00000100 /* Enable RCMP 026Fh Filtering */
-#define E1000_MANC_0298_EN	0x00000200 /* Enable RCMP 0298h Filtering */
-#define E1000_MANC_IPV4_EN	0x00000400 /* Enable IPv4 */
-#define E1000_MANC_IPV6_EN	0x00000800 /* Enable IPv6 */
-#define E1000_MANC_SNAP_EN	0x00001000 /* Accept LLC/SNAP */
-#define E1000_MANC_ARP_EN	0x00002000 /* Enable ARP Request Filtering */
-/* Enable Neighbor Discovery Filtering */
-#define E1000_MANC_NEIGHBOR_EN	0x00004000
-#define E1000_MANC_ARP_RES_EN	0x00008000 /* Enable ARP response Filtering */
-#define E1000_MANC_TCO_RESET	0x00010000 /* TCO Reset Occurred */
-#define E1000_MANC_RCV_TCO_EN	0x00020000 /* Receive TCO Packets Enabled */
-#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
-#define E1000_MANC_RCV_ALL	0x00080000 /* Receive All Enabled */
-#define E1000_MANC_BLK_PHY_RST_ON_IDE	0x00040000 /* Block phy resets */
-/* Enable MAC address filtering */
-#define E1000_MANC_EN_MAC_ADDR_FILTER	0x00100000
-/* Enable MNG packets to host memory */
-#define E1000_MANC_EN_MNG2HOST		0x00200000
-/* Enable IP address filtering */
-#define E1000_MANC_EN_IP_ADDR_FILTER	0x00400000
-#define E1000_MANC_EN_XSUM_FILTER	0x00800000 /* Ena checksum filtering */
-#define E1000_MANC_BR_EN		0x01000000 /* Ena broadcast filtering */
-#define E1000_MANC_SMB_REQ		0x01000000 /* SMBus Request */
-#define E1000_MANC_SMB_GNT		0x02000000 /* SMBus Grant */
-#define E1000_MANC_SMB_CLK_IN		0x04000000 /* SMBus Clock In */
-#define E1000_MANC_SMB_DATA_IN		0x08000000 /* SMBus Data In */
-#define E1000_MANC_SMB_DATA_OUT		0x10000000 /* SMBus Data Out */
-#define E1000_MANC_SMB_CLK_OUT		0x20000000 /* SMBus Clock Out */
-#define E1000_MANC_MPROXYE		0x40000000 /* Mngment Proxy Enable */
-#define E1000_MANC_EN_BMC2OS		0x10000000 /* OS2BMC is enabld or not */
-
-#define E1000_MANC_SMB_DATA_OUT_SHIFT	28 /* SMBus Data Out Shift */
-#define E1000_MANC_SMB_CLK_OUT_SHIFT	29 /* SMBus Clock Out Shift */
-
-#define E1000_MANC2H_PORT_623		0x00000020 /* Port 0x26f */
-#define E1000_MANC2H_PORT_664		0x00000040 /* Port 0x298 */
-#define E1000_MDEF_PORT_623		0x00000800 /* Port 0x26f */
-#define E1000_MDEF_PORT_664		0x00000400 /* Port 0x298 */
-
-/* Receive Control */
-#define E1000_RCTL_RST		0x00000001 /* Software reset */
-#define E1000_RCTL_EN		0x00000002 /* enable */
-#define E1000_RCTL_SBP		0x00000004 /* store bad packet */
-#define E1000_RCTL_UPE		0x00000008 /* unicast promisc enable */
-#define E1000_RCTL_MPE		0x00000010 /* multicast promisc enable */
-#define E1000_RCTL_LPE		0x00000020 /* long packet enable */
-#define E1000_RCTL_LBM_NO	0x00000000 /* no loopback mode */
-#define E1000_RCTL_LBM_MAC	0x00000040 /* MAC loopback mode */
-#define E1000_RCTL_LBM_SLP	0x00000080 /* serial link loopback mode */
-#define E1000_RCTL_LBM_TCVR	0x000000C0 /* tcvr loopback mode */
-#define E1000_RCTL_DTYP_MASK	0x00000C00 /* Descriptor type mask */
-#define E1000_RCTL_DTYP_PS	0x00000400 /* Packet Split descriptor */
-#define E1000_RCTL_RDMTS_HALF	0x00000000 /* Rx desc min thresh size */
-#define E1000_RCTL_RDMTS_QUAT	0x00000100 /* Rx desc min thresh size */
-#define E1000_RCTL_RDMTS_EIGTH	0x00000200 /* Rx desc min thresh size */
-#define E1000_RCTL_MO_SHIFT	12 /* multicast offset shift */
-#define E1000_RCTL_MO_0		0x00000000 /* multicast offset 11:0 */
-#define E1000_RCTL_MO_1		0x00001000 /* multicast offset 12:1 */
-#define E1000_RCTL_MO_2		0x00002000 /* multicast offset 13:2 */
-#define E1000_RCTL_MO_3		0x00003000 /* multicast offset 15:4 */
-#define E1000_RCTL_MDR		0x00004000 /* multicast desc ring 0 */
-#define E1000_RCTL_BAM		0x00008000 /* broadcast enable */
-/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
-#define E1000_RCTL_SZ_2048	0x00000000 /* Rx buffer size 2048 */
-#define E1000_RCTL_SZ_1024	0x00010000 /* Rx buffer size 1024 */
-#define E1000_RCTL_SZ_512	0x00020000 /* Rx buffer size 512 */
-#define E1000_RCTL_SZ_256	0x00030000 /* Rx buffer size 256 */
-/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
-#define E1000_RCTL_SZ_16384	0x00010000 /* Rx buffer size 16384 */
-#define E1000_RCTL_SZ_8192	0x00020000 /* Rx buffer size 8192 */
-#define E1000_RCTL_SZ_4096	0x00030000 /* Rx buffer size 4096 */
-#define E1000_RCTL_VFE		0x00040000 /* vlan filter enable */
-#define E1000_RCTL_CFIEN	0x00080000 /* canonical form enable */
-#define E1000_RCTL_CFI		0x00100000 /* canonical form indicator */
-#define E1000_RCTL_DPF		0x00400000 /* discard pause frames */
-#define E1000_RCTL_PMCF		0x00800000 /* pass MAC control frames */
-#define E1000_RCTL_BSEX		0x02000000 /* Buffer size extension */
-#define E1000_RCTL_SECRC	0x04000000 /* Strip Ethernet CRC */
-#define E1000_RCTL_FLXBUF_MASK	0x78000000 /* Flexible buffer size */
-#define E1000_RCTL_FLXBUF_SHIFT	27 /* Flexible buffer shift */
-
-/*
- * Use byte values for the following shift parameters
- * Usage:
- *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
- *		  E1000_PSRCTL_BSIZE0_MASK) |
- *		((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
- *		  E1000_PSRCTL_BSIZE1_MASK) |
- *		((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
- *		  E1000_PSRCTL_BSIZE2_MASK) |
- *		((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
- *		  E1000_PSRCTL_BSIZE3_MASK))
- * where value0 = [128..16256],  default=256
- *       value1 = [1024..64512], default=4096
- *       value2 = [0..64512],    default=4096
- *       value3 = [0..64512],    default=0
- */
-
-#define E1000_PSRCTL_BSIZE0_MASK	0x0000007F
-#define E1000_PSRCTL_BSIZE1_MASK	0x00003F00
-#define E1000_PSRCTL_BSIZE2_MASK	0x003F0000
-#define E1000_PSRCTL_BSIZE3_MASK	0x3F000000
-
-#define E1000_PSRCTL_BSIZE0_SHIFT	7    /* Shift _right_ 7 */
-#define E1000_PSRCTL_BSIZE1_SHIFT	2    /* Shift _right_ 2 */
-#define E1000_PSRCTL_BSIZE2_SHIFT	6    /* Shift _left_ 6 */
-#define E1000_PSRCTL_BSIZE3_SHIFT	14   /* Shift _left_ 14 */
-
-/* SWFW_SYNC Definitions */
-#define E1000_SWFW_EEP_SM	0x01
-#define E1000_SWFW_PHY0_SM	0x02
-#define E1000_SWFW_PHY1_SM	0x04
-#define E1000_SWFW_CSR_SM	0x08
-#define E1000_SWFW_PHY2_SM	0x20
-#define E1000_SWFW_PHY3_SM	0x40
-#define E1000_SWFW_SW_MNG_SM	0x400
-
-/* FACTPS Definitions */
-#define E1000_FACTPS_LFS	0x40000000  /* LAN Function Select */
-/* Device Control */
-#define E1000_CTRL_FD		0x00000001  /* Full duplex.0=half; 1=full */
-#define E1000_CTRL_BEM		0x00000002  /* Endian Mode.0=little,1=big */
-#define E1000_CTRL_PRIOR	0x00000004  /* Priority on PCI. 0=rx,1=fair */
-#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
-#define E1000_CTRL_LRST		0x00000008  /* Link reset. 0=normal,1=reset */
-#define E1000_CTRL_TME		0x00000010  /* Test mode. 0=normal,1=test */
-#define E1000_CTRL_SLE		0x00000020  /* Serial Link on 0=dis,1=en */
-#define E1000_CTRL_ASDE		0x00000020  /* Auto-speed detect enable */
-#define E1000_CTRL_SLU		0x00000040  /* Set link up (Force Link) */
-#define E1000_CTRL_ILOS		0x00000080  /* Invert Loss-Of Signal */
-#define E1000_CTRL_SPD_SEL	0x00000300  /* Speed Select Mask */
-#define E1000_CTRL_SPD_10	0x00000000  /* Force 10Mb */
-#define E1000_CTRL_SPD_100	0x00000100  /* Force 100Mb */
-#define E1000_CTRL_SPD_1000	0x00000200  /* Force 1Gb */
-#define E1000_CTRL_BEM32	0x00000400  /* Big Endian 32 mode */
-#define E1000_CTRL_FRCSPD	0x00000800  /* Force Speed */
-#define E1000_CTRL_FRCDPX	0x00001000  /* Force Duplex */
-#define E1000_CTRL_D_UD_EN	0x00002000  /* Dock/Undock enable */
-/* Defined polarity of Dock/Undock indication in SDP[0] */
-#define E1000_CTRL_D_UD_POLARITY	0x00004000
-/* Reset both PHY ports, through PHYRST_N pin */
-#define E1000_CTRL_FORCE_PHY_RESET	0x00008000
-/* enable link status from external LINK_0 and LINK_1 pins */
-#define E1000_CTRL_EXT_LINK_EN		0x00010000
-#define E1000_CTRL_SWDPIN0	0x00040000 /* SWDPIN 0 value */
-#define E1000_CTRL_SWDPIN1	0x00080000 /* SWDPIN 1 value */
-#define E1000_CTRL_SWDPIN2	0x00100000 /* SWDPIN 2 value */
-#define E1000_CTRL_ADVD3WUC	0x00100000 /* D3 WUC */
-#define E1000_CTRL_SWDPIN3	0x00200000 /* SWDPIN 3 value */
-#define E1000_CTRL_SWDPIO0	0x00400000 /* SWDPIN 0 Input or output */
-#define E1000_CTRL_SWDPIO1	0x00800000 /* SWDPIN 1 input or output */
-#define E1000_CTRL_SWDPIO2	0x01000000 /* SWDPIN 2 input or output */
-#define E1000_CTRL_SWDPIO3	0x02000000 /* SWDPIN 3 input or output */
-#define E1000_CTRL_RST		0x04000000 /* Global reset */
-#define E1000_CTRL_RFCE		0x08000000 /* Receive Flow Control enable */
-#define E1000_CTRL_TFCE		0x10000000 /* Transmit flow control enable */
-#define E1000_CTRL_RTE		0x20000000 /* Routing tag enable */
-#define E1000_CTRL_VME		0x40000000 /* IEEE VLAN mode enable */
-#define E1000_CTRL_PHY_RST	0x80000000 /* PHY Reset */
-#define E1000_CTRL_SW2FW_INT	0x02000000 /* Initiate an interrupt to ME */
-#define E1000_CTRL_I2C_ENA	0x02000000 /* I2C enable */
-
-/*
- * Bit definitions for the Management Data IO (MDIO) and Management Data
- * Clock (MDC) pins in the Device Control Register.
- */
-#define E1000_CTRL_PHY_RESET_DIR	E1000_CTRL_SWDPIO0
-#define E1000_CTRL_PHY_RESET		E1000_CTRL_SWDPIN0
-#define E1000_CTRL_MDIO_DIR		E1000_CTRL_SWDPIO2
-#define E1000_CTRL_MDIO			E1000_CTRL_SWDPIN2
-#define E1000_CTRL_MDC_DIR		E1000_CTRL_SWDPIO3
-#define E1000_CTRL_MDC			E1000_CTRL_SWDPIN3
-#define E1000_CTRL_PHY_RESET_DIR4	E1000_CTRL_EXT_SDP4_DIR
-#define E1000_CTRL_PHY_RESET4		E1000_CTRL_EXT_SDP4_DATA
-
-#define E1000_CONNSW_ENRGSRC		0x4
-#define E1000_PCS_CFG_PCS_EN		8
-#define E1000_PCS_LCTL_FLV_LINK_UP	1
-#define E1000_PCS_LCTL_FSV_10		0
-#define E1000_PCS_LCTL_FSV_100		2
-#define E1000_PCS_LCTL_FSV_1000		4
-#define E1000_PCS_LCTL_FDV_FULL		8
-#define E1000_PCS_LCTL_FSD		0x10
-#define E1000_PCS_LCTL_FORCE_LINK	0x20
-#define E1000_PCS_LCTL_LOW_LINK_LATCH	0x40
-#define E1000_PCS_LCTL_FORCE_FCTRL	0x80
-#define E1000_PCS_LCTL_AN_ENABLE	0x10000
-#define E1000_PCS_LCTL_AN_RESTART	0x20000
-#define E1000_PCS_LCTL_AN_TIMEOUT	0x40000
-#define E1000_PCS_LCTL_AN_SGMII_BYPASS	0x80000
-#define E1000_PCS_LCTL_AN_SGMII_TRIGGER	0x100000
-#define E1000_PCS_LCTL_FAST_LINK_TIMER	0x1000000
-#define E1000_PCS_LCTL_LINK_OK_FIX	0x2000000
-#define E1000_PCS_LCTL_CRS_ON_NI	0x4000000
-#define E1000_ENABLE_SERDES_LOOPBACK	0x0410
-
-#define E1000_PCS_LSTS_LINK_OK		1
-#define E1000_PCS_LSTS_SPEED_10		0
-#define E1000_PCS_LSTS_SPEED_100	2
-#define E1000_PCS_LSTS_SPEED_1000	4
-#define E1000_PCS_LSTS_DUPLEX_FULL	8
-#define E1000_PCS_LSTS_SYNK_OK		0x10
-#define E1000_PCS_LSTS_AN_COMPLETE	0x10000
-#define E1000_PCS_LSTS_AN_PAGE_RX	0x20000
-#define E1000_PCS_LSTS_AN_TIMED_OUT	0x40000
-#define E1000_PCS_LSTS_AN_REMOTE_FAULT	0x80000
-#define E1000_PCS_LSTS_AN_ERROR_RWS	0x100000
-
-/* Device Status */
-#define E1000_STATUS_FD			0x00000001 /* Duplex 0=half 1=full */
-#define E1000_STATUS_LU			0x00000002 /* Link up.0=no,1=link */
-#define E1000_STATUS_FUNC_MASK		0x0000000C /* PCI Function Mask */
-#define E1000_STATUS_FUNC_SHIFT		2
-#define E1000_STATUS_FUNC_0		0x00000000 /* Function 0 */
-#define E1000_STATUS_FUNC_1		0x00000004 /* Function 1 */
-#define E1000_STATUS_TXOFF		0x00000010 /* transmission paused */
-#define E1000_STATUS_TBIMODE		0x00000020 /* TBI mode */
-#define E1000_STATUS_SPEED_MASK		0x000000C0
-#define E1000_STATUS_SPEED_10		0x00000000 /* Speed 10Mb/s */
-#define E1000_STATUS_SPEED_100		0x00000040 /* Speed 100Mb/s */
-#define E1000_STATUS_SPEED_1000		0x00000080 /* Speed 1000Mb/s */
-#define E1000_STATUS_LAN_INIT_DONE	0x00000200 /* Lan Init Compltn by NVM */
-#define E1000_STATUS_ASDV		0x00000300 /* Auto speed detect value */
-#define E1000_STATUS_PHYRA		0x00000400 /* PHY Reset Asserted */
-/* Change in Dock/Undock state clear on write '0'. */
-#define E1000_STATUS_DOCK_CI		0x00000800
-#define E1000_STATUS_GIO_MASTER_ENABLE	0x00080000 /* Master request status */
-#define E1000_STATUS_MTXCKOK		0x00000400 /* MTX clock running OK */
-#define E1000_STATUS_PCI66		0x00000800 /* In 66Mhz slot */
-#define E1000_STATUS_BUS64		0x00001000 /* In 64 bit slot */
-#define E1000_STATUS_PCIX_MODE		0x00002000 /* PCI-X mode */
-#define E1000_STATUS_PCIX_SPEED		0x0000C000 /* PCI-X bus speed */
-#define E1000_STATUS_BMC_SKU_0		0x00100000 /* BMC USB redirect disbld */
-#define E1000_STATUS_BMC_SKU_1		0x00200000 /* BMC SRAM disabled */
-#define E1000_STATUS_BMC_SKU_2		0x00400000 /* BMC SDRAM disabled */
-#define E1000_STATUS_BMC_CRYPTO		0x00800000 /* BMC crypto disabled */
-/* BMC external code execution disabled */
-#define E1000_STATUS_BMC_LITE		0x01000000
-#define E1000_STATUS_RGMII_ENABLE	0x02000000 /* RGMII disabled */
-#define E1000_STATUS_FUSE_8		0x04000000
-#define E1000_STATUS_FUSE_9		0x08000000
-#define E1000_STATUS_SERDES0_DIS	0x10000000 /* SERDES disbld on port 0 */
-#define E1000_STATUS_SERDES1_DIS	0x20000000 /* SERDES disbld on port 1 */
-
-/* Constants used to interpret the masked PCI-X bus speed. */
-#define E1000_STATUS_PCIX_SPEED_66	0x00000000 /* PCI-X bus spd 50-66MHz */
-#define E1000_STATUS_PCIX_SPEED_100	0x00004000 /* PCI-X bus spd 66-100MHz */
-#define E1000_STATUS_PCIX_SPEED_133	0x00008000 /* PCI-X bus spd 100-133MHz*/
-
-#define SPEED_10	10
-#define SPEED_100	100
-#define SPEED_1000	1000
-#define HALF_DUPLEX	1
-#define FULL_DUPLEX	2
-
-#define PHY_FORCE_TIME	20
-
-#define ADVERTISE_10_HALF		0x0001
-#define ADVERTISE_10_FULL		0x0002
-#define ADVERTISE_100_HALF		0x0004
-#define ADVERTISE_100_FULL		0x0008
-#define ADVERTISE_1000_HALF		0x0010 /* Not used, just FYI */
-#define ADVERTISE_1000_FULL		0x0020
-
-/* 1000/H is not supported, nor spec-compliant. */
-#define E1000_ALL_SPEED_DUPLEX	( \
-	ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
-	ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
-#define E1000_ALL_NOT_GIG	( \
-	ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
-	ADVERTISE_100_FULL)
-#define E1000_ALL_100_SPEED	(ADVERTISE_100_HALF | ADVERTISE_100_FULL)
-#define E1000_ALL_10_SPEED	(ADVERTISE_10_HALF | ADVERTISE_10_FULL)
-#define E1000_ALL_FULL_DUPLEX	( \
-	ADVERTISE_10_FULL | ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
-#define E1000_ALL_HALF_DUPLEX	(ADVERTISE_10_HALF | ADVERTISE_100_HALF)
-
-#define AUTONEG_ADVERTISE_SPEED_DEFAULT		E1000_ALL_SPEED_DUPLEX
-
-/* LED Control */
-#define E1000_LEDCTL_LED0_MODE_MASK	0x0000000F
-#define E1000_LEDCTL_LED0_MODE_SHIFT	0
-#define E1000_LEDCTL_LED0_BLINK_RATE	0x00000020
-#define E1000_LEDCTL_LED0_IVRT		0x00000040
-#define E1000_LEDCTL_LED0_BLINK		0x00000080
-#define E1000_LEDCTL_LED1_MODE_MASK	0x00000F00
-#define E1000_LEDCTL_LED1_MODE_SHIFT	8
-#define E1000_LEDCTL_LED1_BLINK_RATE	0x00002000
-#define E1000_LEDCTL_LED1_IVRT		0x00004000
-#define E1000_LEDCTL_LED1_BLINK		0x00008000
-#define E1000_LEDCTL_LED2_MODE_MASK	0x000F0000
-#define E1000_LEDCTL_LED2_MODE_SHIFT	16
-#define E1000_LEDCTL_LED2_BLINK_RATE	0x00200000
-#define E1000_LEDCTL_LED2_IVRT		0x00400000
-#define E1000_LEDCTL_LED2_BLINK		0x00800000
-#define E1000_LEDCTL_LED3_MODE_MASK	0x0F000000
-#define E1000_LEDCTL_LED3_MODE_SHIFT	24
-#define E1000_LEDCTL_LED3_BLINK_RATE	0x20000000
-#define E1000_LEDCTL_LED3_IVRT		0x40000000
-#define E1000_LEDCTL_LED3_BLINK		0x80000000
-
-#define E1000_LEDCTL_MODE_LINK_10_1000	0x0
-#define E1000_LEDCTL_MODE_LINK_100_1000	0x1
-#define E1000_LEDCTL_MODE_LINK_UP	0x2
-#define E1000_LEDCTL_MODE_ACTIVITY	0x3
-#define E1000_LEDCTL_MODE_LINK_ACTIVITY	0x4
-#define E1000_LEDCTL_MODE_LINK_10	0x5
-#define E1000_LEDCTL_MODE_LINK_100	0x6
-#define E1000_LEDCTL_MODE_LINK_1000	0x7
-#define E1000_LEDCTL_MODE_PCIX_MODE	0x8
-#define E1000_LEDCTL_MODE_FULL_DUPLEX	0x9
-#define E1000_LEDCTL_MODE_COLLISION	0xA
-#define E1000_LEDCTL_MODE_BUS_SPEED	0xB
-#define E1000_LEDCTL_MODE_BUS_SIZE	0xC
-#define E1000_LEDCTL_MODE_PAUSED	0xD
-#define E1000_LEDCTL_MODE_LED_ON	0xE
-#define E1000_LEDCTL_MODE_LED_OFF	0xF
-
-/* Transmit Descriptor bit definitions */
-#define E1000_TXD_DTYP_D	0x00100000 /* Data Descriptor */
-#define E1000_TXD_DTYP_C	0x00000000 /* Context Descriptor */
-#define E1000_TXD_DMA_TXDWB	0x00000002 /* sample DMA time of TXD writeback */
-#define E1000_TXD_POPTS_SHIFT	8          /* POPTS shift */
-#define E1000_TXD_POPTS_IXSM	0x01       /* Insert IP checksum */
-#define E1000_TXD_POPTS_TXSM	0x02       /* Insert TCP/UDP checksum */
-#define E1000_TXD_CMD_EOP	0x01000000 /* End of Packet */
-#define E1000_TXD_CMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
-#define E1000_TXD_CMD_IC	0x04000000 /* Insert Checksum */
-#define E1000_TXD_CMD_RS	0x08000000 /* Report Status */
-#define E1000_TXD_CMD_RPS	0x10000000 /* Report Packet Sent */
-#define E1000_TXD_CMD_DEXT	0x20000000 /* Desc extension (0 = legacy) */
-#define E1000_TXD_CMD_VLE	0x40000000 /* Add VLAN tag */
-#define E1000_TXD_CMD_IDE	0x80000000 /* Enable Tidv register */
-#define E1000_TXD_STAT_DD	0x00000001 /* Descriptor Done */
-#define E1000_TXD_STAT_EC	0x00000002 /* Excess Collisions */
-#define E1000_TXD_STAT_LC	0x00000004 /* Late Collisions */
-#define E1000_TXD_STAT_TU	0x00000008 /* Transmit underrun */
-#define E1000_TXD_CMD_TCP	0x01000000 /* TCP packet */
-#define E1000_TXD_CMD_IP	0x02000000 /* IP packet */
-#define E1000_TXD_CMD_TSE	0x04000000 /* TCP Seg enable */
-#define E1000_TXD_STAT_TC	0x00000004 /* Tx Underrun */
-/* Extended desc bits for Linksec and timesync */
-
-/* Transmit Control */
-#define E1000_TCTL_RST		0x00000001 /* software reset */
-#define E1000_TCTL_EN		0x00000002 /* enable Tx */
-#define E1000_TCTL_BCE		0x00000004 /* busy check enable */
-#define E1000_TCTL_PSP		0x00000008 /* pad short packets */
-#define E1000_TCTL_CT		0x00000ff0 /* collision threshold */
-#define E1000_TCTL_COLD		0x003ff000 /* collision distance */
-#define E1000_TCTL_SWXOFF	0x00400000 /* SW Xoff transmission */
-#define E1000_TCTL_PBE		0x00800000 /* Packet Burst Enable */
-#define E1000_TCTL_RTLC		0x01000000 /* Re-transmit on late collision */
-#define E1000_TCTL_NRTU		0x02000000 /* No Re-transmit on underrun */
-#define E1000_TCTL_MULR		0x10000000 /* Multiple request support */
-
-/* Transmit Arbitration Count */
-#define E1000_TARC0_ENABLE	0x00000400 /* Enable Tx Queue 0 */
-
-/* SerDes Control */
-#define E1000_SCTL_DISABLE_SERDES_LOOPBACK	0x0400
-
-/* Receive Checksum Control */
-#define E1000_RXCSUM_PCSS_MASK	0x000000FF /* Packet Checksum Start */
-#define E1000_RXCSUM_IPOFL	0x00000100 /* IPv4 checksum offload */
-#define E1000_RXCSUM_TUOFL	0x00000200 /* TCP / UDP checksum offload */
-#define E1000_RXCSUM_IPV6OFL	0x00000400 /* IPv6 checksum offload */
-#define E1000_RXCSUM_CRCOFL	0x00000800 /* CRC32 offload enable */
-#define E1000_RXCSUM_IPPCSE	0x00001000 /* IP payload checksum enable */
-#define E1000_RXCSUM_PCSD	0x00002000 /* packet checksum disabled */
-
-/* Header split receive */
-#define E1000_RFCTL_ISCSI_DIS		0x00000001
-#define E1000_RFCTL_ISCSI_DWC_MASK	0x0000003E
-#define E1000_RFCTL_ISCSI_DWC_SHIFT	1
-#define E1000_RFCTL_NFSW_DIS		0x00000040
-#define E1000_RFCTL_NFSR_DIS		0x00000080
-#define E1000_RFCTL_NFS_VER_MASK	0x00000300
-#define E1000_RFCTL_NFS_VER_SHIFT	8
-#define E1000_RFCTL_IPV6_DIS		0x00000400
-#define E1000_RFCTL_IPV6_XSUM_DIS	0x00000800
-#define E1000_RFCTL_ACK_DIS		0x00001000
-#define E1000_RFCTL_ACKD_DIS		0x00002000
-#define E1000_RFCTL_IPFRSP_DIS		0x00004000
-#define E1000_RFCTL_EXTEN		0x00008000
-#define E1000_RFCTL_IPV6_EX_DIS		0x00010000
-#define E1000_RFCTL_NEW_IPV6_EXT_DIS	0x00020000
-#define E1000_RFCTL_LEF			0x00040000
-
-/* Collision related configuration parameters */
-#define E1000_COLLISION_THRESHOLD	15
-#define E1000_CT_SHIFT			4
-#define E1000_COLLISION_DISTANCE	63
-#define E1000_COLD_SHIFT		12
-
-/* Default values for the transmit IPG register */
-#define DEFAULT_82543_TIPG_IPGT_FIBER	9
-#define DEFAULT_82543_TIPG_IPGT_COPPER	8
-
-#define E1000_TIPG_IPGT_MASK		0x000003FF
-#define E1000_TIPG_IPGR1_MASK		0x000FFC00
-#define E1000_TIPG_IPGR2_MASK		0x3FF00000
-
-#define DEFAULT_82543_TIPG_IPGR1	8
-#define E1000_TIPG_IPGR1_SHIFT		10
-
-#define DEFAULT_82543_TIPG_IPGR2	6
-#define DEFAULT_80003ES2LAN_TIPG_IPGR2	7
-#define E1000_TIPG_IPGR2_SHIFT		20
-
-/* Ethertype field values */
-#define ETHERNET_IEEE_VLAN_TYPE		0x8100  /* 802.3ac packet */
-
-#define ETHERNET_FCS_SIZE		4
-#define MAX_JUMBO_FRAME_SIZE		0x3F00
-
-/* Extended Configuration Control and Size */
-#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP	0x00000020
-#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE	0x00000001
-#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE	0x00000008
-#define E1000_EXTCNF_CTRL_SWFLAG		0x00000020
-#define E1000_EXTCNF_CTRL_GATE_PHY_CFG		0x00000080
-#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK	0x00FF0000
-#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT	16
-#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK	0x0FFF0000
-#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT	16
-
-#define E1000_PHY_CTRL_SPD_EN			0x00000001
-#define E1000_PHY_CTRL_D0A_LPLU			0x00000002
-#define E1000_PHY_CTRL_NOND0A_LPLU		0x00000004
-#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE	0x00000008
-#define E1000_PHY_CTRL_GBE_DISABLE		0x00000040
-
-#define E1000_KABGTXD_BGSQLBIAS			0x00050000
-
-/* PBA constants */
-#define E1000_PBA_6K		0x0006    /* 6KB */
-#define E1000_PBA_8K		0x0008    /* 8KB */
-#define E1000_PBA_10K		0x000A    /* 10KB */
-#define E1000_PBA_12K		0x000C    /* 12KB */
-#define E1000_PBA_14K		0x000E    /* 14KB */
-#define E1000_PBA_16K		0x0010    /* 16KB */
-#define E1000_PBA_18K		0x0012
-#define E1000_PBA_20K		0x0014
-#define E1000_PBA_22K		0x0016
-#define E1000_PBA_24K		0x0018
-#define E1000_PBA_26K		0x001A
-#define E1000_PBA_30K		0x001E
-#define E1000_PBA_32K		0x0020
-#define E1000_PBA_34K		0x0022
-#define E1000_PBA_35K		0x0023
-#define E1000_PBA_38K		0x0026
-#define E1000_PBA_40K		0x0028
-#define E1000_PBA_48K		0x0030    /* 48KB */
-#define E1000_PBA_64K		0x0040    /* 64KB */
-
-#define E1000_PBA_RXA_MASK	0xFFFF;
-
-#define E1000_PBS_16K		E1000_PBA_16K
-#define E1000_PBS_24K		E1000_PBA_24K
-
-#define IFS_MAX			80
-#define IFS_MIN			40
-#define IFS_RATIO		4
-#define IFS_STEP		10
-#define MIN_NUM_XMITS		1000
-
-/* SW Semaphore Register */
-#define E1000_SWSM_SMBI		0x00000001 /* Driver Semaphore bit */
-#define E1000_SWSM_SWESMBI	0x00000002 /* FW Semaphore bit */
-#define E1000_SWSM_WMNG		0x00000004 /* Wake MNG Clock */
-#define E1000_SWSM_DRV_LOAD	0x00000008 /* Driver Loaded Bit */
-
-#define E1000_SWSM2_LOCK	0x00000002 /* Secondary driver semaphore bit */
-
-/* Interrupt Cause Read */
-#define E1000_ICR_TXDW		0x00000001 /* Transmit desc written back */
-#define E1000_ICR_TXQE		0x00000002 /* Transmit Queue empty */
-#define E1000_ICR_LSC		0x00000004 /* Link Status Change */
-#define E1000_ICR_RXSEQ		0x00000008 /* Rx sequence error */
-#define E1000_ICR_RXDMT0	0x00000010 /* Rx desc min. threshold (0) */
-#define E1000_ICR_RXO		0x00000040 /* Rx overrun */
-#define E1000_ICR_RXT0		0x00000080 /* Rx timer intr (ring 0) */
-#define E1000_ICR_VMMB		0x00000100 /* VM MB event */
-#define E1000_ICR_MDAC		0x00000200 /* MDIO access complete */
-#define E1000_ICR_RXCFG		0x00000400 /* Rx /c/ ordered set */
-#define E1000_ICR_GPI_EN0	0x00000800 /* GP Int 0 */
-#define E1000_ICR_GPI_EN1	0x00001000 /* GP Int 1 */
-#define E1000_ICR_GPI_EN2	0x00002000 /* GP Int 2 */
-#define E1000_ICR_GPI_EN3	0x00004000 /* GP Int 3 */
-#define E1000_ICR_TXD_LOW	0x00008000
-#define E1000_ICR_SRPD		0x00010000
-#define E1000_ICR_ACK		0x00020000 /* Receive Ack frame */
-#define E1000_ICR_MNG		0x00040000 /* Manageability event */
-#define E1000_ICR_DOCK		0x00080000 /* Dock/Undock */
-#define E1000_ICR_DRSTA		0x40000000 /* Device Reset Asserted */
-/* If this bit asserted, the driver should claim the interrupt */
-#define E1000_ICR_INT_ASSERTED	0x80000000
-#define E1000_ICR_RXD_FIFO_PAR0	0x00100000 /* Q0 Rx desc FIFO parity error */
-#define E1000_ICR_TXD_FIFO_PAR0	0x00200000 /* Q0 Tx desc FIFO parity error */
-#define E1000_ICR_HOST_ARB_PAR	0x00400000 /* host arb read buffer parity err */
-#define E1000_ICR_PB_PAR	0x00800000 /* packet buffer parity error */
-#define E1000_ICR_RXD_FIFO_PAR1	0x01000000 /* Q1 Rx desc FIFO parity error */
-#define E1000_ICR_TXD_FIFO_PAR1	0x02000000 /* Q1 Tx desc FIFO parity error */
-#define E1000_ICR_ALL_PARITY	0x03F00000 /* all parity error bits */
-/* FW changed the status of DISSW bit in the FWSM */
-#define E1000_ICR_DSW		0x00000020
-/* LAN connected device generates an interrupt */
-#define E1000_ICR_PHYINT	0x00001000
-#define E1000_ICR_DOUTSYNC	0x10000000 /* NIC DMA out of sync */
-#define E1000_ICR_EPRST		0x00100000 /* ME hardware reset occurs */
-#define E1000_ICR_FER		0x00400000 /* Fatal Error */
-
-#define E1000_ICR_THS		0x00800000 /* ICR.THS: Thermal Sensor Event*/
-#define E1000_ICR_MDDET		0x10000000 /* Malicious Driver Detect */
-
-#define E1000_ITR_MASK		0x000FFFFF /* ITR value bitfield */
-#define E1000_ITR_MULT		256 /* ITR mulitplier in nsec */
-
-
-/* Extended Interrupt Cause Read */
-#define E1000_EICR_RX_QUEUE0	0x00000001 /* Rx Queue 0 Interrupt */
-#define E1000_EICR_RX_QUEUE1	0x00000002 /* Rx Queue 1 Interrupt */
-#define E1000_EICR_RX_QUEUE2	0x00000004 /* Rx Queue 2 Interrupt */
-#define E1000_EICR_RX_QUEUE3	0x00000008 /* Rx Queue 3 Interrupt */
-#define E1000_EICR_TX_QUEUE0	0x00000100 /* Tx Queue 0 Interrupt */
-#define E1000_EICR_TX_QUEUE1	0x00000200 /* Tx Queue 1 Interrupt */
-#define E1000_EICR_TX_QUEUE2	0x00000400 /* Tx Queue 2 Interrupt */
-#define E1000_EICR_TX_QUEUE3	0x00000800 /* Tx Queue 3 Interrupt */
-#define E1000_EICR_TCP_TIMER	0x40000000 /* TCP Timer */
-#define E1000_EICR_OTHER	0x80000000 /* Interrupt Cause Active */
-/* TCP Timer */
-#define E1000_TCPTIMER_KS	0x00000100 /* KickStart */
-#define E1000_TCPTIMER_COUNT_ENABLE	0x00000200 /* Count Enable */
-#define E1000_TCPTIMER_COUNT_FINISH	0x00000400 /* Count finish */
-#define E1000_TCPTIMER_LOOP	0x00000800 /* Loop */
-
-/*
- * This defines the bits that are set in the Interrupt Mask
- * Set/Read Register.  Each bit is documented below:
- *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
- *   o RXSEQ  = Receive Sequence Error
- */
-#define POLL_IMS_ENABLE_MASK ( \
-	E1000_IMS_RXDMT0 |    \
-	E1000_IMS_RXSEQ)
-
-/*
- * This defines the bits that are set in the Interrupt Mask
- * Set/Read Register.  Each bit is documented below:
- *   o RXT0   = Receiver Timer Interrupt (ring 0)
- *   o TXDW   = Transmit Descriptor Written Back
- *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
- *   o RXSEQ  = Receive Sequence Error
- *   o LSC    = Link Status Change
- */
-#define IMS_ENABLE_MASK ( \
-	E1000_IMS_RXT0   |    \
-	E1000_IMS_TXDW   |    \
-	E1000_IMS_RXDMT0 |    \
-	E1000_IMS_RXSEQ  |    \
-	E1000_IMS_LSC)
-
-/* Interrupt Mask Set */
-#define E1000_IMS_TXDW		E1000_ICR_TXDW    /* Tx desc written back */
-#define E1000_IMS_TXQE		E1000_ICR_TXQE    /* Transmit Queue empty */
-#define E1000_IMS_LSC		E1000_ICR_LSC     /* Link Status Change */
-#define E1000_IMS_VMMB		E1000_ICR_VMMB    /* Mail box activity */
-#define E1000_IMS_RXSEQ		E1000_ICR_RXSEQ   /* Rx sequence error */
-#define E1000_IMS_RXDMT0	E1000_ICR_RXDMT0  /* Rx desc min. threshold */
-#define E1000_IMS_RXO		E1000_ICR_RXO     /* Rx overrun */
-#define E1000_IMS_RXT0		E1000_ICR_RXT0    /* Rx timer intr */
-#define E1000_IMS_MDAC		E1000_ICR_MDAC    /* MDIO access complete */
-#define E1000_IMS_RXCFG		E1000_ICR_RXCFG   /* Rx /c/ ordered set */
-#define E1000_IMS_GPI_EN0	E1000_ICR_GPI_EN0 /* GP Int 0 */
-#define E1000_IMS_GPI_EN1	E1000_ICR_GPI_EN1 /* GP Int 1 */
-#define E1000_IMS_GPI_EN2	E1000_ICR_GPI_EN2 /* GP Int 2 */
-#define E1000_IMS_GPI_EN3	E1000_ICR_GPI_EN3 /* GP Int 3 */
-#define E1000_IMS_TXD_LOW	E1000_ICR_TXD_LOW
-#define E1000_IMS_SRPD		E1000_ICR_SRPD
-#define E1000_IMS_ACK		E1000_ICR_ACK     /* Receive Ack frame */
-#define E1000_IMS_MNG		E1000_ICR_MNG     /* Manageability event */
-#define E1000_IMS_DOCK		E1000_ICR_DOCK    /* Dock/Undock */
-#define E1000_IMS_DRSTA		E1000_ICR_DRSTA   /* Device Reset Asserted */
-/* Q0 Rx desc FIFO parity error */
-#define E1000_IMS_RXD_FIFO_PAR0	E1000_ICR_RXD_FIFO_PAR0
-/* Q0 Tx desc FIFO parity error */
-#define E1000_IMS_TXD_FIFO_PAR0	E1000_ICR_TXD_FIFO_PAR0
-/* host arb read buffer parity error */
-#define E1000_IMS_HOST_ARB_PAR	E1000_ICR_HOST_ARB_PAR
-/* packet buffer parity error */
-#define E1000_IMS_PB_PAR	E1000_ICR_PB_PAR
-/* Q1 Rx desc FIFO parity error */
-#define E1000_IMS_RXD_FIFO_PAR1	E1000_ICR_RXD_FIFO_PAR1
-/* Q1 Tx desc FIFO parity error */
-#define E1000_IMS_TXD_FIFO_PAR1	E1000_ICR_TXD_FIFO_PAR1
-#define E1000_IMS_DSW		E1000_ICR_DSW
-#define E1000_IMS_PHYINT	E1000_ICR_PHYINT
-#define E1000_IMS_DOUTSYNC	E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
-#define E1000_IMS_EPRST		E1000_ICR_EPRST
-#define E1000_IMS_FER		E1000_ICR_FER /* Fatal Error */
-
-#define E1000_IMS_THS		E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/
-#define E1000_IMS_MDDET		E1000_ICR_MDDET /* Malicious Driver Detect */
-/* Extended Interrupt Mask Set */
-#define E1000_EIMS_RX_QUEUE0	E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
-#define E1000_EIMS_RX_QUEUE1	E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
-#define E1000_EIMS_RX_QUEUE2	E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
-#define E1000_EIMS_RX_QUEUE3	E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
-#define E1000_EIMS_TX_QUEUE0	E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
-#define E1000_EIMS_TX_QUEUE1	E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
-#define E1000_EIMS_TX_QUEUE2	E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
-#define E1000_EIMS_TX_QUEUE3	E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
-#define E1000_EIMS_TCP_TIMER	E1000_EICR_TCP_TIMER /* TCP Timer */
-#define E1000_EIMS_OTHER	E1000_EICR_OTHER   /* Interrupt Cause Active */
-
-/* Interrupt Cause Set */
-#define E1000_ICS_TXDW		E1000_ICR_TXDW      /* Tx desc written back */
-#define E1000_ICS_TXQE		E1000_ICR_TXQE      /* Transmit Queue empty */
-#define E1000_ICS_LSC		E1000_ICR_LSC       /* Link Status Change */
-#define E1000_ICS_RXSEQ		E1000_ICR_RXSEQ     /* Rx sequence error */
-#define E1000_ICS_RXDMT0	E1000_ICR_RXDMT0    /* Rx desc min. threshold */
-#define E1000_ICS_RXO		E1000_ICR_RXO       /* Rx overrun */
-#define E1000_ICS_RXT0		E1000_ICR_RXT0      /* Rx timer intr */
-#define E1000_ICS_MDAC		E1000_ICR_MDAC      /* MDIO access complete */
-#define E1000_ICS_RXCFG		E1000_ICR_RXCFG     /* Rx /c/ ordered set */
-#define E1000_ICS_GPI_EN0	E1000_ICR_GPI_EN0   /* GP Int 0 */
-#define E1000_ICS_GPI_EN1	E1000_ICR_GPI_EN1   /* GP Int 1 */
-#define E1000_ICS_GPI_EN2	E1000_ICR_GPI_EN2   /* GP Int 2 */
-#define E1000_ICS_GPI_EN3	E1000_ICR_GPI_EN3   /* GP Int 3 */
-#define E1000_ICS_TXD_LOW	E1000_ICR_TXD_LOW
-#define E1000_ICS_SRPD		E1000_ICR_SRPD
-#define E1000_ICS_ACK		E1000_ICR_ACK       /* Receive Ack frame */
-#define E1000_ICS_MNG		E1000_ICR_MNG       /* Manageability event */
-#define E1000_ICS_DOCK		E1000_ICR_DOCK      /* Dock/Undock */
-#define E1000_ICS_DRSTA		E1000_ICR_DRSTA     /* Device Reset Aserted */
-/* Q0 Rx desc FIFO parity error */
-#define E1000_ICS_RXD_FIFO_PAR0	E1000_ICR_RXD_FIFO_PAR0
-/* Q0 Tx desc FIFO parity error */
-#define E1000_ICS_TXD_FIFO_PAR0	E1000_ICR_TXD_FIFO_PAR0
-/* host arb read buffer parity error */
-#define E1000_ICS_HOST_ARB_PAR	E1000_ICR_HOST_ARB_PAR
-/* packet buffer parity error */
-#define E1000_ICS_PB_PAR	E1000_ICR_PB_PAR
-/* Q1 Rx desc FIFO parity error */
-#define E1000_ICS_RXD_FIFO_PAR1	E1000_ICR_RXD_FIFO_PAR1
-/* Q1 Tx desc FIFO parity error */
-#define E1000_ICS_TXD_FIFO_PAR1	E1000_ICR_TXD_FIFO_PAR1
-#define E1000_ICS_DSW		E1000_ICR_DSW
-#define E1000_ICS_DOUTSYNC	E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
-#define E1000_ICS_PHYINT	E1000_ICR_PHYINT
-#define E1000_ICS_EPRST		E1000_ICR_EPRST
-
-/* Extended Interrupt Cause Set */
-#define E1000_EICS_RX_QUEUE0	E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
-#define E1000_EICS_RX_QUEUE1	E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
-#define E1000_EICS_RX_QUEUE2	E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
-#define E1000_EICS_RX_QUEUE3	E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
-#define E1000_EICS_TX_QUEUE0	E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
-#define E1000_EICS_TX_QUEUE1	E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
-#define E1000_EICS_TX_QUEUE2	E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
-#define E1000_EICS_TX_QUEUE3	E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
-#define E1000_EICS_TCP_TIMER	E1000_EICR_TCP_TIMER /* TCP Timer */
-#define E1000_EICS_OTHER	E1000_EICR_OTHER   /* Interrupt Cause Active */
-
-#define E1000_EITR_ITR_INT_MASK	0x0000FFFF
-/* E1000_EITR_CNT_IGNR is only for 82576 and newer */
-#define E1000_EITR_CNT_IGNR	0x80000000 /* Don't reset counters on write */
-
-/* Transmit Descriptor Control */
-#define E1000_TXDCTL_PTHRESH	0x0000003F /* TXDCTL Prefetch Threshold */
-#define E1000_TXDCTL_HTHRESH	0x00003F00 /* TXDCTL Host Threshold */
-#define E1000_TXDCTL_WTHRESH	0x003F0000 /* TXDCTL Writeback Threshold */
-#define E1000_TXDCTL_GRAN	0x01000000 /* TXDCTL Granularity */
-#define E1000_TXDCTL_LWTHRESH	0xFE000000 /* TXDCTL Low Threshold */
-#define E1000_TXDCTL_FULL_TX_DESC_WB	0x01010000 /* GRAN=1, WTHRESH=1 */
-#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
-/* Enable the counting of descriptors still to be processed. */
-#define E1000_TXDCTL_COUNT_DESC	0x00400000
-
-/* Flow Control Constants */
-#define FLOW_CONTROL_ADDRESS_LOW	0x00C28001
-#define FLOW_CONTROL_ADDRESS_HIGH	0x00000100
-#define FLOW_CONTROL_TYPE		0x8808
-
-/* 802.1q VLAN Packet Size */
-#define VLAN_TAG_SIZE			4    /* 802.3ac tag (not DMA'd) */
-#define E1000_VLAN_FILTER_TBL_SIZE	128  /* VLAN Filter Table (4096 bits) */
-
-/* Receive Address */
-/*
- * Number of high/low register pairs in the RAR. The RAR (Receive Address
- * Registers) holds the directed and multicast addresses that we monitor.
- * Technically, we have 16 spots.  However, we reserve one of these spots
- * (RAR[15]) for our directed address used by controllers with
- * manageability enabled, allowing us room for 15 multicast addresses.
- */
-#define E1000_RAR_ENTRIES	15
-#define E1000_RAH_AV		0x80000000 /* Receive descriptor valid */
-#define E1000_RAL_MAC_ADDR_LEN	4
-#define E1000_RAH_MAC_ADDR_LEN	2
-#define E1000_RAH_QUEUE_MASK_82575	0x000C0000
-#define E1000_RAH_POOL_MASK	0x03FC0000
-#define E1000_RAH_POOL_SHIFT	18
-#define E1000_RAH_POOL_1	0x00040000
-
-/* Error Codes */
-#define E1000_SUCCESS			0
-#define E1000_ERR_NVM			1
-#define E1000_ERR_PHY			2
-#define E1000_ERR_CONFIG		3
-#define E1000_ERR_PARAM			4
-#define E1000_ERR_MAC_INIT		5
-#define E1000_ERR_PHY_TYPE		6
-#define E1000_ERR_RESET			9
-#define E1000_ERR_MASTER_REQUESTS_PENDING	10
-#define E1000_ERR_HOST_INTERFACE_COMMAND	11
-#define E1000_BLK_PHY_RESET		12
-#define E1000_ERR_SWFW_SYNC		13
-#define E1000_NOT_IMPLEMENTED		14
-#define E1000_ERR_MBX			15
-#define E1000_ERR_INVALID_ARGUMENT	16
-#define E1000_ERR_NO_SPACE		17
-#define E1000_ERR_NVM_PBA_SECTION	18
-#define E1000_ERR_I2C			19
-#define E1000_ERR_INVM_VALUE_NOT_FOUND	20
-
-/* Loop limit on how long we wait for auto-negotiation to complete */
-#define FIBER_LINK_UP_LIMIT		50
-#define COPPER_LINK_UP_LIMIT		10
-#define PHY_AUTO_NEG_LIMIT		45
-#define PHY_FORCE_LIMIT			20
-/* Number of 100 microseconds we wait for PCI Express master disable */
-#define MASTER_DISABLE_TIMEOUT		800
-/* Number of milliseconds we wait for PHY configuration done after MAC reset */
-#define PHY_CFG_TIMEOUT			100
-/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
-#define MDIO_OWNERSHIP_TIMEOUT		10
-/* Number of milliseconds for NVM auto read done after MAC reset. */
-#define AUTO_READ_DONE_TIMEOUT		10
-
-/* Flow Control */
-#define E1000_FCRTH_RTH		0x0000FFF8 /* Mask Bits[15:3] for RTH */
-#define E1000_FCRTH_XFCE	0x80000000 /* External Flow Control Enable */
-#define E1000_FCRTL_RTL		0x0000FFF8 /* Mask Bits[15:3] for RTL */
-#define E1000_FCRTL_XONE	0x80000000 /* Enable XON frame transmission */
-
-/* Transmit Configuration Word */
-#define E1000_TXCW_FD		0x00000020 /* TXCW full duplex */
-#define E1000_TXCW_HD		0x00000040 /* TXCW half duplex */
-#define E1000_TXCW_PAUSE	0x00000080 /* TXCW sym pause request */
-#define E1000_TXCW_ASM_DIR	0x00000100 /* TXCW astm pause direction */
-#define E1000_TXCW_PAUSE_MASK	0x00000180 /* TXCW pause request mask */
-#define E1000_TXCW_RF		0x00003000 /* TXCW remote fault */
-#define E1000_TXCW_NP		0x00008000 /* TXCW next page */
-#define E1000_TXCW_CW		0x0000ffff /* TxConfigWord mask */
-#define E1000_TXCW_TXC		0x40000000 /* Transmit Config control */
-#define E1000_TXCW_ANE		0x80000000 /* Auto-neg enable */
-
-/* Receive Configuration Word */
-#define E1000_RXCW_CW		0x0000ffff /* RxConfigWord mask */
-#define E1000_RXCW_NC		0x04000000 /* Receive config no carrier */
-#define E1000_RXCW_IV		0x08000000 /* Receive config invalid */
-#define E1000_RXCW_CC		0x10000000 /* Receive config change */
-#define E1000_RXCW_C		0x20000000 /* Receive config */
-#define E1000_RXCW_SYNCH	0x40000000 /* Receive config synch */
-#define E1000_RXCW_ANC		0x80000000 /* Auto-neg complete */
-
-#define E1000_TSYNCTXCTL_VALID		0x00000001 /* Tx timestamp valid */
-#define E1000_TSYNCTXCTL_ENABLED	0x00000010 /* enable Tx timestamping */
-
-#define E1000_TSYNCRXCTL_VALID		0x00000001 /* Rx timestamp valid */
-#define E1000_TSYNCRXCTL_TYPE_MASK	0x0000000E /* Rx type mask */
-#define E1000_TSYNCRXCTL_TYPE_L2_V2	0x00
-#define E1000_TSYNCRXCTL_TYPE_L4_V1	0x02
-#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2	0x04
-#define E1000_TSYNCRXCTL_TYPE_ALL	0x08
-#define E1000_TSYNCRXCTL_TYPE_EVENT_V2	0x0A
-#define E1000_TSYNCRXCTL_ENABLED	0x00000010 /* enable Rx timestamping */
-
-#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK		0x000000FF
-#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE		0x00
-#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE	0x01
-#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE	0x02
-#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE	0x03
-#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE	0x04
-
-#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK		0x00000F00
-#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE		0x0000
-#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE	0x0100
-#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE	0x0200
-#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE	0x0300
-#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE	0x0800
-#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE	0x0900
-#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
-#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE	0x0B00
-#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE	0x0C00
-#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE	0x0D00
-
-#define E1000_TIMINCA_16NS_SHIFT	24
-/* TUPLE Filtering Configuration */
-#define E1000_TTQF_DISABLE_MASK		0xF0008000 /* TTQF Disable Mask */
-#define E1000_TTQF_QUEUE_ENABLE		0x100   /* TTQF Queue Enable Bit */
-#define E1000_TTQF_PROTOCOL_MASK	0xFF    /* TTQF Protocol Mask */
-/* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
-#define E1000_TTQF_PROTOCOL_TCP		0x0
-/* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
-#define E1000_TTQF_PROTOCOL_UDP		0x1
-/* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
-#define E1000_TTQF_PROTOCOL_SCTP	0x2
-#define E1000_TTQF_PROTOCOL_SHIFT	5       /* TTQF Protocol Shift */
-#define E1000_TTQF_QUEUE_SHIFT		16      /* TTQF Queue Shfit */
-#define E1000_TTQF_RX_QUEUE_MASK	0x70000 /* TTQF Queue Mask */
-#define E1000_TTQF_MASK_ENABLE		0x10000000 /* TTQF Mask Enable Bit */
-#define E1000_IMIR_CLEAR_MASK		0xF001FFFF /* IMIR Reg Clear Mask */
-#define E1000_IMIR_PORT_BYPASS		0x20000 /* IMIR Port Bypass Bit */
-#define E1000_IMIR_PRIORITY_SHIFT	29 /* IMIR Priority Shift */
-#define E1000_IMIREXT_CLEAR_MASK	0x7FFFF /* IMIREXT Reg Clear Mask */
-
-#define E1000_MDICNFG_EXT_MDIO		0x80000000 /* MDI ext/int destination */
-#define E1000_MDICNFG_COM_MDIO		0x40000000 /* MDI shared w/ lan 0 */
-#define E1000_MDICNFG_PHY_MASK		0x03E00000
-#define E1000_MDICNFG_PHY_SHIFT		21
-
-#define E1000_THSTAT_LOW_EVENT		0x20000000 /* Low thermal threshold */
-#define E1000_THSTAT_MID_EVENT		0x00200000 /* Mid thermal threshold */
-#define E1000_THSTAT_HIGH_EVENT		0x00002000 /* High thermal threshold */
-#define E1000_THSTAT_PWR_DOWN		0x00000001 /* Power Down Event */
-#define E1000_THSTAT_LINK_THROTTLE	0x00000002 /* Link Spd Throttle Event */
-
-/* I350 EEE defines */
-#define E1000_IPCNFG_EEE_1G_AN		0x00000008 /* IPCNFG EEE Ena 1G AN */
-#define E1000_IPCNFG_EEE_100M_AN	0x00000004 /* IPCNFG EEE Ena 100M AN */
-#define E1000_EEER_TX_LPI_EN		0x00010000 /* EEER Tx LPI Enable */
-#define E1000_EEER_RX_LPI_EN		0x00020000 /* EEER Rx LPI Enable */
-#define E1000_EEER_LPI_FC		0x00040000 /* EEER Ena on Flow Cntrl */
-/* EEE status */
-#define E1000_EEER_EEE_NEG		0x20000000 /* EEE capability nego */
-#define E1000_EEER_RX_LPI_STATUS	0x40000000 /* Rx in LPI state */
-#define E1000_EEER_TX_LPI_STATUS	0x80000000 /* Tx in LPI state */
-
-/* PCI Express Control */
-#define E1000_GCR_RXD_NO_SNOOP		0x00000001
-#define E1000_GCR_RXDSCW_NO_SNOOP	0x00000002
-#define E1000_GCR_RXDSCR_NO_SNOOP	0x00000004
-#define E1000_GCR_TXD_NO_SNOOP		0x00000008
-#define E1000_GCR_TXDSCW_NO_SNOOP	0x00000010
-#define E1000_GCR_TXDSCR_NO_SNOOP	0x00000020
-#define E1000_GCR_CMPL_TMOUT_MASK	0x0000F000
-#define E1000_GCR_CMPL_TMOUT_10ms	0x00001000
-#define E1000_GCR_CMPL_TMOUT_RESEND	0x00010000
-#define E1000_GCR_CAP_VER2		0x00040000
-
-#define PCIE_NO_SNOOP_ALL	(E1000_GCR_RXD_NO_SNOOP | \
-				 E1000_GCR_RXDSCW_NO_SNOOP | \
-				 E1000_GCR_RXDSCR_NO_SNOOP | \
-				 E1000_GCR_TXD_NO_SNOOP    | \
-				 E1000_GCR_TXDSCW_NO_SNOOP | \
-				 E1000_GCR_TXDSCR_NO_SNOOP)
-
-/* mPHY address control and data registers */
-#define E1000_MPHY_ADDR_CTL		0x0024 /* Address Control Reg */
-#define E1000_MPHY_ADDR_CTL_OFFSET_MASK	0xFFFF0000
-#define E1000_MPHY_DATA			0x0E10 /* Data Register */
-
-/* AFE CSR Offset for PCS CLK */
-#define E1000_MPHY_PCS_CLK_REG_OFFSET	0x0004
-/* Override for near end digital loopback. */
-#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN	0x10
-
-/* PHY Control Register */
-#define MII_CR_SPEED_SELECT_MSB	0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_COLL_TEST_ENABLE	0x0080  /* Collision test enable */
-#define MII_CR_FULL_DUPLEX	0x0100  /* FDX =1, half duplex =0 */
-#define MII_CR_RESTART_AUTO_NEG	0x0200  /* Restart auto negotiation */
-#define MII_CR_ISOLATE		0x0400  /* Isolate PHY from MII */
-#define MII_CR_POWER_DOWN	0x0800  /* Power down */
-#define MII_CR_AUTO_NEG_EN	0x1000  /* Auto Neg Enable */
-#define MII_CR_SPEED_SELECT_LSB	0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_LOOPBACK		0x4000  /* 0 = normal, 1 = loopback */
-#define MII_CR_RESET		0x8000  /* 0 = normal, 1 = PHY reset */
-#define MII_CR_SPEED_1000	0x0040
-#define MII_CR_SPEED_100	0x2000
-#define MII_CR_SPEED_10		0x0000
-
-/* PHY Status Register */
-#define MII_SR_EXTENDED_CAPS	0x0001 /* Extended register capabilities */
-#define MII_SR_JABBER_DETECT	0x0002 /* Jabber Detected */
-#define MII_SR_LINK_STATUS	0x0004 /* Link Status 1 = link */
-#define MII_SR_AUTONEG_CAPS	0x0008 /* Auto Neg Capable */
-#define MII_SR_REMOTE_FAULT	0x0010 /* Remote Fault Detect */
-#define MII_SR_AUTONEG_COMPLETE	0x0020 /* Auto Neg Complete */
-#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
-#define MII_SR_EXTENDED_STATUS	0x0100 /* Ext. status info in Reg 0x0F */
-#define MII_SR_100T2_HD_CAPS	0x0200 /* 100T2 Half Duplex Capable */
-#define MII_SR_100T2_FD_CAPS	0x0400 /* 100T2 Full Duplex Capable */
-#define MII_SR_10T_HD_CAPS	0x0800 /* 10T   Half Duplex Capable */
-#define MII_SR_10T_FD_CAPS	0x1000 /* 10T   Full Duplex Capable */
-#define MII_SR_100X_HD_CAPS	0x2000 /* 100X  Half Duplex Capable */
-#define MII_SR_100X_FD_CAPS	0x4000 /* 100X  Full Duplex Capable */
-#define MII_SR_100T4_CAPS	0x8000 /* 100T4 Capable */
-
-/* Autoneg Advertisement Register */
-#define NWAY_AR_SELECTOR_FIELD	0x0001   /* indicates IEEE 802.3 CSMA/CD */
-#define NWAY_AR_10T_HD_CAPS	0x0020   /* 10T   Half Duplex Capable */
-#define NWAY_AR_10T_FD_CAPS	0x0040   /* 10T   Full Duplex Capable */
-#define NWAY_AR_100TX_HD_CAPS	0x0080   /* 100TX Half Duplex Capable */
-#define NWAY_AR_100TX_FD_CAPS	0x0100   /* 100TX Full Duplex Capable */
-#define NWAY_AR_100T4_CAPS	0x0200   /* 100T4 Capable */
-#define NWAY_AR_PAUSE		0x0400   /* Pause operation desired */
-#define NWAY_AR_ASM_DIR		0x0800   /* Asymmetric Pause Direction bit */
-#define NWAY_AR_REMOTE_FAULT	0x2000   /* Remote Fault detected */
-#define NWAY_AR_NEXT_PAGE	0x8000   /* Next Page ability supported */
-
-/* Link Partner Ability Register (Base Page) */
-#define NWAY_LPAR_SELECTOR_FIELD	0x0000 /* LP protocol selector field */
-#define NWAY_LPAR_10T_HD_CAPS		0x0020 /* LP 10T Half Dplx Capable */
-#define NWAY_LPAR_10T_FD_CAPS		0x0040 /* LP 10T Full Dplx Capable */
-#define NWAY_LPAR_100TX_HD_CAPS		0x0080 /* LP 100TX Half Dplx Capable */
-#define NWAY_LPAR_100TX_FD_CAPS		0x0100 /* LP 100TX Full Dplx Capable */
-#define NWAY_LPAR_100T4_CAPS		0x0200 /* LP is 100T4 Capable */
-#define NWAY_LPAR_PAUSE			0x0400 /* LP Pause operation desired */
-#define NWAY_LPAR_ASM_DIR		0x0800 /* LP Asym Pause Direction bit */
-#define NWAY_LPAR_REMOTE_FAULT		0x2000 /* LP detected Remote Fault */
-#define NWAY_LPAR_ACKNOWLEDGE		0x4000 /* LP rx'd link code word */
-#define NWAY_LPAR_NEXT_PAGE		0x8000 /* Next Page ability supported */
-
-/* Autoneg Expansion Register */
-#define NWAY_ER_LP_NWAY_CAPS		0x0001 /* LP has Auto Neg Capability */
-#define NWAY_ER_PAGE_RXD		0x0002 /* LP 10T Half Dplx Capable */
-#define NWAY_ER_NEXT_PAGE_CAPS		0x0004 /* LP 10T Full Dplx Capable */
-#define NWAY_ER_LP_NEXT_PAGE_CAPS	0x0008 /* LP 100TX Half Dplx Capable */
-#define NWAY_ER_PAR_DETECT_FAULT	0x0010 /* LP 100TX Full Dplx Capable */
-
-/* 1000BASE-T Control Register */
-#define CR_1000T_ASYM_PAUSE	0x0080 /* Advertise asymmetric pause bit */
-#define CR_1000T_HD_CAPS	0x0100 /* Advertise 1000T HD capability */
-#define CR_1000T_FD_CAPS	0x0200 /* Advertise 1000T FD capability  */
-/* 1=Repeater/switch device port 0=DTE device */
-#define CR_1000T_REPEATER_DTE	0x0400
-/* 1=Configure PHY as Master 0=Configure PHY as Slave */
-#define CR_1000T_MS_VALUE	0x0800
-/* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
-#define CR_1000T_MS_ENABLE	0x1000
-#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
-#define CR_1000T_TEST_MODE_1	0x2000 /* Transmit Waveform test */
-#define CR_1000T_TEST_MODE_2	0x4000 /* Master Transmit Jitter test */
-#define CR_1000T_TEST_MODE_3	0x6000 /* Slave Transmit Jitter test */
-#define CR_1000T_TEST_MODE_4	0x8000 /* Transmitter Distortion test */
-
-/* 1000BASE-T Status Register */
-#define SR_1000T_IDLE_ERROR_CNT		0x00FF /* Num idle err since last rd */
-#define SR_1000T_ASYM_PAUSE_DIR		0x0100 /* LP asym pause direction bit */
-#define SR_1000T_LP_HD_CAPS		0x0400 /* LP is 1000T HD capable */
-#define SR_1000T_LP_FD_CAPS		0x0800 /* LP is 1000T FD capable */
-#define SR_1000T_REMOTE_RX_STATUS	0x1000 /* Remote receiver OK */
-#define SR_1000T_LOCAL_RX_STATUS	0x2000 /* Local receiver OK */
-#define SR_1000T_MS_CONFIG_RES		0x4000 /* 1=Local Tx Master, 0=Slave */
-#define SR_1000T_MS_CONFIG_FAULT	0x8000 /* Master/Slave config fault */
-
-#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT	5
-
-/* PHY 1000 MII Register/Bit Definitions */
-/* PHY Registers defined by IEEE */
-#define PHY_CONTROL		0x00 /* Control Register */
-#define PHY_STATUS		0x01 /* Status Register */
-#define PHY_ID1			0x02 /* Phy Id Reg (word 1) */
-#define PHY_ID2			0x03 /* Phy Id Reg (word 2) */
-#define PHY_AUTONEG_ADV		0x04 /* Autoneg Advertisement */
-#define PHY_LP_ABILITY		0x05 /* Link Partner Ability (Base Page) */
-#define PHY_AUTONEG_EXP		0x06 /* Autoneg Expansion Reg */
-#define PHY_NEXT_PAGE_TX	0x07 /* Next Page Tx */
-#define PHY_LP_NEXT_PAGE	0x08 /* Link Partner Next Page */
-#define PHY_1000T_CTRL		0x09 /* 1000Base-T Control Reg */
-#define PHY_1000T_STATUS	0x0A /* 1000Base-T Status Reg */
-#define PHY_EXT_STATUS		0x0F /* Extended Status Reg */
-
-#define PHY_CONTROL_LB		0x4000 /* PHY Loopback bit */
-
-/* NVM Control */
-#define E1000_EECD_SK		0x00000001 /* NVM Clock */
-#define E1000_EECD_CS		0x00000002 /* NVM Chip Select */
-#define E1000_EECD_DI		0x00000004 /* NVM Data In */
-#define E1000_EECD_DO		0x00000008 /* NVM Data Out */
-#define E1000_EECD_FWE_MASK	0x00000030
-#define E1000_EECD_FWE_DIS	0x00000010 /* Disable FLASH writes */
-#define E1000_EECD_FWE_EN	0x00000020 /* Enable FLASH writes */
-#define E1000_EECD_FWE_SHIFT	4
-#define E1000_EECD_REQ		0x00000040 /* NVM Access Request */
-#define E1000_EECD_GNT		0x00000080 /* NVM Access Grant */
-#define E1000_EECD_PRES		0x00000100 /* NVM Present */
-#define E1000_EECD_SIZE		0x00000200 /* NVM Size (0=64 word 1=256 word) */
-#define E1000_EECD_BLOCKED	0x00008000 /* Bit banging access blocked flag */
-#define E1000_EECD_ABORT	0x00010000 /* NVM operation aborted flag */
-#define E1000_EECD_TIMEOUT	0x00020000 /* NVM read operation timeout flag */
-#define E1000_EECD_ERROR_CLR	0x00040000 /* NVM error status clear bit */
-/* NVM Addressing bits based on type 0=small, 1=large */
-#define E1000_EECD_ADDR_BITS	0x00000400
-#define E1000_EECD_TYPE		0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
-#ifndef E1000_NVM_GRANT_ATTEMPTS
-#define E1000_NVM_GRANT_ATTEMPTS	1000 /* NVM # attempts to gain grant */
-#endif
-#define E1000_EECD_AUTO_RD		0x00000200  /* NVM Auto Read done */
-#define E1000_EECD_SIZE_EX_MASK		0x00007800  /* NVM Size */
-#define E1000_EECD_SIZE_EX_SHIFT	11
-#define E1000_EECD_NVADDS		0x00018000 /* NVM Address Size */
-#define E1000_EECD_SELSHAD		0x00020000 /* Select Shadow RAM */
-#define E1000_EECD_INITSRAM		0x00040000 /* Initialize Shadow RAM */
-#define E1000_EECD_FLUPD		0x00080000 /* Update FLASH */
-#define E1000_EECD_AUPDEN		0x00100000 /* Ena Auto FLASH update */
-#define E1000_EECD_SHADV		0x00200000 /* Shadow RAM Data Valid */
-#define E1000_EECD_SEC1VAL		0x00400000 /* Sector One Valid */
-#define E1000_EECD_SECVAL_SHIFT		22
-#define E1000_EECD_SEC1VAL_VALID_MASK	(E1000_EECD_AUTO_RD | E1000_EECD_PRES)
-#define E1000_EECD_FLUPD_I210		0x00800000 /* Update FLASH */
-#define E1000_EECD_FLUDONE_I210		0x04000000 /* Update FLASH done*/
-#define E1000_FLUDONE_ATTEMPTS		20000
-#define E1000_EERD_EEWR_MAX_COUNT	512 /* buffered EEPROM words rw */
-#define E1000_I210_FIFO_SEL_RX		0x00
-#define E1000_I210_FIFO_SEL_TX_QAV(_i)	(0x02 + (_i))
-#define E1000_I210_FIFO_SEL_TX_LEGACY	E1000_I210_FIFO_SEL_TX_QAV(0)
-#define E1000_I210_FIFO_SEL_BMC2OS_TX	0x06
-#define E1000_I210_FIFO_SEL_BMC2OS_RX	0x01
-
-#define E1000_NVM_SWDPIN0	0x0001 /* SWDPIN 0 NVM Value */
-#define E1000_NVM_LED_LOGIC	0x0020 /* Led Logic Word */
-#define E1000_NVM_RW_REG_DATA	16  /* Offset to data in NVM read/write regs */
-#define E1000_NVM_RW_REG_DONE	2   /* Offset to READ/WRITE done bit */
-#define E1000_NVM_RW_REG_START	1   /* Start operation */
-#define E1000_NVM_RW_ADDR_SHIFT	2   /* Shift to the address bits */
-#define E1000_NVM_POLL_WRITE	1   /* Flag for polling for write complete */
-#define E1000_NVM_POLL_READ	0   /* Flag for polling for read complete */
-#define E1000_FLASH_UPDATES	2000
-
-/* NVM Word Offsets */
-#define NVM_COMPAT			0x0003
-#define NVM_ID_LED_SETTINGS		0x0004
-#define NVM_VERSION			0x0005
-#define NVM_SERDES_AMPLITUDE		0x0006 /* SERDES output amplitude */
-#define NVM_PHY_CLASS_WORD		0x0007
-#define NVM_INIT_CONTROL1_REG		0x000A
-#define NVM_INIT_CONTROL2_REG		0x000F
-#define NVM_SWDEF_PINS_CTRL_PORT_1	0x0010
-#define NVM_INIT_CONTROL3_PORT_B	0x0014
-#define NVM_INIT_3GIO_3			0x001A
-#define NVM_SWDEF_PINS_CTRL_PORT_0	0x0020
-#define NVM_INIT_CONTROL3_PORT_A	0x0024
-#define NVM_CFG				0x0012
-#define NVM_FLASH_VERSION		0x0032
-#define NVM_ALT_MAC_ADDR_PTR		0x0037
-#define NVM_CHECKSUM_REG		0x003F
-#define NVM_COMPATIBILITY_REG_3		0x0003
-#define NVM_COMPATIBILITY_BIT_MASK	0x8000
-
-#define E1000_NVM_CFG_DONE_PORT_0	0x040000 /* MNG config cycle done */
-#define E1000_NVM_CFG_DONE_PORT_1	0x080000 /* ...for second port */
-#define E1000_NVM_CFG_DONE_PORT_2	0x100000 /* ...for third port */
-#define E1000_NVM_CFG_DONE_PORT_3	0x200000 /* ...for fourth port */
-
-#define NVM_82580_LAN_FUNC_OFFSET(a)	((a) ? (0x40 + (0x40 * (a))) : 0)
-
-/* Mask bits for fields in Word 0x24 of the NVM */
-#define NVM_WORD24_COM_MDIO		0x0008 /* MDIO interface shared */
-#define NVM_WORD24_EXT_MDIO		0x0004 /* MDIO accesses routed extrnl */
-/* Offset of Link Mode bits for 82575 up to Kawela */
-#define NVM_WORD24_LNK_MODE_OFFSET	8
-/* Offset of Link Mode bits for 82580 up */
-#define NVM_WORD24_82580_LNK_MODE_OFFSET	4
-
-
-/* Mask bits for fields in Word 0x0f of the NVM */
-#define NVM_WORD0F_PAUSE_MASK		0x3000
-#define NVM_WORD0F_PAUSE		0x1000
-#define NVM_WORD0F_ASM_DIR		0x2000
-#define NVM_WORD0F_ANE			0x0800
-#define NVM_WORD0F_SWPDIO_EXT_MASK	0x00F0
-#define NVM_WORD0F_LPLU			0x0001
-
-/* Mask bits for fields in Word 0x1a of the NVM */
-#define NVM_WORD1A_ASPM_MASK		0x000C
-
-/* Mask bits for fields in Word 0x03 of the EEPROM */
-#define NVM_COMPAT_LOM			0x0800
-
-/* length of string needed to store PBA number */
-#define E1000_PBANUM_LENGTH		11
-
-/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
-#define NVM_SUM				0xBABA
-
-#define NVM_MAC_ADDR_OFFSET		0
-#define NVM_PBA_OFFSET_0		8
-#define NVM_PBA_OFFSET_1		9
-#define NVM_PBA_PTR_GUARD		0xFAFA
-#define NVM_RESERVED_WORD		0xFFFF
-#define NVM_PHY_CLASS_A			0x8000
-#define NVM_SERDES_AMPLITUDE_MASK	0x000F
-#define NVM_SIZE_MASK			0x1C00
-#define NVM_SIZE_SHIFT			10
-#define NVM_WORD_SIZE_BASE_SHIFT	6
-#define NVM_SWDPIO_EXT_SHIFT		4
-
-/* NVM Commands - Microwire */
-#define NVM_READ_OPCODE_MICROWIRE	0x6  /* NVM read opcode */
-#define NVM_WRITE_OPCODE_MICROWIRE	0x5  /* NVM write opcode */
-#define NVM_ERASE_OPCODE_MICROWIRE	0x7  /* NVM erase opcode */
-#define NVM_EWEN_OPCODE_MICROWIRE	0x13 /* NVM erase/write enable */
-#define NVM_EWDS_OPCODE_MICROWIRE	0x10 /* NVM erase/write disable */
-
-/* NVM Commands - SPI */
-#define NVM_MAX_RETRY_SPI	5000 /* Max wait of 5ms, for RDY signal */
-#define NVM_READ_OPCODE_SPI	0x03 /* NVM read opcode */
-#define NVM_WRITE_OPCODE_SPI	0x02 /* NVM write opcode */
-#define NVM_A8_OPCODE_SPI	0x08 /* opcode bit-3 = address bit-8 */
-#define NVM_WREN_OPCODE_SPI	0x06 /* NVM set Write Enable latch */
-#define NVM_WRDI_OPCODE_SPI	0x04 /* NVM reset Write Enable latch */
-#define NVM_RDSR_OPCODE_SPI	0x05 /* NVM read Status register */
-#define NVM_WRSR_OPCODE_SPI	0x01 /* NVM write Status register */
-
-/* SPI NVM Status Register */
-#define NVM_STATUS_RDY_SPI	0x01
-#define NVM_STATUS_WEN_SPI	0x02
-#define NVM_STATUS_BP0_SPI	0x04
-#define NVM_STATUS_BP1_SPI	0x08
-#define NVM_STATUS_WPEN_SPI	0x80
-
-/* Word definitions for ID LED Settings */
-#define ID_LED_RESERVED_0000	0x0000
-#define ID_LED_RESERVED_FFFF	0xFFFF
-#define ID_LED_DEFAULT		((ID_LED_OFF1_ON2  << 12) | \
-				 (ID_LED_OFF1_OFF2 <<  8) | \
-				 (ID_LED_DEF1_DEF2 <<  4) | \
-				 (ID_LED_DEF1_DEF2))
-#define ID_LED_DEF1_DEF2	0x1
-#define ID_LED_DEF1_ON2		0x2
-#define ID_LED_DEF1_OFF2	0x3
-#define ID_LED_ON1_DEF2		0x4
-#define ID_LED_ON1_ON2		0x5
-#define ID_LED_ON1_OFF2		0x6
-#define ID_LED_OFF1_DEF2	0x7
-#define ID_LED_OFF1_ON2		0x8
-#define ID_LED_OFF1_OFF2	0x9
-
-#define IGP_ACTIVITY_LED_MASK	0xFFFFF0FF
-#define IGP_ACTIVITY_LED_ENABLE	0x0300
-#define IGP_LED3_MODE		0x07000000
-
-/* PCI/PCI-X/PCI-EX Config space */
-#define PCIX_COMMAND_REGISTER		0xE6
-#define PCIX_STATUS_REGISTER_LO		0xE8
-#define PCIX_STATUS_REGISTER_HI		0xEA
-#define PCI_HEADER_TYPE_REGISTER	0x0E
-#define PCIE_LINK_STATUS		0x12
-#define PCIE_DEVICE_CONTROL2		0x28
-
-#define PCIX_COMMAND_MMRBC_MASK		0x000C
-#define PCIX_COMMAND_MMRBC_SHIFT	0x2
-#define PCIX_STATUS_HI_MMRBC_MASK	0x0060
-#define PCIX_STATUS_HI_MMRBC_SHIFT	0x5
-#define PCIX_STATUS_HI_MMRBC_4K		0x3
-#define PCIX_STATUS_HI_MMRBC_2K		0x2
-#define PCIX_STATUS_LO_FUNC_MASK	0x7
-#define PCI_HEADER_TYPE_MULTIFUNC	0x80
-#define PCIE_LINK_WIDTH_MASK		0x3F0
-#define PCIE_LINK_WIDTH_SHIFT		4
-#define PCIE_LINK_SPEED_MASK		0x0F
-#define PCIE_LINK_SPEED_2500		0x01
-#define PCIE_LINK_SPEED_5000		0x02
-#define PCIE_DEVICE_CONTROL2_16ms	0x0005
-
-#ifndef ETH_ADDR_LEN
-#define ETH_ADDR_LEN			6
-#endif
-
-#define PHY_REVISION_MASK		0xFFFFFFF0
-#define MAX_PHY_REG_ADDRESS		0x1F  /* 5 bit address bus (0-0x1F) */
-#define MAX_PHY_MULTI_PAGE_REG		0xF
-
-/* Bit definitions for valid PHY IDs. */
-/*
- * I = Integrated
- * E = External
- */
-#define M88E1000_E_PHY_ID	0x01410C50
-#define M88E1000_I_PHY_ID	0x01410C30
-#define M88E1011_I_PHY_ID	0x01410C20
-#define IGP01E1000_I_PHY_ID	0x02A80380
-#define M88E1011_I_REV_4	0x04
-#define M88E1111_I_PHY_ID	0x01410CC0
-#define M88E1112_E_PHY_ID	0x01410C90
-#define I347AT4_E_PHY_ID	0x01410DC0
-#define M88E1340M_E_PHY_ID	0x01410DF0
-#define GG82563_E_PHY_ID	0x01410CA0
-#define IGP03E1000_E_PHY_ID	0x02A80390
-#define IFE_E_PHY_ID		0x02A80330
-#define IFE_PLUS_E_PHY_ID	0x02A80320
-#define IFE_C_E_PHY_ID		0x02A80310
-#define I82580_I_PHY_ID		0x015403A0
-#define I350_I_PHY_ID		0x015403B0
-#define I210_I_PHY_ID		0x01410C00
-#define IGP04E1000_E_PHY_ID	0x02A80391
-#define M88_VENDOR		0x0141
-
-/* M88E1000 Specific Registers */
-#define M88E1000_PHY_SPEC_CTRL		0x10  /* PHY Specific Control Reg */
-#define M88E1000_PHY_SPEC_STATUS	0x11  /* PHY Specific Status Reg */
-#define M88E1000_INT_ENABLE		0x12  /* Interrupt Enable Reg */
-#define M88E1000_INT_STATUS		0x13  /* Interrupt Status Reg */
-#define M88E1000_EXT_PHY_SPEC_CTRL	0x14  /* Extended PHY Specific Cntrl */
-#define M88E1000_RX_ERR_CNTR		0x15  /* Receive Error Counter */
-
-#define M88E1000_PHY_EXT_CTRL		0x1A  /* PHY extend control register */
-#define M88E1000_PHY_PAGE_SELECT	0x1D  /* Reg 29 for pg number setting */
-#define M88E1000_PHY_GEN_CONTROL	0x1E  /* meaning depends on reg 29 */
-#define M88E1000_PHY_VCO_REG_BIT8	0x100 /* Bits 8 & 11 are adjusted for */
-#define M88E1000_PHY_VCO_REG_BIT11	0x800 /* improved BER performance */
-
-/* M88E1000 PHY Specific Control Register */
-#define M88E1000_PSCR_JABBER_DISABLE	0x0001 /* 1=Jabber Function disabled */
-#define M88E1000_PSCR_POLARITY_REVERSAL	0x0002 /* 1=Polarity Reverse enabled */
-#define M88E1000_PSCR_SQE_TEST		0x0004 /* 1=SQE Test enabled */
-/* 1=CLK125 low, 0=CLK125 toggling */
-#define M88E1000_PSCR_CLK125_DISABLE	0x0010
-/* MDI Crossover Mode bits 6:5 Manual MDI configuration */
-#define M88E1000_PSCR_MDI_MANUAL_MODE	0x0000
-#define M88E1000_PSCR_MDIX_MANUAL_MODE	0x0020  /* Manual MDIX configuration */
-/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
-#define M88E1000_PSCR_AUTO_X_1000T	0x0040
-/* Auto crossover enabled all speeds */
-#define M88E1000_PSCR_AUTO_X_MODE	0x0060
-/*
- * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
- * 0=Normal 10BASE-T Rx Threshold
- */
-#define M88E1000_PSCR_EN_10BT_EXT_DIST	0x0080
-/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
-#define M88E1000_PSCR_MII_5BIT_ENABLE	0x0100
-#define M88E1000_PSCR_SCRAMBLER_DISABLE	0x0200 /* 1=Scrambler disable */
-#define M88E1000_PSCR_FORCE_LINK_GOOD	0x0400 /* 1=Force link good */
-#define M88E1000_PSCR_ASSERT_CRS_ON_TX	0x0800 /* 1=Assert CRS on Tx */
-
-/* M88E1000 PHY Specific Status Register */
-#define M88E1000_PSSR_JABBER		0x0001 /* 1=Jabber */
-#define M88E1000_PSSR_REV_POLARITY	0x0002 /* 1=Polarity reversed */
-#define M88E1000_PSSR_DOWNSHIFT		0x0020 /* 1=Downshifted */
-#define M88E1000_PSSR_MDIX		0x0040 /* 1=MDIX; 0=MDI */
-/*
- * 0 = <50M
- * 1 = 50-80M
- * 2 = 80-110M
- * 3 = 110-140M
- * 4 = >140M
- */
-#define M88E1000_PSSR_CABLE_LENGTH	0x0380
-#define M88E1000_PSSR_LINK		0x0400 /* 1=Link up, 0=Link down */
-#define M88E1000_PSSR_SPD_DPLX_RESOLVED	0x0800 /* 1=Speed & Duplex resolved */
-#define M88E1000_PSSR_PAGE_RCVD		0x1000 /* 1=Page received */
-#define M88E1000_PSSR_DPLX		0x2000 /* 1=Duplex 0=Half Duplex */
-#define M88E1000_PSSR_SPEED		0xC000 /* Speed, bits 14:15 */
-#define M88E1000_PSSR_10MBS		0x0000 /* 00=10Mbs */
-#define M88E1000_PSSR_100MBS		0x4000 /* 01=100Mbs */
-#define M88E1000_PSSR_1000MBS		0x8000 /* 10=1000Mbs */
-
-#define M88E1000_PSSR_CABLE_LENGTH_SHIFT	7
-
-/* M88E1000 Extended PHY Specific Control Register */
-#define M88E1000_EPSCR_FIBER_LOOPBACK	0x4000 /* 1=Fiber loopback */
-/*
- * 1 = Lost lock detect enabled.
- * Will assert lost lock and bring
- * link down if idle not seen
- * within 1ms in 1000BASE-T
- */
-#define M88E1000_EPSCR_DOWN_NO_IDLE	0x8000
-/*
- * Number of times we will attempt to autonegotiate before downshifting if we
- * are the master
- */
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK	0x0C00
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X	0x0000
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X	0x0400
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X	0x0800
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X	0x0C00
-/*
- * Number of times we will attempt to autonegotiate before downshifting if we
- * are the slave
- */
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK	0x0300
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS	0x0000
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X	0x0100
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X	0x0200
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X	0x0300
-#define M88E1000_EPSCR_TX_CLK_2_5	0x0060 /* 2.5 MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_25	0x0070 /* 25  MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_0		0x0000 /* NO  TX_CLK */
-
-/* M88E1111 Specific Registers */
-#define M88E1111_PHY_PAGE_SELECT1	0x16  /* for registers 0-28 */
-#define M88E1111_PHY_PAGE_SELECT2	0x1D  /* for registers 30-31 */
-
-/* M88E1111 page select register mask */
-#define M88E1111_PHY_PAGE_SELECT_MASK1	0xFF
-#define M88E1111_PHY_PAGE_SELECT_MASK2	0x3F
-
-/* Intel I347AT4 Registers */
-
-#define I347AT4_PCDL		0x10 /* PHY Cable Diagnostics Length */
-#define I347AT4_PCDC		0x15 /* PHY Cable Diagnostics Control */
-#define I347AT4_PAGE_SELECT	0x16
-
-/* I347AT4 Extended PHY Specific Control Register */
-
-/*
- * Number of times we will attempt to autonegotiate before downshifting if we
- * are the master
- */
-#define I347AT4_PSCR_DOWNSHIFT_ENABLE	0x0800
-#define I347AT4_PSCR_DOWNSHIFT_MASK	0x7000
-#define I347AT4_PSCR_DOWNSHIFT_1X	0x0000
-#define I347AT4_PSCR_DOWNSHIFT_2X	0x1000
-#define I347AT4_PSCR_DOWNSHIFT_3X	0x2000
-#define I347AT4_PSCR_DOWNSHIFT_4X	0x3000
-#define I347AT4_PSCR_DOWNSHIFT_5X	0x4000
-#define I347AT4_PSCR_DOWNSHIFT_6X	0x5000
-#define I347AT4_PSCR_DOWNSHIFT_7X	0x6000
-#define I347AT4_PSCR_DOWNSHIFT_8X	0x7000
-
-/* I347AT4 PHY Cable Diagnostics Control */
-#define I347AT4_PCDC_CABLE_LENGTH_UNIT	0x0400 /* 0=cm 1=meters */
-
-/* M88E1112 only registers */
-#define M88E1112_VCT_DSP_DISTANCE	0x001A
-
-/* M88EC018 Rev 2 specific DownShift settings */
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK	0x0E00
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X	0x0000
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X	0x0200
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X	0x0400
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X	0x0600
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X	0x0800
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X	0x0A00
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X	0x0C00
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X	0x0E00
-
-/*
- * Bits...
- * 15-5: page
- * 4-0: register offset
- */
-#define GG82563_PAGE_SHIFT	5
-#define GG82563_REG(page, reg)	\
-	(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
-#define GG82563_MIN_ALT_REG	30
-
-/* GG82563 Specific Registers */
-#define GG82563_PHY_SPEC_CTRL		GG82563_REG(0, 16) /* PHY Spec Cntrl */
-#define GG82563_PHY_SPEC_STATUS		GG82563_REG(0, 17) /* PHY Spec Status */
-#define GG82563_PHY_INT_ENABLE		GG82563_REG(0, 18) /* Interrupt Ena */
-#define GG82563_PHY_SPEC_STATUS_2	GG82563_REG(0, 19) /* PHY Spec Stat2 */
-#define GG82563_PHY_RX_ERR_CNTR		GG82563_REG(0, 21) /* Rx Err Counter */
-#define GG82563_PHY_PAGE_SELECT		GG82563_REG(0, 22) /* Page Select */
-#define GG82563_PHY_SPEC_CTRL_2		GG82563_REG(0, 26) /* PHY Spec Cntrl2 */
-#define GG82563_PHY_PAGE_SELECT_ALT	GG82563_REG(0, 29) /* Alt Page Select */
-/* Test Clock Control (use reg. 29 to select) */
-#define GG82563_PHY_TEST_CLK_CTRL	GG82563_REG(0, 30)
-
-/* MAC Specific Control Register */
-#define GG82563_PHY_MAC_SPEC_CTRL	GG82563_REG(2, 21)
-#define GG82563_PHY_MAC_SPEC_CTRL_2	GG82563_REG(2, 26) /* MAC Spec Ctrl 2 */
-
-#define GG82563_PHY_DSP_DISTANCE	GG82563_REG(5, 26) /* DSP Distance */
-
-/* Page 193 - Port Control Registers */
-/* Kumeran Mode Control */
-#define GG82563_PHY_KMRN_MODE_CTRL	GG82563_REG(193, 16)
-#define GG82563_PHY_PORT_RESET		GG82563_REG(193, 17) /* Port Reset */
-#define GG82563_PHY_REVISION_ID		GG82563_REG(193, 18) /* Revision ID */
-#define GG82563_PHY_DEVICE_ID		GG82563_REG(193, 19) /* Device ID */
-#define GG82563_PHY_PWR_MGMT_CTRL	GG82563_REG(193, 20) /* Pwr Mgt Ctrl */
-/* Rate Adaptation Control */
-#define GG82563_PHY_RATE_ADAPT_CTRL	GG82563_REG(193, 25)
-
-/* Page 194 - KMRN Registers */
-/* FIFO's Control/Status */
-#define GG82563_PHY_KMRN_FIFO_CTRL_STAT	GG82563_REG(194, 16)
-#define GG82563_PHY_KMRN_CTRL		GG82563_REG(194, 17) /* Control */
-#define GG82563_PHY_INBAND_CTRL		GG82563_REG(194, 18) /* Inband Ctrl */
-#define GG82563_PHY_KMRN_DIAGNOSTIC	GG82563_REG(194, 19) /* Diagnostic */
-#define GG82563_PHY_ACK_TIMEOUTS	GG82563_REG(194, 20) /* Ack Timeouts */
-#define GG82563_PHY_ADV_ABILITY		GG82563_REG(194, 21) /* Adver Ability */
-/* Link Partner Advertised Ability */
-#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY	GG82563_REG(194, 23)
-#define GG82563_PHY_ADV_NEXT_PAGE	GG82563_REG(194, 24) /* Adver Next Pg */
-/* Link Partner Advertised Next page */
-#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE	GG82563_REG(194, 25)
-#define GG82563_PHY_KMRN_MISC		GG82563_REG(194, 26) /* Misc. */
-
-/* MDI Control */
-#define E1000_MDIC_DATA_MASK	0x0000FFFF
-#define E1000_MDIC_REG_MASK	0x001F0000
-#define E1000_MDIC_REG_SHIFT	16
-#define E1000_MDIC_PHY_MASK	0x03E00000
-#define E1000_MDIC_PHY_SHIFT	21
-#define E1000_MDIC_OP_WRITE	0x04000000
-#define E1000_MDIC_OP_READ	0x08000000
-#define E1000_MDIC_READY	0x10000000
-#define E1000_MDIC_INT_EN	0x20000000
-#define E1000_MDIC_ERROR	0x40000000
-#define E1000_MDIC_DEST		0x80000000
-
-/* SerDes Control */
-#define E1000_GEN_CTL_READY		0x80000000
-#define E1000_GEN_CTL_ADDRESS_SHIFT	8
-#define E1000_GEN_POLL_TIMEOUT		640
-
-/* LinkSec register fields */
-#define E1000_LSECTXCAP_SUM_MASK	0x00FF0000
-#define E1000_LSECTXCAP_SUM_SHIFT	16
-#define E1000_LSECRXCAP_SUM_MASK	0x00FF0000
-#define E1000_LSECRXCAP_SUM_SHIFT	16
-
-#define E1000_LSECTXCTRL_EN_MASK	0x00000003
-#define E1000_LSECTXCTRL_DISABLE	0x0
-#define E1000_LSECTXCTRL_AUTH		0x1
-#define E1000_LSECTXCTRL_AUTH_ENCRYPT	0x2
-#define E1000_LSECTXCTRL_AISCI		0x00000020
-#define E1000_LSECTXCTRL_PNTHRSH_MASK	0xFFFFFF00
-#define E1000_LSECTXCTRL_RSV_MASK	0x000000D8
-
-#define E1000_LSECRXCTRL_EN_MASK	0x0000000C
-#define E1000_LSECRXCTRL_EN_SHIFT	2
-#define E1000_LSECRXCTRL_DISABLE	0x0
-#define E1000_LSECRXCTRL_CHECK		0x1
-#define E1000_LSECRXCTRL_STRICT		0x2
-#define E1000_LSECRXCTRL_DROP		0x3
-#define E1000_LSECRXCTRL_PLSH		0x00000040
-#define E1000_LSECRXCTRL_RP		0x00000080
-#define E1000_LSECRXCTRL_RSV_MASK	0xFFFFFF33
-
-/* Tx Rate-Scheduler Config fields */
-#define E1000_RTTBCNRC_RS_ENA		0x80000000
-#define E1000_RTTBCNRC_RF_DEC_MASK	0x00003FFF
-#define E1000_RTTBCNRC_RF_INT_SHIFT	14
-#define E1000_RTTBCNRC_RF_INT_MASK	\
-	(E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
-
-/* DMA Coalescing register fields */
-/* DMA Coalescing Watchdog Timer */
-#define E1000_DMACR_DMACWT_MASK		0x00003FFF
-/* DMA Coalescing Rx Threshold */
-#define E1000_DMACR_DMACTHR_MASK	0x00FF0000
-#define E1000_DMACR_DMACTHR_SHIFT	16
-/* Lx when no PCIe transactions */
-#define E1000_DMACR_DMAC_LX_MASK	0x30000000
-#define E1000_DMACR_DMAC_LX_SHIFT	28
-#define E1000_DMACR_DMAC_EN		0x80000000 /* Enable DMA Coalescing */
-
-/* DMA Coalescing Transmit Threshold */
-#define E1000_DMCTXTH_DMCTTHR_MASK	0x00000FFF
-
-#define E1000_DMCTLX_TTLX_MASK		0x00000FFF /* Time to LX request */
-
-/* Rx Traffic Rate Threshold */
-#define E1000_DMCRTRH_UTRESH_MASK	0x0007FFFF
-/* Rx packet rate in current window */
-#define E1000_DMCRTRH_LRPRCW		0x80000000
-
-/* DMA Coal Rx Traffic Current Count */
-#define E1000_DMCCNT_CCOUNT_MASK	0x01FFFFFF
-
-/* Flow ctrl Rx Threshold High val */
-#define E1000_FCRTC_RTH_COAL_MASK	0x0003FFF0
-#define E1000_FCRTC_RTH_COAL_SHIFT	4
-/* Lx power decision based on DMA coal */
-#define E1000_PCIEMISC_LX_DECISION	0x00000080
-
-#define E1000_LTRC_EEEMS_EN		0x00000005 /* Enable EEE LTR max send */
-#define E1000_RXPBS_SIZE_I210_MASK	0x0000003F /* Rx packet buffer size */
-/* Minimum time for 1000BASE-T where no data will be transmit following move out
- * of EEE LPI Tx state
- */
-#define E1000_TW_SYSTEM_1000_MASK	0x000000FF
-/* Minimum time for 100BASE-T where no data will be transmit following move out
- * of EEE LPI Tx state
- */
-#define E1000_TW_SYSTEM_100_MASK	0x0000FF00
-#define E1000_TW_SYSTEM_100_SHIFT	8
-#define E1000_LTRMINV_LTRV_MASK		0x000003FF /* LTR minimum value */
-#define E1000_LTRMAXV_LTRV_MASK		0x000003FF /* LTR maximum value */
-#define E1000_LTRMINV_SCALE_MASK	0x00001C00 /* LTR minimum scale */
-#define E1000_LTRMINV_SCALE_SHIFT	10
-/* Reg val to set scale to 1024 nsec */
-#define E1000_LTRMINV_SCALE_1024	2
-/* Reg val to set scale to 32768 nsec */
-#define E1000_LTRMINV_SCALE_32768	3
-#define E1000_LTRMAXV_SCALE_MASK	0x00001C00 /* LTR maximum scale */
-#define E1000_LTRMAXV_SCALE_SHIFT	10
-/* Reg val to set scale to 1024 nsec */
-#define E1000_LTRMAXV_SCALE_1024	2
-/* Reg val to set scale to 32768 nsec */
-#define E1000_LTRMAXV_SCALE_32768	3
-#define E1000_DOBFFCTL_OBFFTHR_MASK	0x000000FF /* OBFF threshold */
-#define E1000_DOBFFCTL_EXIT_ACT_MASK	0x01000000 /* Exit active CB */
-
-/* Proxy Filer Control */
-#define E1000_PROXYFC_D0		0x00000001 /* Enable offload in D0 */
-#define E1000_PROXYFC_EX		0x00000004 /* Directed exact proxy */
-#define E1000_PROXYFC_MC		0x00000008 /* Directed MC Proxy */
-#define E1000_PROXYFC_BC		0x00000010 /* Broadcast Proxy Enable */
-#define E1000_PROXYFC_ARP_DIRECTED	0x00000020 /* Directed ARP Proxy Ena */
-#define E1000_PROXYFC_IPV4		0x00000040 /* Directed IPv4 Enable */
-#define E1000_PROXYFC_IPV6		0x00000080 /* Directed IPv6 Enable */
-#define E1000_PROXYFC_NS		0x00000200 /* IPv4 NBRHD Solicitation */
-#define E1000_PROXYFC_ARP		0x00000800 /* ARP Request Proxy Ena */
-/* Proxy Status */
-#define E1000_PROXYS_CLEAR		0xFFFFFFFF /* Clear */
-
-/* Firmware Status */
-#define E1000_FWSTS_FWRI		0x80000000 /* FW Reset Indication */
-/* VF Control */
-#define E1000_VTCTRL_RST		0x04000000 /* Reset VF */
-
-#define E1000_STATUS_LAN_ID_MASK	0x00000000C /* Mask for Lan ID field */
-/* Lan ID bit field offset in status register */
-#define E1000_STATUS_LAN_ID_OFFSET	2
-#define E1000_VFTA_ENTRIES		128
-
-#define E1000_TQAVLC_MASK              0x3FFFFFF  /* bits [25:0] only */
-#define E1000_TQAVCC_IDLESLOPE_MASK    0x7FFF     /* Idle slope for given queue */
-#define E1000_TQAVCC_LINKRATE          30517      /* 50% allocation to Class A */
-#define E1000_TQAVCC_KEEP_CREDITS      0x40000000 /* keep credits for deferred packets */
-#define E1000_TQAVCC_QUEUEMODE         0x80000000 /* queue mode, 0=strict, 1=SR mode */
-
-#define E1000_DTXFETCH_CURRPKT_FETCH   0x000FFFFF /* fetch time of current packet */
-#define E1000_DTXFETCH_CURRPKT_ADDR    0xFFF00000 /* LSB of the packet fetch address */
-
-#define E1000_TQAVCTRL_TXMODE          0x00000001 /* Transmit mode, 0=legacy, 1=QAV */
-#define E1000_TQAVCTRL_1588_STAT_EN    0x00000004 /* report DMA time of tx packets */
-#define E1000_TQAVCTRL_FETCH_ARB       0x00000010 /* data fetch arbitration */
-#define E1000_TQAVCTRL_FETCH_TM_VALID  0x00000020 /* data fetch time valid */
-#define E1000_TQAVCTRL_TX_ARB          0x00000100 /* data transmit arbitration */
-#define E1000_TQAVCTRL_LAUNCH_VALID    0x00000200 /* data launch time valid */
-#define E1000_TQAVCTRL_SP_WAIT_SR      0x00000400 /* stall SP to guarantee SR */
-#define E1000_TQAVCTRL_FETCH_TM_MASK   0xFFFF0000 /* fetch time delta offset from launch */
-#define E1000_TQAVCTRL_FETCH_TM_SHIFT  (16)       /* ... and associated shift value */
-
-/*
- *  * example usage:
- *   * E1000_TQAVARBCTRL_TXPRIO(0,3) sets queue0 to priority=3 (highest)
- *    */
-#define E1000_TQAVARBCTRL_TXQPRIO(_q, _n)  (((_n) & 0x3) << (_q << 2))  /* queue priority */
-
-#define E1000_QAV_LAUNCHTIME_EPOCH    0x3B9AC9FF /* nsec rollover 999,999,999 in decimal */
-
-
-#define E1000_TSAUXC_SAMP_AUTO		0x00000008 /* sample current ts */
-
-#endif /* _E1000_DEFINES_H_ */
diff --git a/lib/igb/e1000_hw.h b/lib/igb/e1000_hw.h
deleted file mode 100644
index 1732d502..00000000
--- a/lib/igb/e1000_hw.h
+++ /dev/null
@@ -1,273 +0,0 @@
-/******************************************************************************
-
-  Copyright (c) 2001-2015, Intel Corporation
-  All rights reserved.
-
-  Redistribution and use in source and binary forms, with or without
-  modification, are permitted provided that the following conditions are met:
-
-   1. Redistributions of source code must retain the above copyright notice,
-      this list of conditions and the following disclaimer.
-
-   2. Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-
-   3. Neither the name of the Intel Corporation nor the names of its
-      contributors may be used to endorse or promote products derived from
-      this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE.
-
-******************************************************************************/
-/*$FreeBSD$*/
-
-#ifndef _E1000_HW_H_
-#define _E1000_HW_H_
-
-#include "e1000_osdep.h"
-#include "e1000_regs.h"
-#include "e1000_defines.h"
-
-struct e1000_hw;
-
-#define E1000_DEV_ID_82576			0x10C9
-#define E1000_DEV_ID_82576_FIBER		0x10E6
-#define E1000_DEV_ID_82576_SERDES		0x10E7
-#define E1000_DEV_ID_82576_QUAD_COPPER		0x10E8
-#define E1000_DEV_ID_82576_QUAD_COPPER_ET2	0x1526
-#define E1000_DEV_ID_82576_NS			0x150A
-#define E1000_DEV_ID_82576_NS_SERDES		0x1518
-#define E1000_DEV_ID_82576_SERDES_QUAD		0x150D
-#define E1000_DEV_ID_82576_VF			0x10CA
-#define E1000_DEV_ID_I350_VF			0x1520
-#define E1000_DEV_ID_82575EB_COPPER		0x10A7
-#define E1000_DEV_ID_82575EB_FIBER_SERDES	0x10A9
-#define E1000_DEV_ID_82575GB_QUAD_COPPER	0x10D6
-#define E1000_DEV_ID_82580_COPPER		0x150E
-#define E1000_DEV_ID_82580_FIBER		0x150F
-#define E1000_DEV_ID_82580_SERDES		0x1510
-#define E1000_DEV_ID_82580_SGMII		0x1511
-#define E1000_DEV_ID_82580_COPPER_DUAL		0x1516
-#define E1000_DEV_ID_82580_QUAD_FIBER		0x1527
-#define E1000_DEV_ID_I350_COPPER		0x1521
-#define E1000_DEV_ID_I350_FIBER			0x1522
-#define E1000_DEV_ID_I350_SERDES		0x1523
-#define E1000_DEV_ID_I350_SGMII			0x1524
-#define E1000_DEV_ID_I350_DA4			0x1546
-#define E1000_DEV_ID_I210_COPPER		0x1533
-#define E1000_DEV_ID_I210_COPPER_OEM1		0x1534
-#define E1000_DEV_ID_I210_COPPER_IT		0x1535
-#define E1000_DEV_ID_I210_FIBER			0x1536
-#define E1000_DEV_ID_I210_SERDES		0x1537
-#define E1000_DEV_ID_I210_SGMII			0x1538
-#define E1000_DEV_ID_I210_AUTOMOTIVE		0x15F6
-#define E1000_DEV_ID_I210_COPPER_FLASHLESS	0x157B
-#define E1000_DEV_ID_I210_SERDES_FLASHLESS	0x157C
-#define E1000_DEV_ID_I211_COPPER		0x1539
-#define E1000_DEV_ID_DH89XXCC_SGMII		0x0438
-#define E1000_DEV_ID_DH89XXCC_SERDES		0x043A
-#define E1000_DEV_ID_DH89XXCC_BACKPLANE		0x043C
-#define E1000_DEV_ID_DH89XXCC_SFP		0x0440
-
-#define E1000_REVISION_0	0
-#define E1000_REVISION_1	1
-#define E1000_REVISION_2	2
-#define E1000_REVISION_3	3
-#define E1000_REVISION_4	4
-
-#define E1000_FUNC_0		0
-#define E1000_FUNC_1		1
-#define E1000_FUNC_2		2
-#define E1000_FUNC_3		3
-
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0	0
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1	3
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2	6
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3	9
-
-enum e1000_mac_type {
-	e1000_undefined = 0,
-	e1000_82575,
-	e1000_82576,
-	e1000_82580,
-	e1000_i350,
-	e1000_i210,
-	e1000_i211,
-	e1000_vfadapt,
-	e1000_vfadapt_i350,
-	e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
-};
-
-#define __le16 u16
-#define __le32 u32
-#define __le64 u64
-/* Receive Descriptor */
-struct e1000_rx_desc {
-	__le64 buffer_addr; /* Address of the descriptor's data buffer */
-	__le16 length;      /* Length of data DMAed into data buffer */
-	__le16 csum; /* Packet checksum */
-	u8  status;  /* Descriptor status */
-	u8  errors;  /* Descriptor Errors */
-	__le16 special;
-};
-
-/* Receive Descriptor - Extended */
-union e1000_rx_desc_extended {
-	struct {
-		__le64 buffer_addr;
-		__le64 reserved;
-	} read;
-	struct {
-		struct {
-			__le32 mrq; /* Multiple Rx Queues */
-			union {
-				__le32 rss; /* RSS Hash */
-				struct {
-					__le16 ip_id;  /* IP id */
-					__le16 csum;   /* Packet Checksum */
-				} csum_ip;
-			} hi_dword;
-		} lower;
-		struct {
-			__le32 status_error;  /* ext status/error */
-			__le16 length;
-			__le16 vlan; /* VLAN tag */
-		} upper;
-	} wb;  /* writeback */
-};
-
-#define MAX_PS_BUFFERS 4
-/* Receive Descriptor - Packet Split */
-union e1000_rx_desc_packet_split {
-	struct {
-		/* one buffer for protocol header(s), three data buffers */
-		__le64 buffer_addr[MAX_PS_BUFFERS];
-	} read;
-	struct {
-		struct {
-			__le32 mrq;  /* Multiple Rx Queues */
-			union {
-				__le32 rss; /* RSS Hash */
-				struct {
-					__le16 ip_id;    /* IP id */
-					__le16 csum;     /* Packet Checksum */
-				} csum_ip;
-			} hi_dword;
-		} lower;
-		struct {
-			__le32 status_error;  /* ext status/error */
-			__le16 length0;  /* length of buffer 0 */
-			__le16 vlan;  /* VLAN tag */
-		} middle;
-		struct {
-			__le16 header_status;
-			__le16 length[3];     /* length of buffers 1-3 */
-		} upper;
-		__le64 reserved;
-	} wb; /* writeback */
-};
-
-/* Transmit Descriptor */
-struct e1000_tx_desc {
-	__le64 buffer_addr;   /* Address of the descriptor's data buffer */
-	union {
-		__le32 data;
-		struct {
-			__le16 length;  /* Data buffer length */
-			u8 cso;  /* Checksum offset */
-			u8 cmd;  /* Descriptor control */
-		} flags;
-	} lower;
-	union {
-		__le32 data;
-		struct {
-			u8 status; /* Descriptor status */
-			u8 css;  /* Checksum start */
-			__le16 special;
-		} fields;
-	} upper;
-};
-
-/* Offload Context Descriptor */
-struct e1000_context_desc {
-	union {
-		__le32 ip_config;
-		struct {
-			u8 ipcss;  /* IP checksum start */
-			u8 ipcso;  /* IP checksum offset */
-			__le16 ipcse;  /* IP checksum end */
-		} ip_fields;
-	} lower_setup;
-	union {
-		__le32 tcp_config;
-		struct {
-			u8 tucss;  /* TCP checksum start */
-			u8 tucso;  /* TCP checksum offset */
-			__le16 tucse;  /* TCP checksum end */
-		} tcp_fields;
-	} upper_setup;
-	__le32 cmd_and_length;
-	union {
-		__le32 data;
-		struct {
-			u8 status;  /* Descriptor status */
-			u8 hdr_len;  /* Header length */
-			__le16 mss;  /* Maximum segment size */
-		} fields;
-	} tcp_seg_setup;
-};
-
-/* Offload data descriptor */
-struct e1000_data_desc {
-	__le64 buffer_addr;  /* Address of the descriptor's buffer address */
-	union {
-		__le32 data;
-		struct {
-			__le16 length;  /* Data buffer length */
-			u8 typ_len_ext;
-			u8 cmd;
-		} flags;
-	} lower;
-	union {
-		__le32 data;
-		struct {
-			u8 status;  /* Descriptor status */
-			u8 popts;  /* Packet Options */
-			__le16 special;
-		} fields;
-	} upper;
-};
-
-struct e1000_mac_info {
-	u8 addr[ETH_ADDR_LEN];
-	u8 perm_addr[ETH_ADDR_LEN];
-	enum e1000_mac_type type;
-
-};
-
-struct e1000_hw {
-	void *back;
-
-	u8 *hw_addr;
-
-	struct e1000_mac_info  mac;
-	u16 device_id;
-	u16 subsystem_vendor_id;
-	u16 subsystem_device_id;
-	u16 vendor_id;
-
-	u8  revision_id;
-};
-
-#endif
diff --git a/lib/igb/e1000_osdep.h b/lib/igb/e1000_osdep.h
deleted file mode 100644
index 08600ee6..00000000
--- a/lib/igb/e1000_osdep.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/******************************************************************************
-
-  Copyright (c) 2001-2016, Intel Corporation
-  All rights reserved.
-
-  Redistribution and use in source and binary forms, with or without
-  modification, are permitted provided that the following conditions are met:
-
-   1. Redistributions of source code must retain the above copyright notice,
-      this list of conditions and the following disclaimer.
-
-   2. Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-
-   3. Neither the name of the Intel Corporation nor the names of its
-      contributors may be used to endorse or promote products derived from
-      this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE.
-
-******************************************************************************/
-
-#ifndef _OSDEP_H_
-#define _OSDEP_H_
-
-/* generic boolean compatibility */
-#undef TRUE
-#undef FALSE
-#define TRUE true
-#define FALSE false
-#define _Bool char
-#ifndef bool
-#define bool _Bool
-#define true 1
-#define false 0
-#endif
-
-typedef u_int64_t	u64;
-typedef u_int32_t	u32;
-typedef u_int16_t	u16;
-typedef u_int8_t		u8;
-typedef int64_t		s64;
-typedef int32_t		s32;
-typedef int16_t		s16;
-typedef int8_t		s8;
-
-#define __le16		u16
-#define __le32		u32
-#define __le64		u64
-
-#define mb()
-#define rmb()
-#define wmb()
-#define prefetch(x)
-
-#define E1000_REGISTER(hw, reg) reg
-
-#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
-
-/* Register READ/WRITE macros */
-
-#define E1000_READ_REG(hw, reg) \
-	(*(u32 *)(((hw)->hw_addr + reg)))
-
-#define E1000_WRITE_REG(hw, reg, value) \
-	(*(u32 *)(((hw)->hw_addr + reg)) = value)
-
-#define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \
-	E1000_WRITE_REG((hw), (reg) + ((index) << 2), (value))
-
-#endif  /* _OSDEP_H_ */
-
diff --git a/lib/igb/e1000_regs.h b/lib/igb/e1000_regs.h
deleted file mode 100644
index ab171165..00000000
--- a/lib/igb/e1000_regs.h
+++ /dev/null
@@ -1,637 +0,0 @@
-/******************************************************************************
-
-  Copyright (c) 2001-2012, Intel Corporation
-  All rights reserved.
-
-  Redistribution and use in source and binary forms, with or without
-  modification, are permitted provided that the following conditions are met:
-
-   1. Redistributions of source code must retain the above copyright notice,
-      this list of conditions and the following disclaimer.
-
-   2. Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-
-   3. Neither the name of the Intel Corporation nor the names of its
-      contributors may be used to endorse or promote products derived from
-      this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE.
-
-******************************************************************************/
-/*$FreeBSD$*/
-
-#ifndef _E1000_REGS_H_
-#define _E1000_REGS_H_
-
-#define E1000_CTRL	0x00000  /* Device Control - RW */
-#define E1000_CTRL_DUP	0x00004  /* Device Control Duplicate (Shadow) - RW */
-#define E1000_STATUS	0x00008  /* Device Status - RO */
-#define E1000_EECD	0x00010  /* EEPROM/Flash Control - RW */
-#define E1000_EERD	0x00014  /* EEPROM Read - RW */
-#define E1000_CTRL_EXT	0x00018  /* Extended Device Control - RW */
-#define E1000_FLA	0x0001C  /* Flash Access - RW */
-#define E1000_MDIC	0x00020  /* MDI Control - RW */
-#define E1000_MDICNFG	0x00E04  /* MDI Config - RW */
-#define E1000_REGISTER_SET_SIZE		0x20000 /* CSR Size */
-#define E1000_EEPROM_INIT_CTRL_WORD_2	0x0F /* EEPROM Init Ctrl Word 2 */
-#define E1000_EEPROM_PCIE_CTRL_WORD_2	0x28 /* EEPROM PCIe Ctrl Word 2 */
-#define E1000_BARCTRL			0x5BBC /* BAR ctrl reg */
-#define E1000_BARCTRL_FLSIZE		0x0700 /* BAR ctrl Flsize */
-#define E1000_BARCTRL_CSRSIZE		0x2000 /* BAR ctrl CSR size */
-#define E1000_I350_BARCTRL		0x5BFC /* BAR ctrl reg */
-#define E1000_SCTL	0x00024  /* SerDes Control - RW */
-#define E1000_FCAL	0x00028  /* Flow Control Address Low - RW */
-#define E1000_FCAH	0x0002C  /* Flow Control Address High -RW */
-#define E1000_FEXT	0x0002C  /* Future Extended - RW */
-#define E1000_FEXTNVM4	0x00024  /* Future Extended NVM 4 - RW */
-#define E1000_FEXTNVM	0x00028  /* Future Extended NVM - RW */
-#define E1000_FCT	0x00030  /* Flow Control Type - RW */
-#define E1000_CONNSW	0x00034  /* Copper/Fiber switch control - RW */
-#define E1000_VET	0x00038  /* VLAN Ether Type - RW */
-#define E1000_ICR	0x000C0  /* Interrupt Cause Read - R/clr */
-#define E1000_ITR	0x000C4  /* Interrupt Throttling Rate - RW */
-#define E1000_ICS	0x000C8  /* Interrupt Cause Set - WO */
-#define E1000_IMS	0x000D0  /* Interrupt Mask Set - RW */
-#define E1000_IMC	0x000D8  /* Interrupt Mask Clear - WO */
-#define E1000_IAM	0x000E0  /* Interrupt Acknowledge Auto Mask */
-#define E1000_RCTL	0x00100  /* Rx Control - RW */
-#define E1000_FCTTV	0x00170  /* Flow Control Transmit Timer Value - RW */
-#define E1000_TXCW	0x00178  /* Tx Configuration Word - RW */
-#define E1000_RXCW	0x00180  /* Rx Configuration Word - RO */
-#define E1000_EICR	0x01580  /* Ext. Interrupt Cause Read - R/clr */
-#define E1000_EITR(_n)	(0x01680 + (0x4 * (_n)))
-#define E1000_EICS	0x01520  /* Ext. Interrupt Cause Set - W0 */
-#define E1000_EIMS	0x01524  /* Ext. Interrupt Mask Set/Read - RW */
-#define E1000_EIMC	0x01528  /* Ext. Interrupt Mask Clear - WO */
-#define E1000_EIAC	0x0152C  /* Ext. Interrupt Auto Clear - RW */
-#define E1000_EIAM	0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
-#define E1000_GPIE	0x01514  /* General Purpose Interrupt Enable - RW */
-#define E1000_IVAR0	0x01700  /* Interrupt Vector Allocation (array) - RW */
-#define E1000_IVAR_MISC	0x01740 /* IVAR for "other" causes - RW */
-#define E1000_TCTL	0x00400  /* Tx Control - RW */
-#define E1000_TCTL_EXT	0x00404  /* Extended Tx Control - RW */
-#define E1000_TIPG	0x00410  /* Tx Inter-packet gap -RW */
-#define E1000_TBT	0x00448  /* Tx Burst Timer - RW */
-#define E1000_AIT	0x00458  /* Adaptive Interframe Spacing Throttle - RW */
-#define E1000_LEDCTL	0x00E00  /* LED Control - RW */
-#define E1000_EXTCNF_CTRL	0x00F00  /* Extended Configuration Control */
-#define E1000_EXTCNF_SIZE	0x00F08  /* Extended Configuration Size */
-#define E1000_PHY_CTRL	0x00F10  /* PHY Control Register in CSR */
-#define E1000_PBA	0x01000  /* Packet Buffer Allocation - RW */
-#define E1000_PBS	0x01008  /* Packet Buffer Size */
-#define E1000_EEMNGCTL	0x01010  /* MNG EEprom Control */
-#define E1000_EEARBC	0x01024  /* EEPROM Auto Read Bus Control */
-#define E1000_FLASHT	0x01028  /* FLASH Timer Register */
-#define E1000_EEWR	0x0102C  /* EEPROM Write Register - RW */
-#define E1000_FLSWCTL	0x01030  /* FLASH control register */
-#define E1000_FLSWDATA	0x01034  /* FLASH data register */
-#define E1000_FLSWCNT	0x01038  /* FLASH Access Counter */
-#define E1000_FLOP	0x0103C  /* FLASH Opcode Register */
-#define E1000_I2CCMD	0x01028  /* SFPI2C Command Register - RW */
-#define E1000_I2CPARAMS	0x0102C /* SFPI2C Parameters Register - RW */
-#define E1000_I2CBB_EN	0x00000100  /* I2C - Bit Bang Enable */
-#define E1000_I2C_CLK_OUT	0x00000200  /* I2C- Clock */
-#define E1000_I2C_DATA_OUT	0x00000400  /* I2C- Data Out */
-#define E1000_I2C_DATA_OE_N	0x00000800  /* I2C- Data Output Enable */
-#define E1000_I2C_DATA_IN	0x00001000  /* I2C- Data In */
-#define E1000_I2C_CLK_OE_N	0x00002000  /* I2C- Clock Output Enable */
-#define E1000_I2C_CLK_IN	0x00004000  /* I2C- Clock In */
-#define E1000_I2C_CLK_STRETCH_DIS	0x00008000 /* I2C- Dis Clk Stretching */
-#define E1000_WDSTP	0x01040  /* Watchdog Setup - RW */
-#define E1000_SWDSTS	0x01044  /* SW Device Status - RW */
-#define E1000_FRTIMER	0x01048  /* Free Running Timer - RW */
-#define E1000_TCPTIMER	0x0104C  /* TCP Timer - RW */
-#define E1000_VPDDIAG	0x01060  /* VPD Diagnostic - RO */
-#define E1000_ICR_V2	0x01500  /* Intr Cause - new location - RC */
-#define E1000_ICS_V2	0x01504  /* Intr Cause Set - new location - WO */
-#define E1000_IMS_V2	0x01508  /* Intr Mask Set/Read - new location - RW */
-#define E1000_IMC_V2	0x0150C  /* Intr Mask Clear - new location - WO */
-#define E1000_IAM_V2	0x01510  /* Intr Ack Auto Mask - new location - RW */
-#define E1000_ERT	0x02008  /* Early Rx Threshold - RW */
-#define E1000_FCRTL	0x02160  /* Flow Control Receive Threshold Low - RW */
-#define E1000_FCRTH	0x02168  /* Flow Control Receive Threshold High - RW */
-#define E1000_PSRCTL	0x02170  /* Packet Split Receive Control - RW */
-#define E1000_RDFPCQ(_n)	(0x02430 + (0x4 * (_n)))
-#define E1000_PBRTH	0x02458  /* PB Rx Arbitration Threshold - RW */
-#define E1000_FCRTV	0x02460  /* Flow Control Refresh Timer Value - RW */
-/* Split and Replication Rx Control - RW */
-#define E1000_RDPUMB	0x025CC  /* DMA Rx Descriptor uC Mailbox - RW */
-#define E1000_RDPUAD	0x025D0  /* DMA Rx Descriptor uC Addr Command - RW */
-#define E1000_RDPUWD	0x025D4  /* DMA Rx Descriptor uC Data Write - RW */
-#define E1000_RDPURD	0x025D8  /* DMA Rx Descriptor uC Data Read - RW */
-#define E1000_RDPUCTL	0x025DC  /* DMA Rx Descriptor uC Control - RW */
-#define E1000_PBDIAG	0x02458  /* Packet Buffer Diagnostic - RW */
-#define E1000_RXPBS	0x02404  /* Rx Packet Buffer Size - RW */
-#define E1000_IRPBS	0x02404 /* Same as RXPBS, renamed for newer Si - RW */
-#define E1000_PBRWAC	0x024E8 /* Rx packet buffer wrap around counter - RO */
-#define E1000_RDTR	0x02820  /* Rx Delay Timer - RW */
-#define E1000_RADV	0x0282C  /* Rx Interrupt Absolute Delay Timer - RW */
-#define E1000_SRWR		0x12018  /* Shadow Ram Write Register - RW */
-#define E1000_I210_FLMNGCTL	0x12038
-#define E1000_I210_FLMNGDATA	0x1203C
-#define E1000_I210_FLMNGCNT	0x12040
-
-#define E1000_I210_FLSWCTL	0x12048
-#define E1000_I210_FLSWDATA	0x1204C
-#define E1000_I210_FLSWCNT	0x12050
-
-#define E1000_I210_FLA		0x1201C
-
-#define E1000_INVM_DATA_REG(_n)	(0x12120 + 4*(_n))
-#define E1000_INVM_SIZE		64 /* Number of INVM Data Registers */
-
-/*
- * Convenience macros
- *
- * Note: "_n" is the queue number of the register to be written to.
- *
- * Example usage:
- * E1000_RDBAL_REG(current_rx_queue)
- */
-#define E1000_RDBAL(_n)	((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
-			 (0x0C000 + ((_n) * 0x40)))
-#define E1000_RDBAH(_n)	((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
-			 (0x0C004 + ((_n) * 0x40)))
-#define E1000_RDLEN(_n)	((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
-			 (0x0C008 + ((_n) * 0x40)))
-#define E1000_SRRCTL(_n)	((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
-				 (0x0C00C + ((_n) * 0x40)))
-#define E1000_RDH(_n)	((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
-			 (0x0C010 + ((_n) * 0x40)))
-#define E1000_RXCTL(_n)	((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \
-			 (0x0C014 + ((_n) * 0x40)))
-#define E1000_DCA_RXCTRL(_n)	E1000_RXCTL(_n)
-#define E1000_RDT(_n)	((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
-			 (0x0C018 + ((_n) * 0x40)))
-#define E1000_RXDCTL(_n)	((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
-				 (0x0C028 + ((_n) * 0x40)))
-#define E1000_RQDPC(_n)	((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \
-			 (0x0C030 + ((_n) * 0x40)))
-#define E1000_TDBAL(_n)	((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
-			 (0x0E000 + ((_n) * 0x40)))
-#define E1000_TDBAH(_n)	((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
-			 (0x0E004 + ((_n) * 0x40)))
-#define E1000_TDLEN(_n)	((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
-			 (0x0E008 + ((_n) * 0x40)))
-#define E1000_TDH(_n)	((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
-			 (0x0E010 + ((_n) * 0x40)))
-#define E1000_TXCTL(_n)	((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \
-			 (0x0E014 + ((_n) * 0x40)))
-#define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n)
-#define E1000_TDT(_n)	((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
-			 (0x0E018 + ((_n) * 0x40)))
-#define E1000_TXDCTL(_n)	((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
-				 (0x0E028 + ((_n) * 0x40)))
-#define E1000_TDWBAL(_n)	((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \
-				 (0x0E038 + ((_n) * 0x40)))
-#define E1000_TDWBAH(_n)	((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \
-				 (0x0E03C + ((_n) * 0x40)))
-#define E1000_TARC(_n)		(0x03840 + ((_n) * 0x100))
-#define E1000_RSRPD		0x02C00  /* Rx Small Packet Detect - RW */
-#define E1000_RAID		0x02C08  /* Receive Ack Interrupt Delay - RW */
-#define E1000_TXDMAC		0x03000  /* Tx DMA Control - RW */
-#define E1000_KABGTXD		0x03004  /* AFE Band Gap Transmit Ref Data */
-#define E1000_PSRTYPE(_i)	(0x05480 + ((_i) * 4))
-#define E1000_RAL(_i)		(((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
-				 (0x054E0 + ((_i - 16) * 8)))
-#define E1000_RAH(_i)		(((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
-				 (0x054E4 + ((_i - 16) * 8)))
-#define E1000_SHRAL(_i)		(0x05438 + ((_i) * 8))
-#define E1000_SHRAH(_i)		(0x0543C + ((_i) * 8))
-#define E1000_IP4AT_REG(_i)	(0x05840 + ((_i) * 8))
-#define E1000_IP6AT_REG(_i)	(0x05880 + ((_i) * 4))
-#define E1000_WUPM_REG(_i)	(0x05A00 + ((_i) * 4))
-#define E1000_FFMT_REG(_i)	(0x09000 + ((_i) * 8))
-#define E1000_FFVT_REG(_i)	(0x09800 + ((_i) * 8))
-#define E1000_FFLT_REG(_i)	(0x05F00 + ((_i) * 8))
-#define E1000_PBSLAC		0x03100  /* Pkt Buffer Slave Access Control */
-#define E1000_PBSLAD(_n)	(0x03110 + (0x4 * (_n)))  /* Pkt Buffer DWORD */
-#define E1000_TXPBS		0x03404  /* Tx Packet Buffer Size - RW */
-/* Same as TXPBS, renamed for newer Si - RW */
-#define E1000_ITPBS		0x03404
-#define E1000_TDFH		0x03410  /* Tx Data FIFO Head - RW */
-#define E1000_TDFT		0x03418  /* Tx Data FIFO Tail - RW */
-#define E1000_TDFHS		0x03420  /* Tx Data FIFO Head Saved - RW */
-#define E1000_TDFTS		0x03428  /* Tx Data FIFO Tail Saved - RW */
-#define E1000_TDFPC		0x03430  /* Tx Data FIFO Packet Count - RW */
-#define E1000_TDPUMB		0x0357C  /* DMA Tx Desc uC Mail Box - RW */
-#define E1000_TDPUAD		0x03580  /* DMA Tx Desc uC Addr Command - RW */
-#define E1000_TDPUWD		0x03584  /* DMA Tx Desc uC Data Write - RW */
-#define E1000_TDPURD		0x03588  /* DMA Tx Desc uC Data  Read  - RW */
-#define E1000_TDPUCTL		0x0358C  /* DMA Tx Desc uC Control - RW */
-#define E1000_DTXCTL		0x03590  /* DMA Tx Control - RW */
-#define E1000_DTXTCPFLGL	0x0359C /* DMA Tx Control flag low - RW */
-#define E1000_DTXTCPFLGH	0x035A0 /* DMA Tx Control flag high - RW */
-/* DMA Tx Max Total Allow Size Reqs - RW */
-#define E1000_DTXMXSZRQ		0x03540
-#define E1000_TIDV	0x03820  /* Tx Interrupt Delay Value - RW */
-#define E1000_TADV	0x0382C  /* Tx Interrupt Absolute Delay Val - RW */
-#define E1000_TSPMT	0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
-#define E1000_CRCERRS	0x04000  /* CRC Error Count - R/clr */
-#define E1000_ALGNERRC	0x04004  /* Alignment Error Count - R/clr */
-#define E1000_SYMERRS	0x04008  /* Symbol Error Count - R/clr */
-#define E1000_RXERRC	0x0400C  /* Receive Error Count - R/clr */
-#define E1000_MPC	0x04010  /* Missed Packet Count - R/clr */
-#define E1000_SCC	0x04014  /* Single Collision Count - R/clr */
-#define E1000_ECOL	0x04018  /* Excessive Collision Count - R/clr */
-#define E1000_MCC	0x0401C  /* Multiple Collision Count - R/clr */
-#define E1000_LATECOL	0x04020  /* Late Collision Count - R/clr */
-#define E1000_COLC	0x04028  /* Collision Count - R/clr */
-#define E1000_DC	0x04030  /* Defer Count - R/clr */
-#define E1000_TNCRS	0x04034  /* Tx-No CRS - R/clr */
-#define E1000_SEC	0x04038  /* Sequence Error Count - R/clr */
-#define E1000_CEXTERR	0x0403C  /* Carrier Extension Error Count - R/clr */
-#define E1000_RLEC	0x04040  /* Receive Length Error Count - R/clr */
-#define E1000_XONRXC	0x04048  /* XON Rx Count - R/clr */
-#define E1000_XONTXC	0x0404C  /* XON Tx Count - R/clr */
-#define E1000_XOFFRXC	0x04050  /* XOFF Rx Count - R/clr */
-#define E1000_XOFFTXC	0x04054  /* XOFF Tx Count - R/clr */
-#define E1000_FCRUC	0x04058  /* Flow Control Rx Unsupported Count- R/clr */
-#define E1000_PRC64	0x0405C  /* Packets Rx (64 bytes) - R/clr */
-#define E1000_PRC127	0x04060  /* Packets Rx (65-127 bytes) - R/clr */
-#define E1000_PRC255	0x04064  /* Packets Rx (128-255 bytes) - R/clr */
-#define E1000_PRC511	0x04068  /* Packets Rx (255-511 bytes) - R/clr */
-#define E1000_PRC1023	0x0406C  /* Packets Rx (512-1023 bytes) - R/clr */
-#define E1000_PRC1522	0x04070  /* Packets Rx (1024-1522 bytes) - R/clr */
-#define E1000_GPRC	0x04074  /* Good Packets Rx Count - R/clr */
-#define E1000_BPRC	0x04078  /* Broadcast Packets Rx Count - R/clr */
-#define E1000_MPRC	0x0407C  /* Multicast Packets Rx Count - R/clr */
-#define E1000_GPTC	0x04080  /* Good Packets Tx Count - R/clr */
-#define E1000_GORCL	0x04088  /* Good Octets Rx Count Low - R/clr */
-#define E1000_GORCH	0x0408C  /* Good Octets Rx Count High - R/clr */
-#define E1000_GOTCL	0x04090  /* Good Octets Tx Count Low - R/clr */
-#define E1000_GOTCH	0x04094  /* Good Octets Tx Count High - R/clr */
-#define E1000_RNBC	0x040A0  /* Rx No Buffers Count - R/clr */
-#define E1000_RUC	0x040A4  /* Rx Undersize Count - R/clr */
-#define E1000_RFC	0x040A8  /* Rx Fragment Count - R/clr */
-#define E1000_ROC	0x040AC  /* Rx Oversize Count - R/clr */
-#define E1000_RJC	0x040B0  /* Rx Jabber Count - R/clr */
-#define E1000_MGTPRC	0x040B4  /* Management Packets Rx Count - R/clr */
-#define E1000_MGTPDC	0x040B8  /* Management Packets Dropped Count - R/clr */
-#define E1000_MGTPTC	0x040BC  /* Management Packets Tx Count - R/clr */
-#define E1000_TORL	0x040C0  /* Total Octets Rx Low - R/clr */
-#define E1000_TORH	0x040C4  /* Total Octets Rx High - R/clr */
-#define E1000_TOTL	0x040C8  /* Total Octets Tx Low - R/clr */
-#define E1000_TOTH	0x040CC  /* Total Octets Tx High - R/clr */
-#define E1000_TPR	0x040D0  /* Total Packets Rx - R/clr */
-#define E1000_TPT	0x040D4  /* Total Packets Tx - R/clr */
-#define E1000_PTC64	0x040D8  /* Packets Tx (64 bytes) - R/clr */
-#define E1000_PTC127	0x040DC  /* Packets Tx (65-127 bytes) - R/clr */
-#define E1000_PTC255	0x040E0  /* Packets Tx (128-255 bytes) - R/clr */
-#define E1000_PTC511	0x040E4  /* Packets Tx (256-511 bytes) - R/clr */
-#define E1000_PTC1023	0x040E8  /* Packets Tx (512-1023 bytes) - R/clr */
-#define E1000_PTC1522	0x040EC  /* Packets Tx (1024-1522 Bytes) - R/clr */
-#define E1000_MPTC	0x040F0  /* Multicast Packets Tx Count - R/clr */
-#define E1000_BPTC	0x040F4  /* Broadcast Packets Tx Count - R/clr */
-#define E1000_TSCTC	0x040F8  /* TCP Segmentation Context Tx - R/clr */
-#define E1000_TSCTFC	0x040FC  /* TCP Segmentation Context Tx Fail - R/clr */
-#define E1000_IAC	0x04100  /* Interrupt Assertion Count */
-#define E1000_ICRXPTC	0x04104  /* Interrupt Cause Rx Pkt Timer Expire Count */
-#define E1000_ICRXATC	0x04108  /* Interrupt Cause Rx Abs Timer Expire Count */
-#define E1000_ICTXPTC	0x0410C  /* Interrupt Cause Tx Pkt Timer Expire Count */
-#define E1000_ICTXATC	0x04110  /* Interrupt Cause Tx Abs Timer Expire Count */
-#define E1000_ICTXQEC	0x04118  /* Interrupt Cause Tx Queue Empty Count */
-#define E1000_ICTXQMTC	0x0411C  /* Interrupt Cause Tx Queue Min Thresh Count */
-#define E1000_ICRXDMTC	0x04120  /* Interrupt Cause Rx Desc Min Thresh Count */
-#define E1000_ICRXOC	0x04124  /* Interrupt Cause Receiver Overrun Count */
-
-#define E1000_VFGPRC	0x00F10
-#define E1000_VFGORC	0x00F18
-#define E1000_VFMPRC	0x00F3C
-#define E1000_VFGPTC	0x00F14
-#define E1000_VFGOTC	0x00F34
-#define E1000_VFGOTLBC	0x00F50
-#define E1000_VFGPTLBC	0x00F44
-#define E1000_VFGORLBC	0x00F48
-#define E1000_VFGPRLBC	0x00F40
-/* Virtualization statistical counters */
-#define E1000_PFVFGPRC(_n)	(0x010010 + (0x100 * (_n)))
-#define E1000_PFVFGPTC(_n)	(0x010014 + (0x100 * (_n)))
-#define E1000_PFVFGORC(_n)	(0x010018 + (0x100 * (_n)))
-#define E1000_PFVFGOTC(_n)	(0x010034 + (0x100 * (_n)))
-#define E1000_PFVFMPRC(_n)	(0x010038 + (0x100 * (_n)))
-#define E1000_PFVFGPRLBC(_n)	(0x010040 + (0x100 * (_n)))
-#define E1000_PFVFGPTLBC(_n)	(0x010044 + (0x100 * (_n)))
-#define E1000_PFVFGORLBC(_n)	(0x010048 + (0x100 * (_n)))
-#define E1000_PFVFGOTLBC(_n)	(0x010050 + (0x100 * (_n)))
-
-/* LinkSec */
-#define E1000_LSECTXUT		0x04300  /* Tx Untagged Pkt Cnt */
-#define E1000_LSECTXPKTE	0x04304  /* Encrypted Tx Pkts Cnt */
-#define E1000_LSECTXPKTP	0x04308  /* Protected Tx Pkt Cnt */
-#define E1000_LSECTXOCTE	0x0430C  /* Encrypted Tx Octets Cnt */
-#define E1000_LSECTXOCTP	0x04310  /* Protected Tx Octets Cnt */
-#define E1000_LSECRXUT		0x04314  /* Untagged non-Strict Rx Pkt Cnt */
-#define E1000_LSECRXOCTD	0x0431C  /* Rx Octets Decrypted Count */
-#define E1000_LSECRXOCTV	0x04320  /* Rx Octets Validated */
-#define E1000_LSECRXBAD		0x04324  /* Rx Bad Tag */
-#define E1000_LSECRXNOSCI	0x04328  /* Rx Packet No SCI Count */
-#define E1000_LSECRXUNSCI	0x0432C  /* Rx Packet Unknown SCI Count */
-#define E1000_LSECRXUNCH	0x04330  /* Rx Unchecked Packets Count */
-#define E1000_LSECRXDELAY	0x04340  /* Rx Delayed Packet Count */
-#define E1000_LSECRXLATE	0x04350  /* Rx Late Packets Count */
-#define E1000_LSECRXOK(_n)	(0x04360 + (0x04 * (_n))) /* Rx Pkt OK Cnt */
-#define E1000_LSECRXINV(_n)	(0x04380 + (0x04 * (_n))) /* Rx Invalid Cnt */
-#define E1000_LSECRXNV(_n)	(0x043A0 + (0x04 * (_n))) /* Rx Not Valid Cnt */
-#define E1000_LSECRXUNSA	0x043C0  /* Rx Unused SA Count */
-#define E1000_LSECRXNUSA	0x043D0  /* Rx Not Using SA Count */
-#define E1000_LSECTXCAP		0x0B000  /* Tx Capabilities Register - RO */
-#define E1000_LSECRXCAP		0x0B300  /* Rx Capabilities Register - RO */
-#define E1000_LSECTXCTRL	0x0B004  /* Tx Control - RW */
-#define E1000_LSECRXCTRL	0x0B304  /* Rx Control - RW */
-#define E1000_LSECTXSCL		0x0B008  /* Tx SCI Low - RW */
-#define E1000_LSECTXSCH		0x0B00C  /* Tx SCI High - RW */
-#define E1000_LSECTXSA		0x0B010  /* Tx SA0 - RW */
-#define E1000_LSECTXPN0		0x0B018  /* Tx SA PN 0 - RW */
-#define E1000_LSECTXPN1		0x0B01C  /* Tx SA PN 1 - RW */
-#define E1000_LSECRXSCL		0x0B3D0  /* Rx SCI Low - RW */
-#define E1000_LSECRXSCH		0x0B3E0  /* Rx SCI High - RW */
-/* LinkSec Tx 128-bit Key 0 - WO */
-#define E1000_LSECTXKEY0(_n)	(0x0B020 + (0x04 * (_n)))
-/* LinkSec Tx 128-bit Key 1 - WO */
-#define E1000_LSECTXKEY1(_n)	(0x0B030 + (0x04 * (_n)))
-#define E1000_LSECRXSA(_n)	(0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */
-#define E1000_LSECRXPN(_n)	(0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */
-/*
- * LinkSec Rx Keys  - where _n is the SA no. and _m the 4 dwords of the 128 bit
- * key - RW.
- */
-#define E1000_LSECRXKEY(_n, _m)	(0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))
-
-#define E1000_SSVPC		0x041A0 /* Switch Security Violation Pkt Cnt */
-#define E1000_IPSCTRL		0xB430  /* IpSec Control Register */
-#define E1000_IPSRXCMD		0x0B408 /* IPSec Rx Command Register - RW */
-#define E1000_IPSRXIDX		0x0B400 /* IPSec Rx Index - RW */
-/* IPSec Rx IPv4/v6 Address - RW */
-#define E1000_IPSRXIPADDR(_n)	(0x0B420 + (0x04 * (_n)))
-/* IPSec Rx 128-bit Key - RW */
-#define E1000_IPSRXKEY(_n)	(0x0B410 + (0x04 * (_n)))
-#define E1000_IPSRXSALT		0x0B404  /* IPSec Rx Salt - RW */
-#define E1000_IPSRXSPI		0x0B40C  /* IPSec Rx SPI - RW */
-/* IPSec Tx 128-bit Key - RW */
-#define E1000_IPSTXKEY(_n)	(0x0B460 + (0x04 * (_n)))
-#define E1000_IPSTXSALT		0x0B454  /* IPSec Tx Salt - RW */
-#define E1000_IPSTXIDX		0x0B450  /* IPSec Tx SA IDX - RW */
-#define E1000_PCS_CFG0	0x04200  /* PCS Configuration 0 - RW */
-#define E1000_PCS_LCTL	0x04208  /* PCS Link Control - RW */
-#define E1000_PCS_LSTAT	0x0420C  /* PCS Link Status - RO */
-#define E1000_CBTMPC	0x0402C  /* Circuit Breaker Tx Packet Count */
-#define E1000_HTDPMC	0x0403C  /* Host Transmit Discarded Packets */
-#define E1000_CBRDPC	0x04044  /* Circuit Breaker Rx Dropped Count */
-#define E1000_CBRMPC	0x040FC  /* Circuit Breaker Rx Packet Count */
-#define E1000_RPTHC	0x04104  /* Rx Packets To Host */
-#define E1000_HGPTC	0x04118  /* Host Good Packets Tx Count */
-#define E1000_HTCBDPC	0x04124  /* Host Tx Circuit Breaker Dropped Count */
-#define E1000_HGORCL	0x04128  /* Host Good Octets Received Count Low */
-#define E1000_HGORCH	0x0412C  /* Host Good Octets Received Count High */
-#define E1000_HGOTCL	0x04130  /* Host Good Octets Transmit Count Low */
-#define E1000_HGOTCH	0x04134  /* Host Good Octets Transmit Count High */
-#define E1000_LENERRS	0x04138  /* Length Errors Count */
-#define E1000_SCVPC	0x04228  /* SerDes/SGMII Code Violation Pkt Count */
-#define E1000_HRMPC	0x0A018  /* Header Redirection Missed Packet Count */
-#define E1000_PCS_ANADV	0x04218  /* AN advertisement - RW */
-#define E1000_PCS_LPAB	0x0421C  /* Link Partner Ability - RW */
-#define E1000_PCS_NPTX	0x04220  /* AN Next Page Transmit - RW */
-#define E1000_PCS_LPABNP	0x04224 /* Link Partner Ability Next Pg - RW */
-#define E1000_1GSTAT_RCV	0x04228 /* 1GSTAT Code Violation Pkt Cnt - RW */
-#define E1000_RXCSUM	0x05000  /* Rx Checksum Control - RW */
-#define E1000_RLPML	0x05004  /* Rx Long Packet Max Length */
-#define E1000_RFCTL	0x05008  /* Receive Filter Control*/
-#define E1000_MTA	0x05200  /* Multicast Table Array - RW Array */
-#define E1000_RA	0x05400  /* Receive Address - RW Array */
-#define E1000_RA2	0x054E0  /* 2nd half of Rx address array - RW Array */
-#define E1000_VFTA	0x05600  /* VLAN Filter Table Array - RW Array */
-#define E1000_VT_CTL	0x0581C  /* VMDq Control - RW */
-#define E1000_CIAA	0x05B88  /* Config Indirect Access Address - RW */
-#define E1000_CIAD	0x05B8C  /* Config Indirect Access Data - RW */
-#define E1000_VFQA0	0x0B000  /* VLAN Filter Queue Array 0 - RW Array */
-#define E1000_VFQA1	0x0B200  /* VLAN Filter Queue Array 1 - RW Array */
-#define E1000_WUC	0x05800  /* Wakeup Control - RW */
-#define E1000_WUFC	0x05808  /* Wakeup Filter Control - RW */
-#define E1000_WUS	0x05810  /* Wakeup Status - RO */
-#define E1000_MANC	0x05820  /* Management Control - RW */
-#define E1000_IPAV	0x05838  /* IP Address Valid - RW */
-#define E1000_IP4AT	0x05840  /* IPv4 Address Table - RW Array */
-#define E1000_IP6AT	0x05880  /* IPv6 Address Table - RW Array */
-#define E1000_WUPL	0x05900  /* Wakeup Packet Length - RW */
-#define E1000_WUPM	0x05A00  /* Wakeup Packet Memory - RO A */
-#define E1000_PBACL	0x05B68  /* MSIx PBA Clear - Read/Write 1's to clear */
-#define E1000_FFLT	0x05F00  /* Flexible Filter Length Table - RW Array */
-#define E1000_HOST_IF	0x08800  /* Host Interface */
-#define E1000_FFMT	0x09000  /* Flexible Filter Mask Table - RW Array */
-#define E1000_FFVT	0x09800  /* Flexible Filter Value Table - RW Array */
-#define E1000_HIBBA	0x8F40   /* Host Interface Buffer Base Address */
-/* Flexible Host Filter Table */
-#define E1000_FHFT(_n)	(0x09000 + ((_n) * 0x100))
-/* Ext Flexible Host Filter Table */
-#define E1000_FHFT_EXT(_n)	(0x09A00 + ((_n) * 0x100))
-
-
-#define E1000_KMRNCTRLSTA	0x00034 /* MAC-PHY interface - RW */
-#define E1000_MDPHYA		0x0003C /* PHY address - RW */
-#define E1000_MANC2H		0x05860 /* Management Control To Host - RW */
-/* Management Decision Filters */
-#define E1000_MDEF(_n)		(0x05890 + (4 * (_n)))
-#define E1000_SW_FW_SYNC	0x05B5C /* SW-FW Synchronization - RW */
-#define E1000_CCMCTL	0x05B48 /* CCM Control Register */
-#define E1000_GIOCTL	0x05B44 /* GIO Analog Control Register */
-#define E1000_SCCTL	0x05B4C /* PCIc PLL Configuration Register */
-#define E1000_GCR	0x05B00 /* PCI-Ex Control */
-#define E1000_GCR2	0x05B64 /* PCI-Ex Control #2 */
-#define E1000_GSCL_1	0x05B10 /* PCI-Ex Statistic Control #1 */
-#define E1000_GSCL_2	0x05B14 /* PCI-Ex Statistic Control #2 */
-#define E1000_GSCL_3	0x05B18 /* PCI-Ex Statistic Control #3 */
-#define E1000_GSCL_4	0x05B1C /* PCI-Ex Statistic Control #4 */
-#define E1000_FACTPS	0x05B30 /* Function Active and Power State to MNG */
-#define E1000_SWSM	0x05B50 /* SW Semaphore */
-#define E1000_FWSM	0x05B54 /* FW Semaphore */
-/* Driver-only SW semaphore (not used by BOOT agents) */
-#define E1000_SWSM2	0x05B58
-#define E1000_DCA_ID	0x05B70 /* DCA Requester ID Information - RO */
-#define E1000_DCA_CTRL	0x05B74 /* DCA Control - RW */
-#define E1000_UFUSE	0x05B78 /* UFUSE - RO */
-#define E1000_FFLT_DBG	0x05F04 /* Debug Register */
-#define E1000_HICR	0x08F00 /* Host Interface Control */
-#define E1000_FWSTS	0x08F0C /* FW Status */
-
-/* RSS registers */
-#define E1000_CPUVEC	0x02C10 /* CPU Vector Register - RW */
-#define E1000_MRQC	0x05818 /* Multiple Receive Control - RW */
-#define E1000_IMIR(_i)	(0x05A80 + ((_i) * 4))  /* Immediate Interrupt */
-#define E1000_IMIREXT(_i)	(0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/
-#define E1000_IMIRVP		0x05AC0 /* Immediate INT Rx VLAN Priority -RW */
-#define E1000_MSIXBM(_i)	(0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */
-/* MSI-X Table entry addr low reg - RW */
-#define E1000_MSIXTADD(_i)	(0x0C000 + ((_i) * 0x10))
-/* MSI-X Table entry addr upper reg - RW */
-#define E1000_MSIXTUADD(_i)	(0x0C004 + ((_i) * 0x10))
-/* MSI-X Table entry message reg - RW */
-#define E1000_MSIXTMSG(_i)	(0x0C008 + ((_i) * 0x10))
-/* MSI-X Table entry vector ctrl reg - RW */
-#define E1000_MSIXVCTRL(_i)	(0x0C00C + ((_i) * 0x10))
-#define E1000_MSIXPBA	0x0E000 /* MSI-X Pending bit array */
-#define E1000_RETA(_i)	(0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
-#define E1000_RSSRK(_i)	(0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
-#define E1000_RSSIM	0x05864 /* RSS Interrupt Mask */
-#define E1000_RSSIR	0x05868 /* RSS Interrupt Request */
-/* VT Registers */
-#define E1000_SWPBS	0x03004 /* Switch Packet Buffer Size - RW */
-#define E1000_MBVFICR	0x00C80 /* Mailbox VF Cause - RWC */
-#define E1000_MBVFIMR	0x00C84 /* Mailbox VF int Mask - RW */
-#define E1000_VFLRE	0x00C88 /* VF Register Events - RWC */
-#define E1000_VFRE	0x00C8C /* VF Receive Enables */
-#define E1000_VFTE	0x00C90 /* VF Transmit Enables */
-#define E1000_QDE	0x02408 /* Queue Drop Enable - RW */
-#define E1000_DTXSWC	0x03500 /* DMA Tx Switch Control - RW */
-#define E1000_WVBR	0x03554 /* VM Wrong Behavior - RWS */
-#define E1000_RPLOLR	0x05AF0 /* Replication Offload - RW */
-#define E1000_UTA	0x0A000 /* Unicast Table Array - RW */
-#define E1000_IOVTCL	0x05BBC /* IOV Control Register */
-#define E1000_VMRCTL	0X05D80 /* Virtual Mirror Rule Control */
-#define E1000_VMRVLAN	0x05D90 /* Virtual Mirror Rule VLAN */
-#define E1000_VMRVM	0x05DA0 /* Virtual Mirror Rule VM */
-#define E1000_MDFB	0x03558 /* Malicious Driver free block */
-#define E1000_LVMMC	0x03548 /* Last VM Misbehavior cause */
-#define E1000_TXSWC	0x05ACC /* Tx Switch Control */
-#define E1000_SCCRL	0x05DB0 /* Storm Control Control */
-#define E1000_BSCTRH	0x05DB8 /* Broadcast Storm Control Threshold */
-#define E1000_MSCTRH	0x05DBC /* Multicast Storm Control Threshold */
-/* These act per VF so an array friendly macro is used */
-#define E1000_V2PMAILBOX(_n)	(0x00C40 + (4 * (_n)))
-#define E1000_P2VMAILBOX(_n)	(0x00C00 + (4 * (_n)))
-#define E1000_VMBMEM(_n)	(0x00800 + (64 * (_n)))
-#define E1000_VFVMBMEM(_n)	(0x00800 + (_n))
-#define E1000_VMOLR(_n)		(0x05AD0 + (4 * (_n)))
-/* VLAN Virtual Machine Filter - RW */
-#define E1000_VLVF(_n)		(0x05D00 + (4 * (_n)))
-#define E1000_VMVIR(_n)		(0x03700 + (4 * (_n)))
-#define E1000_DVMOLR(_n)	(0x0C038 + (0x40 * (_n))) /* DMA VM offload */
-#define E1000_VTCTRL(_n)	(0x10000 + (0x100 * (_n))) /* VT Control */
-#define E1000_TSYNCRXCTL	0x0B620 /* Rx Time Sync Control register - RW */
-#define E1000_TSYNCTXCTL	0x0B614 /* Tx Time Sync Control register - RW */
-#define E1000_TSYNCRXCFG	0x05F50 /* Time Sync Rx Configuration - RW */
-#define E1000_RXSTMPL	0x0B624 /* Rx timestamp Low - RO */
-#define E1000_RXSTMPH	0x0B628 /* Rx timestamp High - RO */
-#define E1000_RXSATRL	0x0B62C /* Rx timestamp attribute low - RO */
-#define E1000_RXSATRH	0x0B630 /* Rx timestamp attribute high - RO */
-#define E1000_TXSTMPL	0x0B618 /* Tx timestamp value Low - RO */
-#define E1000_TXSTMPH	0x0B61C /* Tx timestamp value High - RO */
-#define E1000_SYSTIML	0x0B600 /* System time register Low - RO */
-#define E1000_SYSTIMH	0x0B604 /* System time register High - RO */
-#define E1000_TIMINCA	0x0B608 /* Increment attributes register - RW */
-#define E1000_TSAUXC	0x0B640 /* Timesync Auxiliary Control register */
-#define E1000_SYSTIMR	0x0B6F8 /* System time register Residue */
-#define E1000_AUXSTMPL0 0x0B65C /* Auxiliary Time Stamp 0 Reg - Low */
-#define E1000_AUXSTMPH0 0x0B660 /* Auxiliary Time Stamp 0 Reg - Low */
-
-#define E1000_TQAVCTRL      0x03570
-#define E1000_DTXMXPKTSZ    0x0355C
-#define E1000_LAUNCH_OS0    0x03578
-#define E1000_TQAVARBCTRL   0x03574
-#define E1000_TQAVHC(_n)    (0x0300C + ((_n) * 0x40))
-#define E1000_TQAVCC(_n)    (0x03004 + ((_n) * 0x40))
-
-
-/* Filtering Registers */
-#define E1000_SAQF(_n)	(0x05980 + (4 * (_n))) /* Source Address Queue Fltr */
-#define E1000_DAQF(_n)	(0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */
-#define E1000_SPQF(_n)	(0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */
-#define E1000_FTQF(_n)	(0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */
-#define E1000_TTQF(_n)	(0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */
-#define E1000_SYNQF(_n)	(0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
-#define E1000_ETQF(_n)	(0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
-
-#define E1000_RTTDCS	0x3600 /* Reedtown Tx Desc plane control and status */
-#define E1000_RTTPCS	0x3474 /* Reedtown Tx Packet Plane control and status */
-#define E1000_RTRPCS	0x2474 /* Rx packet plane control and status */
-#define E1000_RTRUP2TC	0x05AC4 /* Rx User Priority to Traffic Class */
-#define E1000_RTTUP2TC	0x0418 /* Transmit User Priority to Traffic Class */
-/* Tx Desc plane TC Rate-scheduler config */
-#define E1000_RTTDTCRC(_n)	(0x3610 + ((_n) * 4))
-/* Tx Packet plane TC Rate-Scheduler Config */
-#define E1000_RTTPTCRC(_n)	(0x3480 + ((_n) * 4))
-/* Rx Packet plane TC Rate-Scheduler Config */
-#define E1000_RTRPTCRC(_n)	(0x2480 + ((_n) * 4))
-/* Tx Desc Plane TC Rate-Scheduler Status */
-#define E1000_RTTDTCRS(_n)	(0x3630 + ((_n) * 4))
-/* Tx Desc Plane TC Rate-Scheduler MMW */
-#define E1000_RTTDTCRM(_n)	(0x3650 + ((_n) * 4))
-/* Tx Packet plane TC Rate-Scheduler Status */
-#define E1000_RTTPTCRS(_n)	(0x34A0 + ((_n) * 4))
-/* Tx Packet plane TC Rate-scheduler MMW */
-#define E1000_RTTPTCRM(_n)	(0x34C0 + ((_n) * 4))
-/* Rx Packet plane TC Rate-Scheduler Status */
-#define E1000_RTRPTCRS(_n)	(0x24A0 + ((_n) * 4))
-/* Rx Packet plane TC Rate-Scheduler MMW */
-#define E1000_RTRPTCRM(_n)	(0x24C0 + ((_n) * 4))
-/* Tx Desc plane VM Rate-Scheduler MMW*/
-#define E1000_RTTDVMRM(_n)	(0x3670 + ((_n) * 4))
-/* Tx BCN Rate-Scheduler MMW */
-#define E1000_RTTBCNRM(_n)	(0x3690 + ((_n) * 4))
-#define E1000_RTTDQSEL	0x3604  /* Tx Desc Plane Queue Select */
-#define E1000_RTTDVMRC	0x3608  /* Tx Desc Plane VM Rate-Scheduler Config */
-#define E1000_RTTDVMRS	0x360C  /* Tx Desc Plane VM Rate-Scheduler Status */
-#define E1000_RTTBCNRC	0x36B0  /* Tx BCN Rate-Scheduler Config */
-#define E1000_RTTBCNRS	0x36B4  /* Tx BCN Rate-Scheduler Status */
-#define E1000_RTTBCNCR	0xB200  /* Tx BCN Control Register */
-#define E1000_RTTBCNTG	0x35A4  /* Tx BCN Tagging */
-#define E1000_RTTBCNCP	0xB208  /* Tx BCN Congestion point */
-#define E1000_RTRBCNCR	0xB20C  /* Rx BCN Control Register */
-#define E1000_RTTBCNRD	0x36B8  /* Tx BCN Rate Drift */
-#define E1000_PFCTOP	0x1080  /* Priority Flow Control Type and Opcode */
-#define E1000_RTTBCNIDX	0xB204  /* Tx BCN Congestion Point */
-#define E1000_RTTBCNACH	0x0B214 /* Tx BCN Control High */
-#define E1000_RTTBCNACL	0x0B210 /* Tx BCN Control Low */
-
-/* DMA Coalescing registers */
-#define E1000_DMACR	0x02508 /* Control Register */
-#define E1000_DMCTXTH	0x03550 /* Transmit Threshold */
-#define E1000_DMCTLX	0x02514 /* Time to Lx Request */
-#define E1000_DMCRTRH	0x05DD0 /* Receive Packet Rate Threshold */
-#define E1000_DMCCNT	0x05DD4 /* Current Rx Count */
-#define E1000_FCRTC	0x02170 /* Flow Control Rx high watermark */
-#define E1000_PCIEMISC	0x05BB8 /* PCIE misc config register */
-
-/* PCIe Parity Status Register */
-#define E1000_PCIEERRSTS	0x05BA8
-
-#define E1000_LTRMINV	0x5BB0 /* LTR Minimum Value */
-#define E1000_LTRMAXV	0x5BB4 /* LTR Maximum Value */
-#define E1000_DOBFFCTL	0x3F24 /* DMA OBFF Control Register */
-
-#define E1000_PROXYS	0x5F64 /* Proxying Status */
-#define E1000_PROXYFC	0x5F60 /* Proxying Filter Control */
-/* Thermal sensor configuration and status registers */
-#define E1000_THMJT	0x08100 /* Junction Temperature */
-#define E1000_THLOWTC	0x08104 /* Low Threshold Control */
-#define E1000_THMIDTC	0x08108 /* Mid Threshold Control */
-#define E1000_THHIGHTC	0x0810C /* High Threshold Control */
-#define E1000_THSTAT	0x08110 /* Thermal Sensor Status */
-
-/*Energy Efficient Ethernet "EEE" registers */
-#define E1000_IPCNFG	0x0E38 /* Internal PHY Configuration */
-#define E1000_LTRC	0x01A0 /* Latency Tolerance Reporting Control */
-#define E1000_EEER	0x0E30 /* Energy Efficient Ethernet "EEE"*/
-#define E1000_EEE_SU	0x0E34 /* EEE Setup */
-#define E1000_TLPIC	0x4148 /* EEE Tx LPI Count - TLPIC */
-#define E1000_RLPIC	0x414C /* EEE Rx LPI Count - RLPIC */
-
-/* OS2BMC Registers */
-#define E1000_B2OSPC	0x08FE0 /* BMC2OS packets sent by BMC */
-#define E1000_B2OGPRC	0x04158 /* BMC2OS packets received by host */
-#define E1000_O2BGPTC	0x08FE4 /* OS2BMC packets received by BMC */
-#define E1000_O2BSPC	0x0415C /* OS2BMC packets transmitted by host */
-
-#endif
diff --git a/lib/igb/igb.c b/lib/igb/igb.c
deleted file mode 100644
index 96e18951..00000000
--- a/lib/igb/igb.c
+++ /dev/null
@@ -1,2584 +0,0 @@
-/******************************************************************************
-
-  Copyright (c) 2001-2017, Intel Corporation
-  All rights reserved.
-
-  Redistribution and use in source and binary forms, with or without
-  modification, are permitted provided that the following conditions are met:
-
-   1. Redistributions of source code must retain the above copyright notice,
-      this list of conditions and the following disclaimer.
-
-   2. Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-
-   3. Neither the name of the Intel Corporation nor the names of its
-      contributors may be used to endorse or promote products derived from
-      this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE.
-
-******************************************************************************/
-
-#include <unistd.h>
-#include <fcntl.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <syslog.h>
-#include <signal.h>
-#include <errno.h>
-
-#include <time.h>
-#include <sys/ioctl.h>
-#include <sys/time.h>
-#include <sys/resource.h>
-#include <sys/mman.h>
-#include <sys/user.h>
-#include <sys/stat.h>
-#include <stdint.h>
-#include <semaphore.h>
-#include <pthread.h>
-
-#include "e1000_hw.h"
-#include "e1000_82575.h"
-#include "igb_internal.h"
-
-#undef DEBUG
-
-/*********************************************************************
- *  PCI Device ID Table
- *
- *  Used by probe to select devices to load on
- *  Last field stores an index into e1000_strings
- *  Last entry must be all 0s
- *
- *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
- *********************************************************************/
-
-static igb_vendor_info_t igb_vendor_info_array[] = {
-	{ 0x8086, E1000_DEV_ID_I210_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
-	{ 0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS,
-		PCI_ANY_ID, PCI_ANY_ID, 0},
-	{ 0x8086, E1000_DEV_ID_I210_COPPER_IT, PCI_ANY_ID, PCI_ANY_ID, 0},
-	{ 0x8086, E1000_DEV_ID_I210_COPPER_OEM1,
-		PCI_ANY_ID, PCI_ANY_ID, 0},
-	{ 0x8086, E1000_DEV_ID_I210_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
-	{ 0x8086, E1000_DEV_ID_I210_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
-	{ 0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS,
-		PCI_ANY_ID, PCI_ANY_ID, 0},
-	{ 0x8086, E1000_DEV_ID_I210_SGMII, PCI_ANY_ID, PCI_ANY_ID, 0},
-	{ 0x8086, E1000_DEV_ID_I210_AUTOMOTIVE, PCI_ANY_ID, PCI_ANY_ID, 0},
-	/* required last entry */
-	{ 0, 0, 0, 0, 0}
-};
-
-/*********************************************************************
- *  Function prototypes
- *********************************************************************/
-static int igb_read_mac_addr(struct e1000_hw *hw);
-static int igb_allocate_pci_resources(struct adapter *adapter);
-static void igb_free_pci_resources(struct adapter *adapter);
-static void igb_reset(struct adapter *adapter);
-static int igb_allocate_queues(struct adapter *adapter);
-static int igb_allocate_rx_queues(struct adapter *adapter);
-static void igb_setup_transmit_structures(struct adapter *adapter);
-static void igb_setup_receive_structures(struct adapter *adapter);
-static void igb_setup_transmit_ring(struct tx_ring *txr);
-static void igb_initialize_transmit_units(struct adapter *adapter);
-static void igb_initialize_receive_units(struct adapter *adapter);
-static void igb_free_transmit_structures(struct adapter *adapter);
-static void igb_free_receive_structures(struct adapter *adapter);
-static void igb_tx_ctx_setup(struct tx_ring *txr, struct igb_packet *packet);
-static void igb_free_receive_buffers(struct rx_ring *rxr);
-static int  igb_create_lock(struct adapter *adapter);
-
-int igb_probe(device_t *dev)
-{
-	igb_vendor_info_t *ent;
-
-	if (dev == NULL)
-		return -EINVAL;
-
-	if (dev->pci_vendor_id != IGB_VENDOR_ID)
-		return -ENXIO;
-
-	ent = igb_vendor_info_array;
-	while (ent->vendor_id != 0) {
-		if ((dev->pci_vendor_id == ent->vendor_id) &&
-		    (dev->pci_device_id == ent->device_id)) {
-
-			return 0;
-		}
-		ent++;
-	}
-
-	return -ENXIO;
-}
-
-#define IGB_SEM "/igb_sem"
-
-int igb_attach(char *dev_path, device_t *pdev)
-{
-	struct adapter *adapter;
-	struct igb_bind_cmd	bind = {0};
-	int error = 0;
-	bool locked = false;
-
-	if (pdev == NULL)
-		return -EINVAL;
-
-	adapter = (struct adapter *)pdev->private_data;
-
-	if (adapter != NULL)
-		return -EBUSY;
-
-	/* allocate an adapter */
-	pdev->private_data = malloc(sizeof(struct adapter));
-	if (pdev->private_data == NULL)
-		return -ENXIO;
-
-	memset(pdev->private_data, 0, sizeof(struct adapter));
-
-	adapter = (struct adapter *)pdev->private_data;
-
-	adapter->ldev = open("/dev/igb_avb", O_RDWR);
-
-	if (adapter->ldev < 0) {
-		error = -ENXIO;
-		goto err_prebind;
-	}
-
-	if (igb_create_lock(adapter) != 0) {
-		error = -errno;
-		goto err_bind;
-	}
-
-	adapter->active = 1;
-
-	if (igb_lock(pdev) != 0) {
-		error = -errno;
-		goto err_bind;
-	}
-
-	locked = true;
-
-	/*
-	 * dev_path should look something "0000:01:00.0"
-	 */
-
-	strncpy(bind.iface, dev_path, IGB_BIND_NAMESZ - 1);
-
-	if (ioctl(adapter->ldev, IGB_BIND, &bind) < 0) {
-		error = -ENXIO;
-		goto err_bind;
-	}
-
-	adapter->csr.paddr = 0;
-	adapter->csr.mmap_size = bind.mmap_size;
-
-	/* Determine hardware and mac info */
-	adapter->hw.vendor_id = pdev->pci_vendor_id;
-	adapter->hw.device_id = pdev->pci_vendor_id;
-	adapter->hw.revision_id = 0;
-	adapter->hw.subsystem_vendor_id = 0;
-	adapter->hw.subsystem_device_id = 0;
-
-	/* Set MAC type early for PCI setup */
-	adapter->hw.mac.type = e1000_i210;
-
-	/* Setup PCI resources */
-	error = igb_allocate_pci_resources(adapter);
-	if (error)
-		goto err_pci;
-
-	/*
-	 * Set the frame limits assuming
-	 * standard ethernet sized frames.
-	 */
-	adapter->max_frame_size = 1518;
-	adapter->min_frame_size = 64;
-
-	/*
-	 * Copy the permanent MAC address out of the EEPROM
-	 */
-	if (igb_read_mac_addr(&adapter->hw) < 0) {
-		error = -EIO;
-		goto err_late;
-	}
-
-	if (igb_unlock(pdev) != 0) {
-		error = -errno;
-		goto err_gen;
-	}
-
-	return 0;
-
-err_late:
-err_pci:
-	igb_free_pci_resources(adapter);
-err_bind:
-	if (locked)
-		(void) igb_unlock(pdev);
-	if (adapter && adapter->memlock) {
-		(void) munmap(adapter->memlock, sizeof(pthread_mutex_t));
-		adapter->memlock = NULL;
-	}
-	close(adapter->ldev);
-err_prebind:
-	free(pdev->private_data);
-	pdev->private_data = NULL;
-
-err_gen:
-	return error;
-}
-
-int igb_attach_tx(device_t *pdev)
-{
-	int error;
-	struct adapter *adapter;
-
-	if (pdev == NULL)
-		return -EINVAL;
-
-	adapter = (struct adapter *)pdev->private_data;
-
-	if (adapter == NULL)
-		return -EINVAL;
-
-	if (igb_lock(pdev) != 0)
-		return -errno;
-
-	/* Allocate and Setup Queues */
-	adapter->num_queues = 2;  /* XXX parameterize this */
-	error = igb_allocate_queues(adapter);
-	if (error) {
-		adapter->num_queues = 0;
-		goto release;
-	}
-
-	/*
-	 * Start from a known state, which means
-	 * reset the transmit queues we own to a known
-	 * starting state.
-	 */
-	igb_reset(adapter);
-
-release:
-	if (igb_unlock(pdev) != 0)
-		return -errno;
-
-	return error;
-}
-
-int igb_attach_rx(device_t *pdev)
-{
-	int error;
-	struct adapter *adapter;
-
-	if (pdev == NULL)
-		return -EINVAL;
-
-	adapter = (struct adapter *)pdev->private_data;
-
-	if (adapter == NULL)
-		return -EINVAL;
-
-	if (igb_lock(pdev) != 0)
-		return errno;
-
-	/*
-	 * Allocate and Setup Rx Queues
-	 */
-	adapter->num_queues = 2;  /* XXX parameterize this */
-	error = igb_allocate_rx_queues(adapter);
-	if (error) {
-		adapter->num_queues = 0;
-		goto release;
-	}
-
-release:
-	if (igb_unlock(pdev) != 0)
-		return errno;
-
-	return error;
-}
-
-int igb_detach(device_t *dev)
-{
-	struct adapter *adapter;
-
-	if (dev == NULL)
-		return -EINVAL;
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -ENXIO;
-
-	if (igb_lock(dev) != 0)
-		goto err_nolock;
-
-	/*
-	 * Prevent access to device after calling igb_detach since associated
-	 * resources will be freed up from here thus in particular multi-thread
-	 * application other thread must not access device if this flag is off.
-	 */
-	adapter->active = 0;
-
-	igb_reset(adapter);
-
-	igb_unlock(dev);
-
-	igb_free_pci_resources(adapter);
-
-	if (adapter->tx_rings)
-		igb_free_transmit_structures(adapter);
-
-	if (adapter->rx_rings)
-		igb_free_receive_structures(adapter);
-
-err_nolock:
-	if (adapter->memlock) {
-		/*
-		 * Do not unmap the shared memory region holding the pthread mutex.
-		 *
-		 * (void) munmap(adapter->memlock, sizeof(pthread_mutex_t));
-		 *
-		 * The pthread mutex is configured as a robust type mutex so that
-		 * it can automatically be unlocked on process termination if needed.
-		 * In order to complete the cleanup, the memory region holding the
-		 * mutex instance must be accessible until that cleanup timing.
-		 * Therefore we should not unmap the memory region here, otherwise
-		 * the cleanup may fail.
-		 *
-		 * The mapped regions will automatically be unmapped at the end of
-		 * the process termination.
-		 */
-		adapter->memlock = NULL;
-	}
-
-	close(adapter->ldev);
-
-	free(dev->private_data);
-	dev->private_data = NULL;
-	return 0;
-}
-
-int igb_suspend(device_t *dev)
-{
-	struct adapter *adapter;
-	struct tx_ring *txr;
-	struct rx_ring *rxr;
-	struct e1000_hw *hw;
-	u32 txdctl, srrctl = 0;
-	int i;
-
-	if (dev == NULL)
-		return -EINVAL;
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -ENXIO;
-
-	txr = adapter->tx_rings;
-	rxr = adapter->rx_rings;
-	hw = &adapter->hw;
-
-	txdctl = 0;
-
-	if (igb_lock(dev) != 0)
-		return errno;
-
-	/* stop but don't reset the Tx Descriptor Rings */
-	for (i = 0; i < adapter->num_queues; i++, txr++) {
-		txdctl |= IGB_TX_PTHRESH;
-		txdctl |= IGB_TX_HTHRESH << 8;
-		txdctl |= IGB_TX_WTHRESH << 16;
-		E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
-		txr->queue_status = IGB_QUEUE_IDLE;
-	}
-
-	srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
-	srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
-
-	for (i = 0; i < adapter->num_queues; i++, rxr++) {
-		u64 bus_addr = rxr->rxdma.paddr;
-		u32 rxdctl;
-
-		E1000_WRITE_REG(hw, E1000_RDLEN(i),
-				adapter->num_rx_desc *
-				sizeof(union e1000_adv_rx_desc));
-		E1000_WRITE_REG(hw, E1000_RDBAH(i),
-				(uint32_t)(bus_addr >> 32));
-		E1000_WRITE_REG(hw, E1000_RDBAL(i),
-				(uint32_t)bus_addr);
-		E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
-		/* Enable this Queue */
-		rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
-		rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
-		rxdctl &= 0xFFF00000;
-		rxdctl |= IGB_RX_PTHRESH;
-		rxdctl |= IGB_RX_HTHRESH << 8;
-		rxdctl |= IGB_RX_WTHRESH << 16;
-		E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
-	}
-
-	if (igb_unlock(dev) != 0)
-		return errno;
-
-	return 0;
-}
-
-int igb_resume(device_t *dev)
-{
-	struct adapter *adapter;
-	struct tx_ring *txr;
-	struct rx_ring *rxr;
-	struct e1000_hw *hw;
-	u32 txdctl, srrctl = 0;
-	int i;
-
-	if (dev == NULL)
-		return -EINVAL;
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -ENXIO;
-
-	txr = adapter->tx_rings;
-	rxr = adapter->rx_rings;
-	hw = &adapter->hw;
-
-	txdctl = 0;
-
-	if (igb_lock(dev) != 0)
-		return errno;
-
-	/* resume but don't reset the Tx Descriptor Rings */
-	for (i = 0; i < adapter->num_queues; i++, txr++) {
-		/* idle the queue */
-		txdctl |= IGB_TX_PTHRESH;
-		txdctl |= IGB_TX_HTHRESH << 8;
-		txdctl |= IGB_TX_WTHRESH << 16;
-		txdctl |= E1000_TXDCTL_PRIORITY;
-		txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
-		E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
-		txr->queue_status = IGB_QUEUE_WORKING;
-	}
-
-	srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
-	srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
-
-	for (i = 0; i < adapter->num_queues; i++, rxr++) {
-		u64 bus_addr = rxr->rxdma.paddr;
-		u32 rxdctl;
-
-		E1000_WRITE_REG(hw, E1000_RDLEN(i),
-				adapter->num_rx_desc *
-				sizeof(union e1000_adv_rx_desc));
-		E1000_WRITE_REG(hw, E1000_RDBAH(i),
-				(uint32_t)(bus_addr >> 32));
-		E1000_WRITE_REG(hw, E1000_RDBAL(i),
-				(uint32_t)bus_addr);
-		E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
-		/* Enable this Queue */
-		rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
-		rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
-		rxdctl &= 0xFFF00000;
-		rxdctl |= IGB_RX_PTHRESH;
-		rxdctl |= IGB_RX_HTHRESH << 8;
-		rxdctl |= IGB_RX_WTHRESH << 16;
-		E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
-	}
-
-	if (igb_unlock(dev) != 0)
-		return errno;
-
-	return 0;
-}
-
-int igb_init(device_t *dev)
-{
-	struct adapter *adapter;
-
-	if (dev == NULL)
-		return -EINVAL;
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -ENXIO;
-
-	if (igb_lock(dev) != 0)
-		return errno;
-
-	igb_reset(adapter);
-
-	/* Prepare transmit descriptors and buffers */
-	if (adapter->tx_rings) {
-		igb_setup_transmit_structures(adapter);
-		igb_initialize_transmit_units(adapter);
-	}
-
-	if (adapter->rx_rings) {
-		igb_setup_receive_structures(adapter);
-		igb_initialize_receive_units(adapter);
-	}
-
-	if (igb_unlock(dev) != 0)
-		return errno;
-
-	return 0;
-}
-
-static void
-igb_reset(struct adapter *adapter)
-{
-	struct tx_ring *txr = adapter->tx_rings;
-	struct rx_ring *rxr = adapter->rx_rings;
-	struct e1000_hw *hw = &adapter->hw;
-	u32 txdctl, srrctl;
-	int i;
-
-	srrctl = 0;
-	txdctl = 0;
-
-	/* Set up the Tx Descriptor Rings, leave queues idle */
-	if (adapter->tx_rings == NULL) {
-#if DEBUG
-		printf("txr null\n");
-#endif
-	} else {
-		for (i = 0; i < adapter->num_queues; i++, txr++) {
-			u64 bus_addr = txr->txdma.paddr;
-
-			/* idle the queue */
-			txdctl |= IGB_TX_PTHRESH;
-			txdctl |= IGB_TX_HTHRESH << 8;
-			txdctl |= IGB_TX_WTHRESH << 16;
-			E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
-
-			/* reset the descriptor head/tail */
-			E1000_WRITE_REG(hw, E1000_TDLEN(i),
-					adapter->num_tx_desc *
-					sizeof(struct e1000_tx_desc));
-			E1000_WRITE_REG(hw, E1000_TDBAH(i),
-					(u_int32_t)(bus_addr >> 32));
-			E1000_WRITE_REG(hw, E1000_TDBAL(i),
-					(u_int32_t)bus_addr);
-
-			/* Setup the HW Tx Head and Tail descriptor pointers */
-			E1000_WRITE_REG(hw, E1000_TDT(i), 0);
-			E1000_WRITE_REG(hw, E1000_TDH(i), 0);
-
-			txr->queue_status = IGB_QUEUE_IDLE;
-		}
-	}
-
-	srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
-	srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
-
-	/* Setup the Base and Length of the Rx Descriptor Rings */
-	if (adapter->rx_rings == NULL) {
-#if DEBUG
-		printf("rxr null\n");
-#endif
-	} else {
-
-		for (i = 0; i < adapter->num_queues; i++, rxr++) {
-			u64 bus_addr = rxr->rxdma.paddr;
-			u32 rxdctl;
-
-			/* Disable this Queue */
-			E1000_WRITE_REG(hw, E1000_RXDCTL(i), 0);
-
-			E1000_WRITE_REG(hw, E1000_RDLEN(i),
-					adapter->num_rx_desc *
-					sizeof(union e1000_adv_rx_desc));
-			E1000_WRITE_REG(hw, E1000_RDBAH(i),
-					(uint32_t)(bus_addr >> 32));
-			E1000_WRITE_REG(hw, E1000_RDBAL(i),
-					(uint32_t)bus_addr);
-			E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
-
-			/* Enable this Queue */
-			rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
-			rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
-			rxdctl &= 0xFFF00000;
-			rxdctl |= IGB_RX_PTHRESH;
-			rxdctl |= IGB_RX_HTHRESH << 8;
-			rxdctl |= IGB_RX_WTHRESH << 16;
-			E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
-		}
-	}
-}
-
-static int igb_read_mac_addr(struct e1000_hw *hw)
-{
-	u32 rar_high;
-	u32 rar_low;
-	u16 i;
-
-	rar_high = E1000_READ_REG(hw, E1000_RAH(0));
-	rar_low = E1000_READ_REG(hw, E1000_RAL(0));
-
-	for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
-		hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
-
-	for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
-		hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
-
-	for (i = 0; i < ETH_ADDR_LEN; i++)
-		hw->mac.addr[i] = hw->mac.perm_addr[i];
-
-	return 0;
-
-}
-
-static int igb_allocate_pci_resources(struct adapter *adapter)
-{
-	int dev = adapter->ldev;
-
-	adapter->hw.hw_addr = (u8 *)mmap(NULL, adapter->csr.mmap_size,
-					 PROT_READ | PROT_WRITE, MAP_SHARED,
-					 dev, 0);
-
-	if (adapter->hw.hw_addr == MAP_FAILED)
-		return -ENXIO;
-
-	return 0;
-}
-
-static void igb_free_pci_resources(struct adapter *adapter)
-{
-	munmap(adapter->hw.hw_addr, adapter->csr.mmap_size);
-}
-
-/*
- * Manage DMA'able memory.
- */
-int igb_dma_malloc_page(device_t *dev, struct igb_dma_alloc *dma)
-{
-	struct adapter *adapter;
-	int error = 0;
-	struct igb_buf_cmd ubuf = {0};
-
-	if (dev == NULL)
-		return -EINVAL;
-	if (dma == NULL)
-		return -EINVAL;
-
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -ENXIO;
-
-	if (igb_lock(dev) != 0) {
-		error = errno;
-		goto err;
-	}
-	error = ioctl(adapter->ldev, IGB_IOCTL_MAPBUF, &ubuf);
-	if (igb_unlock(dev) != 0) {
-		error = errno;
-		goto err;
-	}
-
-	if (error < 0) {
-		if(error != -EINVAL)
-			error = -ENOMEM;
-		goto err;
-	}
-
-	dma->dma_paddr = ubuf.physaddr;
-	dma->mmap_size = ubuf.mmap_size;
-	dma->dma_vaddr = (void *)mmap(NULL,
-				      ubuf.mmap_size,
-				      PROT_READ | PROT_WRITE,
-				      MAP_SHARED,
-				      adapter->ldev,
-				      ubuf.pa);
-
-	if (dma->dma_vaddr == MAP_FAILED)
-		error = -ENOMEM;
-err:
-	return error;
-}
-
-void igb_dma_free_page(device_t *dev, struct igb_dma_alloc *dma)
-{
-	struct adapter *adapter;
-	struct igb_buf_cmd      ubuf;
-
-	if (dev == NULL)
-		return;
-	if (dma == NULL)
-		return;
-
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return;
-
-	munmap(dma->dma_vaddr,
-		dma->mmap_size);
-
-	ubuf.physaddr = dma->dma_paddr;
-
-	if (igb_lock(dev) != 0)
-		goto err;
-
-	ioctl(adapter->ldev, IGB_IOCTL_UNMAPBUF, &ubuf);
-	if (igb_unlock(dev) != 0)
-		goto err;
-
-	dma->dma_paddr = 0;
-	dma->dma_vaddr = NULL;
-	dma->mmap_size = 0;
-
-err:
-	return;
-}
-
-/*********************************************************************
- *
- *  Allocate memory for the transmit rings, and then
- *  the descriptors associated with each, called only once at attach.
- *
- **********************************************************************/
-static int igb_allocate_queues(struct adapter *adapter)
-{
-	struct igb_buf_cmd ubuf = {0};
-	int dev = adapter->ldev;
-	int i, error = 0;
-
-	/* allocate the TX ring struct memory */
-	adapter->tx_rings = (struct tx_ring *) malloc(sizeof(struct tx_ring) *
-						      adapter->num_queues);
-
-	if (adapter->tx_rings == NULL) {
-		error = -ENOMEM;
-		goto tx_fail;
-	}
-
-	memset(adapter->tx_rings, 0, sizeof(struct tx_ring) *
-					    adapter->num_queues);
-
-	for (i = 0; i < adapter->num_queues; i++) {
-		ubuf.queue = i;
-		error = ioctl(dev, IGB_IOCTL_MAPRING, &ubuf);
-		if (error < 0) {
-			if(error == -EINVAL)
-				goto tx_fail;
-
-			error = EBUSY;
-			goto tx_desc;
-		}
-
-		if (ubuf.physaddr % 128)
-			printf("warning: tx ring addr (0x%lx) is not a 128 byte-aligned\n",
-				ubuf.physaddr);
-
-		adapter->tx_rings[i].txdma.paddr = ubuf.physaddr;
-		adapter->tx_rings[i].txdma.mmap_size = ubuf.mmap_size;
-		adapter->tx_rings[i].tx_base = NULL;
-		adapter->tx_rings[i].tx_base =
-			(struct e1000_tx_desc *)mmap(NULL, ubuf.mmap_size,
-						     PROT_READ | PROT_WRITE,
-						     MAP_SHARED, adapter->ldev,
-						     ubuf.pa);
-
-		if (adapter->tx_rings[i].tx_base == MAP_FAILED) {
-			error = -ENOMEM;
-			goto tx_desc;
-		}
-
-		adapter->tx_rings[i].adapter = adapter;
-		adapter->tx_rings[i].me = i;
-		/* XXX Initialize a TX lock ?? */
-		adapter->num_tx_desc = ubuf.mmap_size /
-				       sizeof(union e1000_adv_tx_desc);
-
-		/*
-		 * num_tx_desc must be always a multiple of 8 because the value of
-		 * TDLEN must be a multipe of 128 and each descriptor has 16 bytes.
-		 */
-		if (adapter->num_tx_desc % 8)
-			printf("warning: num_tx_desc(%d) is not a multiple of 8\n",
-				adapter->num_tx_desc);
-
-		memset((void *)adapter->tx_rings[i].tx_base, 0, ubuf.mmap_size);
-		adapter->tx_rings[i].tx_buffers =
-			(struct igb_tx_buffer *)
-				malloc(sizeof(struct igb_tx_buffer) *
-				       adapter->num_tx_desc);
-
-		if (adapter->tx_rings[i].tx_buffers == NULL) {
-			error = -ENOMEM;
-			goto tx_desc;
-		}
-
-		memset(adapter->tx_rings[i].tx_buffers, 0,
-		       sizeof(struct igb_tx_buffer) * adapter->num_tx_desc);
-	}
-
-	return 0;
-
-tx_desc:
-	for (i = 0; i < adapter->num_queues; i++) {
-		if (adapter->tx_rings[i].tx_base)
-			munmap(adapter->tx_rings[i].tx_base,
-			       adapter->tx_rings[i].txdma.mmap_size);
-		ubuf.queue = i;
-		ioctl(dev, IGB_IOCTL_UNMAPRING, &ubuf);
-	};
-tx_fail:
-	free(adapter->tx_rings);
-	adapter->tx_rings = NULL;
-	return error;
-}
-
-/* Initialize a transmit ring. */
-static void igb_setup_transmit_ring(struct tx_ring *txr)
-{
-	struct adapter *adapter = txr->adapter;
-
-	/* Clear the old descriptor contents */
-	memset((void *)txr->tx_base,  0,
-	       (sizeof(union e1000_adv_tx_desc)) * adapter->num_tx_desc);
-
-	memset(txr->tx_buffers, 0, sizeof(struct igb_tx_buffer) *
-				   txr->adapter->num_tx_desc);
-
-	/* Reset indices */
-	txr->next_avail_desc = 0;
-	txr->next_to_clean = 0;
-
-	/* Set number of descriptors available */
-	txr->tx_avail = adapter->num_tx_desc;
-}
-
-/*  Initialize all transmit rings. */
-static void igb_setup_transmit_structures(struct adapter *adapter)
-{
-	struct tx_ring *txr = adapter->tx_rings;
-	int i;
-
-	for (i = 0; i < adapter->num_queues; i++, txr++)
-		igb_setup_transmit_ring(txr);
-}
-
-/*Enable transmit unit. */
-static void igb_initialize_transmit_units(struct adapter *adapter)
-{
-	struct tx_ring *txr = adapter->tx_rings;
-	struct e1000_hw *hw = &adapter->hw;
-	u32 txdctl;
-	int i;
-
-	txdctl = 0;
-
-	/* Setup the Tx Descriptor Rings */
-	for (i = 0; i < adapter->num_queues; i++, txr++) {
-		txdctl = 0;
-		E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
-
-		/* Setup the HW Tx Head and Tail descriptor pointers */
-		E1000_WRITE_REG(hw, E1000_TDT(i), 0);
-		E1000_WRITE_REG(hw, E1000_TDH(i), 0);
-
-		txr->queue_status = IGB_QUEUE_IDLE;
-
-		txdctl |= IGB_TX_PTHRESH;
-		txdctl |= IGB_TX_HTHRESH << 8;
-		txdctl |= IGB_TX_WTHRESH << 16;
-		txdctl |= E1000_TXDCTL_PRIORITY;
-		txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
-		E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
-	}
-
-}
-
-/* Free all transmit rings. */
-static void igb_free_transmit_structures(struct adapter *adapter)
-{
-	int i;
-	struct igb_buf_cmd ubuf = {0};
-
-	for (i = 0; i < adapter->num_queues; i++) {
-		if (adapter->tx_rings[i].tx_base)
-			munmap(adapter->tx_rings[i].tx_base,
-			       adapter->tx_rings[i].txdma.mmap_size);
-		ubuf.queue = i;
-		ioctl(adapter->ldev, IGB_IOCTL_UNMAPRING, &ubuf);
-		free(adapter->tx_rings[i].tx_buffers);
-	}
-
-	free(adapter->tx_rings);
-	adapter->tx_rings = NULL;
-}
-
-/* Context Descriptor setup for VLAN or CSUM */
-static void igb_tx_ctx_setup(struct tx_ring *txr, struct igb_packet *packet)
-{
-	struct adapter *adapter = txr->adapter;
-	struct e1000_adv_tx_context_desc *TXD;
-	struct igb_tx_buffer *tx_buffer;
-	u32 type_tucmd_mlhl;
-	int ctxd;
-	u_int64_t remapped_time;
-
-	ctxd = txr->next_avail_desc;
-	tx_buffer = &txr->tx_buffers[ctxd];
-	TXD = (struct e1000_adv_tx_context_desc *) &txr->tx_base[ctxd];
-
-	type_tucmd_mlhl = E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
-
-	/* Now copy bits into descriptor */
-	TXD->vlan_macip_lens = 0;
-	TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
-	TXD->mss_l4len_idx = 0;
-
-	/* remap the 64-bit nsec time to the value represented in the desc */
-	remapped_time = packet->attime - ((packet->attime / 1000000000) *
-					  1000000000);
-
-	remapped_time /= 32; /* scale to 32 nsec increments */
-
-	TXD->seqnum_seed = remapped_time;
-
-	tx_buffer->packet = NULL;
-	tx_buffer->next_eop = -1;
-
-
-	/* We've consumed the first desc, adjust counters */
-	if (++ctxd == adapter->num_tx_desc)
-		ctxd = 0;
-	txr->next_avail_desc = ctxd;
-	--txr->tx_avail;
-}
-
-
-/*********************************************************************
- *
- *  This routine maps a single buffer to an Advanced TX descriptor.
- *  returns ENOSPC if we run low on tx descriptors and the app needs to
- *  cleanup descriptors.
- *
- *  this is a simplified routine which doesn't do LSO, checksum offloads,
- *  multiple fragments, etc. The provided buffers are assumed to have
- *  been previously mapped with the provided dma_malloc_page routines.
- *
- **********************************************************************/
-int igb_xmit(device_t *dev, unsigned int queue_index, struct igb_packet *packet)
-{
-	struct adapter *adapter;
-	struct tx_ring *txr;
-	struct igb_tx_buffer *tx_buffer;
-	union e1000_adv_tx_desc *txd = NULL;
-	u32 cmd_type_len, olinfo_status = 0;
-	int i, first, last = 0;
-	int error = 0;
-
-	if (dev == NULL)
-		return -EINVAL;
-
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -ENXIO;
-
-	txr = &adapter->tx_rings[queue_index];
-	if (!txr)
-		return -EINVAL;
-
-	if (queue_index > adapter->num_queues)
-		return -EINVAL;
-
-	if (packet == NULL)
-		return -EINVAL;
-
-	if (igb_lock(dev) != 0)
-		return errno;
-
-	packet->next = NULL; /* used for cleanup */
-
-	/* Set basic descriptor constants */
-	cmd_type_len = E1000_ADVTXD_DTYP_DATA;
-	cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
-
-	/* cmd_type_len |= E1000_ADVTXD_DCMD_VLE; to enable VLAN insertion */
-
-	/*
-	 * Map the packet for DMA
-	 *
-	 * Capture the first descriptor index,
-	 * this descriptor will have the index
-	 * of the EOP which is the only one that
-	 * now gets a DONE bit writeback.
-	 */
-	first = txr->next_avail_desc;
-	tx_buffer = &txr->tx_buffers[first];
-
-	/*
-	 * Make sure we don't overrun the ring,
-	 * we need nsegs descriptors and one for
-	 * the context descriptor used for the
-	 * offloads.
-	 */
-	if (txr->tx_avail <= 2) {
-		error = ENOSPC;
-		goto unlock;
-	}
-
-	/*
-	 * Set up the context descriptor to specify
-	 * launchtimes for the packet.
-	 */
-	igb_tx_ctx_setup(txr, packet);
-
-	/*
-	 * for performance monitoring, report the DMA time of the tx desc wb
-	 */
-	olinfo_status |= E1000_TXD_DMA_TXDWB;
-
-	/* set payload length */
-	olinfo_status |= packet->len << E1000_ADVTXD_PAYLEN_SHIFT;
-
-	/* Set up our transmit descriptors */
-	i = txr->next_avail_desc;
-
-	/* we assume every packet is contiguous */
-
-	tx_buffer = &txr->tx_buffers[i];
-	txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
-
-	txd->read.buffer_addr = htole64(packet->map.paddr + packet->offset);
-	txd->read.cmd_type_len = htole32(cmd_type_len | packet->len);
-	txd->read.olinfo_status = htole32(olinfo_status);
-	last = i;
-	if (++i == adapter->num_tx_desc)
-		i = 0;
-	tx_buffer->packet = NULL;
-	tx_buffer->next_eop = -1;
-
-	txr->next_avail_desc = i;
-	txr->tx_avail--;
-	tx_buffer->packet = packet;
-
-	/*
-	 * Last Descriptor of Packet
-	 * needs End Of Packet (EOP)
-	 * and Report Status (RS)
-	 */
-	txd->read.cmd_type_len |=
-	    htole32(E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS);
-
-	/*
-	 * Keep track in the first buffer which
-	 * descriptor will be written back
-	 */
-	tx_buffer = &txr->tx_buffers[first];
-	tx_buffer->next_eop = last;
-
-	/*
-	 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
-	 * that this frame is available to transmit.
-	 */
-
-	E1000_WRITE_REG(&adapter->hw, E1000_TDT(txr->me), i);
-	++txr->tx_packets;
-
-unlock:
-	if (igb_unlock(dev) != 0)
-		return errno;
-
-	return error;
-}
-
-void igb_trigger(device_t *dev, u_int32_t data)
-{
-	struct adapter *adapter;
-
-	if (dev == NULL)
-		return;
-
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return;
-
-	if (igb_lock(dev) != 0)
-		return;
-
-	E1000_WRITE_REG(&(adapter->hw), E1000_WUS, data);
-	if (igb_unlock(dev) != 0)
-		return;
-}
-
-void igb_writereg(device_t *dev, u_int32_t reg, u_int32_t data)
-{
-	struct adapter *adapter;
-
-	if (dev == NULL)
-		return;
-
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return;
-
-	E1000_WRITE_REG(&(adapter->hw), reg, data);
-}
-
-void igb_readreg(device_t *dev, u_int32_t reg, u_int32_t *data)
-{
-	struct adapter *adapter;
-
-	if (dev == NULL)
-		return;
-
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return;
-
-	if (data == NULL)
-		return;
-
-	*data = E1000_READ_REG(&(adapter->hw), reg);
-}
-
-int igb_lock(device_t *dev)
-{
-	struct adapter *adapter;
-	int error = -1;
-
-	if (dev == NULL)
-		return -ENODEV;
-
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -ENXIO;
-
-	if (adapter->active != 1)	// detach in progress
-		return -ENXIO;
-
-	if (!adapter->memlock)
-		return -ENXIO;
-
-	error = pthread_mutex_lock(adapter->memlock);
-	switch (error) {
-		case 0:
-			break;
-		case EOWNERDEAD:
-			// some process terminated without unlocking the mutex
-			if (pthread_mutex_consistent(adapter->memlock) != 0)
-				return -errno;
-			break;
-		default:
-			return -errno;
-			break;
-	}
-
-	if (adapter->active != 1) {
-		(void) pthread_mutex_unlock(adapter->memlock);
-		return -ENXIO;
-	}
-
-	return 0;
-}
-
-int igb_unlock(device_t *dev)
-{
-	struct adapter *adapter;
-
-	if (dev == NULL)
-		return -ENODEV;
-
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -ENXIO;
-
-	if (!adapter->memlock)
-		return -ENXIO;
-
-	return pthread_mutex_unlock(adapter->memlock);
-}
-
-/**********************************************************************
- *
- *  Examine each tx_buffer in the used queue. If the hardware is done
- *  processing the packet then return the linked list of associated resources.
- *
- **********************************************************************/
-void igb_clean(device_t *dev, struct igb_packet **cleaned_packets)
-{
-	struct e1000_tx_desc *tx_desc, *eop_desc;
-	struct igb_packet *last_reclaimed;
-	struct igb_tx_buffer *tx_buffer;
-	struct adapter *adapter;
-	struct tx_ring *txr;
-	int first, last, done, processed, i;
-
-	if (dev == NULL)
-		return;
-
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return;
-
-	if (cleaned_packets == NULL)
-		return;
-
-	*cleaned_packets = NULL; /* nothing reclaimed yet */
-
-	if (igb_lock(dev) != 0)
-		return;
-
-	for (i = 0; i < adapter->num_queues; i++) {
-		txr = &adapter->tx_rings[i];
-
-		if (txr->tx_avail == adapter->num_tx_desc) {
-			txr->queue_status = IGB_QUEUE_IDLE;
-			continue;
-		}
-
-		processed = 0;
-		first = txr->next_to_clean;
-		tx_desc = &txr->tx_base[first];
-		tx_buffer = &txr->tx_buffers[first];
-		last = tx_buffer->next_eop;
-		eop_desc = &txr->tx_base[last];
-
-		/*
-		 * What this does is get the index of the
-		 * first descriptor AFTER the EOP of the
-		 * first packet, that way we can do the
-		 * simple comparison on the inner while loop.
-		 */
-		if (++last == adapter->num_tx_desc)
-			last = 0;
-		done = last;
-
-		while (eop_desc->upper.fields.status & E1000_TXD_STAT_DD) {
-			if (tx_buffer->packet)
-				last_reclaimed = tx_buffer->packet;
-
-			/* We clean the range of the packet */
-			while (first != done) {
-				if (tx_buffer->packet) {
-					tx_buffer->packet->dmatime =
-						(0xffffffff) &
-						 tx_desc->buffer_addr;
-					/* tx_buffer->packet->dmatime +=
-					 *	(tx_desc->buffer_addr >> 32) *
-					 *	 1000000000;
-					 */
-					txr->bytes += tx_buffer->packet->len;
-					if (*cleaned_packets == NULL) {
-						*cleaned_packets =
-							tx_buffer->packet;
-					} else {
-						last_reclaimed->next =
-							tx_buffer->packet;
-					}
-					last_reclaimed = tx_buffer->packet;
-
-					tx_buffer->packet = NULL;
-				}
-				tx_buffer->next_eop = -1;
-				tx_desc->upper.data = 0;
-				tx_desc->lower.data = 0;
-				tx_desc->buffer_addr = 0;
-				++txr->tx_avail;
-				++processed;
-
-				if (++first == adapter->num_tx_desc)
-					first = 0;
-
-				tx_buffer = &txr->tx_buffers[first];
-				tx_desc = &txr->tx_base[first];
-			}
-			++txr->packets;
-			/* See if we can continue to the next packet */
-			last = tx_buffer->next_eop;
-			if (last != -1) {
-				eop_desc = &txr->tx_base[last];
-				/* Get new done point */
-				if (++last == adapter->num_tx_desc)
-					last = 0;
-				done = last;
-			} else
-				break;
-		}
-
-		txr->next_to_clean = first;
-
-		if (txr->tx_avail >= IGB_QUEUE_THRESHOLD)
-			txr->queue_status &= ~IGB_QUEUE_DEPLETED;
-	}
-	igb_unlock(dev);
-}
-
-/*********************************************************************
- *
- *  Allocate memory for the receive rings, and then
- *  the descriptors associated with each, called only once at attach.
- *
- **********************************************************************/
-static int igb_allocate_rx_queues(struct adapter *adapter)
-{
-	struct igb_buf_cmd ubuf;
-	int dev = adapter->ldev;
-	int i, error = 0;
-
-	/* allocate the RX ring struct memory */
-	adapter->rx_rings = (struct rx_ring *) malloc(sizeof(struct rx_ring) *
-						      adapter->num_queues);
-
-	if (adapter->rx_rings == NULL) {
-		error = -ENOMEM;
-		goto rx_fail;
-	}
-
-	memset(adapter->rx_rings, 0, sizeof(struct rx_ring) *
-					    adapter->num_queues);
-
-	for (i = 0; i < adapter->num_queues; i++) {
-
-		if (sem_init(&adapter->rx_rings[i].lock, 0, 1) != 0) {
-			error = errno;
-			goto rx_desc;
-		}
-
-		if (sem_wait(&adapter->rx_rings[i].lock) != 0) {
-			error = errno;
-			goto rx_desc;
-		}
-
-		ubuf.queue = i;
-		error = ioctl(dev, IGB_IOCTL_MAP_RX_RING, &ubuf);
-		if (error < 0) {
-
-			if(error == -EINVAL)
-				goto rx_fail;
-
-			error = EBUSY;
-			goto rx_desc;
-		}
-
-		if (ubuf.physaddr % 128)
-			printf("warning: rx ring addr (0x%lx) is not a 128 byte-aligned\n",
-				ubuf.physaddr);
-
-		adapter->rx_rings[i].rxdma.paddr = ubuf.physaddr;
-		adapter->rx_rings[i].rxdma.mmap_size = ubuf.mmap_size;
-		adapter->rx_rings[i].rx_base = NULL;
-		adapter->rx_rings[i].rx_base =
-			mmap(NULL, ubuf.mmap_size, PROT_READ | PROT_WRITE,
-			     MAP_SHARED, adapter->ldev, ubuf.pa);
-
-		if (adapter->rx_rings[i].rx_base == MAP_FAILED) {
-			error = -ENOMEM;
-			goto rx_desc;
-		}
-
-		adapter->rx_rings[i].adapter = adapter;
-		adapter->rx_rings[i].me = i;
-
-		adapter->num_rx_desc = ubuf.mmap_size /
-				       sizeof(union e1000_adv_rx_desc);
-
-		/*
-		 * num_rx_desc must be always a multiple of 8 because the value of
-		 * RDLEN must be a multipe of 128 and each descriptor has 16 bytes.
-		 */
-		if (adapter->num_rx_desc % 8)
-			printf("num_rx_desc(%d) is not a multiple of 8\n",
-				adapter->num_rx_desc);
-
-		memset((void *)adapter->rx_rings[i].rx_base, 0, ubuf.mmap_size);
-		adapter->rx_rings[i].rx_buffers =
-			(struct igb_rx_buffer *)
-				malloc(sizeof(struct igb_rx_buffer) *
-				       adapter->num_rx_desc);
-
-		if (adapter->rx_rings[i].rx_buffers == NULL) {
-			error = -ENOMEM;
-			goto rx_desc;
-		}
-
-		memset(adapter->rx_rings[i].rx_buffers, 0,
-		       sizeof(struct igb_rx_buffer) * adapter->num_rx_desc);
-
-		if (sem_post(&adapter->rx_rings[i].lock) != 0) {
-			error = errno;
-			goto rx_desc;
-		}
-	}
-
-	return 0;
-
-rx_desc:
-	for (i = 0; i < adapter->num_queues; i++) {
-		if (adapter->rx_rings[i].rx_base)
-			munmap(adapter->rx_rings[i].rx_base,
-			       adapter->rx_rings[i].rxdma.mmap_size);
-		ubuf.queue = i;
-		ioctl(dev, IGB_IOCTL_UNMAP_RX_RING, &ubuf);
-
-		sem_destroy(&adapter->rx_rings[i].lock);
-	};
-rx_fail:
-	free(adapter->rx_rings);
-	adapter->rx_rings = NULL;
-	return error;
-}
-
-static void igb_free_receive_ring(struct rx_ring *rxr)
-{
-	struct adapter *adapter = rxr->adapter;
-	struct igb_rx_buffer *rxbuf;
-	int i;
-
-	for (i = 0; i < adapter->num_rx_desc; i++) {
-		rxbuf = &rxr->rx_buffers[i];
-		rxbuf->next_eop = 0;
-		rxbuf->packet = NULL;
-	}
-}
-
-/* Initialize a receive ring. */
-static void igb_setup_receive_ring(struct rx_ring *rxr)
-{
-	struct adapter *adapter = rxr->adapter;
-
-	(void)sem_wait(&rxr->lock);
-
-	/* Clear the ring contents */
-	memset((void *)rxr->rx_base,  0,
-	       (sizeof(union e1000_adv_rx_desc)) * adapter->num_rx_desc);
-
-	memset(rxr->rx_buffers, 0, sizeof(struct igb_rx_buffer) *
-				   rxr->adapter->num_rx_desc);
-
-	/* Free current RX buffer structures */
-	igb_free_receive_ring(rxr);
-
-	/* Setup our descriptor indices */
-	rxr->next_to_check = 0;
-	rxr->next_to_refresh = 0;
-	rxr->rx_split_packets = 0;
-	rxr->rx_bytes = 0;
-
-	(void)sem_post(&rxr->lock);
-}
-
-/* Initialize all receive rings. */
-static void igb_setup_receive_structures(struct adapter *adapter)
-{
-	struct rx_ring *rxr = adapter->rx_rings;
-	int i;
-
-	for (i = 0; i < adapter->num_queues; i++, rxr++)
-		igb_setup_receive_ring(rxr);
-}
-
-/* Enable receive unit. */
-static void igb_initialize_receive_units(struct adapter *adapter)
-{
-	struct rx_ring *rxr = adapter->rx_rings;
-	struct e1000_hw *hw = &adapter->hw;
-	u32 rctl, rxcsum, srrctl = 0;
-	int i;
-
-	/*
-	 * Make sure receives are disabled while setting
-	 * up the descriptor ring
-	 */
-	rctl = E1000_READ_REG(hw, E1000_RCTL);
-	E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
-
-	rctl &= ~E1000_RCTL_LPE;
-	srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
-	srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
-	rctl |= E1000_RCTL_SZ_2048;
-
-	/* Setup the Base and Length of the Rx Descriptor Rings */
-	for (i = 0; i < adapter->num_queues; i++, rxr++) {
-		u64 bus_addr = rxr->rxdma.paddr;
-		u32 rxdctl;
-
-		/* Disable this Queue */
-		E1000_WRITE_REG(hw, E1000_RXDCTL(i), 0);
-
-		E1000_WRITE_REG(hw, E1000_RDLEN(i),
-				adapter->num_rx_desc *
-					sizeof(union e1000_adv_rx_desc));
-		E1000_WRITE_REG(hw, E1000_RDBAH(i),
-				(uint32_t)(bus_addr >> 32));
-		E1000_WRITE_REG(hw, E1000_RDBAL(i),
-				(uint32_t)bus_addr);
-		E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
-
-		/* Enable this Queue */
-		rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
-		rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
-		rxdctl &= 0xFFF00000;
-		rxdctl |= IGB_RX_PTHRESH;
-		rxdctl |= IGB_RX_HTHRESH << 8;
-		rxdctl |= IGB_RX_WTHRESH << 16;
-		E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
-	}
-
-	/*
-	 * Setup for RX MultiQueue
-	 * Non RSS setup
-	 */
-	rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
-	rxcsum |= E1000_RXCSUM_IPPCSE;
-	/*	rxcsum &= ~E1000_RXCSUM_TUOFL; */
-	E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
-
-	/* Setup the Receive Control Register */
-	rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
-	rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
-		E1000_RCTL_RDMTS_HALF;
-	/* Strip CRC bytes. */
-	rctl |= E1000_RCTL_SECRC;
-	/* Make sure VLAN Filters are off */
-	rctl &= ~E1000_RCTL_VFE;
-	/* Don't store bad packets */
-	rctl &= ~E1000_RCTL_SBP;
-
-	/* Enable Receives */
-	E1000_WRITE_REG(hw, E1000_RCTL, rctl);
-
-	/*
-	 * Setup the HW Rx Head and Tail Descriptor Pointers
-	 *   - needs to be after enable
-	 */
-	for (i = 0; i < adapter->num_queues; i++) {
-		rxr = &adapter->rx_rings[i];
-		E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
-		E1000_WRITE_REG(hw, E1000_RDT(i), rxr->next_to_refresh);
-	}
-}
-
-/* Free all receive rings. */
-static void igb_free_receive_structures(struct adapter *adapter)
-{
-	struct rx_ring *rxr = adapter->rx_rings;
-	int i;
-	struct igb_buf_cmd ubuf;
-
-	for (i = 0; i < adapter->num_queues; i++, rxr++) {
-		(void)sem_wait(&adapter->rx_rings[i].lock);
-
-		if (rxr->rx_base) {
-			memset(rxr->rx_base, 0, rxr->rxdma.mmap_size);
-			munmap(rxr->rx_base, rxr->rxdma.mmap_size);
-		}
-		ubuf.queue = i;
-		ioctl(adapter->ldev, IGB_IOCTL_UNMAP_RX_RING, &ubuf);
-		igb_free_receive_buffers(rxr);
-
-		(void)sem_destroy(&adapter->rx_rings[i].lock);
-	}
-
-	free(adapter->rx_rings);
-	adapter->rx_rings = NULL;
-}
-
-
-/* Free receive ring data structures. */
-static void igb_free_receive_buffers(struct rx_ring *rxr)
-{
-	struct adapter *adapter = rxr->adapter;
-	struct igb_rx_buffer *rxbuf;
-	int i;
-
-	/* Cleanup any existing buffers */
-	if (rxr->rx_buffers != NULL) {
-		for (i = 0; i < adapter->num_rx_desc; i++) {
-			rxbuf = &rxr->rx_buffers[i];
-			rxbuf->next_eop = 0;
-			rxbuf->packet = NULL;
-		}
-		if (rxr->rx_buffers != NULL) {
-			free(rxr->rx_buffers);
-			rxr->rx_buffers = NULL;
-		}
-	}
-}
-
-/*
- *  Refresh mbuf buffers for RX descriptor rings
- *   - now keeps its own state so discards due to resource
- *     exhaustion are unnecessary, if an mbuf cannot be obtained
- *     it just returns, keeping its placeholder, thus it can simply
- *     be recalled to try again.
- *
- */
-int igb_refresh_buffers(device_t *dev, u_int32_t idx,
-			 struct igb_packet **rxbuf_packets, u_int32_t num_bufs)
-{
-	struct igb_packet *cur_pkt;
-	struct adapter *adapter;
-	struct rx_ring *rxr;
-	u_int32_t i, j, bufs_used;
-	bool refreshed = FALSE;
-
-	if (dev == NULL)
-		return -EINVAL;
-
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -EINVAL;
-
-	if (adapter->active != 1)	// detach in progress
-		return -ENXIO;
-
-	if (rxbuf_packets == NULL)
-		return -EINVAL;
-
-	if (idx > 1)
-		return -EINVAL;
-
-	rxr = &adapter->rx_rings[idx];
-	if (rxr == NULL)
-		return -EINVAL;
-
-	if (sem_trywait(&rxr->lock) != 0)
-		return errno; /* EAGAIN */
-
-	if (adapter->active != 1) {
-		sem_post(&rxr->lock);
-		return -ENXIO;
-	}
-
-	i = j = rxr->next_to_refresh;
-	cur_pkt = *rxbuf_packets;
-
-	/*
-	 * Get one descriptor beyond
-	 * our work mark to control
-	 * the loop.
-	 */
-	if (++j == adapter->num_rx_desc)
-		j = 0;
-
-	bufs_used = 0;
-
-	while (bufs_used < num_bufs) {
-		if (!cur_pkt)
-			break;
-		rxr->rx_base[i].read.pkt_addr =
-			htole64(cur_pkt->map.paddr + cur_pkt->offset);
-		rxr->rx_buffers[i].packet = cur_pkt;
-
-		refreshed = TRUE; /* I feel wefreshed :) */
-
-		i = j; /* our next is precalculated */
-		rxr->next_to_refresh = i;
-		if (++j == adapter->num_rx_desc)
-			j = 0;
-		bufs_used++;
-		cur_pkt = cur_pkt->next;
-	}
-
-	if (refreshed) /* update tail */
-		E1000_WRITE_REG(&adapter->hw,
-				E1000_RDT(rxr->me), rxr->next_to_refresh);
-
-	if (sem_post(&rxr->lock) != 0)
-		return errno;
-
-	return 0;
-}
-
-
-/**********************************************************************
- *
- *  Examine each rx_buffer in the used queue. If the hardware is done
- *  processing the packet then return the linked list of associated resources.
- *
- **********************************************************************/
-int igb_receive(device_t *dev, unsigned int queue_index,
-					struct igb_packet **received_packets, u_int32_t *count)
-{
-	struct adapter *adapter;
-	struct rx_ring *rxr;
-	union e1000_adv_rx_desc *cur;
-	bool eop = FALSE;
-	u_int32_t staterr = 0;
-	u_int32_t desc    = 0;
-	u_int32_t max_pkt = 0;
-	struct igb_packet *curr_pkt = NULL;
-	struct igb_packet *prev_pkt = NULL;
-
-	if (dev == NULL)
-		return -EINVAL;
-
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -ENXIO;
-
-	if (adapter->active != 1)	// detach in progress
-		return -ENXIO;
-
-	if (queue_index > adapter->num_queues)
-		return -EINVAL;
-
-	rxr = &(adapter->rx_rings[queue_index]);
-	if (!rxr)
-		return -EINVAL;
-
-	if (count == NULL)
-		return -EINVAL;
-
-	max_pkt = *count;
-	*count  = 0;
-
-	if (received_packets == NULL)
-		return -EINVAL;
-
-	*received_packets = NULL; /* nothing reclaimed yet */
-
-	if (sem_trywait(&rxr->lock) != 0)
-		return errno; /* EAGAIN */
-
-	if (adapter->active != 1) {
-		sem_post(&rxr->lock);
-		return -ENXIO;
-	}
-
-	/* Main clean loop - receive packets until no more
-	 * received_packets[]
-	 */
-	for (desc = rxr->next_to_check; *count < max_pkt;) {
-		cur = &(rxr->rx_base[desc]);
-#ifdef DEBUG
-		if (i%2)
-			printf("\033[2A");
-
-		printf("desc.status_error=%x desc.length=%x desc.vlan=%x desc.rss=%x desc.pkt_info=%x desc.hdr_info=%x\n",
-				cur->wb.upper.status_error,
-				cur->wb.upper.length,
-				cur->wb.upper.vlan,
-				cur->wb.lower.hi_dword.rss,
-				cur->wb.lower.lo_dword.hs_rss.pkt_info,
-				cur->wb.lower.lo_dword.hs_rss.hdr_info);
-#endif
-		staterr = le32toh(cur->wb.upper.status_error);
-		if ((staterr & E1000_RXD_STAT_DD) == 0)
-			break;
-
-		cur->wb.upper.status_error = 0;
-
-		eop = ((staterr & E1000_RXD_STAT_EOP) ==
-				E1000_RXD_STAT_EOP);
-
-		if (eop) {
-			/*
-			 * Free the frame (all segments) if we're at EOP and
-			 * it's an error.
-			 *
-			 * The datasheet states that EOP + status is only valid
-			 * for the final segment in a multi-segment frame.
-			 */
-			if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
-				++rxr->rx_discarded;
-				printf ("discard error packet\n");
-				igb_refresh_buffers(dev, queue_index,
-						&rxr->rx_buffers[desc].packet, 1);
-			} else {
-				/*
-				 * add new packet to list of received packets
-				 * to return
-				 */
-				curr_pkt = rxr->rx_buffers[desc].packet;
-				curr_pkt->len = cur->wb.upper.length;
-
-				if (*received_packets == NULL)
-					*received_packets = curr_pkt;
-				if (prev_pkt)
-					prev_pkt->next = curr_pkt;
-				prev_pkt = curr_pkt;
-				(*count)++;
-
-				++rxr->rx_packets;
-			}
-		} else {
-			/* multi-segment frame is not supported yet */
-			++rxr->rx_discarded;
-			printf ("discard non-eop packet\n");
-			igb_refresh_buffers(dev, queue_index,
-					&rxr->rx_buffers[desc].packet, 1);
-		}
-next_desc:
-		/* Advance our pointers to the next descriptor. */
-		if (++desc == adapter->num_rx_desc)
-			desc = 0;
-	}
-
-	rxr->next_to_check = desc;
-
-	if (sem_post(&rxr->lock) != 0)
-		return errno;
-
-	if (*received_packets == NULL) {
-		/* nothing reclaimed yet */
-		errno = EAGAIN;
-		return errno;
-	}
-
-	return 0;
-}
-
-#define MAX_ITER 32
-#define MIN_WALLCLOCK_TSC_WINDOW 80 /* cycles */
-#define MIN_SYSCLOCK_WINDOW 72 /* ns */
-
-static inline void rdtscpll(uint64_t *val)
-{
-	uint32_t high, low;
-
-	__asm__ __volatile__("lfence;"
-						  "rdtsc;"
-						  : "=d"(high), "=a"(low)
-						  :
-						  : "memory");
-	*val = high;
-	*val = (*val << 32) | low;
-}
-
-static inline void __sync(void)
-{
-	__asm__ __volatile__("mfence;"
-						  :
-						  :
-						  : "memory");
-}
-
-int igb_get_wallclock(device_t *dev, u_int64_t *curtime, u_int64_t *rdtsc)
-{
-	u_int64_t t0 = 0, t1 = -1;
-	u_int32_t duration = -1;
-	u_int32_t timh, timl, tsauxc;
-	struct adapter *adapter;
-	struct e1000_hw *hw;
-	int error = 0;
-	int iter = 0;
-
-	if (dev == NULL)
-		return -EINVAL;
-
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -ENXIO;
-
-	hw = &adapter->hw;
-
-	if (igb_lock(dev) != 0)
-		return errno;
-
-	/* sample the timestamp bracketed by the RDTSC */
-	for (iter = 0; iter < MAX_ITER && t1 - t0 > MIN_WALLCLOCK_TSC_WINDOW;
-	     ++iter) {
-		tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
-		tsauxc |= E1000_TSAUXC_SAMP_AUTO;
-
-		/* Invalidate AUXSTMPH/L0 */
-		E1000_READ_REG(hw, E1000_AUXSTMPH0);
-		rdtscpll(&t0);
-		E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
-		rdtscpll(&t1);
-
-		if (t1 - t0 < duration) {
-			duration = t1 - t0;
-			timl = E1000_READ_REG(hw, E1000_AUXSTMPL0);
-			timh = E1000_READ_REG(hw, E1000_AUXSTMPH0);
-
-			if (curtime)
-				*curtime = (u_int64_t)timh * 1000000000 +
-					   (u_int64_t)timl;
-			if (rdtsc)
-				/* average */
-				*rdtsc = (t1 - t0) / 2 + t0;
-		}
-	}
-
-	if (igb_unlock(dev) != 0) {
-		error = errno;
-		goto err;
-	}
-
-	/* Return the window size * -1 */
-	return -duration;
-
-err:
-	return error;
-}
-
-struct timespec timespec_subtract(struct timespec *a, struct timespec *b)
-{
-	a->tv_nsec = a->tv_nsec - b->tv_nsec;
-	if (a->tv_nsec < 0) {
-		/* borrow */
-		a->tv_nsec += 1000000000;
-		--a->tv_sec;
-	}
-
-	a->tv_sec = a->tv_sec - b->tv_sec;
-	return *a;
-}
-
-struct timespec timespec_addns(struct timespec *a, unsigned long addns)
-{
-	a->tv_nsec = a->tv_nsec + (addns % 1000000000);
-	if (a->tv_nsec > 1000000000) {
-		/* carry */
-		a->tv_nsec -= 1000000000;
-		++a->tv_sec;
-	}
-
-	a->tv_sec = a->tv_sec + addns/1000000000;
-	return *a;
-}
-
-static inline u_int32_t TS2NS(struct timespec ts)
-{
-    return ((ts.tv_sec*1000000000)+ts.tv_nsec);
-}
-
-int igb_gettime(device_t *dev, clockid_t clk_id, u_int64_t *curtime,
-		struct timespec *system_time)
-{
-	struct timespec	t0 = { 0, 0 }, t1 = { .tv_sec = 4, .tv_nsec = 0 };
-	u_int32_t timh, timl, tsauxc;
-	u_int32_t duration = -1;
-	struct adapter *adapter;
-	struct e1000_hw *hw;
-	int error = 0;
-	int iter = 0;
-
-	if (dev == NULL)
-		return -EINVAL;
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -ENXIO;
-
-	hw = &adapter->hw;
-
-	if (igb_lock(dev) != 0)
-		return errno;
-
-	/* sample the timestamp bracketed by the clock_gettime() */
-	for (iter = 0; iter < MAX_ITER && duration > MIN_SYSCLOCK_WINDOW;
-	     ++iter) {
-		u_int32_t duration_c;
-
-		tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
-		tsauxc |= E1000_TSAUXC_SAMP_AUTO;
-
-		/* Invalidate AUXSTMPH/L0 */
-		E1000_READ_REG(hw, E1000_AUXSTMPH0);
-		clock_gettime(clk_id, &t0);
-		E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
-		__sync();
-		clock_gettime(clk_id, &t1);
-
-		timespec_subtract(&t1, &t0);
-		duration_c = TS2NS(t1);
-		if (duration_c < duration) {
-			duration = duration_c;
-			timl = E1000_READ_REG(hw, E1000_AUXSTMPL0);
-			timh = E1000_READ_REG(hw, E1000_AUXSTMPH0);
-
-			if (curtime)
-				*curtime = (u_int64_t)timh * 1000000000 +
-					   (u_int64_t)timl;
-			if (system_time)
-				*system_time =
-					timespec_addns(&t0, duration/2);
-		}
-	}
-
-	if (igb_unlock(dev) != 0) {
-		error = errno;
-		goto err;
-	}
-	/* Return the window size * -1 */
-	return -duration;
-
-err:
-	return error;
-}
-
-int igb_set_class_bandwidth(device_t *dev, u_int32_t class_a, u_int32_t class_b,
-			    u_int32_t tpktsz_a, u_int32_t tpktsz_b)
-{
-	u_int32_t tqavctrl;
-	u_int32_t tqavcc0, tqavcc1;
-	u_int32_t tqavhc0, tqavhc1;
-	u_int32_t class_a_idle, class_b_idle;
-	u_int32_t linkrate;
-	struct adapter *adapter;
-	struct e1000_hw *hw;
-	struct igb_link_cmd link = {0};
-	int err;
-	float class_a_percent, class_b_percent;
-	int error = 0;
-
-	if (dev == NULL)
-		return -EINVAL;
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -ENXIO;
-
-	hw = &adapter->hw;
-
-	/* get current link speed */
-
-	err = ioctl(adapter->ldev, IGB_LINKSPEED, &link);
-
-	if (err)
-		return -ENXIO;
-
-	if (link.up == 0)
-		return -EINVAL;
-
-	if (link.speed < 100)
-		return -EINVAL;
-
-	if (link.duplex != FULL_DUPLEX)
-		return -EINVAL;
-
-	if (tpktsz_a < 64)
-		tpktsz_a = 64; /* minimum ethernet frame size */
-
-	if (tpktsz_a > 1500)
-		return -EINVAL;
-
-	if (tpktsz_b < 64)
-		tpktsz_b = 64; /* minimum ethernet frame size */
-
-	if (tpktsz_b > 1500)
-		return -EINVAL;
-
-	if (igb_lock(dev) != 0)
-		return errno;
-
-	tqavctrl = E1000_READ_REG(hw, E1000_TQAVCTRL);
-
-	if ((class_a + class_b) == 0) {
-		/* disable the Qav shaper */
-		tqavctrl &= ~E1000_TQAVCTRL_TX_ARB;
-		E1000_WRITE_REG(hw, E1000_TQAVCTRL, tqavctrl);
-		goto unlock;
-	}
-
-	tqavcc0 = E1000_TQAVCC_QUEUEMODE;
-	tqavcc1 = E1000_TQAVCC_QUEUEMODE;
-
-	linkrate = E1000_TQAVCC_LINKRATE;
-
-	/*
-	 * class_a and class_b are the packets-per-(respective)observation
-	 * interval (125 usec for class A, 250 usec for class B)
-	 * these parameters are also used when establishing the MSRP
-	 * talker advertise attribute (as well as the tpktsize)
-	 *
-	 * note that class_a and class_b are independent of the media
-	 * rate. For our idle slope calculation, we need to scale the
-	 * (tpktsz + (media overhead)) * rate -> percentage of media rate.
-	 */
-
-	/* 12=Ethernet IPG,
-	 * 8=Preamble+Start of Frame,
-	 * 18=Mac Header with VLAN+Etype,
-	 * 4=CRC
-	 */
-	class_a_percent = (float)((tpktsz_a + (12 + 8 + 18 + 4)) * class_a);
-	class_b_percent = (float)((tpktsz_b + (12 + 8 + 18 + 4)) * class_b);
-
-	class_a_percent /= 0.000125; /* class A observation window */
-	class_b_percent /= 0.000250; /* class B observation window */
-
-	if (link.speed == 100) {
-		/* bytes-per-sec @ 100Mbps */
-		class_a_percent /= (100000000.0 / 8);
-		class_b_percent /= (100000000.0 / 8);
-		class_a_idle = (u_int32_t)(class_a_percent * 0.2 *
-				(float)linkrate + 0.5);
-		class_b_idle = (u_int32_t)(class_b_percent * 0.2 *
-				(float)linkrate + 0.5);
-	} else {
-		/* bytes-per-sec @ 1Gbps */
-		class_a_percent /= (1000000000.0 / 8);
-		class_b_percent /= (1000000000.0 / 8);
-		class_a_idle = (u_int32_t)(class_a_percent *
-				2.0 * (float)linkrate + 0.5);
-		class_b_idle = (u_int32_t)(class_b_percent * 2.0 *
-				(float)linkrate + 0.5);
-	}
-
-	if ((class_a_percent + class_b_percent) > 0.75) {
-		error = -EINVAL;
-		goto unlock;
-	}
-	tqavcc0 |= class_a_idle;
-	tqavcc1 |= class_b_idle;
-
-	/*
-	 * hiCredit is the number of idleslope credits accumulated due to delay
-	 *
-	 * we assume the maxInterferenceSize is 18 + 4 + 1500 (1522).
-	 * Note: if EEE is enabled, we should use for maxInterferenceSize
-	 * the overhead of link recovery (a media-specific quantity).
-	 */
-	tqavhc0 = 0x80000000 + (class_a_idle * 1522 / linkrate); /* L.10 */
-
-	/*
-	 * Class B high credit is is the same, except the delay
-	 * is the MaxBurstSize of Class A + maxInterferenceSize of non-SR
-	 * traffic
-	 *
-	 * L.41
-	 * max Class B delay = (1522 + tpktsz_a) / (linkrate - class_a_idle)
-	 */
-
-	tqavhc1 = 0x80000000 + (class_b_idle * ((1522 + tpktsz_a) /
-						(linkrate - class_a_idle)));
-
-	/* implicitly enable the Qav shaper */
-	tqavctrl |= E1000_TQAVCTRL_TX_ARB;
-	E1000_WRITE_REG(hw, E1000_TQAVHC(0), tqavhc0);
-	E1000_WRITE_REG(hw, E1000_TQAVCC(0), tqavcc0);
-	E1000_WRITE_REG(hw, E1000_TQAVHC(1), tqavhc1);
-	E1000_WRITE_REG(hw, E1000_TQAVCC(1), tqavcc1);
-	E1000_WRITE_REG(hw, E1000_TQAVCTRL, tqavctrl);
-
-unlock:
-	if (igb_unlock(dev) != 0)
-		error = errno;
-
-	return error;
-}
-
-int igb_set_class_bandwidth2(device_t *dev, u_int32_t class_a_bytes_per_second,
-			     u_int32_t class_b_bytes_per_second)
-{
-	u_int32_t tqavctrl;
-	u_int32_t tqavcc0, tqavcc1;
-	u_int32_t tqavhc0, tqavhc1;
-	u_int32_t class_a_idle, class_b_idle;
-	u_int32_t linkrate;
-	u_int32_t tpktsz_a;
-	int temp;
-	struct adapter *adapter;
-	struct e1000_hw *hw;
-	struct igb_link_cmd link = {0};
-	int err;
-	float class_a_percent, class_b_percent;
-	int error = 0;
-
-	if (dev == NULL)
-		return -EINVAL;
-
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -ENXIO;
-
-	hw = &adapter->hw;
-
-	/* get current link speed */
-
-	err = ioctl(adapter->ldev, IGB_LINKSPEED, &link);
-
-	if (err)
-		return -ENXIO;
-
-	if (link.up == 0)
-		return -EINVAL;
-
-	if (link.speed < 100)
-		return -EINVAL;
-
-	if (link.duplex != FULL_DUPLEX)
-		return -EINVAL;
-
-	if (igb_lock(dev) != 0)
-		return errno;
-
-	tqavctrl = E1000_READ_REG(hw, E1000_TQAVCTRL);
-
-	if ((class_a_bytes_per_second + class_b_bytes_per_second) == 0) {
-		/* disable the Qav shaper */
-		tqavctrl &= ~E1000_TQAVCTRL_TX_ARB;
-		E1000_WRITE_REG(hw, E1000_TQAVCTRL, tqavctrl);
-		goto unlock;
-	}
-
-	tqavcc0 = E1000_TQAVCC_QUEUEMODE;
-	tqavcc1 = E1000_TQAVCC_QUEUEMODE;
-
-	linkrate = E1000_TQAVCC_LINKRATE;
-
-	/* it is needed for Class B high credit calculations
-	 * so we need to guess it
-	 * TODO: check if it is right
-	 */
-	temp = class_a_bytes_per_second / 8000 - (12 + 8 + 18 + 4);
-	if (temp > 0)
-		tpktsz_a = temp;
-	else
-		tpktsz_a = 0;
-	/* TODO: in igb_set_class_bandwidth if given tpktsz_a < 64
-	 * (for example 0) then the 64 value will be used even if
-	 * there is no class_A streams (class_a is 0)
-	 * I suspect that this is error, so we use 0 here.
-	 */
-
-	class_a_percent = class_a_bytes_per_second;
-	class_b_percent = class_b_bytes_per_second;
-
-	if (link.speed == 100) {
-		/* bytes-per-sec @ 100Mbps */
-		class_a_percent /= (100000000.0 / 8);
-		class_b_percent /= (100000000.0 / 8);
-		class_a_idle = (u_int32_t)(class_a_percent * 0.2 *
-				(float)linkrate + 0.5);
-		class_b_idle = (u_int32_t)(class_b_percent * 0.2 *
-				(float)linkrate + 0.5);
-	} else {
-		/* bytes-per-sec @ 1Gbps */
-		class_a_percent /= (1000000000.0 / 8);
-		class_b_percent /= (1000000000.0 / 8);
-		class_a_idle = (u_int32_t)(class_a_percent * 2.0 *
-				(float)linkrate + 0.5);
-		class_b_idle = (u_int32_t)(class_b_percent * 2.0 *
-				(float)linkrate + 0.5);
-	}
-
-	if ((class_a_percent + class_b_percent) > 0.75) {
-		error = -EINVAL;
-		goto unlock;
-	}
-	tqavcc0 |= class_a_idle;
-	tqavcc1 |= class_b_idle;
-
-	/*
-	 * hiCredit is the number of idleslope credits accumulated due to delay
-	 *
-	 * we assume the maxInterferenceSize is 18 + 4 + 1500 (1522).
-	 * Note: if EEE is enabled, we should use for maxInterferenceSize
-	 * the overhead of link recovery (a media-specific quantity).
-	 */
-	tqavhc0 = 0x80000000 + (class_a_idle * 1522 / linkrate); /* L.10 */
-
-	/*
-	 * Class B high credit is is the same, except the delay
-	 * is the MaxBurstSize of Class A + maxInterferenceSize of non-SR
-	 * traffic
-	 *
-	 * L.41
-	 * max Class B delay = (1522 + tpktsz_a) / (linkrate - class_a_idle)
-	 */
-
-	tqavhc1 = 0x80000000 + (class_b_idle * ((1522 + tpktsz_a) /
-				(linkrate - class_a_idle)));
-
-	/* implicitly enable the Qav shaper */
-	tqavctrl |= E1000_TQAVCTRL_TX_ARB;
-	E1000_WRITE_REG(hw, E1000_TQAVHC(0), tqavhc0);
-	E1000_WRITE_REG(hw, E1000_TQAVCC(0), tqavcc0);
-	E1000_WRITE_REG(hw, E1000_TQAVHC(1), tqavhc1);
-	E1000_WRITE_REG(hw, E1000_TQAVCC(1), tqavcc1);
-	E1000_WRITE_REG(hw, E1000_TQAVCTRL, tqavctrl);
-
-unlock:
-	if (igb_unlock(dev) != 0)
-		error = errno;
-
-	return error;
-}
-
-int igb_get_mac_addr(device_t *dev, u_int8_t mac_addr[ETH_ADDR_LEN])
-{
-	struct adapter *adapter;
-	struct e1000_hw *hw;
-
-	if (dev == NULL)
-		return -EINVAL;
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -ENXIO;
-
-	hw = &adapter->hw;
-
-	memcpy(mac_addr, hw->mac.addr, ETH_ADDR_LEN);
-	return 0;
-}
-
-int igb_setup_flex_filter(device_t *dev, unsigned int queue_id,
-			  unsigned int filter_id, unsigned int filter_len,
-			  u_int8_t *filter, u_int8_t *mask)
-{
-	struct adapter *adapter;
-	struct e1000_hw *hw;
-	u32 i = 0, j, k;
-	u32 fhft, wufc;
-	u_int8_t *filter_buf = filter;
-
-	if (dev == NULL)
-		return -EINVAL;
-
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -ENXIO;
-
-	if (filter_id > 7)
-		return -EINVAL;
-
-	if (queue_id > 1)
-		return -EINVAL;
-
-	if (filter_len > 128)
-		return -EINVAL;
-
-	if (filter_len % 8) {
-		unsigned int aligned_filter_len = ((filter_len + (8 - 1)) / 8) * 8;
-
-		printf ("warning: filter_len(%d) should be a 8 byte aligned value\n",
-					filter_len);
-
-		filter_buf = calloc(1, aligned_filter_len);
-		if (!filter_buf)
-			return -ENOMEM;
-
-		memcpy((void*)filter_buf, (void*)filter, (size_t)filter_len);
-		filter_len = aligned_filter_len;
-	}
-
-	hw = &adapter->hw;
-
-	/*
-	 * example pattern to set to match on the following in a Magic Packet
-	 * 0x00: xx xx xx xx xx xx xx xx  xx xx xx xx 08 00 45 00
-	 * 0x10: xx xx xx xx xx xx xx 11  xx xx xx xx xx xx xx xx
-	 * 0x20: xx xx xx xx 00 07 00 86  xx xx ff ff ff ff ff ff
-	 * 0x30: m0 m1 m2 m3 m4 m5 xx xx  xx xx xx xx xx xx xx xx
-	 *
-	 * Where m0-m5 are the 6 bytes of the mac address in network order
-	 *
-	 * example code follows
-	 *
-	 * ethertype should be IP which is 0x0800
-	 * filter[0x0C] = 0x08;
-	 * filter[0x0D] = 0x00;
-
-	 * verify IPv4 and header length 20
-	 * filter[0x0E] = 0x45;
-	 * filter[0x0F] = 0x00;
-	 * mask[1] = 0xF0;
-
-	 * verify L3 protocol is UDP
-	 * filter[0x17] = 0x11;
-	 * mask[2] = 0x80;
-
-	 * verify source and destination port numbers
-	 * filter[0x24] = 0x00;
-	 * filter[0x25] = 0x07;
-	 * filter[0x26] = 0x00;
-	 * filter[0x27] = 0x86;
-	 * mask[4] = 0xF0;
-
-* add start filter of 6 bytes all 0xFF
-	 * memset(&filter[0x2a], 0xff, 6);
-	 * mask[5] = 0xFC;
-
-	 * add mac address
-	 * memcpy(&filter[0x30], hw->mac.addr, 6);
-	 * mask[6] |= 0x3F;
-	 */
-
-	while (i < filter_len) {
-		for (j = 0; j < 8; j += 4) {
-			fhft = 0;
-			for (k = 0; k < 4; k++)
-				fhft |= ((u32)(filter_buf[i + j + k])) << (k * 8);
-			E1000_WRITE_REG_ARRAY(hw, E1000_FHFT(filter_id),
-					(i/2) + (j/4), fhft);
-		}
-		E1000_WRITE_REG_ARRAY(hw, E1000_FHFT(filter_id),
-				(i/2) + 2, mask[i/8]);
-		i += 8;
-	}
-
-	E1000_WRITE_REG_ARRAY(hw, E1000_FHFT(filter_id),
-			63, (queue_id << 8) | filter_len);
-
-	E1000_WRITE_REG(hw, E1000_WUC, 0x21); /* XXX is this right ? */
-
-	wufc = E1000_READ_REG(hw, E1000_WUFC);
-	wufc |= (E1000_WUFC_FLX0 << filter_id) | E1000_WUFC_FLEX_HQ;
-	E1000_WRITE_REG(hw, E1000_WUFC, wufc);
-
-	if (filter_buf && (filter_buf != filter))
-		free(filter_buf);
-
-	return 0;
-}
-
-int igb_clear_flex_filter(device_t *dev, unsigned int filter_id)
-{
-	struct adapter *adapter;
-	struct e1000_hw *hw;
-	u32 wufc;
-
-	if (dev == NULL)
-		return -EINVAL;
-
-	adapter = (struct adapter *)dev->private_data;
-	if (adapter == NULL)
-		return -ENXIO;
-
-	if (filter_id > 7)
-		return -EINVAL;
-
-
-	hw = &adapter->hw;
-
-	wufc = E1000_READ_REG(hw, E1000_WUFC);
-	wufc &= ~(E1000_WUFC_FLX0 << filter_id);
-	E1000_WRITE_REG(hw, E1000_WUFC, wufc);
-
-	return 0;
-}
-
-static int igb_create_lock(struct adapter *adapter)
-{
-	int error = -1;
-	int fd = -1;
-	bool locked = false;
-	struct flock fl;
-	struct stat stat;
-	mode_t fmode = S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP;
-
-	bool attr_allocated = false;
-	pthread_mutexattr_t attr;
-
-	if (!adapter) {
-		errno = EINVAL;
-		goto err;
-	}
-
-	if (adapter->memlock) {	// already created
-		errno = EINVAL;
-		goto err;
-	}
-
-	/*
-	 * inter-process syncronization
-	 *
-	 * Use a posix mutex for inter-process syncronization
-	 *
-	 * igb lib used a posix named semaphore to protect concurrent accesses
-	 * from multiple processes. But since the posix semaphore cannot be
-	 * automatically released on process termination, if some process holding
-	 * the semaphore terminates without releasing it, other processes cannot
-	 * acquire the semaphore afterward. This could potentially cause a denial
-	 * of service condition.
-	 */
-
-	fd = shm_open(IGB_SEM, O_RDWR|O_CREAT|O_CLOEXEC, fmode);
-	if (fd < 0)
-		goto err;
-
-	(void) fchmod(fd, fmode); // just to make sure fmode is applied
-
-	// shared memory holding the mutex instance
-	adapter->memlock = (pthread_mutex_t*) mmap(NULL, sizeof(pthread_mutex_t),
-							PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
-	if (!adapter->memlock)
-		goto err;
-
-	/*
-	 * Exclusive access lock
-	 *
-	 * At this moment the posix mutex in the shared memory might not be
-	 * available yet and it needs initialization. We need to protect the
-	 * initialization code otherwise multiple processes could concurrently
-	 * do initialization. Create an exclusive access section by applying
-	 * the file-lock against the shared memory file.
-	 *
-	 * By the way the file-lock itself could safely be used for inter-process
-	 * synchronization because it also automatically gets unlocked on process
-	 * termination. But it is slower than the posix-mutex. So we should use
-	 * the posix-mutex once its initialization done.
-	 */
-	fl.l_type = F_WRLCK;
-	fl.l_whence = SEEK_SET;
-	fl.l_start = 0;
-	fl.l_len = 1;
-	fl.l_pid = getpid();
-
-	if (fcntl(fd, F_SETLKW, &fl) != 0)
-		goto err;
-
-	locked = true;
-
-	if (fstat(fd, &stat) != 0)
-		goto err;
-
-	if (stat.st_size == 0) { // file is empty, do initialization
-		/*
-		 * file-size becomes non-zero and given that when other processes
-		 * attach lib igb we can skip the initialization code for the mutex.
-		 */
-		if (ftruncate(fd, sizeof(pthread_mutex_t)) != 0)
-			goto err;
-
-		if (pthread_mutexattr_init(&attr) != 0)
-			goto err;
-
-		attr_allocated = true;
-
-		// to be used for both inter-process and inter-thread synchronization
-		if (pthread_mutexattr_setpshared(&attr, PTHREAD_PROCESS_SHARED) != 0)
-			goto err;
-
-		// to avoid dead lock due to a dead process holding the semaphore
-		if (pthread_mutexattr_setrobust(&attr, PTHREAD_MUTEX_ROBUST) != 0)
-			goto err;
-
-		if (pthread_mutex_init(adapter->memlock, &attr) != 0)
-			goto err;
-	}
-
-	error = 0;
-err:
-	// no actual effect but to avoid a warning from a static code analyzer
-	if (attr_allocated)
-		(void) pthread_mutexattr_destroy(&attr);
-
-	if (error != 0) {
-		error = -errno;
-		if (adapter && adapter->memlock) {
-			(void) munmap(adapter->memlock, sizeof(pthread_mutex_t));
-			adapter->memlock = NULL;
-		}
-	}
-
-	if (fd >= 0) {
-		if (locked) {
-			fl.l_type = F_UNLCK;
-			(void) fcntl(fd, F_SETLK, &fl);
-		}
-		(void) close(fd);
-	}
-
-	return error;
-}
diff --git a/lib/igb/igb.h b/lib/igb/igb.h
deleted file mode 100644
index 85b8d74e..00000000
--- a/lib/igb/igb.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/******************************************************************************
-
-  Copyright (c) 2001-2016, Intel Corporation
-  All rights reserved.
-
-  Redistribution and use in source and binary forms, with or without
-  modification, are permitted provided that the following conditions are met:
-
-   1. Redistributions of source code must retain the above copyright notice,
-      this list of conditions and the following disclaimer.
-
-   2. Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-
-   3. Neither the name of the Intel Corporation nor the names of its
-      contributors may be used to endorse or promote products derived from
-      this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE.
-
-******************************************************************************/
-/*$FreeBSD$*/
-
-#ifndef _IGB_H_DEFINED_
-#define _IGB_H_DEFINED_
-
-#include <sys/types.h>
-
-struct resource {
-	u_int64_t paddr;
-	u_int32_t mmap_size;
-};
-
-/* datastructure used to transmit a timed packet */
-#define IGB_PACKET_LAUNCHTIME	1	/* control when packet transmitted */
-#define IGB_PACKET_LATCHTIME	2	/* grab a timestamp of transmission */
-
-struct igb_packet {
-	struct resource map;	/* bus_dma map for packet */
-	unsigned int offset;	/* offset into physical page */
-	void *vaddr;
-	u_int32_t len;
-	u_int32_t flags;
-	u_int64_t attime;	/* launchtime */
-	u_int64_t dmatime;	/* when dma tx desc wb*/
-	struct igb_packet *next;	/* used in the clean routine */
-};
-
-typedef struct _device_t {
-	void *private_data;
-	u_int16_t pci_vendor_id;
-	u_int16_t pci_device_id;
-	u_int16_t domain;
-	u_int8_t bus;
-	u_int8_t dev;
-	u_int8_t func;
-} device_t;
-
-/*
- * Bus dma allocation structure used by
- * e1000_dma_malloc_page and e1000_dma_free_page.
- */
-struct igb_dma_alloc {
-	u_int64_t dma_paddr;
-	void *dma_vaddr;
-	unsigned int mmap_size;
-};
-
-int igb_probe(device_t *dev);
-int igb_attach(char *dev_path, device_t *pdev);
-int igb_attach_rx(device_t *pdev);
-int igb_attach_tx(device_t *pdev);
-int igb_detach(device_t *dev);
-int igb_suspend(device_t *dev);
-int igb_resume(device_t *dev);
-int igb_init(device_t *dev);
-int igb_dma_malloc_page(device_t *dev, struct igb_dma_alloc *page);
-void igb_dma_free_page(device_t *dev, struct igb_dma_alloc *page);
-int igb_xmit(device_t *dev, unsigned int queue_index,
-	     struct igb_packet *packet);
-int igb_refresh_buffers(device_t *dev, u_int32_t idx,
-			 struct igb_packet **rxbuf_packets,
-			 u_int32_t num_bufs);
-int igb_receive(device_t *dev, unsigned int queue_index, 
-	     struct igb_packet **received_packets, u_int32_t *count);
-void igb_clean(device_t *dev, struct igb_packet **cleaned_packets);
-int igb_get_wallclock(device_t *dev, u_int64_t *curtime, u_int64_t *rdtsc);
-int igb_gettime(device_t *dev, clockid_t clk_id, u_int64_t *curtime,
-		struct timespec *system_time);
-int igb_set_class_bandwidth(device_t *dev, u_int32_t class_a, u_int32_t class_b,
-			    u_int32_t tpktsz_a, u_int32_t tpktsz_b);
-int igb_set_class_bandwidth2(device_t *dev, u_int32_t class_a_bytes_per_second,
-			     u_int32_t class_b_bytes_per_second);
-int igb_setup_flex_filter(device_t *dev, unsigned int queue_id,
-			  unsigned int filter_id, unsigned int filter_len,
-			  u_int8_t *filter, u_int8_t *mask);
-int igb_clear_flex_filter(device_t *dev, unsigned int filter_id);
-void igb_trigger(device_t *dev, u_int32_t data);
-void igb_readreg(device_t *dev, u_int32_t reg, u_int32_t *data);
-void igb_writereg(device_t *dev, u_int32_t reg, u_int32_t data);
-
-int igb_lock(device_t *dev);
-int igb_unlock(device_t *dev);
-
-int igb_get_mac_addr(device_t *dev, u_int8_t mac_addr[6]);
-
-#endif /* _IGB_H_DEFINED_ */
diff --git a/lib/igb/igb_internal.h b/lib/igb/igb_internal.h
deleted file mode 100644
index 24dd7496..00000000
--- a/lib/igb/igb_internal.h
+++ /dev/null
@@ -1,257 +0,0 @@
-/******************************************************************************
-
-  Copyright (c) 2001-2016, Intel Corporation
-  All rights reserved.
-
-  Redistribution and use in source and binary forms, with or without
-  modification, are permitted provided that the following conditions are met:
-
-   1. Redistributions of source code must retain the above copyright notice,
-      this list of conditions and the following disclaimer.
-
-   2. Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-
-   3. Neither the name of the Intel Corporation nor the names of its
-      contributors may be used to endorse or promote products derived from
-      this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE.
-
-******************************************************************************/
-/*$FreeBSD$*/
-
-#ifndef _IGB_INTERNAL_H_DEFINED_
-#define _IGB_INTERNAL_H_DEFINED_
-
-#include "igb.h"
-
-/*
- * Micellaneous constants
- */
-#define IGB_VENDOR_ID			0x8086
-
-#define IGB_DEFAULT_PBA			0x00000030
-
-#define PCI_ANY_ID                      (~0U)
-#define ETHER_ALIGN                     2
-#define IGB_TX_BUFFER_SIZE		((uint32_t) 1514)
-
-
-#define IGB_RX_PTHRESH		8
-#define IGB_RX_HTHRESH		8
-#define IGB_RX_WTHRESH          4
-
-#define IGB_TX_PTHRESH		8
-#define IGB_TX_HTHRESH		1
-#define IGB_TX_WTHRESH		16
-
-/*
- * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
- * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
- * also optimize cache line size effect. H/W supports up to cache line size 128.
- */
-#define IGB_DBA_ALIGN			128
-
-#define SPEED_MODE_BIT (1<<21)		/* On PCI-E MACs only */
-
-#define IGB_MAX_SCATTER		64
-#define IGB_VFTA_SIZE		128
-#define IGB_BR_SIZE		4096	/* ring buf size */
-#define IGB_TSO_SIZE		(65535 + sizeof(struct ether_vlan_header))
-#define IGB_TSO_SEG_SIZE	4096	/* Max dma segment size */
-#define IGB_HDR_BUF		128
-#define IGB_PKTTYPE_MASK	0x0000FFF0
-#define ETH_ZLEN		60
-#define ETH_ADDR_LEN		6
-
-
-/* Queue bit defines */
-#define IGB_QUEUE_IDLE                  1
-#define IGB_QUEUE_WORKING               2
-#define IGB_QUEUE_HUNG                  4
-#define IGB_QUEUE_DEPLETED              8
-
-/*
- * This parameter controls when the driver calls the routine to reclaim
- * transmit descriptors. Cleaning earlier seems a win.
- **/
-#define IGB_TX_CLEANUP_THRESHOLD        (adapter->num_tx_desc / 2)
-#define IGB_QUEUE_THRESHOLD		(2)
-
-/* Precision Time Sync (IEEE 1588) defines */
-#define ETHERTYPE_IEEE1588	0x88F7
-#define PICOSECS_PER_TICK	20833
-#define TSYNC_PORT		319 /* UDP port for the protocol */
-
-struct igb_tx_buffer {
-	int next_eop; /* Index of the desc to watch */
-	struct igb_packet *packet; /* app-relevant handle */
-};
-
-/*
- * Transmit ring: one per queue
- */
-struct tx_ring {
-	struct adapter *adapter;
-	u32 me;
-	struct resource txdma;
-	struct e1000_tx_desc *tx_base;
-	struct igb_tx_buffer *tx_buffers;
-	u32 next_avail_desc;
-	u32 next_to_clean;
-
-	u16 tx_avail;
-
-	u32 bytes;
-	u32 packets;
-
-	int tdt;
-	int tdh;
-	u64 no_desc_avail;
-	u64 tx_packets;
-	int queue_status;
-};
-
-struct igb_rx_buffer {
-	int next_eop; /* Index of the desc to watch */
-	struct igb_packet *packet; /* app-relevant handle */
-};
-
-/*
- * Receive ring: one per queue
- */
-struct rx_ring {
-	struct adapter *adapter;
-	u32 me;
-	struct resource rxdma;
-	union e1000_adv_rx_desc *rx_base;
-	bool hdr_split;
-	u32 next_to_refresh;
-	u32 next_to_check;
-	struct igb_rx_buffer *rx_buffers;
-	u32 bytes;
-	u32 packets;
-	int rdt;
-	int rdh;
-
-	/* Soft stats */
-	u64 rx_split_packets;
-	u64 rx_discarded;
-	u64 rx_packets;
-	u64 rx_bytes;
-
-	sem_t lock;
-};
-
-struct adapter {
-	struct e1000_hw hw;
-
-	pthread_mutex_t *memlock;
-
-	int ldev; /* file descriptor to igb */
-
-	struct resource csr;
-	int max_frame_size;
-	int min_frame_size;
-	int igb_insert_vlan_header;
-	u16 num_queues;
-
-	/* Interface queues */
-	struct igb_queue *queues;
-
-	/*
-	 * rings
-	 */
-	struct tx_ring *tx_rings;
-	u16 num_tx_desc;
-	struct rx_ring *rx_rings;
-	u16 num_rx_desc;
-#ifdef IGB_IEEE1588
-	/* IEEE 1588 precision time support */
-	struct cyclecounter cycles;
-	struct nettimer clock;
-	struct nettime_compare compare;
-	struct hwtstamp_ctrl hwtstamp;
-#endif
-	int active;
-};
-
-/*
- * vendor_info_array
- *
- * This array contains the list of Subvendor/Subdevice IDs on which the driver
- * should load.
- *
- */
-typedef struct _igb_vendor_info_t {
-	unsigned int vendor_id;
-	unsigned int device_id;
-	unsigned int subvendor_id;
-	unsigned int subdevice_id;
-	unsigned int index;
-} igb_vendor_info_t;
-
-/* external API requirements */
-#define IGB_BIND       _IOW('E', 200, int)
-#define IGB_UNBIND     _IOW('E', 201, int)
-#define IGB_MAPRING    _IOW('E', 202, int)
-#define IGB_MAP_TX_RING    IGB_MAPRING
-#define IGB_UNMAPRING  _IOW('E', 203, int)
-#define IGB_UNMAP_TX_RING  IGB_UNMAPRING
-#define IGB_MAPBUF     _IOW('E', 204, int)
-#define IGB_UNMAPBUF   _IOW('E', 205, int)
-#define IGB_LINKSPEED  _IOW('E', 206, int)
-#define IGB_MAP_RX_RING    _IOW('E', 207, int)
-#define IGB_UNMAP_RX_RING  _IOW('E', 208, int)
-
-/*set of newly defined ioctl calls - new libigb compatibility
-  each of them is an equivalent of the old ioctl
-  changed numberiong convention: new_ioctl = old_ioctl + 100*/
-
-#define IGB_IOCTL_MAPRING	_IOW('E', 302, int)
-#define IGB_IOCTL_MAP_TX_RING	 IGB_IOCTL_MAPRING
-#define IGB_IOCTL_UNMAPRING	_IOW('E', 303, int)
-#define IGB_IOCTL_UNMAP_TX_RING  IGB_IOCTL_UNMAPRING
-#define IGB_IOCTL_MAPBUF	_IOW('E', 304, int)
-#define IGB_IOCTL_UNMAPBUF	_IOW('E', 305, int)
-#define IGB_IOCTL_MAP_RX_RING	_IOW('E', 307, int)
-#define IGB_IOCTL_UNMAP_RX_RING _IOW('E', 308, int)
-
-/*END*/
-
-#define IGB_BIND_NAMESZ 24
-
-struct igb_bind_cmd {
-	char iface[IGB_BIND_NAMESZ];
-	unsigned mmap_size;
-};
-
-struct igb_buf_cmd {
-	u_int64_t physaddr; /* dma_addr_t is 64-bit */
-	unsigned int queue;
-	unsigned int mmap_size;
-	u_int64_t pa;
-};
-
-struct igb_link_cmd {
-	u_int32_t up; /* dma_addr_t is 64-bit */
-	u_int32_t speed;
-	u_int32_t duplex;
-};
-
-
-#endif /* _IGB_H_DEFINED_ */
-
-
diff --git a/lib/igb_avb b/lib/igb_avb
new file mode 160000
+Subproject 797496806aed8be065a55417e07b7ccd170429d