iprt/armv8.h: Add system register definitions for the GICv3, bugref:10404

git-svn-id: https://www.virtualbox.org/svn/vbox/trunk@99384 cfe28804-0f27-0410-a406-dd0f0b0b656f

1 files changed, 57 insertions, 0 deletions

diff --git a/include/iprt/armv8.h b/include/iprt/armv8.h
index b7e77828a87..ea89877f084 100644
--- a/include/iprt/armv8.h
+++ b/include/iprt/armv8.h
@@ -317,6 +317,8 @@
 /** PSTATE.ALLINT value. */
 #define ARMV8_AARCH64_SYSREG_ALLINT                 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
 
+/** ICC_PMR_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ICC_PMR_EL1            ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 6, 0)
 
 /** AFSR0_EL1 register - RW. */
 #define ARMV8_AARCH64_SYSREG_AFSR0_EL1              ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
@@ -331,6 +333,61 @@
 /** ERRSELR_EL1 register - RW. */
 #define ARMV8_AARCH64_SYSREG_ERRSELR_EL1            ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
 
+/** ICC_IAR0_EL1 register - RO. */
+#define ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1           ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 0)
+/** ICC_EOIR0_EL1 register - WO. */
+#define ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1          ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 1)
+/** ICC_HPPIR0_EL1 register - WO. */
+#define ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1         ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 2)
+/** ICC_BPR0_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1           ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 3)
+/** ICC_AP0R0_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1          ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 4)
+/** ICC_AP0R1_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1          ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 5)
+/** ICC_AP0R2_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1          ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 6)
+/** ICC_AP0R3_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1          ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 7)
+
+/** ICC_AP1R0_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1          ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 0)
+/** ICC_AP1R1_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1          ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 1)
+/** ICC_AP1R2_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1          ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 2)
+/** ICC_AP1R3_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1          ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 3)
+/** ICC_NMIAR1_EL1 register - RO. */
+#define ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1         ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 5)
+
+/** ICC_DIR_EL1 register - WO. */
+#define ARMV8_AARCH64_SYSREG_ICC_DIR_EL1            ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 1)
+/** ICC_RPR_EL1 register - RO. */
+#define ARMV8_AARCH64_SYSREG_ICC_RPR_EL1            ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 3)
+/** ICC_SGI1R_EL1 register - WO. */
+#define ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1          ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 5)
+/** ICC_ASGI1R_EL1 register - WO. */
+#define ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1         ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 6)
+/** ICC_SGI0R_EL1 register - WO. */
+#define ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1          ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 7)
+
+/** ICC_IAR1_EL1 register - RO. */
+#define ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1           ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 0)
+/** ICC_EOIR1_EL1 register - WO. */
+#define ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1          ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 1)
+/** ICC_HPPIR1_EL1 register - RO. */
+#define ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1         ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 2)
+/** ICC_BPR1_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1           ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 3)
+/** ICC_CTLR_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1           ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 4)
+/** ICC_SRE_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL1            ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 5)
+/** ICC_IGRPEN0_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1        ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 6)
+/** ICC_IGRPEN1_EL1 register - RW. */
+#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1        ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 7)
 /** @} */
 
 /** @} */