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| author | vboxsync <vboxsync@cfe28804-0f27-0410-a406-dd0f0b0b656f> | 2018-01-23 16:56:59 +0000 |
|---|---|---|
| committer | vboxsync <vboxsync@cfe28804-0f27-0410-a406-dd0f0b0b656f> | 2018-01-23 16:56:59 +0000 |
| commit | 2604a475b98efff9a07aac92e0283cf702f1ca42 (patch) | |
| tree | d81e3260b21bed8a3f0ae9c046d0bb72234a54d2 /src/VBox/Devices/PC/vbox.dsl | |
| parent | bd058265fe53c80641cbfd46a6ead4e2ad8ae51d (diff) | |
| download | VirtualBox-svn-2604a475b98efff9a07aac92e0283cf702f1ca42.tar.gz | |
vbox.dsl: Make sure that a parallel port with base address 0x3BC has alignment and length of 4 ports, because more isn't possible (VGA registers at 0x3C0).
git-svn-id: https://www.virtualbox.org/svn/vbox/trunk@70713 cfe28804-0f27-0410-a406-dd0f0b0b656f
Diffstat (limited to 'src/VBox/Devices/PC/vbox.dsl')
| -rw-r--r-- | src/VBox/Devices/PC/vbox.dsl | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/VBox/Devices/PC/vbox.dsl b/src/VBox/Devices/PC/vbox.dsl index 8fc48ccffbc..e6ec883be20 100644 --- a/src/VBox/Devices/PC/vbox.dsl +++ b/src/VBox/Devices/PC/vbox.dsl @@ -910,9 +910,15 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "VBOX ", "VBOXBIOS", 2) { CreateWordField (CRS, \_SB.PCI0.LPT0._Y18._MIN, PMI0) CreateWordField (CRS, \_SB.PCI0.LPT0._Y18._MAX, PMA0) + CreateWordField (CRS, \_SB.PCI0.LPT0._Y18._ALN, PAL0) + CreateWordField (CRS, \_SB.PCI0.LPT0._Y18._LEN, PLE0) CreateWordField (CRS, \_SB.PCI0.LPT0._Y19._INT, PIQ0) Store (PP0B, PMI0) Store (PP0B, PMA0) + If (LEqual (0x3BC, PP0B)) { + Store (0x04, PAL0) + Store (0x04, PLE0) + } ShiftLeft (0x01, PP0I, PIQ0) Return (CRS) } @@ -943,9 +949,15 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "VBOX ", "VBOXBIOS", 2) { CreateWordField (CRS, \_SB.PCI0.LPT1._Y20._MIN, PMI1) CreateWordField (CRS, \_SB.PCI0.LPT1._Y20._MAX, PMA1) + CreateWordField (CRS, \_SB.PCI0.LPT1._Y20._ALN, PAL1) + CreateWordField (CRS, \_SB.PCI0.LPT1._Y20._LEN, PLE1) CreateWordField (CRS, \_SB.PCI0.LPT1._Y21._INT, PIQ1) Store (PP1B, PMI1) Store (PP1B, PMA1) + If (LEqual (0x3BC, PP1B)) { + Store (0x04, PAL1) + Store (0x04, PLE1) + } ShiftLeft (0x01, PP1I, PIQ1) Return (CRS) } |