VMM,SUPDrv,x86.h: Nits.

- supdrvTscMeasureDeltaOne: No bulldozer Hygon, right, so don't muddle complicated if expression with impossibilities.
- CPUMMICROARCH: Put the Hygon and Shanghai immediately after the CPU families they are derived from (in the enum).
- cpumR3CpuIdExplodeFeatures: No K7 Hygon, right, so just flag all Hygons having leaking FxSR when FFXSR is set.
- cpumR3LoadCpuIdInner: Incorrect indent.
- getMsrNameHandled: Unnecessary parentheses and space.




git-svn-id: https://www.virtualbox.org/svn/vbox/trunk@81613 cfe28804-0f27-0410-a406-dd0f0b0b656f

3 files changed, 23 insertions, 19 deletions

diff --git a/src/VBox/HostDrivers/Support/SUPDrvGip.cpp b/src/VBox/HostDrivers/Support/SUPDrvGip.cpp
index 35528b9a242..77c48583807 100644
--- a/src/VBox/HostDrivers/Support/SUPDrvGip.cpp
+++ b/src/VBox/HostDrivers/Support/SUPDrvGip.cpp
@@ -4020,7 +4020,7 @@ static int supdrvTscMeasureDeltaOne(PSUPDRVDEVEXT pDevExt, uint32_t idxWorker)
             && ASMHasCpuId()
             && ASMIsValidStdRange(ASMCpuId_EAX(0))
             && (ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_HTT)
-            && (   (!ASMIsAmdCpu() && !ASMIsHygonCpu())
+            && (   !ASMIsAmdCpu()
                 || ASMGetCpuFamily(u32Tmp = ASMCpuId_EAX(1)) > 0x15
                 || (   ASMGetCpuFamily(u32Tmp)   == 0x15           /* Piledriver+, not bulldozer (FX-4150 didn't like it). */
                     && ASMGetCpuModelAMD(u32Tmp) >= 0x02) ) )
diff --git a/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp b/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp
index ff9db159ae2..e5e3d1987c5 100644
--- a/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp
+++ b/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp
@@ -609,6 +609,9 @@ VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
 
         CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
 
+        CASE_RET_STR(kCpumMicroarch_Hygon_Dhyana);
+        CASE_RET_STR(kCpumMicroarch_Hygon_Unknown);
+
         CASE_RET_STR(kCpumMicroarch_Centaur_C6);
         CASE_RET_STR(kCpumMicroarch_Centaur_C2);
         CASE_RET_STR(kCpumMicroarch_Centaur_C3);
@@ -636,9 +639,6 @@ VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
         CASE_RET_STR(kCpumMicroarch_NEC_V20);
         CASE_RET_STR(kCpumMicroarch_NEC_V30);
 
-        CASE_RET_STR(kCpumMicroarch_Hygon_Dhyana);
-        CASE_RET_STR(kCpumMicroarch_Hygon_Unknown);
-
         CASE_RET_STR(kCpumMicroarch_Unknown);
 
 #undef CASE_RET_STR
@@ -656,11 +656,11 @@ VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
         case kCpumMicroarch_AMD_16h_End:
         case kCpumMicroarch_AMD_Zen_End:
         case kCpumMicroarch_AMD_End:
+        case kCpumMicroarch_Hygon_End:
         case kCpumMicroarch_VIA_End:
+        case kCpumMicroarch_Shanghai_End:
         case kCpumMicroarch_Cyrix_End:
         case kCpumMicroarch_NEC_End:
-        case kCpumMicroarch_Shanghai_End:
-        case kCpumMicroarch_Hygon_End:
         case kCpumMicroarch_32BitHack:
             break;
         /* no default! */
@@ -1992,9 +1992,9 @@ int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPU
          */
         pFeatures->fLeakyFxSR = pExtLeaf
                              && (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
-                             && (   pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
-                                 || pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON)
-                             && pFeatures->uFamily >= 6 /* K7 and up */;
+                             && (   (   pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
+                                     && pFeatures->uFamily >= 6 /* K7 and up */)
+                                 || pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON);
 
         /*
          * Max extended (/FPU) state.
@@ -2963,6 +2963,8 @@ static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
      * VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
      */
     if (   (   pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
+            /** @todo The following ASSUMES that Hygon uses the same version numbering
+             * as AMD and that they shipped buggy firmware. */
             || pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
         && uMicrocodeRev < 0x8001126
         && !pConfig->fForceVme)
@@ -4149,15 +4151,16 @@ static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pC
     rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
     AssertLogRelRCReturn(rc, rc);
 
-    bool fQueryNestedHwvirt = false;
+    bool fQueryNestedHwvirt = false
 #ifdef VBOX_WITH_NESTED_HWVIRT_SVM
-    fQueryNestedHwvirt |= RT_BOOL(   pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
-                                  || pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON);
+                           || pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
+                           || pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON
 #endif
 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX
-    fQueryNestedHwvirt |= RT_BOOL(   pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
-                                  || pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
+                           || pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
+                           || pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA
 #endif
+                           ;
     if (fQueryNestedHwvirt)
     {
         /** @cfgm{/CPUM/NestedHWVirt, bool, false}
@@ -5699,9 +5702,9 @@ int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUID
     {
         /** @todo deal with no 0x80000001 on the host. */
         bool const fHostAmd  = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
-                               || ASMIsHygonCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
+                            || ASMIsHygonCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
         bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
-                               || ASMIsHygonCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
+                            || ASMIsHygonCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
 
         /* CPUID(0x80000001).ecx */
         CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);   // -> EMU
diff --git a/src/VBox/VMM/tools/VBoxCpuReport.cpp b/src/VBox/VMM/tools/VBoxCpuReport.cpp
index 53705948e49..4eff1a0f982 100644
--- a/src/VBox/VMM/tools/VBoxCpuReport.cpp
+++ b/src/VBox/VMM/tools/VBoxCpuReport.cpp
@@ -695,7 +695,7 @@ static const char *getMsrNameHandled(uint32_t uMsr)
         case 0x00000088: return "BBL_CR_D0";
         case 0x00000089: return "BBL_CR_D1";
         case 0x0000008a: return "BBL_CR_D2";
-        case 0x0000008b: return (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor ==  CPUMCPUVENDOR_HYGON) ? "AMD_K8_PATCH_LEVEL"
+        case 0x0000008b: return g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON ? "AMD_K8_PATCH_LEVEL"
                               : g_fIntelNetBurst ? "IA32_BIOS_SIGN_ID" : "BBL_CR_D3|BIOS_SIGN";
         case 0x0000008c: return "P6_UNK_0000_008c"; /* P6_M_Dothan. */
         case 0x0000008d: return "P6_UNK_0000_008d"; /* P6_M_Dothan. */
@@ -1945,7 +1945,8 @@ static const char *getMsrFnName(uint32_t uMsr, bool *pfTakesValue)
         case 0x00000047:
             return "IntelLastBranchFromToN";
 
-        case 0x0000008b: return (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON) ? "AmdK8PatchLevel" : "Ia32BiosSignId";
+        case 0x0000008b: return g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON
+                              ? "AmdK8PatchLevel" : "Ia32BiosSignId";
         case 0x0000009b: return "Ia32SmmMonitorCtl";
 
         case 0x000000a8:
@@ -3565,7 +3566,7 @@ static int reportMsr_Ia32MtrrFixedOrPat(uint32_t uMsr)
     if (   uMsr != 0x00000277
         || (  g_enmVendor == CPUMCPUVENDOR_INTEL
             ? g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First
-            : (g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON)
+            : g_enmVendor == CPUMCPUVENDOR_AMD || g_enmVendor == CPUMCPUVENDOR_HYGON
             ? g_enmMicroarch != kCpumMicroarch_AMD_K8_90nm_AMDV
             : true) )
     {