diff options
| -rw-r--r-- | src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f38.cpp.h | 38 | ||||
| -rw-r--r-- | src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f3a.cpp.h | 84 | ||||
| -rw-r--r-- | src/VBox/VMM/include/IEMOpHlp.h | 18 | ||||
| -rw-r--r-- | src/VBox/VMM/testcase/tstIEMCheckMc.cpp | 1 |
4 files changed, 78 insertions, 63 deletions
diff --git a/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f38.cpp.h b/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f38.cpp.h index e4d8ba682e2..ade28b1da48 100644 --- a/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f38.cpp.h +++ b/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f38.cpp.h @@ -109,7 +109,7 @@ FNIEMOP_DEF_1(iemOpCommonSse41_FullFull_To_Full, PFNIEMAIMPLMEDIAF2U128, pfnU128 /* * Register, register. */ - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_BEGIN(2, 0); IEM_MC_ARG(PRTUINT128U, puDst, 0); IEM_MC_ARG(PCRTUINT128U, puSrc, 1); @@ -133,7 +133,7 @@ FNIEMOP_DEF_1(iemOpCommonSse41_FullFull_To_Full, PFNIEMAIMPLMEDIAF2U128, pfnU128 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -168,7 +168,7 @@ FNIEMOP_DEF_1(iemOpCommonSse41Opt_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, p /* * Register, register. */ - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_BEGIN(2, 0); IEM_MC_ARG(PRTUINT128U, puDst, 0); IEM_MC_ARG(PCRTUINT128U, puSrc, 1); @@ -192,7 +192,7 @@ FNIEMOP_DEF_1(iemOpCommonSse41Opt_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, p IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -224,7 +224,7 @@ FNIEMOP_DEF_1(iemOpCommonSse42_FullFull_To_Full, PFNIEMAIMPLMEDIAF2U128, pfnU128 /* * Register, register. */ - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); IEM_MC_BEGIN(2, 0); IEM_MC_ARG(PRTUINT128U, puDst, 0); IEM_MC_ARG(PCRTUINT128U, puSrc, 1); @@ -248,7 +248,7 @@ FNIEMOP_DEF_1(iemOpCommonSse42_FullFull_To_Full, PFNIEMAIMPLMEDIAF2U128, pfnU128 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT(); IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -284,7 +284,7 @@ FNIEMOP_DEF_1(iemOpCommonAesNi_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, pfnU /* * Register, register. */ - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi); IEM_MC_BEGIN(2, 0); IEM_MC_ARG(PRTUINT128U, puDst, 0); IEM_MC_ARG(PCRTUINT128U, puSrc, 1); @@ -308,7 +308,7 @@ FNIEMOP_DEF_1(iemOpCommonAesNi_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, pfnU IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi); IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT(); IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -344,7 +344,7 @@ FNIEMOP_DEF_1(iemOpCommonSha_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, pfnU12 /* * Register, register. */ - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha); IEM_MC_BEGIN(2, 0); IEM_MC_ARG(PRTUINT128U, puDst, 0); IEM_MC_ARG(PCRTUINT128U, puSrc, 1); @@ -368,7 +368,7 @@ FNIEMOP_DEF_1(iemOpCommonSha_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, pfnU12 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha); IEM_MC_MAYBE_RAISE_SHA_RELATED_XCPT(); IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -644,7 +644,7 @@ FNIEMOP_DEF(iemOp_pmulhrsw_Vx_Wx) /* \ * Register, register. \ */ \ - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); \ IEM_MC_BEGIN(3, 0); \ IEM_MC_ARG(PRTUINT128U, puDst, 0); \ IEM_MC_ARG(PCRTUINT128U, puSrc, 1); \ @@ -673,7 +673,7 @@ FNIEMOP_DEF(iemOp_pmulhrsw_Vx_Wx) IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1); \ IEM_MC_ARG(PCRTUINT128U, puMask, 2); \ IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \ - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); \ IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); \ IEM_MC_PREPARE_SSE_USAGE(); \ IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \ @@ -739,7 +739,7 @@ FNIEMOP_DEF(iemOp_ptest_Vx_Wx) /* * Register, register. */ - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_BEGIN(3, 0); IEM_MC_ARG(PCRTUINT128U, puSrc1, 0); IEM_MC_ARG(PCRTUINT128U, puSrc2, 1); @@ -766,7 +766,7 @@ FNIEMOP_DEF(iemOp_ptest_Vx_Wx) IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -863,7 +863,7 @@ FNIEMOP_DEF(iemOp_pabsd_Vx_Wx) /* \ * Register, register. \ */ \ - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); \ IEM_MC_BEGIN(2, 0); \ IEM_MC_ARG(PRTUINT128U, puDst, 0); \ IEM_MC_ARG(uint64_t, uSrc, 1); \ @@ -888,7 +888,7 @@ FNIEMOP_DEF(iemOp_pabsd_Vx_Wx) IEM_MC_ARG(PRTUINT128U, puDst, 0); \ IEM_MC_ARG(uint ## a_SrcWidth ## _t, uSrc, 1); \ IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \ - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); \ IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); \ IEM_MC_PREPARE_SSE_USAGE(); \ IEM_MC_FETCH_MEM_U## a_SrcWidth (uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \ @@ -1001,7 +1001,7 @@ FNIEMOP_DEF(iemOp_movntdqa_Vdq_Mdq) IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE(); @@ -1518,7 +1518,7 @@ FNIEMOP_DEF(iemOp_sha256rnds2_Vdq_Wdq) /* * Register, register. */ - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha); IEM_MC_BEGIN(3, 0); IEM_MC_ARG(PRTUINT128U, puDst, 0); IEM_MC_ARG(PCRTUINT128U, puSrc, 1); @@ -1546,7 +1546,7 @@ FNIEMOP_DEF(iemOp_sha256rnds2_Vdq_Wdq) IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha); IEM_MC_MAYBE_RAISE_SHA_RELATED_XCPT(); IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); diff --git a/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f3a.cpp.h b/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f3a.cpp.h index a42c3e4f51d..d455cfb3cf4 100644 --- a/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f3a.cpp.h +++ b/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f3a.cpp.h @@ -110,7 +110,7 @@ FNIEMOP_DEF_1(iemOpCommonSse41_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IM * XMM, XMM, imm8 */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_BEGIN(3, 0); IEM_MC_ARG(PRTUINT128U, puDst, 0); IEM_MC_ARG(PCRTUINT128U, puSrc, 1); @@ -137,7 +137,7 @@ FNIEMOP_DEF_1(iemOpCommonSse41_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IM IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -170,7 +170,7 @@ FNIEMOP_DEF_1(iemOpCommonSse41Fp_FullFullImm8_To_Full, PFNIEMAIMPLMXCSRF2XMMIMM8 * XMM, XMM, imm8. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_BEGIN(4, 2); IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src); IEM_MC_LOCAL(X86XMMREG, Dst); @@ -206,7 +206,7 @@ FNIEMOP_DEF_1(iemOpCommonSse41Fp_FullFullImm8_To_Full, PFNIEMAIMPLMXCSRF2XMMIMM8 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -242,7 +242,7 @@ FNIEMOP_DEF_1(iemOpCommonAesNi_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IM * Register, register. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi); IEM_MC_BEGIN(3, 0); IEM_MC_ARG(PRTUINT128U, puDst, 0); IEM_MC_ARG(PCRTUINT128U, puSrc, 1); @@ -269,7 +269,7 @@ FNIEMOP_DEF_1(iemOpCommonAesNi_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IM IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi); IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT(); IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -322,7 +322,7 @@ FNIEMOP_DEF(iemOp_roundss_Vss_Wss_Ib) * XMM32, XMM32. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_BEGIN(4, 2); IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src); IEM_MC_LOCAL(X86XMMREG, Dst); @@ -358,7 +358,7 @@ FNIEMOP_DEF(iemOp_roundss_Vss_Wss_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_FETCH_MEM_XMM_U32(Src.uSrc2, 0 /*a_iDword */, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -387,7 +387,7 @@ FNIEMOP_DEF(iemOp_roundsd_Vsd_Wsd_Ib) * XMM64, XMM64, imm8. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_BEGIN(4, 2); IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src); IEM_MC_LOCAL(X86XMMREG, Dst); @@ -423,7 +423,7 @@ FNIEMOP_DEF(iemOp_roundsd_Vsd_Wsd_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_FETCH_MEM_XMM_U64(Src.uSrc2, 0 /*a_iQword */, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -552,7 +552,7 @@ FNIEMOP_DEF(iemOp_pextrb_RdMb_Vdq_Ib) * greg32, XMM. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_BEGIN(0, 1); IEM_MC_LOCAL(uint8_t, uValue); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); @@ -573,7 +573,7 @@ FNIEMOP_DEF(iemOp_pextrb_RdMb_Vdq_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_PREPARE_SSE_USAGE(); @@ -596,7 +596,7 @@ FNIEMOP_DEF(iemOp_pextrw_RdMw_Vdq_Ib) * greg32, XMM. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_BEGIN(0, 1); IEM_MC_LOCAL(uint16_t, uValue); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); @@ -617,7 +617,7 @@ FNIEMOP_DEF(iemOp_pextrw_RdMw_Vdq_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_PREPARE_SSE_USAGE(); @@ -647,7 +647,7 @@ FNIEMOP_DEF(iemOp_pextrd_q_RdMw_Vdq_Ib) * greg64, XMM. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_BEGIN(0, 1); IEM_MC_LOCAL(uint64_t, uSrc); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); @@ -668,7 +668,7 @@ FNIEMOP_DEF(iemOp_pextrd_q_RdMw_Vdq_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_PREPARE_SSE_USAGE(); @@ -694,7 +694,7 @@ FNIEMOP_DEF(iemOp_pextrd_q_RdMw_Vdq_Ib) * greg32, XMM. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_BEGIN(0, 1); IEM_MC_LOCAL(uint32_t, uSrc); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); @@ -715,7 +715,7 @@ FNIEMOP_DEF(iemOp_pextrd_q_RdMw_Vdq_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_PREPARE_SSE_USAGE(); IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/); @@ -738,7 +738,7 @@ FNIEMOP_DEF(iemOp_extractps_Ed_Vdq_Ib) * greg32, XMM. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_BEGIN(0, 1); IEM_MC_LOCAL(uint32_t, uSrc); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); @@ -759,7 +759,7 @@ FNIEMOP_DEF(iemOp_extractps_Ed_Vdq_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_PREPARE_SSE_USAGE(); IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/); @@ -791,7 +791,7 @@ FNIEMOP_DEF(iemOp_pinsrb_Vdq_RyMb_Ib) * XMM, greg32. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_BEGIN(0, 1); IEM_MC_LOCAL(uint8_t, uSrc); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); @@ -812,7 +812,7 @@ FNIEMOP_DEF(iemOp_pinsrb_Vdq_RyMb_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_PREPARE_SSE_USAGE(); @@ -834,7 +834,7 @@ FNIEMOP_DEF(iemOp_insertps_Vdq_UdqMd_Ib) * XMM, XMM. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_BEGIN(0, 3); IEM_MC_LOCAL(uint32_t, uSrc); IEM_MC_LOCAL(uint8_t, uSrcSel); @@ -865,7 +865,7 @@ FNIEMOP_DEF(iemOp_insertps_Vdq_UdqMd_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_PREPARE_SSE_USAGE(); @@ -898,7 +898,7 @@ FNIEMOP_DEF(iemOp_pinsrd_q_Vdq_Ey_Ib) * XMM, greg64. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_BEGIN(0, 1); IEM_MC_LOCAL(uint64_t, uSrc); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); @@ -919,7 +919,7 @@ FNIEMOP_DEF(iemOp_pinsrd_q_Vdq_Ey_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_PREPARE_SSE_USAGE(); @@ -945,7 +945,7 @@ FNIEMOP_DEF(iemOp_pinsrd_q_Vdq_Ey_Ib) * XMM, greg32. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_BEGIN(0, 1); IEM_MC_LOCAL(uint32_t, uSrc); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); @@ -966,7 +966,7 @@ FNIEMOP_DEF(iemOp_pinsrd_q_Vdq_Ey_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); IEM_MC_PREPARE_SSE_USAGE(); @@ -1146,7 +1146,7 @@ FNIEMOP_DEF(iemOp_pcmpestrm_Vdq_Wdq_Ib) * Register, register. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); IEM_MC_BEGIN(4, 1); IEM_MC_ARG(PRTUINT128U, puDst, 0); IEM_MC_ARG(uint32_t *, pEFlags, 1); @@ -1183,7 +1183,7 @@ FNIEMOP_DEF(iemOp_pcmpestrm_Vdq_Wdq_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT(); IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -1210,7 +1210,7 @@ FNIEMOP_DEF(iemOp_pcmpestrm_Vdq_Wdq_Ib) * Register, register. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); IEM_MC_BEGIN(4, 1); IEM_MC_ARG(PRTUINT128U, puDst, 0); IEM_MC_ARG(uint32_t *, pEFlags, 1); @@ -1247,7 +1247,7 @@ FNIEMOP_DEF(iemOp_pcmpestrm_Vdq_Wdq_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT(); IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -1282,7 +1282,7 @@ FNIEMOP_DEF(iemOp_pcmpestri_Vdq_Wdq_Ib) * Register, register. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); IEM_MC_BEGIN(4, 1); IEM_MC_ARG(uint32_t *, pu32Ecx, 0); IEM_MC_ARG(uint32_t *, pEFlags, 1); @@ -1320,7 +1320,7 @@ FNIEMOP_DEF(iemOp_pcmpestri_Vdq_Wdq_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT(); IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -1347,7 +1347,7 @@ FNIEMOP_DEF(iemOp_pcmpestri_Vdq_Wdq_Ib) * Register, register. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); IEM_MC_BEGIN(4, 1); IEM_MC_ARG(uint32_t *, pu32Ecx, 0); IEM_MC_ARG(uint32_t *, pEFlags, 1); @@ -1385,7 +1385,7 @@ FNIEMOP_DEF(iemOp_pcmpestri_Vdq_Wdq_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT(); IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -1419,7 +1419,7 @@ FNIEMOP_DEF(iemOp_pcmpistrm_Vdq_Wdq_Ib) * Register, register. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); IEM_MC_BEGIN(4, 1); IEM_MC_ARG(PRTUINT128U, puDst, 0); IEM_MC_ARG(uint32_t *, pEFlags, 1); @@ -1454,7 +1454,7 @@ FNIEMOP_DEF(iemOp_pcmpistrm_Vdq_Wdq_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT(); IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -1484,7 +1484,7 @@ FNIEMOP_DEF(iemOp_pcmpistri_Vdq_Wdq_Ib) * Register, register. */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); IEM_MC_BEGIN(4, 1); IEM_MC_ARG(uint32_t *, pu32Ecx, 0); IEM_MC_ARG(uint32_t *, pEFlags, 1); @@ -1520,7 +1520,7 @@ FNIEMOP_DEF(iemOp_pcmpistri_Vdq_Wdq_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT(); IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); @@ -1581,7 +1581,7 @@ FNIEMOP_DEF(iemOp_sha1rnds4_Vdq_Wdq_Ib) * XMM, XMM, imm8 */ uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha); IEM_MC_BEGIN(3, 0); IEM_MC_ARG(PRTUINT128U, puDst, 0); IEM_MC_ARG(PCRTUINT128U, puSrc, 1); @@ -1611,7 +1611,7 @@ FNIEMOP_DEF(iemOp_sha1rnds4_Vdq_Wdq_Ib) IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2); - IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha); IEM_MC_MAYBE_RAISE_SHA_RELATED_XCPT(); IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); diff --git a/src/VBox/VMM/include/IEMOpHlp.h b/src/VBox/VMM/include/IEMOpHlp.h index e62f395694e..0d4b309f13d 100644 --- a/src/VBox/VMM/include/IEMOpHlp.h +++ b/src/VBox/VMM/include/IEMOpHlp.h @@ -420,6 +420,20 @@ void iemOpStubMsg2(PVMCPUCC pVCpu) RT_NOEXCEPT; return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \ } while (0) +/** + * Done decoding, raise \#UD exception if lock prefix present, or if the + * a_fFeature is present in the guest CPU. + */ +#define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(a_fFeature) \ + do \ + { \ + if (RT_LIKELY( !(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK) \ + && IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature)) \ + { /* likely */ } \ + else \ + return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \ + } while (0) + /** * Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz, @@ -508,7 +522,7 @@ void iemOpStubMsg2(PVMCPUCC pVCpu) RT_NOEXCEPT; * Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz, * repnz or size prefixes are present, or if the VEX.VVVV field doesn't indicate * register 0, if in real or v8086 mode, or if the a_fFeature is not present in - * the guest CPU. + * the guest CPU. */ #define IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(a_fFeature) \ do \ @@ -545,7 +559,7 @@ void iemOpStubMsg2(PVMCPUCC pVCpu) RT_NOEXCEPT; * Done decoding VEX, no V, L=0. * Raises \#UD exception if rex, rep, opsize or lock prefixes are present, if * we're in real or v8086 mode, if VEX.V!=0xf, if VEX.L!=0, or if the a_fFeature - * is not present in the guest CPU. + * is not present in the guest CPU. */ #define IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(a_fFeature) \ do \ diff --git a/src/VBox/VMM/testcase/tstIEMCheckMc.cpp b/src/VBox/VMM/testcase/tstIEMCheckMc.cpp index 959b48b07dc..1ced94bacb4 100644 --- a/src/VBox/VMM/testcase/tstIEMCheckMc.cpp +++ b/src/VBox/VMM/testcase/tstIEMCheckMc.cpp @@ -159,6 +159,7 @@ typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPU pVCpu, uint8_t bRm); #define IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX() do { } while (0) #define IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE(a_szPrf) do { } while (0) #define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX() do { } while (0) +#define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(a_fFeature) do { } while (0) #define IEMOP_HLP_DONE_VEX_DECODING() do { } while (0) #define IEMOP_HLP_DONE_VEX_DECODING_EX(a_fFeature) do { } while (0) #define IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeature) do { } while (0) |