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-rw-r--r--include/VBox/vmm/hm.h26
-rw-r--r--include/VBox/vmm/vmm.h2
-rw-r--r--src/VBox/VMM/VMMR0/CPUMR0.cpp90
-rw-r--r--src/VBox/VMM/VMMR0/HMR0.cpp62
-rw-r--r--src/VBox/VMM/VMMR0/HMSVMR0.cpp88
-rw-r--r--src/VBox/VMM/VMMR0/HMSVMR0.h5
-rw-r--r--src/VBox/VMM/VMMR0/HMVMXR0.cpp326
-rw-r--r--src/VBox/VMM/VMMR0/HMVMXR0.h5
-rw-r--r--src/VBox/VMM/VMMR0/VMMR0.cpp9
-rw-r--r--src/VBox/VMM/VMMR3/HM.cpp4
-rw-r--r--src/VBox/VMM/VMMRZ/CPUMRZ.cpp38
-rw-r--r--src/VBox/VMM/include/HMInternal.h2
12 files changed, 38 insertions, 619 deletions
diff --git a/include/VBox/vmm/hm.h b/include/VBox/vmm/hm.h
index b9d49c22004..d2769cde9e5 100644
--- a/include/VBox/vmm/hm.h
+++ b/include/VBox/vmm/hm.h
@@ -106,26 +106,6 @@ RT_C_DECLS_BEGIN
# define HMIsInHwVirtNoLongJmpCtx(a_pVCpu) (false)
#endif
-/**
- * 64-bit raw-mode (intermediate memory context) operations.
- *
- * These are special hypervisor eip values used when running 64-bit guests on
- * 32-bit hosts. Each operation corresponds to a routine.
- *
- * @note Duplicated in the assembly code!
- */
-typedef enum HM64ON32OP
-{
- HM64ON32OP_INVALID = 0,
- HM64ON32OP_VMXRCStartVM64,
- HM64ON32OP_SVMRCVMRun64,
- HM64ON32OP_HMRCSaveGuestFPU64,
- HM64ON32OP_HMRCSaveGuestDebug64,
- HM64ON32OP_HMRCTestSwitcher64,
- HM64ON32OP_END,
- HM64ON32OP_32BIT_HACK = 0x7fffffff
-} HM64ON32OP;
-
/** @name All-context HM API.
* @{ */
VMMDECL(bool) HMIsEnabledNotMacro(PVM pVM);
@@ -247,12 +227,6 @@ VMMR0_INT_DECL(bool) HMR0SuspendPending(void);
VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat);
-# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
-VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
-VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
-VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM);
-# endif
-
/** @} */
#endif /* IN_RING0 */
diff --git a/include/VBox/vmm/vmm.h b/include/VBox/vmm/vmm.h
index 22c40dc0ac5..2be054ef9c2 100644
--- a/include/VBox/vmm/vmm.h
+++ b/include/VBox/vmm/vmm.h
@@ -445,8 +445,6 @@ typedef enum VMMR0OPERATION
/** Official call we use for testing Ring-0 APIs. */
VMMR0_DO_TESTS = 640,
- /** Test the 32->64 bits switcher. */
- VMMR0_DO_TEST_SWITCHER3264,
/** The usual 32-bit type blow up. */
VMMR0_DO_32BIT_HACK = 0x7fffffff
diff --git a/src/VBox/VMM/VMMR0/CPUMR0.cpp b/src/VBox/VMM/VMMR0/CPUMR0.cpp
index 15ae4044065..e93e0b82771 100644
--- a/src/VBox/VMM/VMMR0/CPUMR0.cpp
+++ b/src/VBox/VMM/VMMR0/CPUMR0.cpp
@@ -506,40 +506,24 @@ VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu)
if (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST | CPUM_USED_FPU_HOST))
{
fSavedGuest = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
-#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
- if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
+ if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
+ cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
+ else
{
- if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
+ /* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
+ save/restore the XMM state with fxsave/fxrstor. */
+ uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
+ if (uHostEfer & MSR_K6_EFER_FFXSR)
{
- Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
- HMR0SaveFPUState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
+ RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
+ ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
+ cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
+ ASMWrMsr(MSR_K6_EFER, uHostEfer | MSR_K6_EFER_FFXSR);
+ ASMSetFlags(uSavedFlags);
}
else
- pVCpu->cpum.s.fUseFlags &= ~CPUM_SYNC_FPU_STATE;
- cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
- }
- else
-#endif
- {
- if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
- else
- {
- /* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
- save/restore the XMM state with fxsave/fxrstor. */
- uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
- if (uHostEfer & MSR_K6_EFER_FFXSR)
- {
- RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
- ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
- cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
- ASMWrMsr(MSR_K6_EFER, uHostEfer | MSR_K6_EFER_FFXSR);
- ASMSetFlags(uSavedFlags);
- }
- else
- cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
- pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
- }
+ pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
}
}
else
@@ -609,24 +593,12 @@ VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu,
*/
if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
{
-#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
- if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
- {
- uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
- HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
- if (!fDr6)
- pVCpu->cpum.s.Guest.dr[6] = uDr6;
- }
- else
-#endif
- {
- pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
- pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
- pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
- pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
- if (fDr6)
- pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
- }
+ pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
+ pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
+ pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
+ pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
+ if (fDr6)
+ pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
}
ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~( CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER
| CPUM_SYNC_DEBUG_REGS_GUEST | CPUM_SYNC_DEBUG_REGS_HYPER));
@@ -677,24 +649,12 @@ VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6)
*/
if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
{
-#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
- if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
- {
- uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
- HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
- if (!fDr6)
- pVCpu->cpum.s.Guest.dr[6] = uDr6;
- }
- else
-#endif
- {
- pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
- pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
- pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
- pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
- if (fDr6)
- pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
- }
+ pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
+ pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
+ pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
+ pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
+ if (fDr6)
+ pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
return true;
}
return false;
diff --git a/src/VBox/VMM/VMMR0/HMR0.cpp b/src/VBox/VMM/VMMR0/HMR0.cpp
index 015c8084984..95833c88fad 100644
--- a/src/VBox/VMM/VMMR0/HMR0.cpp
+++ b/src/VBox/VMM/VMMR0/HMR0.cpp
@@ -1545,68 +1545,6 @@ VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPU pVCpu)
}
-#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
-
-/**
- * Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
- *
- * @returns VBox status code.
- * @param pVM The cross context VM structure.
- * @param pVCpu The cross context virtual CPU structure.
- * @param pCtx Pointer to the guest CPU context.
- */
-VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
-{
- RT_NOREF(pCtx);
- STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
- if (pVM->hm.s.vmx.fSupported)
- return VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
- return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
-}
-
-
-/**
- * Save guest debug state (64 bits guest mode & 32 bits host only)
- *
- * @returns VBox status code.
- * @param pVM The cross context VM structure.
- * @param pVCpu The cross context virtual CPU structure.
- * @param pCtx Pointer to the guest CPU context.
- */
-VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
-{
- RT_NOREF(pCtx);
- STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
- if (pVM->hm.s.vmx.fSupported)
- return VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
- return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
-}
-
-
-/**
- * Test the 32->64 bits switcher.
- *
- * @returns VBox status code.
- * @param pVM The cross context VM structure.
- */
-VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
-{
- PVMCPU pVCpu = &pVM->aCpus[0];
- uint32_t aParam[5] = { 0, 1, 2, 3, 4 };
- int rc;
-
- STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
- if (pVM->hm.s.vmx.fSupported)
- rc = VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
- else
- rc = SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
- STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
-
- return rc;
-}
-
-#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) */
-
/**
* Returns suspend status of the host.
*
diff --git a/src/VBox/VMM/VMMR0/HMSVMR0.cpp b/src/VBox/VMM/VMMR0/HMSVMR0.cpp
index 121953f6937..358c6159d17 100644
--- a/src/VBox/VMM/VMMR0/HMSVMR0.cpp
+++ b/src/VBox/VMM/VMMR0/HMSVMR0.cpp
@@ -1323,83 +1323,6 @@ static void hmR0SvmFlushTaggedTlb(PHMPHYSCPU pHostCpu, PVMCPU pVCpu, PSVMVMCB pV
}
-/** @name 64-bit guest on 32-bit host OS helper functions.
- *
- * The host CPU is still 64-bit capable but the host OS is running in 32-bit
- * mode (code segment, paging). These wrappers/helpers perform the necessary
- * bits for the 32->64 switcher.
- *
- * @{ */
-#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
-/**
- * Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
- *
- * @returns VBox status code.
- * @param HCPhysVmcbHost Physical address of host VMCB.
- * @param HCPhysVmcb Physical address of the VMCB.
- * @param pCtx Pointer to the guest-CPU context.
- * @param pVM The cross context VM structure.
- * @param pVCpu The cross context virtual CPU structure.
- */
-DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
-{
- RT_NOREF2(pVM, pCtx);
- uint32_t aParam[8];
- aParam[0] = RT_LO_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
- aParam[1] = RT_HI_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Hi. */
- aParam[2] = RT_LO_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
- aParam[3] = RT_HI_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Hi. */
- aParam[4] = VM_RC_ADDR(pVM, pVM);
- aParam[5] = 0;
- aParam[6] = VM_RC_ADDR(pVM, pVCpu);
- aParam[7] = 0;
-
- return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
-}
-
-
-/**
- * Executes the specified VMRUN handler in 64-bit mode.
- *
- * @returns VBox status code.
- * @param pVCpu The cross context virtual CPU structure.
- * @param enmOp The operation to perform.
- * @param cParams Number of parameters.
- * @param paParam Array of 32-bit parameters.
- */
-VMMR0DECL(int) SVMR0Execute64BitsHandler(PVMCPU pVCpu, HM64ON32OP enmOp, uint32_t cParams, uint32_t *paParam)
-{
- PVM pVM = pVCpu->CTX_SUFF(pVM);
- AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
- Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
-
- /* Disable interrupts. */
- RTHCUINTREG const fEFlags = ASMIntDisableFlags();
-
-#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
- RTCPUID idHostCpu = RTMpCpuId();
- CPUMR0SetLApic(pVCpu, idHostCpu);
-#endif
-
- CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
- CPUMSetHyperEIP(pVCpu, enmOp);
- for (int i = (int)cParams - 1; i >= 0; i--)
- CPUMPushHyper(pVCpu, paParam[i]);
-
- /* Call the switcher. */
- STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
- int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_UOFFSETOF_DYN(VM, aCpus[pVCpu->idCpu].cpum) - RT_UOFFSETOF(VM, cpum));
- STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
-
- /* Restore interrupts. */
- ASMSetFlags(fEFlags);
- return rc;
-}
-
-#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
-/** @} */
-
-
/**
* Sets an exception intercept in the specified VMCB.
*
@@ -2295,13 +2218,12 @@ static int hmR0SvmSelectVMRunHandler(PVMCPU pVCpu)
{
#ifndef VBOX_ENABLE_64_BITS_GUESTS
return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
-#endif
- Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
-#if HC_ARCH_BITS == 32
- /* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
- pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
#else
- /* 64-bit host or hybrid host. */
+# if HC_ARCH_BITS != 64 || ARCH_BITS != 64
+# error "Only 64-bit hosts are supported!"
+# endif
+ Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
+ /* Guest in long mode, use 64-bit handler (host is 64-bit). */
pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
#endif
}
diff --git a/src/VBox/VMM/VMMR0/HMSVMR0.h b/src/VBox/VMM/VMMR0/HMSVMR0.h
index 0aa2f0fe63a..1ff63b4d07e 100644
--- a/src/VBox/VMM/VMMR0/HMSVMR0.h
+++ b/src/VBox/VMM/VMMR0/HMSVMR0.h
@@ -51,11 +51,6 @@ VMMR0DECL(int) SVMR0ExportHostState(PVMCPU pVCpu);
VMMR0DECL(int) SVMR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat);
VMMR0DECL(int) SVMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
-#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
-DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
-VMMR0DECL(int) SVMR0Execute64BitsHandler(PVMCPU pVCpu, HM64ON32OP enmOp, uint32_t cbParam, uint32_t *paParam);
-#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) */
-
/**
* Prepares for and executes VMRUN (32-bit guests).
*
diff --git a/src/VBox/VMM/VMMR0/HMVMXR0.cpp b/src/VBox/VMM/VMMR0/HMVMXR0.cpp
index 9a498d921e9..a4afc8e867e 100644
--- a/src/VBox/VMM/VMMR0/HMVMXR0.cpp
+++ b/src/VBox/VMM/VMMR0/HMVMXR0.cpp
@@ -4385,238 +4385,6 @@ VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
}
-#if HC_ARCH_BITS == 32
-# ifdef VBOX_ENABLE_64_BITS_GUESTS
-/**
- * Check if guest state allows safe use of 32-bit switcher again.
- *
- * Segment bases and protected mode structures must be 32-bit addressable
- * because the 32-bit switcher will ignore high dword when writing these VMCS
- * fields. See @bugref{8432} for details.
- *
- * @returns true if safe, false if must continue to use the 64-bit switcher.
- * @param pCtx Pointer to the guest-CPU context.
- *
- * @remarks No-long-jump zone!!!
- */
-static bool hmR0VmxIs32BitSwitcherSafe(PCCPUMCTX pCtx)
-{
- if (pCtx->gdtr.pGdt & UINT64_C(0xffffffff00000000)) return false;
- if (pCtx->idtr.pIdt & UINT64_C(0xffffffff00000000)) return false;
- if (pCtx->ldtr.u64Base & UINT64_C(0xffffffff00000000)) return false;
- if (pCtx->tr.u64Base & UINT64_C(0xffffffff00000000)) return false;
- if (pCtx->es.u64Base & UINT64_C(0xffffffff00000000)) return false;
- if (pCtx->cs.u64Base & UINT64_C(0xffffffff00000000)) return false;
- if (pCtx->ss.u64Base & UINT64_C(0xffffffff00000000)) return false;
- if (pCtx->ds.u64Base & UINT64_C(0xffffffff00000000)) return false;
- if (pCtx->fs.u64Base & UINT64_C(0xffffffff00000000)) return false;
- if (pCtx->gs.u64Base & UINT64_C(0xffffffff00000000)) return false;
-
- /* All good, bases are 32-bit. */
- return true;
-}
-# endif /* VBOX_ENABLE_64_BITS_GUESTS */
-
-# ifdef VBOX_STRICT
-static bool hmR0VmxIsValidWriteFieldInCache(uint32_t idxField)
-{
- switch (idxField)
- {
- case VMX_VMCS_GUEST_RIP:
- case VMX_VMCS_GUEST_RSP:
- case VMX_VMCS_GUEST_SYSENTER_EIP:
- case VMX_VMCS_GUEST_SYSENTER_ESP:
- case VMX_VMCS_GUEST_GDTR_BASE:
- case VMX_VMCS_GUEST_IDTR_BASE:
- case VMX_VMCS_GUEST_CS_BASE:
- case VMX_VMCS_GUEST_DS_BASE:
- case VMX_VMCS_GUEST_ES_BASE:
- case VMX_VMCS_GUEST_FS_BASE:
- case VMX_VMCS_GUEST_GS_BASE:
- case VMX_VMCS_GUEST_SS_BASE:
- case VMX_VMCS_GUEST_LDTR_BASE:
- case VMX_VMCS_GUEST_TR_BASE:
- case VMX_VMCS_GUEST_CR3:
- return true;
- }
- return false;
-}
-
-static bool hmR0VmxIsValidReadFieldInCache(uint32_t idxField)
-{
- switch (idxField)
- {
- /* Read-only fields. */
- case VMX_VMCS_RO_EXIT_QUALIFICATION:
- return true;
- }
- /* Remaining readable fields should also be writable. */
- return hmR0VmxIsValidWriteFieldInCache(idxField);
-}
-# endif /* VBOX_STRICT */
-
-
-/**
- * Executes the specified handler in 64-bit mode.
- *
- * @returns VBox status code (no informational status codes).
- * @param pVCpu The cross context virtual CPU structure.
- * @param enmOp The operation to perform.
- * @param cParams Number of parameters.
- * @param paParam Array of 32-bit parameters.
- */
-VMMR0DECL(int) VMXR0Execute64BitsHandler(PVMCPU pVCpu, HM64ON32OP enmOp, uint32_t cParams, uint32_t *paParam)
-{
- AssertPtr(pVCpu);
- PVM pVM = pVCpu->CTX_SUFF(pVM);
- AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
- Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
- Assert(pVCpu->hm.s.vmx.VmcsCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VmcsCache.Write.aField));
- Assert(pVCpu->hm.s.vmx.VmcsCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VmcsCache.Read.aField));
-
-#ifdef VBOX_STRICT
- for (uint32_t i = 0; i < pVCpu->hm.s.vmx.VmcsCache.Write.cValidEntries; i++)
- Assert(hmR0VmxIsValidWriteFieldInCache(pVCpu->hm.s.vmx.VmcsCache.Write.aField[i]));
-
- for (uint32_t i = 0; i <pVCpu->hm.s.vmx.VmcsCache.Read.cValidEntries; i++)
- Assert(hmR0VmxIsValidReadFieldInCache(pVCpu->hm.s.vmx.VmcsCache.Read.aField[i]));
-#endif
-
- /* Disable interrupts. */
- RTCCUINTREG fOldEFlags = ASMIntDisableFlags();
-
-#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
- RTCPUID idHostCpu = RTMpCpuId();
- CPUMR0SetLApic(pVCpu, idHostCpu);
-#endif
-
- /** @todo replace with hmR0VmxEnterRootMode() and hmR0VmxLeaveRootMode(). */
-
- PCHMPHYSCPU pHostCpu = hmR0GetCurrentCpu();
- RTHCPHYS const HCPhysCpuPage = pHostCpu->HCPhysMemObj;
-
- /* Clear VMCS. Marking it inactive, clearing implementation-specific data and writing VMCS data back to memory. */
- PVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
- hmR0VmxClearVmcs(pVmcsInfo);
-
- /* Leave VMX root mode and disable VMX. */
- VMXDisable();
- SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
-
- CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
- CPUMSetHyperEIP(pVCpu, enmOp);
- for (int i = (int)cParams - 1; i >= 0; i--)
- CPUMPushHyper(pVCpu, paParam[i]);
-
- STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
-
- /* Call the switcher. */
- int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_UOFFSETOF_DYN(VM, aCpus[pVCpu->idCpu].cpum) - RT_UOFFSETOF(VM, cpum));
- STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
-
- /* Re-enable VMX to make sure the VMX instructions don't cause #UD faults. */
- SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
-
- /* Re-enter VMX root mode. */
- int rc2 = VMXEnable(HCPhysCpuPage);
- if (RT_FAILURE(rc2))
- {
- SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
- ASMSetFlags(fOldEFlags);
- pVM->hm.s.vmx.HCPhysVmxEnableError = HCPhysCpuPage;
- return rc2;
- }
-
- /* Restore the VMCS as the current VMCS. */
- rc2 = hmR0VmxLoadVmcs(pVmcsInfo);
- AssertRC(rc2);
- Assert(!(ASMGetFlags() & X86_EFL_IF));
- ASMSetFlags(fOldEFlags);
- return rc;
-}
-
-
-/**
- * Prepares for and executes VMLAUNCH (64-bit guests) for 32-bit hosts
- * supporting 64-bit guests.
- *
- * @returns VBox status code.
- * @param fResume Whether to VMLAUNCH or VMRESUME.
- * @param pCtx Pointer to the guest-CPU context.
- * @param pCache Pointer to the VMCS batch cache.
- * @param pVM The cross context VM structure.
- * @param pVCpu The cross context virtual CPU structure.
- */
-DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMXVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
-{
- NOREF(fResume);
-
- PVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
- PCHMPHYSCPU pHostCpu = hmR0GetCurrentCpu();
- RTHCPHYS const HCPhysCpuPage = pHostCpu->HCPhysMemObj;
-
-#ifdef VBOX_WITH_CRASHDUMP_MAGIC
- pCache->uPos = 1;
- pCache->interPD = PGMGetInterPaeCR3(pVM);
- pCache->pSwitcher = (uint64_t)pVM->hm.s.pfnHost32ToGuest64R0;
-#endif
-
-#if defined(DEBUG) && defined(VMX_USE_CACHED_VMCS_ACCESSES)
- pCache->TestIn.HCPhysCpuPage = 0;
- pCache->TestIn.HCPhysVmcs = 0;
- pCache->TestIn.pCache = 0;
- pCache->TestOut.HCPhysVmcs = 0;
- pCache->TestOut.pCache = 0;
- pCache->TestOut.pCtx = 0;
- pCache->TestOut.eflags = 0;
-#else
- NOREF(pCache);
-#endif
-
- uint32_t aParam[10];
- aParam[0] = RT_LO_U32(HCPhysCpuPage); /* Param 1: VMXON physical address - Lo. */
- aParam[1] = RT_HI_U32(HCPhysCpuPage); /* Param 1: VMXON physical address - Hi. */
- aParam[2] = RT_LO_U32(pVmcsInfo->HCPhysVmcs); /* Param 2: VMCS physical address - Lo. */
- aParam[3] = RT_HI_U32(pVmcsInfo->HCPhysVmcs); /* Param 2: VMCS physical address - Hi. */
- aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VmcsCache);
- aParam[5] = 0;
- aParam[6] = VM_RC_ADDR(pVM, pVM);
- aParam[7] = 0;
- aParam[8] = VM_RC_ADDR(pVM, pVCpu);
- aParam[9] = 0;
-
-#ifdef VBOX_WITH_CRASHDUMP_MAGIC
- pCtx->dr[4] = pVM->hm.s.vmx.pScratchPhys + 16 + 8;
- *(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) = 1;
-#endif
- int rc = VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_VMXRCStartVM64, RT_ELEMENTS(aParam), &aParam[0]);
-
-#ifdef VBOX_WITH_CRASHDUMP_MAGIC
- Assert(*(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) == 5);
- Assert(pCtx->dr[4] == 10);
- *(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) = 0xff;
-#endif
-
-#if defined(DEBUG) && defined(VMX_USE_CACHED_VMCS_ACCESSES)
- AssertMsg(pCache->TestIn.HCPhysCpuPage == HCPhysCpuPage, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysCpuPage, HCPhysCpuPage));
- AssertMsg(pCache->TestIn.HCPhysVmcs == pVmcsInfo->HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs,
- pVmcsInfo->HCPhysVmcs));
- AssertMsg(pCache->TestIn.HCPhysVmcs == pCache->TestOut.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs,
- pCache->TestOut.HCPhysVmcs));
- AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache,
- pCache->TestOut.pCache));
- AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VmcsCache),
- ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VmcsCache)));
- AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx,
- pCache->TestOut.pCtx));
- Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
-#endif
- NOREF(pCtx);
- return rc;
-}
-#endif
-
-
/**
* Saves the host control registers (CR0, CR3, CR4) into the host-state area in
* the VMCS.
@@ -5111,21 +4879,7 @@ static int hmR0VmxExportGuestEntryExitCtls(PVMCPU pVCpu, PVMXTRANSIENT pVmxTrans
* For nested-guests, we always set this bit as we do not support 32-bit
* hosts.
*/
-#if HC_ARCH_BITS == 64
fVal |= VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE;
-#else
- Assert(!pVmxTransient->fIsNestedGuest);
- Assert( pVmcsInfo->pfnStartVM == VMXR0SwitcherStartVM64
- || pVmcsInfo->pfnStartVM == VMXR0StartVM32);
- /* Set the host address-space size based on the switcher, not guest state. See @bugref{8432}. */
- if (pVmcsInfo->pfnStartVM == VMXR0SwitcherStartVM64)
- {
- /* The switcher returns to long mode, the EFER MSR is managed by the switcher. */
- fVal |= VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE;
- }
- else
- Assert(!(fVal & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE));
-#endif
/*
* If the VMCS EFER MSR fields are supported by the hardware, we use it.
@@ -6968,82 +6722,13 @@ static int hmR0VmxSelectVMRunHandler(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
#endif
Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
-#if HC_ARCH_BITS == 32
- /* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
- if (pVmcsInfo->pfnStartVM != VMXR0SwitcherStartVM64)
- {
-#ifdef VBOX_STRICT
- if (pVmcsInfo->pfnStartVM != NULL) /* Very first VM-entry would have saved host-state already, ignore it. */
- {
- /* Currently, all mode changes sends us back to ring-3, so these should be set. See @bugref{6944}. */
- uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
- RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
- AssertMsg(fCtxChanged & (HM_CHANGED_VMX_ENTRY_EXIT_CTLS | HM_CHANGED_GUEST_EFER_MSR),
- ("fCtxChanged=%#RX64\n", fCtxChanged));
- }
-#endif
- pVmcsInfo->pfnStartVM = VMXR0SwitcherStartVM64;
-
- /* Mark that we've switched to 64-bit handler, we can't safely switch back to 32-bit for
- the rest of the VM run (until VM reset). See @bugref{8432#c7}. */
- pVmcsInfo->fSwitchedTo64on32 = true;
- Log4Func(("Selected 64-bit switcher\n"));
- }
-#else
- /* 64-bit host. */
+ /* Guest is in long mode, use the 64-bit handler (host is 64-bit). */
pVmcsInfo->pfnStartVM = VMXR0StartVM64;
-#endif
}
else
{
/* Guest is not in long mode, use the 32-bit handler. */
-#if HC_ARCH_BITS == 32
- if ( pVmcsInfo->pfnStartVM != VMXR0StartVM32
- && !pVmcsInfo->fSwitchedTo64on32 /* If set, guest mode change does not imply switcher change. */
- && pVmcsInfo->pfnStartVM != NULL) /* Very first VM-entry would have saved host-state already, ignore it. */
- {
-# ifdef VBOX_STRICT
- /* Currently, all mode changes sends us back to ring-3, so these should be set. See @bugref{6944}. */
- uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
- RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
- AssertMsg(fCtxChanged & (HM_CHANGED_VMX_ENTRY_EXIT_CTLS | HM_CHANGED_GUEST_EFER_MSR),
- ("fCtxChanged=%#RX64\n", fCtxChanged));
-# endif
- }
-# ifdef VBOX_ENABLE_64_BITS_GUESTS
- /*
- * Keep using the 64-bit switcher even though we're in 32-bit because of bad Intel
- * design, see @bugref{8432#c7}. If real-on-v86 mode is active, clear the 64-bit
- * switcher flag now because we know the guest is in a sane state where it's safe
- * to use the 32-bit switcher. Otherwise, check the guest state if it's safe to use
- * the much faster 32-bit switcher again.
- */
- if (!pVmcsInfo->fSwitchedTo64on32)
- {
- if (pVmcsInfo->pfnStartVM != VMXR0StartVM32)
- Log4Func(("Selected 32-bit switcher\n"));
- pVmcsInfo->pfnStartVM = VMXR0StartVM32;
- }
- else
- {
- Assert(pVmcsInfo->pfnStartVM == VMXR0SwitcherStartVM64);
- if ( pVmcsInfo->RealMode.fRealOnV86Active
- || hmR0VmxIs32BitSwitcherSafe(pCtx))
- {
- pVmcsInfo->fSwitchedTo64on32 = false;
- pVmcsInfo->pfnStartVM = VMXR0StartVM32;
- ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR
- | HM_CHANGED_VMX_ENTRY_EXIT_CTLS
- | HM_CHANGED_HOST_CONTEXT);
- Log4Func(("Selected 32-bit switcher (safe)\n"));
- }
- }
-# else
pVmcsInfo->pfnStartVM = VMXR0StartVM32;
-# endif
-#else
- pVmcsInfo->pfnStartVM = VMXR0StartVM32;
-#endif
}
Assert(pVmcsInfo->pfnStartVM);
return VINF_SUCCESS;
@@ -11520,17 +11205,8 @@ static void hmR0VmxPostRunGuest(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, int r
TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
-#if HC_ARCH_BITS == 64
pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_REQUIRED; /* Some host state messed up by VMX needs restoring. */
-#endif
-#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
- /* The 64-on-32 switcher maintains VMCS-launch state on its own
- and we need to leave it alone here. */
- if (pVmcsInfo->pfnStartVM != VMXR0SwitcherStartVM64)
- pVmcsInfo->fVmcsState |= VMX_V_VMCS_LAUNCH_STATE_LAUNCHED; /* Use VMRESUME instead of VMLAUNCH in the next run. */
-#else
pVmcsInfo->fVmcsState |= VMX_V_VMCS_LAUNCH_STATE_LAUNCHED; /* Use VMRESUME instead of VMLAUNCH in the next run. */
-#endif
#ifdef VBOX_STRICT
hmR0VmxCheckHostEferMsr(pVCpu, pVmcsInfo); /* Verify that the host EFER MSR wasn't modified. */
#endif
diff --git a/src/VBox/VMM/VMMR0/HMVMXR0.h b/src/VBox/VMM/VMMR0/HMVMXR0.h
index 0edb55d3cb8..489fbe62e21 100644
--- a/src/VBox/VMM/VMMR0/HMVMXR0.h
+++ b/src/VBox/VMM/VMMR0/HMVMXR0.h
@@ -48,11 +48,6 @@ VMMR0DECL(VBOXSTRICTRC) VMXR0RunGuestCode(PVMCPU pVCpu);
DECLASM(int) VMXR0StartVM32(RTHCUINT fResume, PCPUMCTX pCtx, PVMXVMCSCACHE pVmcsCache, PVM pVM, PVMCPU pVCpu);
DECLASM(int) VMXR0StartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMXVMCSCACHE pVmcsCache, PVM pVM, PVMCPU pVCpu);
-# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
-DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMXVMCSCACHE pVmcsCache, PVM pVM, PVMCPU pVCpu);
-VMMR0DECL(int) VMXR0Execute64BitsHandler(PVMCPU pVCpu, HM64ON32OP enmOp, uint32_t cbParam, uint32_t *paParam);
-# endif
-
/* Cached VMCS accesses -- defined only for 32-bit hosts (with 64-bit guest support). */
# ifdef VMX_USE_CACHED_VMCS_ACCESSES
VMMR0DECL(int) VMXWriteCachedVmcsEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
diff --git a/src/VBox/VMM/VMMR0/VMMR0.cpp b/src/VBox/VMM/VMMR0/VMMR0.cpp
index bd1d1fdae05..409849909d2 100644
--- a/src/VBox/VMM/VMMR0/VMMR0.cpp
+++ b/src/VBox/VMM/VMMR0/VMMR0.cpp
@@ -2209,15 +2209,6 @@ static int vmmR0EntryExWorker(PGVM pGVM, PVM pVM, VMCPUID idCpu, VMMR0OPERATION
/** @todo make new test */
return VINF_SUCCESS;
-
-#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
- case VMMR0_DO_TEST_SWITCHER3264:
- if (idCpu == NIL_VMCPUID)
- return VERR_INVALID_CPU_ID;
- rc = HMR0TestSwitcher3264(pVM);
- VMM_CHECK_SMAP_CHECK2(pVM, RT_NOTHING);
- break;
-#endif
default:
/*
* We're returning VERR_NOT_SUPPORT here so we've got something else
diff --git a/src/VBox/VMM/VMMR3/HM.cpp b/src/VBox/VMM/VMMR3/HM.cpp
index 8caa2820048..8931afc3a2f 100644
--- a/src/VBox/VMM/VMMR3/HM.cpp
+++ b/src/VBox/VMM/VMMR3/HM.cpp
@@ -2059,12 +2059,12 @@ VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
pVCpu->hm.s.fActive = false;
pVCpu->hm.s.Event.fPending = false;
pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
- pVCpu->hm.s.vmx.VmcsInfo.fSwitchedTo64on32 = false;
+ pVCpu->hm.s.vmx.VmcsInfo.fSwitchedTo64on32Obsolete = false;
pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
{
- pVCpu->hm.s.vmx.VmcsInfoNstGst.fSwitchedTo64on32 = false;
+ pVCpu->hm.s.vmx.VmcsInfoNstGst.fSwitchedTo64on32Obsolete = false;
pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
}
#endif
diff --git a/src/VBox/VMM/VMMRZ/CPUMRZ.cpp b/src/VBox/VMM/VMMRZ/CPUMRZ.cpp
index 32e948ac2cf..2bd007cc53b 100644
--- a/src/VBox/VMM/VMMRZ/CPUMRZ.cpp
+++ b/src/VBox/VMM/VMMRZ/CPUMRZ.cpp
@@ -65,13 +65,7 @@ VMMRZ_INT_DECL(void) CPUMRZFpuStatePrepareHostCpuForUse(PVMCPU pVCpu)
break;
case CPUM_USED_FPU_GUEST | CPUM_USED_FPU_HOST:
-#if defined(IN_RING0) && ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
- Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
- if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
- HMR0SaveFPUState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
- else
-#endif
- cpumRZSaveGuestFpuState(&pVCpu->cpum.s, true /*fLeaveFpuAccessible*/);
+ cpumRZSaveGuestFpuState(&pVCpu->cpum.s, true /*fLeaveFpuAccessible*/);
#ifdef IN_RING0
HMR0NotifyCpumUnloadedGuestFpuState(pVCpu);
#endif
@@ -110,13 +104,7 @@ VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForRead(PVMCPU pVCpu)
{
if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
{
-#if defined(IN_RING0) && ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
- Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
- if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
- HMR0SaveFPUState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
- else
-#endif
- cpumRZSaveGuestFpuState(&pVCpu->cpum.s, false /*fLeaveFpuAccessible*/);
+ cpumRZSaveGuestFpuState(&pVCpu->cpum.s, false /*fLeaveFpuAccessible*/);
pVCpu->cpum.s.fUseFlags |= CPUM_USED_FPU_GUEST;
Log7(("CPUMRZFpuStateActualizeForRead\n"));
}
@@ -137,16 +125,7 @@ VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeSseForRead(PVMCPU pVCpu)
#else
if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
{
-# if defined(IN_RING0) && ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
- if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
- {
- Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
- HMR0SaveFPUState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
- pVCpu->cpum.s.fUseFlags |= CPUM_USED_FPU_GUEST;
- }
- else
-# endif
- cpumRZSaveGuestSseRegisters(&pVCpu->cpum.s);
+ cpumRZSaveGuestSseRegisters(&pVCpu->cpum.s);
Log7(("CPUMRZFpuStateActualizeSseForRead\n"));
}
#endif
@@ -164,16 +143,7 @@ VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeAvxForRead(PVMCPU pVCpu)
{
if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
{
-#if defined(IN_RING0) && ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
- if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
- {
- Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
- HMR0SaveFPUState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
- pVCpu->cpum.s.fUseFlags |= CPUM_USED_FPU_GUEST;
- }
- else
-#endif
- cpumRZSaveGuestAvxRegisters(&pVCpu->cpum.s);
+ cpumRZSaveGuestAvxRegisters(&pVCpu->cpum.s);
Log7(("CPUMRZFpuStateActualizeAvxForRead\n"));
}
}
diff --git a/src/VBox/VMM/include/HMInternal.h b/src/VBox/VMM/include/HMInternal.h
index 3ad534c6a3c..fde5ef76a26 100644
--- a/src/VBox/VMM/include/HMInternal.h
+++ b/src/VBox/VMM/include/HMInternal.h
@@ -852,7 +852,7 @@ typedef struct VMXVMCSINFO
/** Set if guest was executing in real mode (extra checks). */
bool fWasInRealMode;
/** Set if the guest switched to 64-bit mode on a 32-bit host. */
- bool fSwitchedTo64on32;
+ bool fSwitchedTo64on32Obsolete;
/** Padding. */
bool afPadding0[6];
/** The host CPU for which we have currently exported the host state. */
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