apr_atomic: Use __atomic builtins when available.

Unlike Intel's atomic builtins (__sync_*), the more recent __atomic builtins
provide atomic load and store for weakly ordered architectures like ARM32 or
powerpc[64], so use them when available (gcc 4.6.3+).



git-svn-id: https://svn.apache.org/repos/asf/apr/apr/trunk@1894618 13f79535-47bb-0310-9956-ffa450edef68

10 files changed, 230 insertions, 37 deletions

diff --git a/atomic/unix/builtins.c b/atomic/unix/builtins.c
index ebf8833d1..d0f1b454c 100644
--- a/atomic/unix/builtins.c
+++ b/atomic/unix/builtins.c
@@ -25,57 +25,97 @@ APR_DECLARE(apr_status_t) apr_atomic_init(apr_pool_t *p)
 
 APR_DECLARE(apr_uint32_t) apr_atomic_read32(volatile apr_uint32_t *mem)
 {
+#if HAVE__ATOMIC_BUILTINS
+    return __atomic_load_n(mem, __ATOMIC_SEQ_CST);
+#else
     return *mem;
+#endif
 }
 
 APR_DECLARE(void) apr_atomic_set32(volatile apr_uint32_t *mem, apr_uint32_t val)
 {
+#if HAVE__ATOMIC_BUILTINS
+    __atomic_store_n(mem, val, __ATOMIC_SEQ_CST);
+#else
     *mem = val;
+#endif
 }
 
 APR_DECLARE(apr_uint32_t) apr_atomic_add32(volatile apr_uint32_t *mem, apr_uint32_t val)
 {
+#if HAVE__ATOMIC_BUILTINS
+    return __atomic_fetch_add(mem, val, __ATOMIC_SEQ_CST);
+#else
     return __sync_fetch_and_add(mem, val);
+#endif
 }
 
 APR_DECLARE(void) apr_atomic_sub32(volatile apr_uint32_t *mem, apr_uint32_t val)
 {
+#if HAVE__ATOMIC_BUILTINS
+    __atomic_fetch_sub(mem, val, __ATOMIC_SEQ_CST);
+#else
     __sync_fetch_and_sub(mem, val);
+#endif
 }
 
 APR_DECLARE(apr_uint32_t) apr_atomic_inc32(volatile apr_uint32_t *mem)
 {
+#if HAVE__ATOMIC_BUILTINS
+    return __atomic_fetch_add(mem, 1, __ATOMIC_SEQ_CST);
+#else
     return __sync_fetch_and_add(mem, 1);
+#endif
 }
 
 APR_DECLARE(int) apr_atomic_dec32(volatile apr_uint32_t *mem)
 {
+#if HAVE__ATOMIC_BUILTINS
+    return __atomic_sub_fetch(mem, 1, __ATOMIC_SEQ_CST);
+#else
     return __sync_sub_and_fetch(mem, 1);
+#endif
 }
 
-APR_DECLARE(apr_uint32_t) apr_atomic_cas32(volatile apr_uint32_t *mem, apr_uint32_t with,
+APR_DECLARE(apr_uint32_t) apr_atomic_cas32(volatile apr_uint32_t *mem, apr_uint32_t val,
                                            apr_uint32_t cmp)
 {
-    return __sync_val_compare_and_swap(mem, cmp, with);
+#if HAVE__ATOMIC_BUILTINS
+    __atomic_compare_exchange_n(mem, &cmp, val, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST);
+    return cmp;
+#else
+    return __sync_val_compare_and_swap(mem, cmp, val);
+#endif
 }
 
 APR_DECLARE(apr_uint32_t) apr_atomic_xchg32(volatile apr_uint32_t *mem, apr_uint32_t val)
 {
+#if HAVE__ATOMIC_BUILTINS
+    return __atomic_exchange_n(mem, val, __ATOMIC_SEQ_CST);
+#else
     __sync_synchronize();
-
     return __sync_lock_test_and_set(mem, val);
+#endif
 }
 
-APR_DECLARE(void*) apr_atomic_casptr(void *volatile *mem, void *with, const void *cmp)
+APR_DECLARE(void*) apr_atomic_casptr(void *volatile *mem, void *ptr, const void *cmp)
 {
-    return (void*) __sync_val_compare_and_swap(mem, cmp, with);
+#if HAVE__ATOMIC_BUILTINS
+    __atomic_compare_exchange_n(mem, (void **)&cmp, ptr, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST);
+    return (void *)cmp;
+#else
+    return (void *)__sync_val_compare_and_swap(mem, (void *)cmp, ptr);
+#endif
 }
 
-APR_DECLARE(void*) apr_atomic_xchgptr(void *volatile *mem, void *with)
+APR_DECLARE(void*) apr_atomic_xchgptr(void *volatile *mem, void *ptr)
 {
+#if HAVE__ATOMIC_BUILTINS
+    return __atomic_exchange_n(mem, ptr, __ATOMIC_SEQ_CST);
+#else
     __sync_synchronize();
-
-    return (void*) __sync_lock_test_and_set(mem, with);
+    return __sync_lock_test_and_set(mem, ptr);
+#endif
 }
 
 #endif /* USE_ATOMICS_BUILTINS */
diff --git a/atomic/unix/builtins64.c b/atomic/unix/builtins64.c
index 4a4b685c7..0ac950c15 100644
--- a/atomic/unix/builtins64.c
+++ b/atomic/unix/builtins64.c
@@ -20,45 +20,77 @@
 
 APR_DECLARE(apr_uint64_t) apr_atomic_read64(volatile apr_uint64_t *mem)
 {
+#if HAVE__ATOMIC_BUILTINS
+    return __atomic_load_n(mem, __ATOMIC_SEQ_CST);
+#else
     return *mem;
+#endif
 }
 
 APR_DECLARE(void) apr_atomic_set64(volatile apr_uint64_t *mem, apr_uint64_t val)
 {
+#if HAVE__ATOMIC_BUILTINS
+    __atomic_store_n(mem, val, __ATOMIC_SEQ_CST);
+#else
     *mem = val;
+#endif
 }
 
 APR_DECLARE(apr_uint64_t) apr_atomic_add64(volatile apr_uint64_t *mem, apr_uint64_t val)
 {
+#if HAVE__ATOMIC_BUILTINS
+    return __atomic_fetch_add(mem, val, __ATOMIC_SEQ_CST);
+#else
     return __sync_fetch_and_add(mem, val);
+#endif
 }
 
 APR_DECLARE(void) apr_atomic_sub64(volatile apr_uint64_t *mem, apr_uint64_t val)
 {
+#if HAVE__ATOMIC_BUILTINS
+    __atomic_fetch_sub(mem, val, __ATOMIC_SEQ_CST);
+#else
     __sync_fetch_and_sub(mem, val);
+#endif
 }
 
 APR_DECLARE(apr_uint64_t) apr_atomic_inc64(volatile apr_uint64_t *mem)
 {
+#if HAVE__ATOMIC_BUILTINS
+    return __atomic_fetch_add(mem, 1, __ATOMIC_SEQ_CST);
+#else
     return __sync_fetch_and_add(mem, 1);
+#endif
 }
 
 APR_DECLARE(int) apr_atomic_dec64(volatile apr_uint64_t *mem)
 {
+#if HAVE__ATOMIC_BUILTINS
+    return __atomic_sub_fetch(mem, 1, __ATOMIC_SEQ_CST);
+#else
     return __sync_sub_and_fetch(mem, 1);
+#endif
 }
 
-APR_DECLARE(apr_uint64_t) apr_atomic_cas64(volatile apr_uint64_t *mem, apr_uint64_t with,
+APR_DECLARE(apr_uint64_t) apr_atomic_cas64(volatile apr_uint64_t *mem, apr_uint64_t val,
                                            apr_uint64_t cmp)
 {
-    return __sync_val_compare_and_swap(mem, cmp, with);
+#if HAVE__ATOMIC_BUILTINS
+    __atomic_compare_exchange_n(mem, &cmp, val, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST);
+    return cmp;
+#else
+    return __sync_val_compare_and_swap(mem, cmp, val);
+#endif
 }
 
 APR_DECLARE(apr_uint64_t) apr_atomic_xchg64(volatile apr_uint64_t *mem, apr_uint64_t val)
 {
+#if HAVE__ATOMIC_BUILTINS
+    return __atomic_exchange_n(mem, val, __ATOMIC_SEQ_CST);
+#else
     __sync_synchronize();
-
     return __sync_lock_test_and_set(mem, val);
+#endif
 }
 
 #endif /* USE_ATOMICS_BUILTINS */
diff --git a/atomic/unix/mutex.c b/atomic/unix/mutex.c
index 78ad75336..b9d1cedc9 100644
--- a/atomic/unix/mutex.c
+++ b/atomic/unix/mutex.c
@@ -89,7 +89,7 @@ static APR_INLINE apr_thread_mutex_t *mutex_hash(volatile apr_uint32_t *mem)
 
 APR_DECLARE(apr_status_t) apr_atomic_init(apr_pool_t *p)
 {
-    return apr__atomic_generic64_init(p);
+    return APR_SUCCESS;
 }
 
 #endif /* APR_HAS_THREADS */
diff --git a/atomic/unix/ppc.c b/atomic/unix/ppc.c
index 55bbdd50c..ffba3c27a 100644
--- a/atomic/unix/ppc.c
+++ b/atomic/unix/ppc.c
@@ -35,24 +35,39 @@ APR_DECLARE(apr_status_t) apr_atomic_init(apr_pool_t *p)
 
 APR_DECLARE(apr_uint32_t) apr_atomic_read32(volatile apr_uint32_t *mem)
 {
-    return *mem;
+    apr_uint32_t val;
+    asm volatile ("    sync\n"                 /* full barrier           */
+                  "    lwz %0,%1\n"            /* load                   */
+                  "    cmpw 7,%0,%0\n"         /* compare (always equal) */
+                  "    bne- 7,$+4\n"           /* goto next in any case  */
+                  "    isync"                  /* acquire barrier (bc+isync) */
+                  : "=r"(val)
+                  : "m"(*mem)
+                  : "cc", "memory");
+    return val;
 }
 
 APR_DECLARE(void) apr_atomic_set32(volatile apr_uint32_t *mem, apr_uint32_t val)
 {
-    *mem = val;
+    asm volatile ("    sync\n"                 /* full barrier         */
+                  "    stw %1,%0"              /* store                */
+                  : "=m"(*mem)
+                  : "r"(val)
+                  : "memory");
 }
 
 APR_DECLARE(apr_uint32_t) apr_atomic_add32(volatile apr_uint32_t *mem, apr_uint32_t val)
 {
     apr_uint32_t prev, temp;
 
-    asm volatile ("1:\n"                       /* lost reservation     */
+    asm volatile ("    sync\n"                 /* full barrier         */
+                  "1:\n"                       /* lost reservation     */
                   "    lwarx   %0,0,%3\n"      /* load and reserve     */
                   "    add     %1,%0,%4\n"     /* add val and prev     */
                   PPC405_ERR77_SYNC            /* ppc405 Erratum 77    */
-                  "    stwcx.  %1,0,%3\n"      /* store new value      */
+                  "    stwcx.  %1,0,%3\n"      /* store if still reserved */
                   "    bne-    1b\n"           /* loop if lost         */
+                  "    isync\n"                /* acquire barrier (bc+isync) */
                   : "=&r" (prev), "=&r" (temp), "=m" (*mem)
                   : "b" (mem), "r" (val)
                   : "cc", "memory");
@@ -64,12 +79,14 @@ APR_DECLARE(void) apr_atomic_sub32(volatile apr_uint32_t *mem, apr_uint32_t val)
 {
     apr_uint32_t temp;
 
-    asm volatile ("1:\n"                       /* lost reservation     */
+    asm volatile ("    sync\n"                 /* full barrier         */
+                  "1:\n"                       /* lost reservation     */
                   "    lwarx   %0,0,%2\n"      /* load and reserve     */
                   "    subf    %0,%3,%0\n"     /* subtract val         */
                   PPC405_ERR77_SYNC            /* ppc405 Erratum 77    */
                   "    stwcx.  %0,0,%2\n"      /* store new value      */
                   "    bne-    1b\n"           /* loop if lost         */
+                  "    isync\n"                /* acquire barrier (bc+isync) */
                   : "=&r" (temp), "=m" (*mem)
                   : "b" (mem), "r" (val)
                   : "cc", "memory");
@@ -79,13 +96,15 @@ APR_DECLARE(apr_uint32_t) apr_atomic_inc32(volatile apr_uint32_t *mem)
 {
     apr_uint32_t prev;
 
-    asm volatile ("1:\n"                       /* lost reservation     */
+    asm volatile ("    sync\n"                 /* full barrier         */
+                  "1:\n"                       /* lost reservation     */
                   "    lwarx   %0,0,%2\n"      /* load and reserve     */
                   "    addi    %0,%0,1\n"      /* add immediate        */
                   PPC405_ERR77_SYNC            /* ppc405 Erratum 77    */
                   "    stwcx.  %0,0,%2\n"      /* store new value      */
                   "    bne-    1b\n"           /* loop if lost         */
                   "    subi    %0,%0,1\n"      /* return old value     */
+                  "    isync\n"                /* acquire barrier (bc+isync) */
                   : "=&b" (prev), "=m" (*mem)
                   : "b" (mem), "m" (*mem)
                   : "cc", "memory");
@@ -97,12 +116,14 @@ APR_DECLARE(int) apr_atomic_dec32(volatile apr_uint32_t *mem)
 {
     apr_uint32_t prev;
 
-    asm volatile ("1:\n"                       /* lost reservation     */
+    asm volatile ("    sync\n"                 /* full barrier         */
+                  "1:\n"                       /* lost reservation     */
                   "    lwarx   %0,0,%2\n"      /* load and reserve     */
                   "    subi    %0,%0,1\n"      /* subtract immediate   */
                   PPC405_ERR77_SYNC            /* ppc405 Erratum 77    */
                   "    stwcx.  %0,0,%2\n"      /* store new value      */
                   "    bne-    1b\n"           /* loop if lost         */
+                  "    isync\n"                /* acquire barrier (bc+isync) */
                   : "=&b" (prev), "=m" (*mem)
                   : "b" (mem), "m" (*mem)
                   : "cc", "memory");
@@ -115,7 +136,8 @@ APR_DECLARE(apr_uint32_t) apr_atomic_cas32(volatile apr_uint32_t *mem, apr_uint3
 {
     apr_uint32_t prev;
 
-    asm volatile ("1:\n"                       /* lost reservation     */
+    asm volatile ("    sync\n"                 /* full barrier         */
+                  "1:\n"                       /* lost reservation     */
                   "    lwarx   %0,0,%1\n"      /* load and reserve     */
                   "    cmpw    %0,%3\n"        /* compare operands     */
                   "    bne-    exit_%=\n"      /* skip if not equal    */
@@ -123,6 +145,7 @@ APR_DECLARE(apr_uint32_t) apr_atomic_cas32(volatile apr_uint32_t *mem, apr_uint3
                   "    stwcx.  %2,0,%1\n"      /* store new value      */
                   "    bne-    1b\n"           /* loop if lost         */
                   "exit_%=:\n"                 /* not equal            */
+                  "    isync\n"                /* acquire barrier (bc+isync) */
                   : "=&r" (prev)
                   : "b" (mem), "r" (with), "r" (cmp)
                   : "cc", "memory");
@@ -134,11 +157,13 @@ APR_DECLARE(apr_uint32_t) apr_atomic_xchg32(volatile apr_uint32_t *mem, apr_uint
 {
     apr_uint32_t prev;
 
-    asm volatile ("1:\n"                       /* lost reservation     */
+    asm volatile ("    sync\n"                 /* full barrier         */
+                  "1:\n"                       /* lost reservation     */
                   "    lwarx   %0,0,%1\n"      /* load and reserve     */
                   PPC405_ERR77_SYNC            /* ppc405 Erratum 77    */
                   "    stwcx.  %2,0,%1\n"      /* store new value      */
-                  "    bne-    1b"             /* loop if lost         */
+                  "    bne-    1b\n"           /* loop if lost         */
+                  "    isync\n"                /* acquire barrier (bc+isync) */
                   : "=&r" (prev)
                   : "b" (mem), "r" (val)
                   : "cc", "memory");
@@ -150,7 +175,8 @@ APR_DECLARE(void*) apr_atomic_casptr(void *volatile *mem, void *with, const void
 {
     void *prev;
 #if APR_SIZEOF_VOIDP == 4
-    asm volatile ("1:\n"                       /* lost reservation     */
+    asm volatile ("    sync\n"                 /* full barrier         */
+                  "1:\n"                       /* lost reservation     */
                   "    lwarx   %0,0,%1\n"      /* load and reserve     */
                   "    cmpw    %0,%3\n"        /* compare operands     */
                   "    bne-    2f\n"           /* skip if not equal    */
@@ -158,11 +184,13 @@ APR_DECLARE(void*) apr_atomic_casptr(void *volatile *mem, void *with, const void
                   "    stwcx.  %2,0,%1\n"      /* store new value      */
                   "    bne-    1b\n"           /* loop if lost         */
                   "2:\n"                       /* not equal            */
+                  "    isync\n"                /* acquire barrier (bc+isync) */
                   : "=&r" (prev)
                   : "b" (mem), "r" (with), "r" (cmp)
                   : "cc", "memory");
 #elif APR_SIZEOF_VOIDP == 8
-    asm volatile ("1:\n"                       /* lost reservation     */
+    asm volatile ("    sync\n"                 /* full barrier         */
+                  "1:\n"                       /* lost reservation     */
                   "    ldarx   %0,0,%1\n"      /* load and reserve     */
                   "    cmpd    %0,%3\n"        /* compare operands     */
                   "    bne-    2f\n"           /* skip if not equal    */
@@ -170,6 +198,7 @@ APR_DECLARE(void*) apr_atomic_casptr(void *volatile *mem, void *with, const void
                   "    stdcx.  %2,0,%1\n"      /* store new value      */
                   "    bne-    1b\n"           /* loop if lost         */
                   "2:\n"                       /* not equal            */
+                  "    isync\n"                /* acquire barrier (bc+isync) */
                   : "=&r" (prev)
                   : "b" (mem), "r" (with), "r" (cmp)
                   : "cc", "memory");
@@ -183,22 +212,24 @@ APR_DECLARE(void*) apr_atomic_xchgptr(void *volatile *mem, void *with)
 {
     void *prev;
 #if APR_SIZEOF_VOIDP == 4
-    asm volatile ("1:\n"                       /* lost reservation     */
+    asm volatile ("    sync\n"                 /* full barrier         */
+                  "1:\n"                       /* lost reservation     */
                   "    lwarx   %0,0,%1\n"      /* load and reserve     */
                   PPC405_ERR77_SYNC            /* ppc405 Erratum 77    */
                   "    stwcx.  %2,0,%1\n"      /* store new value      */
                   "    bne-    1b\n"           /* loop if lost         */
-                  "    isync\n"                /* memory barrier       */
+                  "    isync\n"                /* acquire barrier (bc+isync) */
                   : "=&r" (prev)
                   : "b" (mem), "r" (with)
                   : "cc", "memory");
 #elif APR_SIZEOF_VOIDP == 8
-    asm volatile ("1:\n"                       /* lost reservation     */
+    asm volatile ("    sync\n"                 /* full barrier         */
+                  "1:\n"                       /* lost reservation     */
                   "    ldarx   %0,0,%1\n"      /* load and reserve     */
                   PPC405_ERR77_SYNC            /* ppc405 Erratum 77    */
                   "    stdcx.  %2,0,%1\n"      /* store new value      */
                   "    bne-    1b\n"           /* loop if lost         */
-                  "    isync\n"                /* memory barrier       */
+                  "    isync\n"                /* acquire barrier (bc+isync) */
                   : "=&r" (prev)
                   : "b" (mem), "r" (with)
                   : "cc", "memory");
diff --git a/configure.in b/configure.in
index 5fa318306..3e4be99cc 100644
--- a/configure.in
+++ b/configure.in
@@ -487,7 +487,7 @@ esac
 
 AC_CACHE_CHECK([whether the compiler provides atomic builtins], [ap_cv_atomic_builtins],
 [AC_TRY_RUN([
-int main()
+int main(int argc, const char *const *argv)
 {
     unsigned long val = 1010, tmp, *mem = &val;
 
@@ -495,7 +495,6 @@ int main()
         return 1;
 
     tmp = val;
-
     if (__sync_fetch_and_sub(mem, 1010) != tmp || val != 1010)
         return 1;
 
@@ -503,28 +502,56 @@ int main()
         return 1;
 
     tmp = 3030;
-
     if (__sync_val_compare_and_swap(mem, 0, tmp) != 0 || val != tmp)
         return 1;
 
+    __sync_synchronize();
     if (__sync_lock_test_and_set(&val, 4040) != 3030)
         return 1;
 
-    mem = &tmp;
+    if (__sync_val_compare_and_swap(&mem, &val, &tmp) != &val || mem != &tmp)
+        return 1;
+
+    return 0;
+}], [ap_cv_atomic_builtins=yes], [ap_cv_atomic_builtins=no], [ap_cv_atomic_builtins=no])])
+
+AC_CACHE_CHECK([whether the compiler provides __atomic builtins], [ap_cv__atomic_builtins],
+[AC_TRY_RUN([
+int main(int argc, const char *const *argv)
+{
+    unsigned long val = 1010, tmp, *mem = &val, *ptmp;
 
-    if (__sync_val_compare_and_swap(&mem, &tmp, &val) != &tmp)
+    if (__atomic_fetch_add(&val, 1010, __ATOMIC_SEQ_CST) != 1010 || val != 2020)
         return 1;
 
-    __sync_synchronize();
+    tmp = val;
+    if (__atomic_fetch_sub(mem, 1010, __ATOMIC_SEQ_CST) != tmp || val != 1010)
+        return 1;
+
+    if (__atomic_sub_fetch(&val, 1010, __ATOMIC_SEQ_CST) != 0 || val != 0)
+        return 1;
 
-    if (mem != &val)
+    tmp = val;
+    if (!__atomic_compare_exchange_n(mem, &tmp, 3030, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST)
+            || tmp != 0)
+        return 1;
+
+    if (__atomic_exchange_n(&val, 4040, __ATOMIC_SEQ_CST) != 3030)
+        return 1;
+
+    ptmp = &val;
+    if (!__atomic_compare_exchange_n(&mem, &ptmp, &tmp, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST)
+            || ptmp != &val || mem != &tmp)
         return 1;
 
     return 0;
-}], [ap_cv_atomic_builtins=yes], [ap_cv_atomic_builtins=no], [ap_cv_atomic_builtins=no])])
+}], [ap_cv__atomic_builtins=yes], [ap_cv__atomic_builtins=no], [ap_cv__atomic_builtins=no])])
 
-if test "$ap_cv_atomic_builtins" = "yes"; then
+if test "$ap_cv_atomic_builtins" = "yes" -o "$ap_cv__atomic_builtins" = "yes"; then
     AC_DEFINE(HAVE_ATOMIC_BUILTINS, 1, [Define if compiler provides atomic builtins])
+    if test "$ap_cv__atomic_builtins" = "yes"; then
+        AC_DEFINE(HAVE__ATOMIC_BUILTINS, 1, [Define if compiler provides __atomic builtins])
+    fi
 fi
 
 AC_CACHE_CHECK([whether the compiler handles weak symbols], [ap_cv_weak_symbols],
diff --git a/include/apr.h.in b/include/apr.h.in
index c498376d9..efb791a22 100644
--- a/include/apr.h.in
+++ b/include/apr.h.in
@@ -45,6 +45,26 @@
  * are platform specific and should NOT be relied upon!</em></strong>
  */
 
+/* So that we can test for clang features */
+#ifndef	__has_feature
+#define	__has_feature(x) 0
+#endif
+#ifndef	__has_extension
+#define	__has_extension  __has_feature
+#endif
+#ifndef	__has_include
+#define	__has_include(x) 0
+#endif
+#ifndef	__has_builtin
+#define	__has_builtin(x) 0
+#endif
+
+#if !(defined(__attribute__) \
+      || (defined(__GNUC__) && (__GNUC__ > 2 || (__GNUC__ == 2 && \
+                                                 __GNUC_MINOR__ >= 4))))
+#define __attribute__(x)
+#endif
+
 /* So that we can use inline on some critical functions, and use
  * GNUC attributes (such as to get -Wall warnings for printf-like
  * functions).  Only do this in gcc 2.7 or later ... it may work
@@ -70,6 +90,7 @@
 #endif
 
 #define APR_HAVE_ARPA_INET_H     @arpa_ineth@
+#define APR_HAVE_ASSERT_H        @asserth@
 #define APR_HAVE_CONIO_H         @conioh@
 #define APR_HAVE_CRYPT_H         @crypth@
 #define APR_HAVE_CTYPE_H         @ctypeh@
diff --git a/include/apr.hnw b/include/apr.hnw
index 6db0c9b5e..10ebb390a 100644
--- a/include/apr.hnw
+++ b/include/apr.hnw
@@ -80,6 +80,7 @@ extern "C" {
 #endif
 #define ENUM_BITFIELD(e,n,w)  signed int n : w
 
+#define APR_HAVE_ASSERT_H               1
 #define APR_HAVE_CONIO_H                0
 #define APR_HAVE_CRYPT_H                0
 #define APR_HAVE_CTYPE_H                1
diff --git a/include/apr.hw b/include/apr.hw
index 7cdfd1570..b0c2fe524 100644
--- a/include/apr.hw
+++ b/include/apr.hw
@@ -130,6 +130,7 @@
 #endif
 
 #define APR_HAVE_ARPA_INET_H    0
+#define APR_HAVE_ASSERT_H       1
 #define APR_HAVE_CONIO_H         APR_NOT_IN_WCE
 #define APR_HAVE_CRYPT_H        0
 #define APR_HAVE_CTYPE_H         APR_NOT_IN_WCE
diff --git a/include/apr.hwc b/include/apr.hwc
index 03bcd5e8e..8362fffcb 100644
--- a/include/apr.hwc
+++ b/include/apr.hwc
@@ -129,6 +129,7 @@
 #define APR_NOT_IN_WCE          1
 #endif
 
+#define APR_HAVE_ASSERT_H       1
 #define APR_HAVE_ARPA_INET_H    0
 #define APR_HAVE_CONIO_H         APR_NOT_IN_WCE
 #define APR_HAVE_CRYPT_H        0
diff --git a/include/apr_general.h b/include/apr_general.h
index 4f2a6e8c4..5e53bb63d 100644
--- a/include/apr_general.h
+++ b/include/apr_general.h
@@ -29,6 +29,9 @@
 #include "apr_pools.h"
 #include "apr_errno.h"
 
+#if APR_HAVE_ASSERT_H
+#include <assert.h>
+#endif
 #if APR_HAVE_SIGNAL_H
 #include <signal.h>
 #endif
@@ -112,6 +115,42 @@ typedef enum { APR_WAIT_READ, APR_WAIT_WRITE } apr_wait_type_t;
 #define APR_OFFSETOF(s_type,field) APR_OFFSET(s_type*,field)
 #endif
 
+/**
+ * Compile time assertions.
+ * @param predicate static condition
+ * @param errstring static error message (literal)
+ */
+#if defined(static_assert) \
+    || __has_builtin(static_assert) \
+    || (defined(__cplusplus) && (__cplusplus >= 201103L || \
+                                 __has_extension(cxx_static_assert))) \
+    || (defined(_MSC_VER ) && _MSC_VER >= 1600)
+#define APR_STATIC_ASSERT static_assert
+
+#elif defined(_Static_assert) \
+    || __has_builtin(_Static_assert) \
+    || __has_extension(c_static_assert) \
+    || (defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == 4 && \
+                                               __GNUC_MINOR__ >= 6)))
+#define APR_STATIC_ASSERT _Static_assert
+
+#else  /* !static_assert && !_Static_assert */
+#define APR__STATIC_CONCAT_(x, y) x##y
+#define APR__STATIC_CONCAT(x, y) APR__STATIC_CONCAT_(x, y)
+#if defined(__COUNTER__)
+#define APR_STATIC_ASSERT(predicate, errstring) \
+    typedef struct { \
+        int static_assert_failure:!!(predicate)*2-1; \
+    } APR__STATIC_CONCAT(static_assert_test_, __COUNTER__);
+#else  /* !__COUNTER__ */
+#define APR_STATIC_ASSERT(predicate, errstring) \
+    typedef struct { \
+        int static_assert_failure:!!(predicate)*2-1; \
+    } APR__STATIC_CONCAT(static_assert_test_, __LINE__);
+#endif /* !__COUNTER__ */
+
+#endif /* !static_assert && !_Static_assert */
+
 #ifndef DOXYGEN
 
 /* A couple of prototypes for functions in case some platform doesn't