diff options
| author | Renaud Barbier <Renaud.Barbier@ametek.com> | 2023-04-10 14:58:08 +0000 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-04-11 14:33:16 +0200 |
| commit | 02418643b149fca43ac760dc1d91194e209de516 (patch) | |
| tree | 16e6d020d489ea6ab7947156738554f79cda6266 | |
| parent | 76616c22ba57b7112f761a64cdd4916de814e7b4 (diff) | |
| download | barebox-02418643b149fca43ac760dc1d91194e209de516.tar.gz | |
ARM: LS1021A: slow boot
It was noticed that the LS1021A-IOT was slow to boot and perform
computing intensive operations. Enable SMP so the cortex-a7 cache
works as expected.
Signed-off-by: Renaud Barbier mailto:renaud.barbier@ametek.com
Link: https://lore.barebox.org/BL0PR07MB5665E8DA118845ED96A8289DEC959@BL0PR07MB5665.namprd07.prod.outlook.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/boards/ls1021aiot/lowlevel.c | 1 | ||||
| -rw-r--r-- | arch/arm/mach-layerscape/lowlevel-ls102xa.c | 4 |
2 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/boards/ls1021aiot/lowlevel.c b/arch/arm/boards/ls1021aiot/lowlevel.c index 4dec451558..b7106887f2 100644 --- a/arch/arm/boards/ls1021aiot/lowlevel.c +++ b/arch/arm/boards/ls1021aiot/lowlevel.c @@ -86,7 +86,6 @@ static noinline __noreturn void ls1021aiot_r_entry(void) __dtb_fsl_ls1021a_iot_start); } - arm_cpu_lowlevel_init(); ls102xa_init_lowlevel(); ls102xa_debug_ll_init(); diff --git a/arch/arm/mach-layerscape/lowlevel-ls102xa.c b/arch/arm/mach-layerscape/lowlevel-ls102xa.c index 7f4fcdf55c..259d8866d5 100644 --- a/arch/arm/mach-layerscape/lowlevel-ls102xa.c +++ b/arch/arm/mach-layerscape/lowlevel-ls102xa.c @@ -6,6 +6,7 @@ #include <common.h> #include <io.h> #include <clock.h> +#include <asm/barebox-arm-head.h> #include <asm/syscounter.h> #include <asm/system.h> #include <mach/layerscape/errata.h> @@ -311,6 +312,9 @@ void ls102xa_init_lowlevel(void) uint32_t state, major, ctrl, freq; uint64_t val; + cortex_a7_lowlevel_init(); + arm_cpu_lowlevel_init(); + init_csu(); writel(SYS_COUNTER_CTRL_ENABLE, LSCH2_SYS_COUNTER_ADDR); |