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authorSascha Hauer <s.hauer@pengutronix.de>2014-06-04 21:04:28 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2014-06-04 21:04:28 +0200
commitad9f56888f00afca589e3a9e14ff856cebf540a7 (patch)
treeb12b889ef1ce04141d3fe3520706ad29fb15668f /arch
parentc9bbafe1dc98a7264f756e84c3c32eb5bebe0218 (diff)
parent7b8f46983e2bc00952f2e2afb9dec80cbb266621 (diff)
downloadbarebox-ad9f56888f00afca589e3a9e14ff856cebf540a7.tar.gz
Merge branch 'for-next/tegra'
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/boards/nvidia-beaver/Makefile3
-rw-r--r--arch/arm/boards/nvidia-beaver/beaver-2gb-emmc.bct.cfg819
-rw-r--r--arch/arm/boards/nvidia-beaver/board.c38
-rw-r--r--arch/arm/boards/toradex-colibri-t20/Makefile4
-rw-r--r--arch/arm/boards/toradex-colibri-t20/colibri-t20_256_hsmmc.bct.cfg451
-rw-r--r--arch/arm/boards/toradex-colibri-t20/colibri-t20_256_v11_nand.bct.cfg459
-rw-r--r--arch/arm/boards/toradex-colibri-t20/colibri-t20_256_v12_nand.bct.cfg459
-rw-r--r--arch/arm/boards/toradex-colibri-t20/colibri-t20_512_hsmmc.bct.cfg451
-rw-r--r--arch/arm/boards/toradex-colibri-t20/colibri-t20_512_v11_nand.bct.cfg459
-rw-r--r--arch/arm/boards/toradex-colibri-t20/colibri-t20_512_v12_nand.bct.cfg459
-rw-r--r--arch/arm/boards/toradex-colibri-t20/entry.c42
-rw-r--r--arch/arm/dts/tegra30-beaver.dts10
-rw-r--r--arch/arm/mach-tegra/Kconfig2
-rw-r--r--arch/arm/mach-tegra/include/mach/lowlevel-dvc.h6
-rw-r--r--arch/arm/mach-tegra/include/mach/lowlevel.h6
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra30-car.h2
-rw-r--r--arch/arm/mach-tegra/tegra20-pmc.c2
18 files changed, 3669 insertions, 4 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d1c5caecfa..6e54c8f55a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -192,6 +192,7 @@ config ARCH_TEGRA
select OFDEVICE
select OFTREE
select RELOCATABLE
+ select RESET_CONTROLLER
config ARCH_ZYNQ
bool "Xilinx Zynq-based boards"
diff --git a/arch/arm/boards/nvidia-beaver/Makefile b/arch/arm/boards/nvidia-beaver/Makefile
index d2d217319b..7ade54e854 100644
--- a/arch/arm/boards/nvidia-beaver/Makefile
+++ b/arch/arm/boards/nvidia-beaver/Makefile
@@ -1,4 +1,7 @@
CFLAGS_pbl-entry.o := \
-mcpu=arm7tdmi -march=armv4t \
-fno-tree-switch-conversion -fno-jump-tables
+soc := tegra30
lwl-y += entry.o
+obj-y += board.o
+extra-y += beaver-2gb-emmc.bct
diff --git a/arch/arm/boards/nvidia-beaver/beaver-2gb-emmc.bct.cfg b/arch/arm/boards/nvidia-beaver/beaver-2gb-emmc.bct.cfg
new file mode 100644
index 0000000000..49f302fc45
--- /dev/null
+++ b/arch/arm/boards/nvidia-beaver/beaver-2gb-emmc.bct.cfg
@@ -0,0 +1,819 @@
+# Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+# claim that you wrote the original software. If you use this software
+# in a product, an acknowledgment in the product documentation would be
+# appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+# misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+Version = 0x00030001;
+BlockSize = 0x00004000;
+PageSize = 0x00000200;
+PartitionSize = 0x02000000;
+OdmData = 0x800c0000;
+
+DevType[0] = NvBootDevType_Sdmmc;
+DeviceParam[0].SdmmcParams.ClockDivider = 0x00000009;
+DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[0].SdmmcParams.SdController = 0x00000000;
+
+DevType[1] = NvBootDevType_Sdmmc;
+DeviceParam[1].SdmmcParams.ClockDivider = 0x00000009;
+DeviceParam[1].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[1].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[1].SdmmcParams.SdController = 0x00000000;
+
+DevType[2] = NvBootDevType_Sdmmc;
+DeviceParam[2].SdmmcParams.ClockDivider = 0x00000009;
+DeviceParam[2].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[2].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[2].SdmmcParams.SdController = 0x00000000;
+
+DevType[3] = NvBootDevType_Sdmmc;
+DeviceParam[3].SdmmcParams.ClockDivider = 0x00000009;
+DeviceParam[3].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[3].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[3].SdmmcParams.SdController = 0x00000000;
+
+SDRAM[0].MemoryType = NvBootMemoryType_Ddr3;
+SDRAM[0].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[0].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[0].PllMInputDivider = 0x0000000c;
+SDRAM[0].PllMFeedbackDivider = 0x00000320;
+SDRAM[0].PllMPostDivider = 0x00000000;
+SDRAM[0].PllMStableTime = 0x0000012c;
+SDRAM[0].EmcClockDivider = 0x00000002;
+SDRAM[0].EmcAutoCalInterval = 0x001fffff;
+SDRAM[0].EmcAutoCalConfig = 0xa0f10000;
+SDRAM[0].EmcAutoCalWait = 0x00000064;
+SDRAM[0].EmcPinProgramWait = 0x00000001;
+SDRAM[0].EmcRc = 0x00000012;
+SDRAM[0].EmcRfc = 0x00000066;
+SDRAM[0].EmcRas = 0x0000000c;
+SDRAM[0].EmcRp = 0x00000004;
+SDRAM[0].EmcR2w = 0x00000003;
+SDRAM[0].EmcW2r = 0x00000008;
+SDRAM[0].EmcR2p = 0x00000002;
+SDRAM[0].EmcW2p = 0x0000000a;
+SDRAM[0].EmcRrd = 0x00000002;
+SDRAM[0].EmcRdRcd = 0x00000004;
+SDRAM[0].EmcWrRcd = 0x00000004;
+SDRAM[0].EmcRext = 0x00000001;
+SDRAM[0].EmcWdv = 0x00000004;
+SDRAM[0].EmcQUseExtra = 0x00000000;
+SDRAM[0].EmcQUse = 0x00000006;
+SDRAM[0].EmcQRst = 0x00000004;
+SDRAM[0].EmcQSafe = 0x0000000a;
+SDRAM[0].EmcRdv = 0x0000000d;
+SDRAM[0].EmcRefresh = 0x00000bf0;
+SDRAM[0].EmcBurstRefreshNum = 0x00000000;
+SDRAM[0].EmcPdEx2Wr = 0x00000001;
+SDRAM[0].EmcPdEx2Rd = 0x00000008;
+SDRAM[0].EmcPChg2Pden = 0x00000001;
+SDRAM[0].EmcAct2Pden = 0x00000000;
+SDRAM[0].EmcAr2Pden = 0x00000008;
+SDRAM[0].EmcRw2Pden = 0x0000000f;
+SDRAM[0].EmcTxsr = 0x0000006c;
+SDRAM[0].EmcTcke = 0x00000004;
+SDRAM[0].EmcTfaw = 0x0000000c;
+SDRAM[0].EmcTrpab = 0x00000000;
+SDRAM[0].EmcTClkStable = 0x00000004;
+SDRAM[0].EmcTClkStop = 0x00000005;
+SDRAM[0].EmcTRefBw = 0x00000c30;
+SDRAM[0].EmcFbioCfg5 = 0x00007088;
+SDRAM[0].EmcFbioCfg6 = 0x00000006;
+SDRAM[0].EmcFbioSpare = 0xe8000000;
+SDRAM[0].EmcMrsResetDllWait = 0x00000000;
+SDRAM[0].EmcMrsResetDll = 0x00000000;
+SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[0].EmcMrs = 0x80000521;
+SDRAM[0].EmcEmrsEmr2 = 0x80200000;
+SDRAM[0].EmcEmrsEmr3 = 0x80300000;
+SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[0].EmcEmrs = 0x80100002;
+SDRAM[0].EmcMrw1 = 0x00000000;
+SDRAM[0].EmcMrw2 = 0x00000000;
+SDRAM[0].EmcMrw3 = 0x00000000;
+SDRAM[0].EmcMrwResetCommand = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[0].EmcAdrCfg = 0x00000080;
+SDRAM[0].McEmemCfg = 0x00000800;
+SDRAM[0].EmcCfg2 = 0x000c0099;
+SDRAM[0].EmcCfgDigDll = 0x001d0084;
+SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[0].EmcCfg = 0x23c00000;
+SDRAM[0].EmcDbg = 0x01000400;
+SDRAM[0].WarmBootWait = 0x00000002;
+SDRAM[0].EmcCttTermCtrl = 0x00000802;
+SDRAM[0].EmcOdtWrite = 0x00000000;
+SDRAM[0].EmcOdtRead = 0x00000000;
+SDRAM[0].EmcZcalWaitCnt = 0x00000040;
+SDRAM[0].EmcZcalMrwCmd = 0x80000000;
+SDRAM[0].EmcDdr2Wait = 0x00000000;
+SDRAM[0].PmcDdrPwr = 0x00000003;
+SDRAM[0].EmcClockSource = 0x00000000;
+SDRAM[0].EmcClockUsePllMUD = 0x00000000;
+SDRAM[0].EmcPinExtraWait = 0x00000000;
+SDRAM[0].EmcTimingControlWait = 0x00000000;
+SDRAM[0].EmcWext = 0x00000000;
+SDRAM[0].EmcCtt = 0x00000000;
+SDRAM[0].EmcCttDuration = 0x00000000;
+SDRAM[0].EmcPreRefreshReqCnt = 0x000002fc;
+SDRAM[0].EmcTxsrDll = 0x00000200;
+SDRAM[0].EmcCfgRsv = 0xff00ff89;
+SDRAM[0].EmcMrwExtra = 0x00000000;
+SDRAM[0].EmcWarmBootMrw1 = 0x00000000;
+SDRAM[0].EmcWarmBootMrw2 = 0x00000000;
+SDRAM[0].EmcWarmBootMrw3 = 0x00000000;
+SDRAM[0].EmcWarmBootMrwExtra = 0x00000000;
+SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[0].EmcMrsWaitCnt = 0x0158000c;
+SDRAM[0].EmcCmdQ = 0x10004408;
+SDRAM[0].EmcMc2EmcQ = 0x06000404;
+SDRAM[0].EmcDynSelfRefControl = 0x800018c8;
+SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[0].EmcDevSelect = 0x00000002;
+SDRAM[0].EmcSelDpdCtrl = 0x0004032c;
+SDRAM[0].EmcDllXformDqs0 = 0x00038000;
+SDRAM[0].EmcDllXformDqs1 = 0x00038000;
+SDRAM[0].EmcDllXformDqs2 = 0x00038000;
+SDRAM[0].EmcDllXformDqs3 = 0x00038000;
+SDRAM[0].EmcDllXformDqs4 = 0x00038000;
+SDRAM[0].EmcDllXformDqs5 = 0x00038000;
+SDRAM[0].EmcDllXformDqs6 = 0x00038000;
+SDRAM[0].EmcDllXformDqs7 = 0x00038000;
+SDRAM[0].EmcDllXformQUse0 = 0x00000000;
+SDRAM[0].EmcDllXformQUse1 = 0x00000000;
+SDRAM[0].EmcDllXformQUse2 = 0x00000000;
+SDRAM[0].EmcDllXformQUse3 = 0x00000000;
+SDRAM[0].EmcDllXformQUse4 = 0x00000000;
+SDRAM[0].EmcDllXformQUse5 = 0x00000000;
+SDRAM[0].EmcDllXformQUse6 = 0x00000000;
+SDRAM[0].EmcDllXformQUse7 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000;
+SDRAM[0].EmcDllXformDq0 = 0x00030000;
+SDRAM[0].EmcDllXformDq1 = 0x00030000;
+SDRAM[0].EmcDllXformDq2 = 0x00030000;
+SDRAM[0].EmcDllXformDq3 = 0x00030000;
+SDRAM[0].EmcZcalInterval = 0x00020000;
+SDRAM[0].EmcZcalInitDev0 = 0x80000011;
+SDRAM[0].EmcZcalInitDev1 = 0x00000000;
+SDRAM[0].EmcZcalInitWait = 0x00000002;
+SDRAM[0].EmcZcalColdBootEnable = 0x00000001;
+SDRAM[0].EmcZcalWarmBootEnable = 0x00000001;
+SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x000a00ab;
+SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000011;
+SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[0].EmcMrsExtra = 0x80000521;
+SDRAM[0].EmcWarmBootMrs = 0x80100002;
+SDRAM[0].EmcWarmBootEmrs = 0x80000521;
+SDRAM[0].EmcWarmBootEmr2 = 0x80200000;
+SDRAM[0].EmcWarmBootEmr3 = 0x80300000;
+SDRAM[0].EmcWarmBootMrsExtra = 0x80100002;
+SDRAM[0].EmcClkenOverride = 0x00000000;
+SDRAM[0].EmcExtraRefreshNum = 0x00000002;
+SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[0].PmcVddpSel = 0x00000002;
+SDRAM[0].PmcDdrCfg = 0x00000002;
+SDRAM[0].PmcIoDpdReq = 0x80800000;
+SDRAM[0].PmcENoVttGen = 0x00000000;
+SDRAM[0].PmcNoIoPower = 0x00000000;
+SDRAM[0].EmcXm2CmdPadCtrl = 0x000002a0;
+SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0800013d;
+SDRAM[0].EmcXm2DqsPadCtrl3 = 0x08000021;
+SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[0].EmcXm2ClkPadCtrl = 0x77fff884;
+SDRAM[0].EmcXm2CompPadCtrl = 0x01f1f508;
+SDRAM[0].EmcXm2VttGenPadCtrl = 0x05057404;
+SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x54000007;
+SDRAM[0].EmcXm2QUsePadCtrl = 0x080001e8;
+SDRAM[0].McEmemAdrCfg = 0x00000000;
+SDRAM[0].McEmemAdrCfgDev0 = 0x00090303;
+SDRAM[0].McEmemAdrCfgDev1 = 0x00090303;
+SDRAM[0].McEmemArbCfg = 0x00000006;
+SDRAM[0].McEmemArbOutstandingReq = 0x80000048;
+SDRAM[0].McEmemArbTimingRcd = 0x00000001;
+SDRAM[0].McEmemArbTimingRp = 0x00000002;
+SDRAM[0].McEmemArbTimingRc = 0x00000009;
+SDRAM[0].McEmemArbTimingRas = 0x00000005;
+SDRAM[0].McEmemArbTimingFaw = 0x00000005;
+SDRAM[0].McEmemArbTimingRrd = 0x00000001;
+SDRAM[0].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[0].McEmemArbTimingWap2Pre = 0x00000008;
+SDRAM[0].McEmemArbTimingR2R = 0x00000002;
+SDRAM[0].McEmemArbTimingW2W = 0x00000002;
+SDRAM[0].McEmemArbTimingR2W = 0x00000003;
+SDRAM[0].McEmemArbTimingW2R = 0x00000006;
+SDRAM[0].McEmemArbDaTurns = 0x06030202;
+SDRAM[0].McEmemArbDaCovers = 0x000d0709;
+SDRAM[0].McEmemArbMisc0 = 0x7086120a;
+SDRAM[0].McEmemArbMisc1 = 0x78000000;
+SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[0].McEmemArbOverride = 0x00000080;
+SDRAM[0].McEmemArbRsv = 0xff00ff00;
+SDRAM[0].McClkenOverride = 0x00000000;
+
+SDRAM[1].MemoryType = NvBootMemoryType_Ddr3;
+SDRAM[1].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[1].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[1].PllMInputDivider = 0x0000000c;
+SDRAM[1].PllMFeedbackDivider = 0x00000320;
+SDRAM[1].PllMPostDivider = 0x00000000;
+SDRAM[1].PllMStableTime = 0x0000012c;
+SDRAM[1].EmcClockDivider = 0x00000002;
+SDRAM[1].EmcAutoCalInterval = 0x001fffff;
+SDRAM[1].EmcAutoCalConfig = 0xa0f10000;
+SDRAM[1].EmcAutoCalWait = 0x00000064;
+SDRAM[1].EmcPinProgramWait = 0x00000001;
+SDRAM[1].EmcRc = 0x00000012;
+SDRAM[1].EmcRfc = 0x00000066;
+SDRAM[1].EmcRas = 0x0000000c;
+SDRAM[1].EmcRp = 0x00000004;
+SDRAM[1].EmcR2w = 0x00000003;
+SDRAM[1].EmcW2r = 0x00000008;
+SDRAM[1].EmcR2p = 0x00000002;
+SDRAM[1].EmcW2p = 0x0000000a;
+SDRAM[1].EmcRrd = 0x00000002;
+SDRAM[1].EmcRdRcd = 0x00000004;
+SDRAM[1].EmcWrRcd = 0x00000004;
+SDRAM[1].EmcRext = 0x00000001;
+SDRAM[1].EmcWdv = 0x00000004;
+SDRAM[1].EmcQUseExtra = 0x00000000;
+SDRAM[1].EmcQUse = 0x00000006;
+SDRAM[1].EmcQRst = 0x00000004;
+SDRAM[1].EmcQSafe = 0x0000000a;
+SDRAM[1].EmcRdv = 0x0000000d;
+SDRAM[1].EmcRefresh = 0x00000bf0;
+SDRAM[1].EmcBurstRefreshNum = 0x00000000;
+SDRAM[1].EmcPdEx2Wr = 0x00000001;
+SDRAM[1].EmcPdEx2Rd = 0x00000008;
+SDRAM[1].EmcPChg2Pden = 0x00000001;
+SDRAM[1].EmcAct2Pden = 0x00000000;
+SDRAM[1].EmcAr2Pden = 0x00000008;
+SDRAM[1].EmcRw2Pden = 0x0000000f;
+SDRAM[1].EmcTxsr = 0x0000006c;
+SDRAM[1].EmcTcke = 0x00000004;
+SDRAM[1].EmcTfaw = 0x0000000c;
+SDRAM[1].EmcTrpab = 0x00000000;
+SDRAM[1].EmcTClkStable = 0x00000004;
+SDRAM[1].EmcTClkStop = 0x00000005;
+SDRAM[1].EmcTRefBw = 0x00000c30;
+SDRAM[1].EmcFbioCfg5 = 0x00007088;
+SDRAM[1].EmcFbioCfg6 = 0x00000006;
+SDRAM[1].EmcFbioSpare = 0xe8000000;
+SDRAM[1].EmcMrsResetDllWait = 0x00000000;
+SDRAM[1].EmcMrsResetDll = 0x00000000;
+SDRAM[1].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[1].EmcMrs = 0x80000521;
+SDRAM[1].EmcEmrsEmr2 = 0x80200000;
+SDRAM[1].EmcEmrsEmr3 = 0x80300000;
+SDRAM[1].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[1].EmcEmrs = 0x80100002;
+SDRAM[1].EmcMrw1 = 0x00000000;
+SDRAM[1].EmcMrw2 = 0x00000000;
+SDRAM[1].EmcMrw3 = 0x00000000;
+SDRAM[1].EmcMrwResetCommand = 0x00000000;
+SDRAM[1].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[1].EmcAdrCfg = 0x00000080;
+SDRAM[1].McEmemCfg = 0x00000800;
+SDRAM[1].EmcCfg2 = 0x000c0099;
+SDRAM[1].EmcCfgDigDll = 0x001d0084;
+SDRAM[1].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[1].EmcCfg = 0x23c00000;
+SDRAM[1].EmcDbg = 0x01000400;
+SDRAM[1].WarmBootWait = 0x00000002;
+SDRAM[1].EmcCttTermCtrl = 0x00000802;
+SDRAM[1].EmcOdtWrite = 0x00000000;
+SDRAM[1].EmcOdtRead = 0x00000000;
+SDRAM[1].EmcZcalWaitCnt = 0x00000040;
+SDRAM[1].EmcZcalMrwCmd = 0x80000000;
+SDRAM[1].EmcDdr2Wait = 0x00000000;
+SDRAM[1].PmcDdrPwr = 0x00000003;
+SDRAM[1].EmcClockSource = 0x00000000;
+SDRAM[1].EmcClockUsePllMUD = 0x00000000;
+SDRAM[1].EmcPinExtraWait = 0x00000000;
+SDRAM[1].EmcTimingControlWait = 0x00000000;
+SDRAM[1].EmcWext = 0x00000000;
+SDRAM[1].EmcCtt = 0x00000000;
+SDRAM[1].EmcCttDuration = 0x00000000;
+SDRAM[1].EmcPreRefreshReqCnt = 0x000002fc;
+SDRAM[1].EmcTxsrDll = 0x00000200;
+SDRAM[1].EmcCfgRsv = 0xff00ff89;
+SDRAM[1].EmcMrwExtra = 0x00000000;
+SDRAM[1].EmcWarmBootMrw1 = 0x00000000;
+SDRAM[1].EmcWarmBootMrw2 = 0x00000000;
+SDRAM[1].EmcWarmBootMrw3 = 0x00000000;
+SDRAM[1].EmcWarmBootMrwExtra = 0x00000000;
+SDRAM[1].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[1].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[1].EmcMrsWaitCnt = 0x0158000c;
+SDRAM[1].EmcCmdQ = 0x10004408;
+SDRAM[1].EmcMc2EmcQ = 0x06000404;
+SDRAM[1].EmcDynSelfRefControl = 0x800018c8;
+SDRAM[1].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[1].EmcDevSelect = 0x00000002;
+SDRAM[1].EmcSelDpdCtrl = 0x0004032c;
+SDRAM[1].EmcDllXformDqs0 = 0x00038000;
+SDRAM[1].EmcDllXformDqs1 = 0x00038000;
+SDRAM[1].EmcDllXformDqs2 = 0x00038000;
+SDRAM[1].EmcDllXformDqs3 = 0x00038000;
+SDRAM[1].EmcDllXformDqs4 = 0x00038000;
+SDRAM[1].EmcDllXformDqs5 = 0x00038000;
+SDRAM[1].EmcDllXformDqs6 = 0x00038000;
+SDRAM[1].EmcDllXformDqs7 = 0x00038000;
+SDRAM[1].EmcDllXformQUse0 = 0x00000000;
+SDRAM[1].EmcDllXformQUse1 = 0x00000000;
+SDRAM[1].EmcDllXformQUse2 = 0x00000000;
+SDRAM[1].EmcDllXformQUse3 = 0x00000000;
+SDRAM[1].EmcDllXformQUse4 = 0x00000000;
+SDRAM[1].EmcDllXformQUse5 = 0x00000000;
+SDRAM[1].EmcDllXformQUse6 = 0x00000000;
+SDRAM[1].EmcDllXformQUse7 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs0 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs1 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs2 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs3 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs4 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs5 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs6 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs7 = 0x00000000;
+SDRAM[1].EmcDllXformDq0 = 0x00030000;
+SDRAM[1].EmcDllXformDq1 = 0x00030000;
+SDRAM[1].EmcDllXformDq2 = 0x00030000;
+SDRAM[1].EmcDllXformDq3 = 0x00030000;
+SDRAM[1].EmcZcalInterval = 0x00020000;
+SDRAM[1].EmcZcalInitDev0 = 0x80000011;
+SDRAM[1].EmcZcalInitDev1 = 0x00000000;
+SDRAM[1].EmcZcalInitWait = 0x00000002;
+SDRAM[1].EmcZcalColdBootEnable = 0x00000001;
+SDRAM[1].EmcZcalWarmBootEnable = 0x00000001;
+SDRAM[1].EmcMrwLpddr2ZcalWarmBoot = 0x000a00ab;
+SDRAM[1].EmcZqCalDdr3WarmBoot = 0x00000011;
+SDRAM[1].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[1].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[1].EmcMrsExtra = 0x80000521;
+SDRAM[1].EmcWarmBootMrs = 0x80100002;
+SDRAM[1].EmcWarmBootEmrs = 0x80000521;
+SDRAM[1].EmcWarmBootEmr2 = 0x80200000;
+SDRAM[1].EmcWarmBootEmr3 = 0x80300000;
+SDRAM[1].EmcWarmBootMrsExtra = 0x80100002;
+SDRAM[1].EmcClkenOverride = 0x00000000;
+SDRAM[1].EmcExtraRefreshNum = 0x00000002;
+SDRAM[1].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[1].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[1].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[1].PmcVddpSel = 0x00000002;
+SDRAM[1].PmcDdrCfg = 0x00000002;
+SDRAM[1].PmcIoDpdReq = 0x80800000;
+SDRAM[1].PmcENoVttGen = 0x00000000;
+SDRAM[1].PmcNoIoPower = 0x00000000;
+SDRAM[1].EmcXm2CmdPadCtrl = 0x000002a0;
+SDRAM[1].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[1].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[1].EmcXm2DqsPadCtrl2 = 0x0800013d;
+SDRAM[1].EmcXm2DqsPadCtrl3 = 0x08000021;
+SDRAM[1].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[1].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[1].EmcXm2ClkPadCtrl = 0x77fff884;
+SDRAM[1].EmcXm2CompPadCtrl = 0x01f1f508;
+SDRAM[1].EmcXm2VttGenPadCtrl = 0x05057404;
+SDRAM[1].EmcXm2VttGenPadCtrl2 = 0x54000007;
+SDRAM[1].EmcXm2QUsePadCtrl = 0x080001e8;
+SDRAM[1].McEmemAdrCfg = 0x00000000;
+SDRAM[1].McEmemAdrCfgDev0 = 0x00090303;
+SDRAM[1].McEmemAdrCfgDev1 = 0x00090303;
+SDRAM[1].McEmemArbCfg = 0x00000006;
+SDRAM[1].McEmemArbOutstandingReq = 0x80000048;
+SDRAM[1].McEmemArbTimingRcd = 0x00000001;
+SDRAM[1].McEmemArbTimingRp = 0x00000002;
+SDRAM[1].McEmemArbTimingRc = 0x00000009;
+SDRAM[1].McEmemArbTimingRas = 0x00000005;
+SDRAM[1].McEmemArbTimingFaw = 0x00000005;
+SDRAM[1].McEmemArbTimingRrd = 0x00000001;
+SDRAM[1].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[1].McEmemArbTimingWap2Pre = 0x00000008;
+SDRAM[1].McEmemArbTimingR2R = 0x00000002;
+SDRAM[1].McEmemArbTimingW2W = 0x00000002;
+SDRAM[1].McEmemArbTimingR2W = 0x00000003;
+SDRAM[1].McEmemArbTimingW2R = 0x00000006;
+SDRAM[1].McEmemArbDaTurns = 0x06030202;
+SDRAM[1].McEmemArbDaCovers = 0x000d0709;
+SDRAM[1].McEmemArbMisc0 = 0x7086120a;
+SDRAM[1].McEmemArbMisc1 = 0x78000000;
+SDRAM[1].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[1].McEmemArbOverride = 0x00000080;
+SDRAM[1].McEmemArbRsv = 0xff00ff00;
+SDRAM[1].McClkenOverride = 0x00000000;
+
+SDRAM[2].MemoryType = NvBootMemoryType_Ddr3;
+SDRAM[2].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[2].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[2].PllMInputDivider = 0x0000000c;
+SDRAM[2].PllMFeedbackDivider = 0x00000320;
+SDRAM[2].PllMPostDivider = 0x00000000;
+SDRAM[2].PllMStableTime = 0x0000012c;
+SDRAM[2].EmcClockDivider = 0x00000002;
+SDRAM[2].EmcAutoCalInterval = 0x001fffff;
+SDRAM[2].EmcAutoCalConfig = 0xa0f10000;
+SDRAM[2].EmcAutoCalWait = 0x00000064;
+SDRAM[2].EmcPinProgramWait = 0x00000001;
+SDRAM[2].EmcRc = 0x00000012;
+SDRAM[2].EmcRfc = 0x00000066;
+SDRAM[2].EmcRas = 0x0000000c;
+SDRAM[2].EmcRp = 0x00000004;
+SDRAM[2].EmcR2w = 0x00000003;
+SDRAM[2].EmcW2r = 0x00000008;
+SDRAM[2].EmcR2p = 0x00000002;
+SDRAM[2].EmcW2p = 0x0000000a;
+SDRAM[2].EmcRrd = 0x00000002;
+SDRAM[2].EmcRdRcd = 0x00000004;
+SDRAM[2].EmcWrRcd = 0x00000004;
+SDRAM[2].EmcRext = 0x00000001;
+SDRAM[2].EmcWdv = 0x00000004;
+SDRAM[2].EmcQUseExtra = 0x00000000;
+SDRAM[2].EmcQUse = 0x00000006;
+SDRAM[2].EmcQRst = 0x00000004;
+SDRAM[2].EmcQSafe = 0x0000000a;
+SDRAM[2].EmcRdv = 0x0000000d;
+SDRAM[2].EmcRefresh = 0x00000bf0;
+SDRAM[2].EmcBurstRefreshNum = 0x00000000;
+SDRAM[2].EmcPdEx2Wr = 0x00000001;
+SDRAM[2].EmcPdEx2Rd = 0x00000008;
+SDRAM[2].EmcPChg2Pden = 0x00000001;
+SDRAM[2].EmcAct2Pden = 0x00000000;
+SDRAM[2].EmcAr2Pden = 0x00000008;
+SDRAM[2].EmcRw2Pden = 0x0000000f;
+SDRAM[2].EmcTxsr = 0x0000006c;
+SDRAM[2].EmcTcke = 0x00000004;
+SDRAM[2].EmcTfaw = 0x0000000c;
+SDRAM[2].EmcTrpab = 0x00000000;
+SDRAM[2].EmcTClkStable = 0x00000004;
+SDRAM[2].EmcTClkStop = 0x00000005;
+SDRAM[2].EmcTRefBw = 0x00000c30;
+SDRAM[2].EmcFbioCfg5 = 0x00007088;
+SDRAM[2].EmcFbioCfg6 = 0x00000006;
+SDRAM[2].EmcFbioSpare = 0xe8000000;
+SDRAM[2].EmcMrsResetDllWait = 0x00000000;
+SDRAM[2].EmcMrsResetDll = 0x00000000;
+SDRAM[2].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[2].EmcMrs = 0x80000521;
+SDRAM[2].EmcEmrsEmr2 = 0x80200000;
+SDRAM[2].EmcEmrsEmr3 = 0x80300000;
+SDRAM[2].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[2].EmcEmrs = 0x80100002;
+SDRAM[2].EmcMrw1 = 0x00000000;
+SDRAM[2].EmcMrw2 = 0x00000000;
+SDRAM[2].EmcMrw3 = 0x00000000;
+SDRAM[2].EmcMrwResetCommand = 0x00000000;
+SDRAM[2].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[2].EmcAdrCfg = 0x00000080;
+SDRAM[2].McEmemCfg = 0x00000800;
+SDRAM[2].EmcCfg2 = 0x000c0099;
+SDRAM[2].EmcCfgDigDll = 0x001d0084;
+SDRAM[2].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[2].EmcCfg = 0x23c00000;
+SDRAM[2].EmcDbg = 0x01000400;
+SDRAM[2].WarmBootWait = 0x00000002;
+SDRAM[2].EmcCttTermCtrl = 0x00000802;
+SDRAM[2].EmcOdtWrite = 0x00000000;
+SDRAM[2].EmcOdtRead = 0x00000000;
+SDRAM[2].EmcZcalWaitCnt = 0x00000040;
+SDRAM[2].EmcZcalMrwCmd = 0x80000000;
+SDRAM[2].EmcDdr2Wait = 0x00000000;
+SDRAM[2].PmcDdrPwr = 0x00000003;
+SDRAM[2].EmcClockSource = 0x00000000;
+SDRAM[2].EmcClockUsePllMUD = 0x00000000;
+SDRAM[2].EmcPinExtraWait = 0x00000000;
+SDRAM[2].EmcTimingControlWait = 0x00000000;
+SDRAM[2].EmcWext = 0x00000000;
+SDRAM[2].EmcCtt = 0x00000000;
+SDRAM[2].EmcCttDuration = 0x00000000;
+SDRAM[2].EmcPreRefreshReqCnt = 0x000002fc;
+SDRAM[2].EmcTxsrDll = 0x00000200;
+SDRAM[2].EmcCfgRsv = 0xff00ff89;
+SDRAM[2].EmcMrwExtra = 0x00000000;
+SDRAM[2].EmcWarmBootMrw1 = 0x00000000;
+SDRAM[2].EmcWarmBootMrw2 = 0x00000000;
+SDRAM[2].EmcWarmBootMrw3 = 0x00000000;
+SDRAM[2].EmcWarmBootMrwExtra = 0x00000000;
+SDRAM[2].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[2].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[2].EmcMrsWaitCnt = 0x0158000c;
+SDRAM[2].EmcCmdQ = 0x10004408;
+SDRAM[2].EmcMc2EmcQ = 0x06000404;
+SDRAM[2].EmcDynSelfRefControl = 0x800018c8;
+SDRAM[2].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[2].EmcDevSelect = 0x00000002;
+SDRAM[2].EmcSelDpdCtrl = 0x0004032c;
+SDRAM[2].EmcDllXformDqs0 = 0x00038000;
+SDRAM[2].EmcDllXformDqs1 = 0x00038000;
+SDRAM[2].EmcDllXformDqs2 = 0x00038000;
+SDRAM[2].EmcDllXformDqs3 = 0x00038000;
+SDRAM[2].EmcDllXformDqs4 = 0x00038000;
+SDRAM[2].EmcDllXformDqs5 = 0x00038000;
+SDRAM[2].EmcDllXformDqs6 = 0x00038000;
+SDRAM[2].EmcDllXformDqs7 = 0x00038000;
+SDRAM[2].EmcDllXformQUse0 = 0x00000000;
+SDRAM[2].EmcDllXformQUse1 = 0x00000000;
+SDRAM[2].EmcDllXformQUse2 = 0x00000000;
+SDRAM[2].EmcDllXformQUse3 = 0x00000000;
+SDRAM[2].EmcDllXformQUse4 = 0x00000000;
+SDRAM[2].EmcDllXformQUse5 = 0x00000000;
+SDRAM[2].EmcDllXformQUse6 = 0x00000000;
+SDRAM[2].EmcDllXformQUse7 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs0 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs1 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs2 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs3 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs4 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs5 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs6 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs7 = 0x00000000;
+SDRAM[2].EmcDllXformDq0 = 0x00030000;
+SDRAM[2].EmcDllXformDq1 = 0x00030000;
+SDRAM[2].EmcDllXformDq2 = 0x00030000;
+SDRAM[2].EmcDllXformDq3 = 0x00030000;
+SDRAM[2].EmcZcalInterval = 0x00020000;
+SDRAM[2].EmcZcalInitDev0 = 0x80000011;
+SDRAM[2].EmcZcalInitDev1 = 0x00000000;
+SDRAM[2].EmcZcalInitWait = 0x00000002;
+SDRAM[2].EmcZcalColdBootEnable = 0x00000001;
+SDRAM[2].EmcZcalWarmBootEnable = 0x00000001;
+SDRAM[2].EmcMrwLpddr2ZcalWarmBoot = 0x000a00ab;
+SDRAM[2].EmcZqCalDdr3WarmBoot = 0x00000011;
+SDRAM[2].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[2].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[2].EmcMrsExtra = 0x80000521;
+SDRAM[2].EmcWarmBootMrs = 0x80100002;
+SDRAM[2].EmcWarmBootEmrs = 0x80000521;
+SDRAM[2].EmcWarmBootEmr2 = 0x80200000;
+SDRAM[2].EmcWarmBootEmr3 = 0x80300000;
+SDRAM[2].EmcWarmBootMrsExtra = 0x80100002;
+SDRAM[2].EmcClkenOverride = 0x00000000;
+SDRAM[2].EmcExtraRefreshNum = 0x00000002;
+SDRAM[2].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[2].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[2].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[2].PmcVddpSel = 0x00000002;
+SDRAM[2].PmcDdrCfg = 0x00000002;
+SDRAM[2].PmcIoDpdReq = 0x80800000;
+SDRAM[2].PmcENoVttGen = 0x00000000;
+SDRAM[2].PmcNoIoPower = 0x00000000;
+SDRAM[2].EmcXm2CmdPadCtrl = 0x000002a0;
+SDRAM[2].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[2].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[2].EmcXm2DqsPadCtrl2 = 0x0800013d;
+SDRAM[2].EmcXm2DqsPadCtrl3 = 0x08000021;
+SDRAM[2].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[2].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[2].EmcXm2ClkPadCtrl = 0x77fff884;
+SDRAM[2].EmcXm2CompPadCtrl = 0x01f1f508;
+SDRAM[2].EmcXm2VttGenPadCtrl = 0x05057404;
+SDRAM[2].EmcXm2VttGenPadCtrl2 = 0x54000007;
+SDRAM[2].EmcXm2QUsePadCtrl = 0x080001e8;
+SDRAM[2].McEmemAdrCfg = 0x00000000;
+SDRAM[2].McEmemAdrCfgDev0 = 0x00090303;
+SDRAM[2].McEmemAdrCfgDev1 = 0x00090303;
+SDRAM[2].McEmemArbCfg = 0x00000006;
+SDRAM[2].McEmemArbOutstandingReq = 0x80000048;
+SDRAM[2].McEmemArbTimingRcd = 0x00000001;
+SDRAM[2].McEmemArbTimingRp = 0x00000002;
+SDRAM[2].McEmemArbTimingRc = 0x00000009;
+SDRAM[2].McEmemArbTimingRas = 0x00000005;
+SDRAM[2].McEmemArbTimingFaw = 0x00000005;
+SDRAM[2].McEmemArbTimingRrd = 0x00000001;
+SDRAM[2].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[2].McEmemArbTimingWap2Pre = 0x00000008;
+SDRAM[2].McEmemArbTimingR2R = 0x00000002;
+SDRAM[2].McEmemArbTimingW2W = 0x00000002;
+SDRAM[2].McEmemArbTimingR2W = 0x00000003;
+SDRAM[2].McEmemArbTimingW2R = 0x00000006;
+SDRAM[2].McEmemArbDaTurns = 0x06030202;
+SDRAM[2].McEmemArbDaCovers = 0x000d0709;
+SDRAM[2].McEmemArbMisc0 = 0x7086120a;
+SDRAM[2].McEmemArbMisc1 = 0x78000000;
+SDRAM[2].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[2].McEmemArbOverride = 0x00000080;
+SDRAM[2].McEmemArbRsv = 0xff00ff00;
+SDRAM[2].McClkenOverride = 0x00000000;
+
+SDRAM[3].MemoryType = NvBootMemoryType_Ddr3;
+SDRAM[3].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[3].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[3].PllMInputDivider = 0x0000000c;
+SDRAM[3].PllMFeedbackDivider = 0x00000320;
+SDRAM[3].PllMPostDivider = 0x00000000;
+SDRAM[3].PllMStableTime = 0x0000012c;
+SDRAM[3].EmcClockDivider = 0x00000002;
+SDRAM[3].EmcAutoCalInterval = 0x001fffff;
+SDRAM[3].EmcAutoCalConfig = 0xa0f10000;
+SDRAM[3].EmcAutoCalWait = 0x00000064;
+SDRAM[3].EmcPinProgramWait = 0x00000001;
+SDRAM[3].EmcRc = 0x00000012;
+SDRAM[3].EmcRfc = 0x00000066;
+SDRAM[3].EmcRas = 0x0000000c;
+SDRAM[3].EmcRp = 0x00000004;
+SDRAM[3].EmcR2w = 0x00000003;
+SDRAM[3].EmcW2r = 0x00000008;
+SDRAM[3].EmcR2p = 0x00000002;
+SDRAM[3].EmcW2p = 0x0000000a;
+SDRAM[3].EmcRrd = 0x00000002;
+SDRAM[3].EmcRdRcd = 0x00000004;
+SDRAM[3].EmcWrRcd = 0x00000004;
+SDRAM[3].EmcRext = 0x00000001;
+SDRAM[3].EmcWdv = 0x00000004;
+SDRAM[3].EmcQUseExtra = 0x00000000;
+SDRAM[3].EmcQUse = 0x00000006;
+SDRAM[3].EmcQRst = 0x00000004;
+SDRAM[3].EmcQSafe = 0x0000000a;
+SDRAM[3].EmcRdv = 0x0000000d;
+SDRAM[3].EmcRefresh = 0x00000bf0;
+SDRAM[3].EmcBurstRefreshNum = 0x00000000;
+SDRAM[3].EmcPdEx2Wr = 0x00000001;
+SDRAM[3].EmcPdEx2Rd = 0x00000008;
+SDRAM[3].EmcPChg2Pden = 0x00000001;
+SDRAM[3].EmcAct2Pden = 0x00000000;
+SDRAM[3].EmcAr2Pden = 0x00000008;
+SDRAM[3].EmcRw2Pden = 0x0000000f;
+SDRAM[3].EmcTxsr = 0x0000006c;
+SDRAM[3].EmcTcke = 0x00000004;
+SDRAM[3].EmcTfaw = 0x0000000c;
+SDRAM[3].EmcTrpab = 0x00000000;
+SDRAM[3].EmcTClkStable = 0x00000004;
+SDRAM[3].EmcTClkStop = 0x00000005;
+SDRAM[3].EmcTRefBw = 0x00000c30;
+SDRAM[3].EmcFbioCfg5 = 0x00007088;
+SDRAM[3].EmcFbioCfg6 = 0x00000006;
+SDRAM[3].EmcFbioSpare = 0xe8000000;
+SDRAM[3].EmcMrsResetDllWait = 0x00000000;
+SDRAM[3].EmcMrsResetDll = 0x00000000;
+SDRAM[3].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[3].EmcMrs = 0x80000521;
+SDRAM[3].EmcEmrsEmr2 = 0x80200000;
+SDRAM[3].EmcEmrsEmr3 = 0x80300000;
+SDRAM[3].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[3].EmcEmrs = 0x80100002;
+SDRAM[3].EmcMrw1 = 0x00000000;
+SDRAM[3].EmcMrw2 = 0x00000000;
+SDRAM[3].EmcMrw3 = 0x00000000;
+SDRAM[3].EmcMrwResetCommand = 0x00000000;
+SDRAM[3].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[3].EmcAdrCfg = 0x00000080;
+SDRAM[3].McEmemCfg = 0x00000800;
+SDRAM[3].EmcCfg2 = 0x000c0099;
+SDRAM[3].EmcCfgDigDll = 0x001d0084;
+SDRAM[3].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[3].EmcCfg = 0x23c00000;
+SDRAM[3].EmcDbg = 0x01000400;
+SDRAM[3].WarmBootWait = 0x00000002;
+SDRAM[3].EmcCttTermCtrl = 0x00000802;
+SDRAM[3].EmcOdtWrite = 0x00000000;
+SDRAM[3].EmcOdtRead = 0x00000000;
+SDRAM[3].EmcZcalWaitCnt = 0x00000040;
+SDRAM[3].EmcZcalMrwCmd = 0x80000000;
+SDRAM[3].EmcDdr2Wait = 0x00000000;
+SDRAM[3].PmcDdrPwr = 0x00000003;
+SDRAM[3].EmcClockSource = 0x00000000;
+SDRAM[3].EmcClockUsePllMUD = 0x00000000;
+SDRAM[3].EmcPinExtraWait = 0x00000000;
+SDRAM[3].EmcTimingControlWait = 0x00000000;
+SDRAM[3].EmcWext = 0x00000000;
+SDRAM[3].EmcCtt = 0x00000000;
+SDRAM[3].EmcCttDuration = 0x00000000;
+SDRAM[3].EmcPreRefreshReqCnt = 0x000002fc;
+SDRAM[3].EmcTxsrDll = 0x00000200;
+SDRAM[3].EmcCfgRsv = 0xff00ff89;
+SDRAM[3].EmcMrwExtra = 0x00000000;
+SDRAM[3].EmcWarmBootMrw1 = 0x00000000;
+SDRAM[3].EmcWarmBootMrw2 = 0x00000000;
+SDRAM[3].EmcWarmBootMrw3 = 0x00000000;
+SDRAM[3].EmcWarmBootMrwExtra = 0x00000000;
+SDRAM[3].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[3].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[3].EmcMrsWaitCnt = 0x0158000c;
+SDRAM[3].EmcCmdQ = 0x10004408;
+SDRAM[3].EmcMc2EmcQ = 0x06000404;
+SDRAM[3].EmcDynSelfRefControl = 0x800018c8;
+SDRAM[3].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[3].EmcDevSelect = 0x00000002;
+SDRAM[3].EmcSelDpdCtrl = 0x0004032c;
+SDRAM[3].EmcDllXformDqs0 = 0x00038000;
+SDRAM[3].EmcDllXformDqs1 = 0x00038000;
+SDRAM[3].EmcDllXformDqs2 = 0x00038000;
+SDRAM[3].EmcDllXformDqs3 = 0x00038000;
+SDRAM[3].EmcDllXformDqs4 = 0x00038000;
+SDRAM[3].EmcDllXformDqs5 = 0x00038000;
+SDRAM[3].EmcDllXformDqs6 = 0x00038000;
+SDRAM[3].EmcDllXformDqs7 = 0x00038000;
+SDRAM[3].EmcDllXformQUse0 = 0x00000000;
+SDRAM[3].EmcDllXformQUse1 = 0x00000000;
+SDRAM[3].EmcDllXformQUse2 = 0x00000000;
+SDRAM[3].EmcDllXformQUse3 = 0x00000000;
+SDRAM[3].EmcDllXformQUse4 = 0x00000000;
+SDRAM[3].EmcDllXformQUse5 = 0x00000000;
+SDRAM[3].EmcDllXformQUse6 = 0x00000000;
+SDRAM[3].EmcDllXformQUse7 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs0 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs1 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs2 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs3 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs4 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs5 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs6 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs7 = 0x00000000;
+SDRAM[3].EmcDllXformDq0 = 0x00030000;
+SDRAM[3].EmcDllXformDq1 = 0x00030000;
+SDRAM[3].EmcDllXformDq2 = 0x00030000;
+SDRAM[3].EmcDllXformDq3 = 0x00030000;
+SDRAM[3].EmcZcalInterval = 0x00020000;
+SDRAM[3].EmcZcalInitDev0 = 0x80000011;
+SDRAM[3].EmcZcalInitDev1 = 0x00000000;
+SDRAM[3].EmcZcalInitWait = 0x00000002;
+SDRAM[3].EmcZcalColdBootEnable = 0x00000001;
+SDRAM[3].EmcZcalWarmBootEnable = 0x00000001;
+SDRAM[3].EmcMrwLpddr2ZcalWarmBoot = 0x000a00ab;
+SDRAM[3].EmcZqCalDdr3WarmBoot = 0x00000011;
+SDRAM[3].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[3].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[3].EmcMrsExtra = 0x80000521;
+SDRAM[3].EmcWarmBootMrs = 0x80100002;
+SDRAM[3].EmcWarmBootEmrs = 0x80000521;
+SDRAM[3].EmcWarmBootEmr2 = 0x80200000;
+SDRAM[3].EmcWarmBootEmr3 = 0x80300000;
+SDRAM[3].EmcWarmBootMrsExtra = 0x80100002;
+SDRAM[3].EmcClkenOverride = 0x00000000;
+SDRAM[3].EmcExtraRefreshNum = 0x00000002;
+SDRAM[3].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[3].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[3].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[3].PmcVddpSel = 0x00000002;
+SDRAM[3].PmcDdrCfg = 0x00000002;
+SDRAM[3].PmcIoDpdReq = 0x80800000;
+SDRAM[3].PmcENoVttGen = 0x00000000;
+SDRAM[3].PmcNoIoPower = 0x00000000;
+SDRAM[3].EmcXm2CmdPadCtrl = 0x000002a0;
+SDRAM[3].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[3].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[3].EmcXm2DqsPadCtrl2 = 0x0800013d;
+SDRAM[3].EmcXm2DqsPadCtrl3 = 0x08000021;
+SDRAM[3].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[3].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[3].EmcXm2ClkPadCtrl = 0x77fff884;
+SDRAM[3].EmcXm2CompPadCtrl = 0x01f1f508;
+SDRAM[3].EmcXm2VttGenPadCtrl = 0x05057404;
+SDRAM[3].EmcXm2VttGenPadCtrl2 = 0x54000007;
+SDRAM[3].EmcXm2QUsePadCtrl = 0x080001e8;
+SDRAM[3].McEmemAdrCfg = 0x00000000;
+SDRAM[3].McEmemAdrCfgDev0 = 0x00090303;
+SDRAM[3].McEmemAdrCfgDev1 = 0x00090303;
+SDRAM[3].McEmemArbCfg = 0x00000006;
+SDRAM[3].McEmemArbOutstandingReq = 0x80000048;
+SDRAM[3].McEmemArbTimingRcd = 0x00000001;
+SDRAM[3].McEmemArbTimingRp = 0x00000002;
+SDRAM[3].McEmemArbTimingRc = 0x00000009;
+SDRAM[3].McEmemArbTimingRas = 0x00000005;
+SDRAM[3].McEmemArbTimingFaw = 0x00000005;
+SDRAM[3].McEmemArbTimingRrd = 0x00000001;
+SDRAM[3].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[3].McEmemArbTimingWap2Pre = 0x00000008;
+SDRAM[3].McEmemArbTimingR2R = 0x00000002;
+SDRAM[3].McEmemArbTimingW2W = 0x00000002;
+SDRAM[3].McEmemArbTimingR2W = 0x00000003;
+SDRAM[3].McEmemArbTimingW2R = 0x00000006;
+SDRAM[3].McEmemArbDaTurns = 0x06030202;
+SDRAM[3].McEmemArbDaCovers = 0x000d0709;
+SDRAM[3].McEmemArbMisc0 = 0x7086120a;
+SDRAM[3].McEmemArbMisc1 = 0x78000000;
+SDRAM[3].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[3].McEmemArbOverride = 0x00000080;
+SDRAM[3].McEmemArbRsv = 0xff00ff00;
+SDRAM[3].McClkenOverride = 0x00000000;
diff --git a/arch/arm/boards/nvidia-beaver/board.c b/arch/arm/boards/nvidia-beaver/board.c
new file mode 100644
index 0000000000..e87594d5b7
--- /dev/null
+++ b/arch/arm/boards/nvidia-beaver/board.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <i2c/i2c.h>
+
+static int nvidia_beaver_devices_init(void)
+{
+ struct i2c_client client;
+ u8 data;
+
+ if (!of_machine_is_compatible("nvidia,beaver"))
+ return 0;
+
+ client.adapter = i2c_get_adapter(4);
+ client.addr = 0x2d;
+
+ /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 */
+ data = 0x65;
+ i2c_write_reg(&client, 0x32, &data, 1);
+
+ return 0;
+}
+device_initcall(nvidia_beaver_devices_init);
diff --git a/arch/arm/boards/toradex-colibri-t20/Makefile b/arch/arm/boards/toradex-colibri-t20/Makefile
index d2d217319b..1f767328fa 100644
--- a/arch/arm/boards/toradex-colibri-t20/Makefile
+++ b/arch/arm/boards/toradex-colibri-t20/Makefile
@@ -1,4 +1,8 @@
CFLAGS_pbl-entry.o := \
-mcpu=arm7tdmi -march=armv4t \
-fno-tree-switch-conversion -fno-jump-tables
+soc := tegra20
lwl-y += entry.o
+extra-y += colibri-t20_256_hsmmc.bct colibri-t20_256_v11_nand.bct \
+ colibri-t20_256_v12_nand.bct colibri-t20_512_hsmmc.bct \
+ colibri-t20_512_v11_nand.bct colibri-t20_512_v12_nand.bct \ No newline at end of file
diff --git a/arch/arm/boards/toradex-colibri-t20/colibri-t20_256_hsmmc.bct.cfg b/arch/arm/boards/toradex-colibri-t20/colibri-t20_256_hsmmc.bct.cfg
new file mode 100644
index 0000000000..aeb7cdf603
--- /dev/null
+++ b/arch/arm/boards/toradex-colibri-t20/colibri-t20_256_hsmmc.bct.cfg
@@ -0,0 +1,451 @@
+# Copyright (c) 2013, Toradex AG. All rights reserved.
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+# claim that you wrote the original software. If you use this software
+# in a product, an acknowledgment in the product documentation would be
+# appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+# misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+Version = 0x00020001;
+PartitionSize = 16777216;
+BlockSize = 16384;
+PageSize = 512;
+OdmData = 0x100C0000;
+
+DevType[0] = Sdmmc;
+DeviceParam[0].SdmmcParams.ClockDivider = 12; # 432/24 = 18MHz.
+DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit;
+DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0;
+
+DevType[1] = Sdmmc;
+DeviceParam[1].SdmmcParams.ClockDivider = 12; # 432/24 = 18MHz.
+DeviceParam[1].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit;
+DeviceParam[1].SdmmcParams.MaxPowerClassSupported = 0;
+
+DevType[2] = Sdmmc;
+DeviceParam[2].SdmmcParams.ClockDivider = 12; # 432/24 = 18MHz.
+DeviceParam[2].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit;
+DeviceParam[2].SdmmcParams.MaxPowerClassSupported = 0;
+
+DevType[3] = Sdmmc;
+DeviceParam[3].SdmmcParams.ClockDivider = 12; # 432/24 = 18MHz.
+DeviceParam[3].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit;
+DeviceParam[3].SdmmcParams.MaxPowerClassSupported = 0;
+
+SDRAM[0].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[0].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[0].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[0].PllMInputDivider = 0x0000000d;
+SDRAM[0].PllMFeedbackDivider = 0x0000029a;
+SDRAM[0].PllMPostDivider = 0x00000000;
+SDRAM[0].PllMStableTime = 0x0000012c;
+SDRAM[0].EmcClockDivider = 0x00000001;
+SDRAM[0].EmcAutoCalInterval = 0x00000000;
+SDRAM[0].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[0].EmcAutoCalWait = 0x00000000;
+SDRAM[0].EmcPinProgramWait = 0x00000000;
+SDRAM[0].EmcRc = 0x00000014;
+SDRAM[0].EmcRfc = 0x0000002b;
+SDRAM[0].EmcRas = 0x0000000f;
+SDRAM[0].EmcRp = 0x00000005;
+SDRAM[0].EmcR2w = 0x00000005;
+SDRAM[0].EmcW2r = 0x00000005;
+SDRAM[0].EmcR2p = 0x00000003;
+SDRAM[0].EmcW2p = 0x0000000c;
+SDRAM[0].EmcRdRcd = 0x00000005;
+SDRAM[0].EmcWrRcd = 0x00000005;
+SDRAM[0].EmcRrd = 0x00000003;
+SDRAM[0].EmcRext = 0x00000001;
+SDRAM[0].EmcWdv = 0x00000004;
+SDRAM[0].EmcQUse = 0x00000005;
+SDRAM[0].EmcQRst = 0x00000004;
+SDRAM[0].EmcQSafe = 0x00000009;
+SDRAM[0].EmcRdv = 0x0000000d;
+SDRAM[0].EmcRefresh = 0x000009ff;
+SDRAM[0].EmcBurstRefreshNum = 0x00000000;
+SDRAM[0].EmcPdEx2Wr = 0x00000003;
+SDRAM[0].EmcPdEx2Rd = 0x00000003;
+SDRAM[0].EmcPChg2Pden = 0x00000005;
+SDRAM[0].EmcAct2Pden = 0x00000005;
+SDRAM[0].EmcAr2Pden = 0x00000001;
+SDRAM[0].EmcRw2Pden = 0x0000000f;
+SDRAM[0].EmcTxsr = 0x000000c8;
+SDRAM[0].EmcTcke = 0x00000003;
+SDRAM[0].EmcTfaw = 0x0000000c;
+SDRAM[0].EmcTrpab = 0x00000006;
+SDRAM[0].EmcTClkStable = 0x00000008;
+SDRAM[0].EmcTClkStop = 0x00000002;
+SDRAM[0].EmcTRefBw = 0x00000000;
+SDRAM[0].EmcQUseExtra = 0x00000000;
+SDRAM[0].EmcFbioCfg1 = 0x00000000;
+SDRAM[0].EmcFbioDqsibDly = 0x20202020;
+SDRAM[0].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[0].EmcFbioQuseDly = 0x50465046;
+SDRAM[0].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[0].EmcFbioCfg5 = 0x00000183;
+SDRAM[0].EmcFbioCfg6 = 0x00000002;
+SDRAM[0].EmcFbioSpare = 0x00000000;
+SDRAM[0].EmcMrs = 0x00000a6a;
+SDRAM[0].EmcEmrs = 0x00100006;
+SDRAM[0].EmcMrw1 = 0x00000000;
+SDRAM[0].EmcMrw2 = 0x00000000;
+SDRAM[0].EmcMrw3 = 0x00000000;
+SDRAM[0].EmcMrwResetCommand = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[0].EmcAdrCfg = 0x00060303;
+SDRAM[0].EmcAdrCfg1 = 0x00060303;
+SDRAM[0].McEmemCfg = 0x00040000;
+SDRAM[0].McLowLatencyConfig = 0x80000003;
+SDRAM[0].EmcCfg = 0x0301ff00;
+SDRAM[0].EmcCfg2 = 0x00000405;
+SDRAM[0].EmcDbg = 0x01000400;
+SDRAM[0].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[0].EmcCfgDigDll = 0xf0000313;
+SDRAM[0].EmcDllXformDqs = 0x00000010;
+SDRAM[0].EmcDllXformQUse = 0x00000008;
+SDRAM[0].WarmBootWait = 0x00000002;
+SDRAM[0].EmcCttTermCtrl = 0x00000802;
+SDRAM[0].EmcOdtWrite = 0x80000001;
+SDRAM[0].EmcOdtRead = 0x80000001;
+SDRAM[0].EmcZcalRefCnt = 0x00000000;
+SDRAM[0].EmcZcalWaitCnt = 0x00000000;
+SDRAM[0].EmcZcalMrwCmd = 0x00000000;
+SDRAM[0].EmcMrsResetDll = 0x00000000;
+SDRAM[0].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[0].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[0].EmcMrwZqInitWait = 0x00000000;
+SDRAM[0].EmcMrsResetDllWait = 0x00000000;
+SDRAM[0].EmcEmrsEmr2 = 0x00200000;
+SDRAM[0].EmcEmrsEmr3 = 0x00300000;
+SDRAM[0].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[0].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[0].EmcDdr2Wait = 0x00000002;
+SDRAM[0].EmcCfgClktrim0 = 0x00000000;
+SDRAM[0].EmcCfgClktrim1 = 0x00000000;
+SDRAM[0].EmcCfgClktrim2 = 0x00000000;
+SDRAM[0].PmcDdrPwr = 0x00000001;
+SDRAM[0].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[0].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[0].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[0].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[0].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[1].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[1].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[1].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[1].PllMInputDivider = 0x0000000d;
+SDRAM[1].PllMFeedbackDivider = 0x0000029a;
+SDRAM[1].PllMPostDivider = 0x00000000;
+SDRAM[1].PllMStableTime = 0x0000012c;
+SDRAM[1].EmcClockDivider = 0x00000001;
+SDRAM[1].EmcAutoCalInterval = 0x00000000;
+SDRAM[1].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[1].EmcAutoCalWait = 0x00000000;
+SDRAM[1].EmcPinProgramWait = 0x00000000;
+SDRAM[1].EmcRc = 0x00000014;
+SDRAM[1].EmcRfc = 0x0000002b;
+SDRAM[1].EmcRas = 0x0000000f;
+SDRAM[1].EmcRp = 0x00000005;
+SDRAM[1].EmcR2w = 0x00000005;
+SDRAM[1].EmcW2r = 0x00000005;
+SDRAM[1].EmcR2p = 0x00000003;
+SDRAM[1].EmcW2p = 0x0000000c;
+SDRAM[1].EmcRdRcd = 0x00000005;
+SDRAM[1].EmcWrRcd = 0x00000005;
+SDRAM[1].EmcRrd = 0x00000003;
+SDRAM[1].EmcRext = 0x00000001;
+SDRAM[1].EmcWdv = 0x00000004;
+SDRAM[1].EmcQUse = 0x00000005;
+SDRAM[1].EmcQRst = 0x00000004;
+SDRAM[1].EmcQSafe = 0x00000009;
+SDRAM[1].EmcRdv = 0x0000000d;
+SDRAM[1].EmcRefresh = 0x000009ff;
+SDRAM[1].EmcBurstRefreshNum = 0x00000000;
+SDRAM[1].EmcPdEx2Wr = 0x00000003;
+SDRAM[1].EmcPdEx2Rd = 0x00000003;
+SDRAM[1].EmcPChg2Pden = 0x00000005;
+SDRAM[1].EmcAct2Pden = 0x00000005;
+SDRAM[1].EmcAr2Pden = 0x00000001;
+SDRAM[1].EmcRw2Pden = 0x0000000f;
+SDRAM[1].EmcTxsr = 0x000000c8;
+SDRAM[1].EmcTcke = 0x00000003;
+SDRAM[1].EmcTfaw = 0x0000000c;
+SDRAM[1].EmcTrpab = 0x00000006;
+SDRAM[1].EmcTClkStable = 0x00000008;
+SDRAM[1].EmcTClkStop = 0x00000002;
+SDRAM[1].EmcTRefBw = 0x00000000;
+SDRAM[1].EmcQUseExtra = 0x00000000;
+SDRAM[1].EmcFbioCfg1 = 0x00000000;
+SDRAM[1].EmcFbioDqsibDly = 0x20202020;
+SDRAM[1].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[1].EmcFbioQuseDly = 0x50465046;
+SDRAM[1].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[1].EmcFbioCfg5 = 0x00000183;
+SDRAM[1].EmcFbioCfg6 = 0x00000002;
+SDRAM[1].EmcFbioSpare = 0x00000000;
+SDRAM[1].EmcMrs = 0x00000a6a;
+SDRAM[1].EmcEmrs = 0x00100006;
+SDRAM[1].EmcMrw1 = 0x00000000;
+SDRAM[1].EmcMrw2 = 0x00000000;
+SDRAM[1].EmcMrw3 = 0x00000000;
+SDRAM[1].EmcMrwResetCommand = 0x00000000;
+SDRAM[1].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[1].EmcAdrCfg = 0x00060303;
+SDRAM[1].EmcAdrCfg1 = 0x00060303;
+SDRAM[1].McEmemCfg = 0x00040000;
+SDRAM[1].McLowLatencyConfig = 0x80000003;
+SDRAM[1].EmcCfg = 0x0301ff00;
+SDRAM[1].EmcCfg2 = 0x00000405;
+SDRAM[1].EmcDbg = 0x01000400;
+SDRAM[1].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[1].EmcCfgDigDll = 0xf0000313;
+SDRAM[1].EmcDllXformDqs = 0x00000010;
+SDRAM[1].EmcDllXformQUse = 0x00000008;
+SDRAM[1].WarmBootWait = 0x00000002;
+SDRAM[1].EmcCttTermCtrl = 0x00000802;
+SDRAM[1].EmcOdtWrite = 0x80000001;
+SDRAM[1].EmcOdtRead = 0x80000001;
+SDRAM[1].EmcZcalRefCnt = 0x00000000;
+SDRAM[1].EmcZcalWaitCnt = 0x00000000;
+SDRAM[1].EmcZcalMrwCmd = 0x00000000;
+SDRAM[1].EmcMrsResetDll = 0x00000000;
+SDRAM[1].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[1].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[1].EmcMrwZqInitWait = 0x00000000;
+SDRAM[1].EmcMrsResetDllWait = 0x00000000;
+SDRAM[1].EmcEmrsEmr2 = 0x00200000;
+SDRAM[1].EmcEmrsEmr3 = 0x00300000;
+SDRAM[1].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[1].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[1].EmcDdr2Wait = 0x00000002;
+SDRAM[1].EmcCfgClktrim0 = 0x00000000;
+SDRAM[1].EmcCfgClktrim1 = 0x00000000;
+SDRAM[1].EmcCfgClktrim2 = 0x00000000;
+SDRAM[1].PmcDdrPwr = 0x00000001;
+SDRAM[1].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[1].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[1].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[1].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[1].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[1].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[1].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[1].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[2].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[2].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[2].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[2].PllMInputDivider = 0x0000000d;
+SDRAM[2].PllMFeedbackDivider = 0x0000029a;
+SDRAM[2].PllMPostDivider = 0x00000000;
+SDRAM[2].PllMStableTime = 0x0000012c;
+SDRAM[2].EmcClockDivider = 0x00000001;
+SDRAM[2].EmcAutoCalInterval = 0x00000000;
+SDRAM[2].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[2].EmcAutoCalWait = 0x00000000;
+SDRAM[2].EmcPinProgramWait = 0x00000000;
+SDRAM[2].EmcRc = 0x00000014;
+SDRAM[2].EmcRfc = 0x0000002b;
+SDRAM[2].EmcRas = 0x0000000f;
+SDRAM[2].EmcRp = 0x00000005;
+SDRAM[2].EmcR2w = 0x00000005;
+SDRAM[2].EmcW2r = 0x00000005;
+SDRAM[2].EmcR2p = 0x00000003;
+SDRAM[2].EmcW2p = 0x0000000c;
+SDRAM[2].EmcRdRcd = 0x00000005;
+SDRAM[2].EmcWrRcd = 0x00000005;
+SDRAM[2].EmcRrd = 0x00000003;
+SDRAM[2].EmcRext = 0x00000001;
+SDRAM[2].EmcWdv = 0x00000004;
+SDRAM[2].EmcQUse = 0x00000005;
+SDRAM[2].EmcQRst = 0x00000004;
+SDRAM[2].EmcQSafe = 0x00000009;
+SDRAM[2].EmcRdv = 0x0000000d;
+SDRAM[2].EmcRefresh = 0x000009ff;
+SDRAM[2].EmcBurstRefreshNum = 0x00000000;
+SDRAM[2].EmcPdEx2Wr = 0x00000003;
+SDRAM[2].EmcPdEx2Rd = 0x00000003;
+SDRAM[2].EmcPChg2Pden = 0x00000005;
+SDRAM[2].EmcAct2Pden = 0x00000005;
+SDRAM[2].EmcAr2Pden = 0x00000001;
+SDRAM[2].EmcRw2Pden = 0x0000000f;
+SDRAM[2].EmcTxsr = 0x000000c8;
+SDRAM[2].EmcTcke = 0x00000003;
+SDRAM[2].EmcTfaw = 0x0000000c;
+SDRAM[2].EmcTrpab = 0x00000006;
+SDRAM[2].EmcTClkStable = 0x00000008;
+SDRAM[2].EmcTClkStop = 0x00000002;
+SDRAM[2].EmcTRefBw = 0x00000000;
+SDRAM[2].EmcQUseExtra = 0x00000000;
+SDRAM[2].EmcFbioCfg1 = 0x00000000;
+SDRAM[2].EmcFbioDqsibDly = 0x20202020;
+SDRAM[2].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[2].EmcFbioQuseDly = 0x50465046;
+SDRAM[2].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[2].EmcFbioCfg5 = 0x00000183;
+SDRAM[2].EmcFbioCfg6 = 0x00000002;
+SDRAM[2].EmcFbioSpare = 0x00000000;
+SDRAM[2].EmcMrs = 0x00000a6a;
+SDRAM[2].EmcEmrs = 0x00100006;
+SDRAM[2].EmcMrw1 = 0x00000000;
+SDRAM[2].EmcMrw2 = 0x00000000;
+SDRAM[2].EmcMrw3 = 0x00000000;
+SDRAM[2].EmcMrwResetCommand = 0x00000000;
+SDRAM[2].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[2].EmcAdrCfg = 0x00060303;
+SDRAM[2].EmcAdrCfg1 = 0x00060303;
+SDRAM[2].McEmemCfg = 0x00040000;
+SDRAM[2].McLowLatencyConfig = 0x80000003;
+SDRAM[2].EmcCfg = 0x0301ff00;
+SDRAM[2].EmcCfg2 = 0x00000405;
+SDRAM[2].EmcDbg = 0x01000400;
+SDRAM[2].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[2].EmcCfgDigDll = 0xf0000313;
+SDRAM[2].EmcDllXformDqs = 0x00000010;
+SDRAM[2].EmcDllXformQUse = 0x00000008;
+SDRAM[2].WarmBootWait = 0x00000002;
+SDRAM[2].EmcCttTermCtrl = 0x00000802;
+SDRAM[2].EmcOdtWrite = 0x80000001;
+SDRAM[2].EmcOdtRead = 0x80000001;
+SDRAM[2].EmcZcalRefCnt = 0x00000000;
+SDRAM[2].EmcZcalWaitCnt = 0x00000000;
+SDRAM[2].EmcZcalMrwCmd = 0x00000000;
+SDRAM[2].EmcMrsResetDll = 0x00000000;
+SDRAM[2].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[2].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[2].EmcMrwZqInitWait = 0x00000000;
+SDRAM[2].EmcMrsResetDllWait = 0x00000000;
+SDRAM[2].EmcEmrsEmr2 = 0x00200000;
+SDRAM[2].EmcEmrsEmr3 = 0x00300000;
+SDRAM[2].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[2].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[2].EmcDdr2Wait = 0x00000002;
+SDRAM[2].EmcCfgClktrim0 = 0x00000000;
+SDRAM[2].EmcCfgClktrim1 = 0x00000000;
+SDRAM[2].EmcCfgClktrim2 = 0x00000000;
+SDRAM[2].PmcDdrPwr = 0x00000001;
+SDRAM[2].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[2].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[2].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[2].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[2].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[2].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[2].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[2].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[3].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[3].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[3].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[3].PllMInputDivider = 0x0000000d;
+SDRAM[3].PllMFeedbackDivider = 0x0000029a;
+SDRAM[3].PllMPostDivider = 0x00000000;
+SDRAM[3].PllMStableTime = 0x0000012c;
+SDRAM[3].EmcClockDivider = 0x00000001;
+SDRAM[3].EmcAutoCalInterval = 0x00000000;
+SDRAM[3].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[3].EmcAutoCalWait = 0x00000000;
+SDRAM[3].EmcPinProgramWait = 0x00000000;
+SDRAM[3].EmcRc = 0x00000014;
+SDRAM[3].EmcRfc = 0x0000002b;
+SDRAM[3].EmcRas = 0x0000000f;
+SDRAM[3].EmcRp = 0x00000005;
+SDRAM[3].EmcR2w = 0x00000005;
+SDRAM[3].EmcW2r = 0x00000005;
+SDRAM[3].EmcR2p = 0x00000003;
+SDRAM[3].EmcW2p = 0x0000000c;
+SDRAM[3].EmcRdRcd = 0x00000005;
+SDRAM[3].EmcWrRcd = 0x00000005;
+SDRAM[3].EmcRrd = 0x00000003;
+SDRAM[3].EmcRext = 0x00000001;
+SDRAM[3].EmcWdv = 0x00000004;
+SDRAM[3].EmcQUse = 0x00000005;
+SDRAM[3].EmcQRst = 0x00000004;
+SDRAM[3].EmcQSafe = 0x00000009;
+SDRAM[3].EmcRdv = 0x0000000d;
+SDRAM[3].EmcRefresh = 0x000009ff;
+SDRAM[3].EmcBurstRefreshNum = 0x00000000;
+SDRAM[3].EmcPdEx2Wr = 0x00000003;
+SDRAM[3].EmcPdEx2Rd = 0x00000003;
+SDRAM[3].EmcPChg2Pden = 0x00000005;
+SDRAM[3].EmcAct2Pden = 0x00000005;
+SDRAM[3].EmcAr2Pden = 0x00000001;
+SDRAM[3].EmcRw2Pden = 0x0000000f;
+SDRAM[3].EmcTxsr = 0x000000c8;
+SDRAM[3].EmcTcke = 0x00000003;
+SDRAM[3].EmcTfaw = 0x0000000c;
+SDRAM[3].EmcTrpab = 0x00000006;
+SDRAM[3].EmcTClkStable = 0x00000008;
+SDRAM[3].EmcTClkStop = 0x00000002;
+SDRAM[3].EmcTRefBw = 0x00000000;
+SDRAM[3].EmcQUseExtra = 0x00000000;
+SDRAM[3].EmcFbioCfg1 = 0x00000000;
+SDRAM[3].EmcFbioDqsibDly = 0x20202020;
+SDRAM[3].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[3].EmcFbioQuseDly = 0x50465046;
+SDRAM[3].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[3].EmcFbioCfg5 = 0x00000183;
+SDRAM[3].EmcFbioCfg6 = 0x00000002;
+SDRAM[3].EmcFbioSpare = 0x00000000;
+SDRAM[3].EmcMrs = 0x00000a6a;
+SDRAM[3].EmcEmrs = 0x00100006;
+SDRAM[3].EmcMrw1 = 0x00000000;
+SDRAM[3].EmcMrw2 = 0x00000000;
+SDRAM[3].EmcMrw3 = 0x00000000;
+SDRAM[3].EmcMrwResetCommand = 0x00000000;
+SDRAM[3].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[3].EmcAdrCfg = 0x00060303;
+SDRAM[3].EmcAdrCfg1 = 0x00060303;
+SDRAM[3].McEmemCfg = 0x00040000;
+SDRAM[3].McLowLatencyConfig = 0x80000003;
+SDRAM[3].EmcCfg = 0x0301ff00;
+SDRAM[3].EmcCfg2 = 0x00000405;
+SDRAM[3].EmcDbg = 0x01000400;
+SDRAM[3].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[3].EmcCfgDigDll = 0xf0000313;
+SDRAM[3].EmcDllXformDqs = 0x00000010;
+SDRAM[3].EmcDllXformQUse = 0x00000008;
+SDRAM[3].WarmBootWait = 0x00000002;
+SDRAM[3].EmcCttTermCtrl = 0x00000802;
+SDRAM[3].EmcOdtWrite = 0x80000001;
+SDRAM[3].EmcOdtRead = 0x80000001;
+SDRAM[3].EmcZcalRefCnt = 0x00000000;
+SDRAM[3].EmcZcalWaitCnt = 0x00000000;
+SDRAM[3].EmcZcalMrwCmd = 0x00000000;
+SDRAM[3].EmcMrsResetDll = 0x00000000;
+SDRAM[3].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[3].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[3].EmcMrwZqInitWait = 0x00000000;
+SDRAM[3].EmcMrsResetDllWait = 0x00000000;
+SDRAM[3].EmcEmrsEmr2 = 0x00200000;
+SDRAM[3].EmcEmrsEmr3 = 0x00300000;
+SDRAM[3].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[3].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[3].EmcDdr2Wait = 0x00000002;
+SDRAM[3].EmcCfgClktrim0 = 0x00000000;
+SDRAM[3].EmcCfgClktrim1 = 0x00000000;
+SDRAM[3].EmcCfgClktrim2 = 0x00000000;
+SDRAM[3].PmcDdrPwr = 0x00000001;
+SDRAM[3].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[3].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[3].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[3].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[3].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[3].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[3].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[3].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
diff --git a/arch/arm/boards/toradex-colibri-t20/colibri-t20_256_v11_nand.bct.cfg b/arch/arm/boards/toradex-colibri-t20/colibri-t20_256_v11_nand.bct.cfg
new file mode 100644
index 0000000000..2ec736bfac
--- /dev/null
+++ b/arch/arm/boards/toradex-colibri-t20/colibri-t20_256_v11_nand.bct.cfg
@@ -0,0 +1,459 @@
+# Copyright (c) 2013, Toradex AG. All rights reserved.
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+# claim that you wrote the original software. If you use this software
+# in a product, an acknowledgment in the product documentation would be
+# appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+# misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+Version = 0x00020001;
+PartitionSize = 8388608;
+BlockSize = 524288;
+PageSize = 4096;
+OdmData = 0x100C0000;
+
+DevType[0] = Nand;
+DeviceParam[0].NandParams.ClockDivider = 0x4; # Clock source of 108MHz
+DeviceParam[0].NandParams.NandTiming2 = 0xA; # For 108MHz clock
+DeviceParam[0].NandParams.NandTiming = 0x3B269213; # For 108MHz clock
+DeviceParam[0].NandParams.BlockSizeLog2 = 0;
+DeviceParam[0].NandParams.PageSizeLog2 = 0;
+
+DevType[1] = Nand;
+DeviceParam[1].NandParams.ClockDivider = 0x4; # Clock source of 108MHz
+DeviceParam[1].NandParams.NandTiming2 = 0xA; # For 108MHz clock
+DeviceParam[1].NandParams.NandTiming = 0x3B269213; # For 108MHz clock
+DeviceParam[1].NandParams.BlockSizeLog2 = 0;
+DeviceParam[1].NandParams.PageSizeLog2 = 0;
+
+DevType[2] = Nand;
+DeviceParam[2].NandParams.ClockDivider = 0x4; # Clock source of 108MHz
+DeviceParam[2].NandParams.NandTiming2 = 0xA; # For 108MHz clock
+DeviceParam[2].NandParams.NandTiming = 0x3B269213; # For 108MHz clock
+DeviceParam[2].NandParams.BlockSizeLog2 = 0;
+DeviceParam[2].NandParams.PageSizeLog2 = 0;
+
+DevType[3] = Nand;
+DeviceParam[3].NandParams.ClockDivider = 0x4; # Clock source of 108MHz
+DeviceParam[3].NandParams.NandTiming2 = 0xA; # For 108MHz clock
+DeviceParam[3].NandParams.NandTiming = 0x3B269213; # For 108MHz clock
+DeviceParam[3].NandParams.BlockSizeLog2 = 0;
+DeviceParam[3].NandParams.PageSizeLog2 = 0;
+
+SDRAM[0].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[0].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[0].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[0].PllMInputDivider = 0x0000000d;
+SDRAM[0].PllMFeedbackDivider = 0x0000029a;
+SDRAM[0].PllMPostDivider = 0x00000000;
+SDRAM[0].PllMStableTime = 0x0000012c;
+SDRAM[0].EmcClockDivider = 0x00000001;
+SDRAM[0].EmcAutoCalInterval = 0x00000000;
+SDRAM[0].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[0].EmcAutoCalWait = 0x00000000;
+SDRAM[0].EmcPinProgramWait = 0x00000000;
+SDRAM[0].EmcRc = 0x00000014;
+SDRAM[0].EmcRfc = 0x0000002b;
+SDRAM[0].EmcRas = 0x0000000f;
+SDRAM[0].EmcRp = 0x00000005;
+SDRAM[0].EmcR2w = 0x00000004;
+SDRAM[0].EmcW2r = 0x00000005;
+SDRAM[0].EmcR2p = 0x00000003;
+SDRAM[0].EmcW2p = 0x0000000a;
+SDRAM[0].EmcRdRcd = 0x00000005;
+SDRAM[0].EmcWrRcd = 0x00000005;
+SDRAM[0].EmcRrd = 0x00000004;
+SDRAM[0].EmcRext = 0x00000001;
+SDRAM[0].EmcWdv = 0x00000003;
+SDRAM[0].EmcQUse = 0x00000004;
+SDRAM[0].EmcQRst = 0x00000003;
+SDRAM[0].EmcQSafe = 0x00000009;
+SDRAM[0].EmcRdv = 0x0000000c;
+SDRAM[0].EmcRefresh = 0x000009ff;
+SDRAM[0].EmcBurstRefreshNum = 0x00000000;
+SDRAM[0].EmcPdEx2Wr = 0x00000003;
+SDRAM[0].EmcPdEx2Rd = 0x00000003;
+SDRAM[0].EmcPChg2Pden = 0x00000005;
+SDRAM[0].EmcAct2Pden = 0x00000005;
+SDRAM[0].EmcAr2Pden = 0x00000001;
+SDRAM[0].EmcRw2Pden = 0x0000000e;
+SDRAM[0].EmcTxsr = 0x000000c8;
+SDRAM[0].EmcTcke = 0x00000003;
+SDRAM[0].EmcTfaw = 0x00000011;
+SDRAM[0].EmcTrpab = 0x00000006;
+SDRAM[0].EmcTClkStable = 0x00000006;
+SDRAM[0].EmcTClkStop = 0x00000002;
+SDRAM[0].EmcTRefBw = 0x00000000;
+SDRAM[0].EmcQUseExtra = 0x00000000;
+SDRAM[0].EmcFbioCfg1 = 0x00000000;
+SDRAM[0].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[0].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[0].EmcFbioQuseDly = 0x74747474;
+SDRAM[0].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[0].EmcFbioCfg5 = 0x00000083;
+SDRAM[0].EmcFbioCfg6 = 0x00000002;
+SDRAM[0].EmcFbioSpare = 0x00000000;
+SDRAM[0].EmcMrs = 0x0000085a;
+SDRAM[0].EmcEmrs = 0x00100002;
+SDRAM[0].EmcMrw1 = 0x00000000;
+SDRAM[0].EmcMrw2 = 0x00000000;
+SDRAM[0].EmcMrw3 = 0x00000000;
+SDRAM[0].EmcMrwResetCommand = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[0].EmcAdrCfg = 0x00060303;
+SDRAM[0].EmcAdrCfg1 = 0x00060303;
+SDRAM[0].McEmemCfg = 0x00040000;
+SDRAM[0].McLowLatencyConfig = 0x80000003;
+SDRAM[0].EmcCfg = 0x0301ff00;
+SDRAM[0].EmcCfg2 = 0x00000405;
+SDRAM[0].EmcDbg = 0x01000400;
+SDRAM[0].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[0].EmcCfgDigDll = 0xf0000313;
+SDRAM[0].EmcDllXformDqs = 0x00000010;
+SDRAM[0].EmcDllXformQUse = 0x00000008;
+SDRAM[0].WarmBootWait = 0x00000002;
+SDRAM[0].EmcCttTermCtrl = 0x00000802;
+SDRAM[0].EmcOdtWrite = 0x00000000;
+SDRAM[0].EmcOdtRead = 0x00000000;
+SDRAM[0].EmcZcalRefCnt = 0x00000000;
+SDRAM[0].EmcZcalWaitCnt = 0x00000000;
+SDRAM[0].EmcZcalMrwCmd = 0x00000000;
+SDRAM[0].EmcMrsResetDll = 0x00000000;
+SDRAM[0].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[0].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[0].EmcMrwZqInitWait = 0x00000000;
+SDRAM[0].EmcMrsResetDllWait = 0x00000000;
+SDRAM[0].EmcEmrsEmr2 = 0x00200000;
+SDRAM[0].EmcEmrsEmr3 = 0x00300000;
+SDRAM[0].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[0].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[0].EmcDdr2Wait = 0x00000002;
+SDRAM[0].EmcCfgClktrim0 = 0x00000000;
+SDRAM[0].EmcCfgClktrim1 = 0x00000000;
+SDRAM[0].EmcCfgClktrim2 = 0x00000000;
+SDRAM[0].PmcDdrPwr = 0x00000001;
+SDRAM[0].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[0].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[0].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[0].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[0].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[1].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[1].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[1].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[1].PllMInputDivider = 0x0000000d;
+SDRAM[1].PllMFeedbackDivider = 0x0000029a;
+SDRAM[1].PllMPostDivider = 0x00000000;
+SDRAM[1].PllMStableTime = 0x0000012c;
+SDRAM[1].EmcClockDivider = 0x00000001;
+SDRAM[1].EmcAutoCalInterval = 0x00000000;
+SDRAM[1].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[1].EmcAutoCalWait = 0x00000000;
+SDRAM[1].EmcPinProgramWait = 0x00000000;
+SDRAM[1].EmcRc = 0x00000014;
+SDRAM[1].EmcRfc = 0x0000002b;
+SDRAM[1].EmcRas = 0x0000000f;
+SDRAM[1].EmcRp = 0x00000005;
+SDRAM[1].EmcR2w = 0x00000004;
+SDRAM[1].EmcW2r = 0x00000005;
+SDRAM[1].EmcR2p = 0x00000003;
+SDRAM[1].EmcW2p = 0x0000000a;
+SDRAM[1].EmcRdRcd = 0x00000005;
+SDRAM[1].EmcWrRcd = 0x00000005;
+SDRAM[1].EmcRrd = 0x00000004;
+SDRAM[1].EmcRext = 0x00000001;
+SDRAM[1].EmcWdv = 0x00000003;
+SDRAM[1].EmcQUse = 0x00000004;
+SDRAM[1].EmcQRst = 0x00000003;
+SDRAM[1].EmcQSafe = 0x00000009;
+SDRAM[1].EmcRdv = 0x0000000c;
+SDRAM[1].EmcRefresh = 0x000009ff;
+SDRAM[1].EmcBurstRefreshNum = 0x00000000;
+SDRAM[1].EmcPdEx2Wr = 0x00000003;
+SDRAM[1].EmcPdEx2Rd = 0x00000003;
+SDRAM[1].EmcPChg2Pden = 0x00000005;
+SDRAM[1].EmcAct2Pden = 0x00000005;
+SDRAM[1].EmcAr2Pden = 0x00000001;
+SDRAM[1].EmcRw2Pden = 0x0000000e;
+SDRAM[1].EmcTxsr = 0x000000c8;
+SDRAM[1].EmcTcke = 0x00000003;
+SDRAM[1].EmcTfaw = 0x00000011;
+SDRAM[1].EmcTrpab = 0x00000006;
+SDRAM[1].EmcTClkStable = 0x00000006;
+SDRAM[1].EmcTClkStop = 0x00000002;
+SDRAM[1].EmcTRefBw = 0x00000000;
+SDRAM[1].EmcQUseExtra = 0x00000000;
+SDRAM[1].EmcFbioCfg1 = 0x00000000;
+SDRAM[1].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[1].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[1].EmcFbioQuseDly = 0x74747474;
+SDRAM[1].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[1].EmcFbioCfg5 = 0x00000083;
+SDRAM[1].EmcFbioCfg6 = 0x00000002;
+SDRAM[1].EmcFbioSpare = 0x00000000;
+SDRAM[1].EmcMrs = 0x0000085a;
+SDRAM[1].EmcEmrs = 0x00100002;
+SDRAM[1].EmcMrw1 = 0x00000000;
+SDRAM[1].EmcMrw2 = 0x00000000;
+SDRAM[1].EmcMrw3 = 0x00000000;
+SDRAM[1].EmcMrwResetCommand = 0x00000000;
+SDRAM[1].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[1].EmcAdrCfg = 0x00060303;
+SDRAM[1].EmcAdrCfg1 = 0x00060303;
+SDRAM[1].McEmemCfg = 0x00040000;
+SDRAM[1].McLowLatencyConfig = 0x80000003;
+SDRAM[1].EmcCfg = 0x0301ff00;
+SDRAM[1].EmcCfg2 = 0x00000405;
+SDRAM[1].EmcDbg = 0x01000400;
+SDRAM[1].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[1].EmcCfgDigDll = 0xf0000313;
+SDRAM[1].EmcDllXformDqs = 0x00000010;
+SDRAM[1].EmcDllXformQUse = 0x00000008;
+SDRAM[1].WarmBootWait = 0x00000002;
+SDRAM[1].EmcCttTermCtrl = 0x00000802;
+SDRAM[1].EmcOdtWrite = 0x00000000;
+SDRAM[1].EmcOdtRead = 0x00000000;
+SDRAM[1].EmcZcalRefCnt = 0x00000000;
+SDRAM[1].EmcZcalWaitCnt = 0x00000000;
+SDRAM[1].EmcZcalMrwCmd = 0x00000000;
+SDRAM[1].EmcMrsResetDll = 0x00000000;
+SDRAM[1].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[1].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[1].EmcMrwZqInitWait = 0x00000000;
+SDRAM[1].EmcMrsResetDllWait = 0x00000000;
+SDRAM[1].EmcEmrsEmr2 = 0x00200000;
+SDRAM[1].EmcEmrsEmr3 = 0x00300000;
+SDRAM[1].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[1].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[1].EmcDdr2Wait = 0x00000002;
+SDRAM[1].EmcCfgClktrim0 = 0x00000000;
+SDRAM[1].EmcCfgClktrim1 = 0x00000000;
+SDRAM[1].EmcCfgClktrim2 = 0x00000000;
+SDRAM[1].PmcDdrPwr = 0x00000001;
+SDRAM[1].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[1].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[1].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[1].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[1].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[1].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[1].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[1].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[2].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[2].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[2].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[2].PllMInputDivider = 0x0000000d;
+SDRAM[2].PllMFeedbackDivider = 0x0000029a;
+SDRAM[2].PllMPostDivider = 0x00000000;
+SDRAM[2].PllMStableTime = 0x0000012c;
+SDRAM[2].EmcClockDivider = 0x00000001;
+SDRAM[2].EmcAutoCalInterval = 0x00000000;
+SDRAM[2].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[2].EmcAutoCalWait = 0x00000000;
+SDRAM[2].EmcPinProgramWait = 0x00000000;
+SDRAM[2].EmcRc = 0x00000014;
+SDRAM[2].EmcRfc = 0x0000002b;
+SDRAM[2].EmcRas = 0x0000000f;
+SDRAM[2].EmcRp = 0x00000005;
+SDRAM[2].EmcR2w = 0x00000004;
+SDRAM[2].EmcW2r = 0x00000005;
+SDRAM[2].EmcR2p = 0x00000003;
+SDRAM[2].EmcW2p = 0x0000000a;
+SDRAM[2].EmcRdRcd = 0x00000005;
+SDRAM[2].EmcWrRcd = 0x00000005;
+SDRAM[2].EmcRrd = 0x00000004;
+SDRAM[2].EmcRext = 0x00000001;
+SDRAM[2].EmcWdv = 0x00000003;
+SDRAM[2].EmcQUse = 0x00000004;
+SDRAM[2].EmcQRst = 0x00000003;
+SDRAM[2].EmcQSafe = 0x00000009;
+SDRAM[2].EmcRdv = 0x0000000c;
+SDRAM[2].EmcRefresh = 0x000009ff;
+SDRAM[2].EmcBurstRefreshNum = 0x00000000;
+SDRAM[2].EmcPdEx2Wr = 0x00000003;
+SDRAM[2].EmcPdEx2Rd = 0x00000003;
+SDRAM[2].EmcPChg2Pden = 0x00000005;
+SDRAM[2].EmcAct2Pden = 0x00000005;
+SDRAM[2].EmcAr2Pden = 0x00000001;
+SDRAM[2].EmcRw2Pden = 0x0000000e;
+SDRAM[2].EmcTxsr = 0x000000c8;
+SDRAM[2].EmcTcke = 0x00000003;
+SDRAM[2].EmcTfaw = 0x00000011;
+SDRAM[2].EmcTrpab = 0x00000006;
+SDRAM[2].EmcTClkStable = 0x00000006;
+SDRAM[2].EmcTClkStop = 0x00000002;
+SDRAM[2].EmcTRefBw = 0x00000000;
+SDRAM[2].EmcQUseExtra = 0x00000000;
+SDRAM[2].EmcFbioCfg1 = 0x00000000;
+SDRAM[2].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[2].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[2].EmcFbioQuseDly = 0x74747474;
+SDRAM[2].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[2].EmcFbioCfg5 = 0x00000083;
+SDRAM[2].EmcFbioCfg6 = 0x00000002;
+SDRAM[2].EmcFbioSpare = 0x00000000;
+SDRAM[2].EmcMrs = 0x0000085a;
+SDRAM[2].EmcEmrs = 0x00100002;
+SDRAM[2].EmcMrw1 = 0x00000000;
+SDRAM[2].EmcMrw2 = 0x00000000;
+SDRAM[2].EmcMrw3 = 0x00000000;
+SDRAM[2].EmcMrwResetCommand = 0x00000000;
+SDRAM[2].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[2].EmcAdrCfg = 0x00060303;
+SDRAM[2].EmcAdrCfg1 = 0x00060303;
+SDRAM[2].McEmemCfg = 0x00040000;
+SDRAM[2].McLowLatencyConfig = 0x80000003;
+SDRAM[2].EmcCfg = 0x0301ff00;
+SDRAM[2].EmcCfg2 = 0x00000405;
+SDRAM[2].EmcDbg = 0x01000400;
+SDRAM[2].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[2].EmcCfgDigDll = 0xf0000313;
+SDRAM[2].EmcDllXformDqs = 0x00000010;
+SDRAM[2].EmcDllXformQUse = 0x00000008;
+SDRAM[2].WarmBootWait = 0x00000002;
+SDRAM[2].EmcCttTermCtrl = 0x00000802;
+SDRAM[2].EmcOdtWrite = 0x00000000;
+SDRAM[2].EmcOdtRead = 0x00000000;
+SDRAM[2].EmcZcalRefCnt = 0x00000000;
+SDRAM[2].EmcZcalWaitCnt = 0x00000000;
+SDRAM[2].EmcZcalMrwCmd = 0x00000000;
+SDRAM[2].EmcMrsResetDll = 0x00000000;
+SDRAM[2].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[2].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[2].EmcMrwZqInitWait = 0x00000000;
+SDRAM[2].EmcMrsResetDllWait = 0x00000000;
+SDRAM[2].EmcEmrsEmr2 = 0x00200000;
+SDRAM[2].EmcEmrsEmr3 = 0x00300000;
+SDRAM[2].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[2].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[2].EmcDdr2Wait = 0x00000002;
+SDRAM[2].EmcCfgClktrim0 = 0x00000000;
+SDRAM[2].EmcCfgClktrim1 = 0x00000000;
+SDRAM[2].EmcCfgClktrim2 = 0x00000000;
+SDRAM[2].PmcDdrPwr = 0x00000001;
+SDRAM[2].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[2].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[2].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[2].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[2].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[2].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[2].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[2].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[3].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[3].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[3].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[3].PllMInputDivider = 0x0000000d;
+SDRAM[3].PllMFeedbackDivider = 0x0000029a;
+SDRAM[3].PllMPostDivider = 0x00000000;
+SDRAM[3].PllMStableTime = 0x0000012c;
+SDRAM[3].EmcClockDivider = 0x00000001;
+SDRAM[3].EmcAutoCalInterval = 0x00000000;
+SDRAM[3].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[3].EmcAutoCalWait = 0x00000000;
+SDRAM[3].EmcPinProgramWait = 0x00000000;
+SDRAM[3].EmcRc = 0x00000014;
+SDRAM[3].EmcRfc = 0x0000002b;
+SDRAM[3].EmcRas = 0x0000000f;
+SDRAM[3].EmcRp = 0x00000005;
+SDRAM[3].EmcR2w = 0x00000004;
+SDRAM[3].EmcW2r = 0x00000005;
+SDRAM[3].EmcR2p = 0x00000003;
+SDRAM[3].EmcW2p = 0x0000000a;
+SDRAM[3].EmcRdRcd = 0x00000005;
+SDRAM[3].EmcWrRcd = 0x00000005;
+SDRAM[3].EmcRrd = 0x00000004;
+SDRAM[3].EmcRext = 0x00000001;
+SDRAM[3].EmcWdv = 0x00000003;
+SDRAM[3].EmcQUse = 0x00000004;
+SDRAM[3].EmcQRst = 0x00000003;
+SDRAM[3].EmcQSafe = 0x00000009;
+SDRAM[3].EmcRdv = 0x0000000c;
+SDRAM[3].EmcRefresh = 0x000009ff;
+SDRAM[3].EmcBurstRefreshNum = 0x00000000;
+SDRAM[3].EmcPdEx2Wr = 0x00000003;
+SDRAM[3].EmcPdEx2Rd = 0x00000003;
+SDRAM[3].EmcPChg2Pden = 0x00000005;
+SDRAM[3].EmcAct2Pden = 0x00000005;
+SDRAM[3].EmcAr2Pden = 0x00000001;
+SDRAM[3].EmcRw2Pden = 0x0000000e;
+SDRAM[3].EmcTxsr = 0x000000c8;
+SDRAM[3].EmcTcke = 0x00000003;
+SDRAM[3].EmcTfaw = 0x00000011;
+SDRAM[3].EmcTrpab = 0x00000006;
+SDRAM[3].EmcTClkStable = 0x00000006;
+SDRAM[3].EmcTClkStop = 0x00000002;
+SDRAM[3].EmcTRefBw = 0x00000000;
+SDRAM[3].EmcQUseExtra = 0x00000000;
+SDRAM[3].EmcFbioCfg1 = 0x00000000;
+SDRAM[3].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[3].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[3].EmcFbioQuseDly = 0x74747474;
+SDRAM[3].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[3].EmcFbioCfg5 = 0x00000083;
+SDRAM[3].EmcFbioCfg6 = 0x00000002;
+SDRAM[3].EmcFbioSpare = 0x00000000;
+SDRAM[3].EmcMrs = 0x0000085a;
+SDRAM[3].EmcEmrs = 0x00100002;
+SDRAM[3].EmcMrw1 = 0x00000000;
+SDRAM[3].EmcMrw2 = 0x00000000;
+SDRAM[3].EmcMrw3 = 0x00000000;
+SDRAM[3].EmcMrwResetCommand = 0x00000000;
+SDRAM[3].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[3].EmcAdrCfg = 0x00060303;
+SDRAM[3].EmcAdrCfg1 = 0x00060303;
+SDRAM[3].McEmemCfg = 0x00040000;
+SDRAM[3].McLowLatencyConfig = 0x80000003;
+SDRAM[3].EmcCfg = 0x0301ff00;
+SDRAM[3].EmcCfg2 = 0x00000405;
+SDRAM[3].EmcDbg = 0x01000400;
+SDRAM[3].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[3].EmcCfgDigDll = 0xf0000313;
+SDRAM[3].EmcDllXformDqs = 0x00000010;
+SDRAM[3].EmcDllXformQUse = 0x00000008;
+SDRAM[3].WarmBootWait = 0x00000002;
+SDRAM[3].EmcCttTermCtrl = 0x00000802;
+SDRAM[3].EmcOdtWrite = 0x00000000;
+SDRAM[3].EmcOdtRead = 0x00000000;
+SDRAM[3].EmcZcalRefCnt = 0x00000000;
+SDRAM[3].EmcZcalWaitCnt = 0x00000000;
+SDRAM[3].EmcZcalMrwCmd = 0x00000000;
+SDRAM[3].EmcMrsResetDll = 0x00000000;
+SDRAM[3].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[3].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[3].EmcMrwZqInitWait = 0x00000000;
+SDRAM[3].EmcMrsResetDllWait = 0x00000000;
+SDRAM[3].EmcEmrsEmr2 = 0x00200000;
+SDRAM[3].EmcEmrsEmr3 = 0x00300000;
+SDRAM[3].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[3].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[3].EmcDdr2Wait = 0x00000002;
+SDRAM[3].EmcCfgClktrim0 = 0x00000000;
+SDRAM[3].EmcCfgClktrim1 = 0x00000000;
+SDRAM[3].EmcCfgClktrim2 = 0x00000000;
+SDRAM[3].PmcDdrPwr = 0x00000001;
+SDRAM[3].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[3].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[3].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[3].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[3].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[3].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[3].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[3].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
diff --git a/arch/arm/boards/toradex-colibri-t20/colibri-t20_256_v12_nand.bct.cfg b/arch/arm/boards/toradex-colibri-t20/colibri-t20_256_v12_nand.bct.cfg
new file mode 100644
index 0000000000..86ee537628
--- /dev/null
+++ b/arch/arm/boards/toradex-colibri-t20/colibri-t20_256_v12_nand.bct.cfg
@@ -0,0 +1,459 @@
+# Copyright (c) 2013, Toradex AG. All rights reserved.
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+# claim that you wrote the original software. If you use this software
+# in a product, an acknowledgment in the product documentation would be
+# appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+# misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+Version = 0x00020001;
+PartitionSize = 8388608;
+BlockSize = 262144;
+PageSize = 4096;
+OdmData = 0x100C0000;
+
+DevType[0] = Nand;
+DeviceParam[0].NandParams.ClockDivider = 0x4; # Clock source of 108MHz
+DeviceParam[0].NandParams.NandTiming2 = 0xA; # For 108MHz clock
+DeviceParam[0].NandParams.NandTiming = 0x3B269213; # For 108MHz clock
+DeviceParam[0].NandParams.BlockSizeLog2 = 0;
+DeviceParam[0].NandParams.PageSizeLog2 = 0;
+
+DevType[1] = Nand;
+DeviceParam[1].NandParams.ClockDivider = 0x4; # Clock source of 108MHz
+DeviceParam[1].NandParams.NandTiming2 = 0xA; # For 108MHz clock
+DeviceParam[1].NandParams.NandTiming = 0x3B269213; # For 108MHz clock
+DeviceParam[1].NandParams.BlockSizeLog2 = 0;
+DeviceParam[1].NandParams.PageSizeLog2 = 0;
+
+DevType[2] = Nand;
+DeviceParam[2].NandParams.ClockDivider = 0x4; # Clock source of 108MHz
+DeviceParam[2].NandParams.NandTiming2 = 0xA; # For 108MHz clock
+DeviceParam[2].NandParams.NandTiming = 0x3B269213; # For 108MHz clock
+DeviceParam[2].NandParams.BlockSizeLog2 = 0;
+DeviceParam[2].NandParams.PageSizeLog2 = 0;
+
+DevType[3] = Nand;
+DeviceParam[3].NandParams.ClockDivider = 0x4; # Clock source of 108MHz
+DeviceParam[3].NandParams.NandTiming2 = 0xA; # For 108MHz clock
+DeviceParam[3].NandParams.NandTiming = 0x3B269213; # For 108MHz clock
+DeviceParam[3].NandParams.BlockSizeLog2 = 0;
+DeviceParam[3].NandParams.PageSizeLog2 = 0;
+
+SDRAM[0].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[0].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[0].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[0].PllMInputDivider = 0x0000000d;
+SDRAM[0].PllMFeedbackDivider = 0x0000029a;
+SDRAM[0].PllMPostDivider = 0x00000000;
+SDRAM[0].PllMStableTime = 0x0000012c;
+SDRAM[0].EmcClockDivider = 0x00000001;
+SDRAM[0].EmcAutoCalInterval = 0x00000000;
+SDRAM[0].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[0].EmcAutoCalWait = 0x00000000;
+SDRAM[0].EmcPinProgramWait = 0x00000000;
+SDRAM[0].EmcRc = 0x00000014;
+SDRAM[0].EmcRfc = 0x0000002b;
+SDRAM[0].EmcRas = 0x0000000f;
+SDRAM[0].EmcRp = 0x00000005;
+SDRAM[0].EmcR2w = 0x00000004;
+SDRAM[0].EmcW2r = 0x00000005;
+SDRAM[0].EmcR2p = 0x00000003;
+SDRAM[0].EmcW2p = 0x0000000a;
+SDRAM[0].EmcRdRcd = 0x00000005;
+SDRAM[0].EmcWrRcd = 0x00000005;
+SDRAM[0].EmcRrd = 0x00000004;
+SDRAM[0].EmcRext = 0x00000001;
+SDRAM[0].EmcWdv = 0x00000003;
+SDRAM[0].EmcQUse = 0x00000004;
+SDRAM[0].EmcQRst = 0x00000003;
+SDRAM[0].EmcQSafe = 0x00000009;
+SDRAM[0].EmcRdv = 0x0000000c;
+SDRAM[0].EmcRefresh = 0x000009ff;
+SDRAM[0].EmcBurstRefreshNum = 0x00000000;
+SDRAM[0].EmcPdEx2Wr = 0x00000003;
+SDRAM[0].EmcPdEx2Rd = 0x00000003;
+SDRAM[0].EmcPChg2Pden = 0x00000005;
+SDRAM[0].EmcAct2Pden = 0x00000005;
+SDRAM[0].EmcAr2Pden = 0x00000001;
+SDRAM[0].EmcRw2Pden = 0x0000000e;
+SDRAM[0].EmcTxsr = 0x000000c8;
+SDRAM[0].EmcTcke = 0x00000003;
+SDRAM[0].EmcTfaw = 0x00000011;
+SDRAM[0].EmcTrpab = 0x00000006;
+SDRAM[0].EmcTClkStable = 0x00000006;
+SDRAM[0].EmcTClkStop = 0x00000002;
+SDRAM[0].EmcTRefBw = 0x00000000;
+SDRAM[0].EmcQUseExtra = 0x00000000;
+SDRAM[0].EmcFbioCfg1 = 0x00000000;
+SDRAM[0].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[0].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[0].EmcFbioQuseDly = 0x74747474;
+SDRAM[0].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[0].EmcFbioCfg5 = 0x00000083;
+SDRAM[0].EmcFbioCfg6 = 0x00000002;
+SDRAM[0].EmcFbioSpare = 0x00000000;
+SDRAM[0].EmcMrs = 0x0000085a;
+SDRAM[0].EmcEmrs = 0x00100002;
+SDRAM[0].EmcMrw1 = 0x00000000;
+SDRAM[0].EmcMrw2 = 0x00000000;
+SDRAM[0].EmcMrw3 = 0x00000000;
+SDRAM[0].EmcMrwResetCommand = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[0].EmcAdrCfg = 0x00060303;
+SDRAM[0].EmcAdrCfg1 = 0x00060303;
+SDRAM[0].McEmemCfg = 0x00040000;
+SDRAM[0].McLowLatencyConfig = 0x80000003;
+SDRAM[0].EmcCfg = 0x0301ff00;
+SDRAM[0].EmcCfg2 = 0x00000405;
+SDRAM[0].EmcDbg = 0x01000400;
+SDRAM[0].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[0].EmcCfgDigDll = 0xf0000313;
+SDRAM[0].EmcDllXformDqs = 0x00000010;
+SDRAM[0].EmcDllXformQUse = 0x00000008;
+SDRAM[0].WarmBootWait = 0x00000002;
+SDRAM[0].EmcCttTermCtrl = 0x00000802;
+SDRAM[0].EmcOdtWrite = 0x00000000;
+SDRAM[0].EmcOdtRead = 0x00000000;
+SDRAM[0].EmcZcalRefCnt = 0x00000000;
+SDRAM[0].EmcZcalWaitCnt = 0x00000000;
+SDRAM[0].EmcZcalMrwCmd = 0x00000000;
+SDRAM[0].EmcMrsResetDll = 0x00000000;
+SDRAM[0].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[0].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[0].EmcMrwZqInitWait = 0x00000000;
+SDRAM[0].EmcMrsResetDllWait = 0x00000000;
+SDRAM[0].EmcEmrsEmr2 = 0x00200000;
+SDRAM[0].EmcEmrsEmr3 = 0x00300000;
+SDRAM[0].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[0].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[0].EmcDdr2Wait = 0x00000002;
+SDRAM[0].EmcCfgClktrim0 = 0x00000000;
+SDRAM[0].EmcCfgClktrim1 = 0x00000000;
+SDRAM[0].EmcCfgClktrim2 = 0x00000000;
+SDRAM[0].PmcDdrPwr = 0x00000001;
+SDRAM[0].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[0].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[0].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[0].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[0].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[1].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[1].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[1].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[1].PllMInputDivider = 0x0000000d;
+SDRAM[1].PllMFeedbackDivider = 0x0000029a;
+SDRAM[1].PllMPostDivider = 0x00000000;
+SDRAM[1].PllMStableTime = 0x0000012c;
+SDRAM[1].EmcClockDivider = 0x00000001;
+SDRAM[1].EmcAutoCalInterval = 0x00000000;
+SDRAM[1].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[1].EmcAutoCalWait = 0x00000000;
+SDRAM[1].EmcPinProgramWait = 0x00000000;
+SDRAM[1].EmcRc = 0x00000014;
+SDRAM[1].EmcRfc = 0x0000002b;
+SDRAM[1].EmcRas = 0x0000000f;
+SDRAM[1].EmcRp = 0x00000005;
+SDRAM[1].EmcR2w = 0x00000004;
+SDRAM[1].EmcW2r = 0x00000005;
+SDRAM[1].EmcR2p = 0x00000003;
+SDRAM[1].EmcW2p = 0x0000000a;
+SDRAM[1].EmcRdRcd = 0x00000005;
+SDRAM[1].EmcWrRcd = 0x00000005;
+SDRAM[1].EmcRrd = 0x00000004;
+SDRAM[1].EmcRext = 0x00000001;
+SDRAM[1].EmcWdv = 0x00000003;
+SDRAM[1].EmcQUse = 0x00000004;
+SDRAM[1].EmcQRst = 0x00000003;
+SDRAM[1].EmcQSafe = 0x00000009;
+SDRAM[1].EmcRdv = 0x0000000c;
+SDRAM[1].EmcRefresh = 0x000009ff;
+SDRAM[1].EmcBurstRefreshNum = 0x00000000;
+SDRAM[1].EmcPdEx2Wr = 0x00000003;
+SDRAM[1].EmcPdEx2Rd = 0x00000003;
+SDRAM[1].EmcPChg2Pden = 0x00000005;
+SDRAM[1].EmcAct2Pden = 0x00000005;
+SDRAM[1].EmcAr2Pden = 0x00000001;
+SDRAM[1].EmcRw2Pden = 0x0000000e;
+SDRAM[1].EmcTxsr = 0x000000c8;
+SDRAM[1].EmcTcke = 0x00000003;
+SDRAM[1].EmcTfaw = 0x00000011;
+SDRAM[1].EmcTrpab = 0x00000006;
+SDRAM[1].EmcTClkStable = 0x00000006;
+SDRAM[1].EmcTClkStop = 0x00000002;
+SDRAM[1].EmcTRefBw = 0x00000000;
+SDRAM[1].EmcQUseExtra = 0x00000000;
+SDRAM[1].EmcFbioCfg1 = 0x00000000;
+SDRAM[1].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[1].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[1].EmcFbioQuseDly = 0x74747474;
+SDRAM[1].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[1].EmcFbioCfg5 = 0x00000083;
+SDRAM[1].EmcFbioCfg6 = 0x00000002;
+SDRAM[1].EmcFbioSpare = 0x00000000;
+SDRAM[1].EmcMrs = 0x0000085a;
+SDRAM[1].EmcEmrs = 0x00100002;
+SDRAM[1].EmcMrw1 = 0x00000000;
+SDRAM[1].EmcMrw2 = 0x00000000;
+SDRAM[1].EmcMrw3 = 0x00000000;
+SDRAM[1].EmcMrwResetCommand = 0x00000000;
+SDRAM[1].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[1].EmcAdrCfg = 0x00060303;
+SDRAM[1].EmcAdrCfg1 = 0x00060303;
+SDRAM[1].McEmemCfg = 0x00040000;
+SDRAM[1].McLowLatencyConfig = 0x80000003;
+SDRAM[1].EmcCfg = 0x0301ff00;
+SDRAM[1].EmcCfg2 = 0x00000405;
+SDRAM[1].EmcDbg = 0x01000400;
+SDRAM[1].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[1].EmcCfgDigDll = 0xf0000313;
+SDRAM[1].EmcDllXformDqs = 0x00000010;
+SDRAM[1].EmcDllXformQUse = 0x00000008;
+SDRAM[1].WarmBootWait = 0x00000002;
+SDRAM[1].EmcCttTermCtrl = 0x00000802;
+SDRAM[1].EmcOdtWrite = 0x00000000;
+SDRAM[1].EmcOdtRead = 0x00000000;
+SDRAM[1].EmcZcalRefCnt = 0x00000000;
+SDRAM[1].EmcZcalWaitCnt = 0x00000000;
+SDRAM[1].EmcZcalMrwCmd = 0x00000000;
+SDRAM[1].EmcMrsResetDll = 0x00000000;
+SDRAM[1].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[1].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[1].EmcMrwZqInitWait = 0x00000000;
+SDRAM[1].EmcMrsResetDllWait = 0x00000000;
+SDRAM[1].EmcEmrsEmr2 = 0x00200000;
+SDRAM[1].EmcEmrsEmr3 = 0x00300000;
+SDRAM[1].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[1].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[1].EmcDdr2Wait = 0x00000002;
+SDRAM[1].EmcCfgClktrim0 = 0x00000000;
+SDRAM[1].EmcCfgClktrim1 = 0x00000000;
+SDRAM[1].EmcCfgClktrim2 = 0x00000000;
+SDRAM[1].PmcDdrPwr = 0x00000001;
+SDRAM[1].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[1].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[1].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[1].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[1].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[1].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[1].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[1].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[2].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[2].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[2].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[2].PllMInputDivider = 0x0000000d;
+SDRAM[2].PllMFeedbackDivider = 0x0000029a;
+SDRAM[2].PllMPostDivider = 0x00000000;
+SDRAM[2].PllMStableTime = 0x0000012c;
+SDRAM[2].EmcClockDivider = 0x00000001;
+SDRAM[2].EmcAutoCalInterval = 0x00000000;
+SDRAM[2].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[2].EmcAutoCalWait = 0x00000000;
+SDRAM[2].EmcPinProgramWait = 0x00000000;
+SDRAM[2].EmcRc = 0x00000014;
+SDRAM[2].EmcRfc = 0x0000002b;
+SDRAM[2].EmcRas = 0x0000000f;
+SDRAM[2].EmcRp = 0x00000005;
+SDRAM[2].EmcR2w = 0x00000004;
+SDRAM[2].EmcW2r = 0x00000005;
+SDRAM[2].EmcR2p = 0x00000003;
+SDRAM[2].EmcW2p = 0x0000000a;
+SDRAM[2].EmcRdRcd = 0x00000005;
+SDRAM[2].EmcWrRcd = 0x00000005;
+SDRAM[2].EmcRrd = 0x00000004;
+SDRAM[2].EmcRext = 0x00000001;
+SDRAM[2].EmcWdv = 0x00000003;
+SDRAM[2].EmcQUse = 0x00000004;
+SDRAM[2].EmcQRst = 0x00000003;
+SDRAM[2].EmcQSafe = 0x00000009;
+SDRAM[2].EmcRdv = 0x0000000c;
+SDRAM[2].EmcRefresh = 0x000009ff;
+SDRAM[2].EmcBurstRefreshNum = 0x00000000;
+SDRAM[2].EmcPdEx2Wr = 0x00000003;
+SDRAM[2].EmcPdEx2Rd = 0x00000003;
+SDRAM[2].EmcPChg2Pden = 0x00000005;
+SDRAM[2].EmcAct2Pden = 0x00000005;
+SDRAM[2].EmcAr2Pden = 0x00000001;
+SDRAM[2].EmcRw2Pden = 0x0000000e;
+SDRAM[2].EmcTxsr = 0x000000c8;
+SDRAM[2].EmcTcke = 0x00000003;
+SDRAM[2].EmcTfaw = 0x00000011;
+SDRAM[2].EmcTrpab = 0x00000006;
+SDRAM[2].EmcTClkStable = 0x00000006;
+SDRAM[2].EmcTClkStop = 0x00000002;
+SDRAM[2].EmcTRefBw = 0x00000000;
+SDRAM[2].EmcQUseExtra = 0x00000000;
+SDRAM[2].EmcFbioCfg1 = 0x00000000;
+SDRAM[2].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[2].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[2].EmcFbioQuseDly = 0x74747474;
+SDRAM[2].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[2].EmcFbioCfg5 = 0x00000083;
+SDRAM[2].EmcFbioCfg6 = 0x00000002;
+SDRAM[2].EmcFbioSpare = 0x00000000;
+SDRAM[2].EmcMrs = 0x0000085a;
+SDRAM[2].EmcEmrs = 0x00100002;
+SDRAM[2].EmcMrw1 = 0x00000000;
+SDRAM[2].EmcMrw2 = 0x00000000;
+SDRAM[2].EmcMrw3 = 0x00000000;
+SDRAM[2].EmcMrwResetCommand = 0x00000000;
+SDRAM[2].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[2].EmcAdrCfg = 0x00060303;
+SDRAM[2].EmcAdrCfg1 = 0x00060303;
+SDRAM[2].McEmemCfg = 0x00040000;
+SDRAM[2].McLowLatencyConfig = 0x80000003;
+SDRAM[2].EmcCfg = 0x0301ff00;
+SDRAM[2].EmcCfg2 = 0x00000405;
+SDRAM[2].EmcDbg = 0x01000400;
+SDRAM[2].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[2].EmcCfgDigDll = 0xf0000313;
+SDRAM[2].EmcDllXformDqs = 0x00000010;
+SDRAM[2].EmcDllXformQUse = 0x00000008;
+SDRAM[2].WarmBootWait = 0x00000002;
+SDRAM[2].EmcCttTermCtrl = 0x00000802;
+SDRAM[2].EmcOdtWrite = 0x00000000;
+SDRAM[2].EmcOdtRead = 0x00000000;
+SDRAM[2].EmcZcalRefCnt = 0x00000000;
+SDRAM[2].EmcZcalWaitCnt = 0x00000000;
+SDRAM[2].EmcZcalMrwCmd = 0x00000000;
+SDRAM[2].EmcMrsResetDll = 0x00000000;
+SDRAM[2].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[2].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[2].EmcMrwZqInitWait = 0x00000000;
+SDRAM[2].EmcMrsResetDllWait = 0x00000000;
+SDRAM[2].EmcEmrsEmr2 = 0x00200000;
+SDRAM[2].EmcEmrsEmr3 = 0x00300000;
+SDRAM[2].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[2].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[2].EmcDdr2Wait = 0x00000002;
+SDRAM[2].EmcCfgClktrim0 = 0x00000000;
+SDRAM[2].EmcCfgClktrim1 = 0x00000000;
+SDRAM[2].EmcCfgClktrim2 = 0x00000000;
+SDRAM[2].PmcDdrPwr = 0x00000001;
+SDRAM[2].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[2].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[2].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[2].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[2].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[2].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[2].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[2].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[3].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[3].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[3].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[3].PllMInputDivider = 0x0000000d;
+SDRAM[3].PllMFeedbackDivider = 0x0000029a;
+SDRAM[3].PllMPostDivider = 0x00000000;
+SDRAM[3].PllMStableTime = 0x0000012c;
+SDRAM[3].EmcClockDivider = 0x00000001;
+SDRAM[3].EmcAutoCalInterval = 0x00000000;
+SDRAM[3].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[3].EmcAutoCalWait = 0x00000000;
+SDRAM[3].EmcPinProgramWait = 0x00000000;
+SDRAM[3].EmcRc = 0x00000014;
+SDRAM[3].EmcRfc = 0x0000002b;
+SDRAM[3].EmcRas = 0x0000000f;
+SDRAM[3].EmcRp = 0x00000005;
+SDRAM[3].EmcR2w = 0x00000004;
+SDRAM[3].EmcW2r = 0x00000005;
+SDRAM[3].EmcR2p = 0x00000003;
+SDRAM[3].EmcW2p = 0x0000000a;
+SDRAM[3].EmcRdRcd = 0x00000005;
+SDRAM[3].EmcWrRcd = 0x00000005;
+SDRAM[3].EmcRrd = 0x00000004;
+SDRAM[3].EmcRext = 0x00000001;
+SDRAM[3].EmcWdv = 0x00000003;
+SDRAM[3].EmcQUse = 0x00000004;
+SDRAM[3].EmcQRst = 0x00000003;
+SDRAM[3].EmcQSafe = 0x00000009;
+SDRAM[3].EmcRdv = 0x0000000c;
+SDRAM[3].EmcRefresh = 0x000009ff;
+SDRAM[3].EmcBurstRefreshNum = 0x00000000;
+SDRAM[3].EmcPdEx2Wr = 0x00000003;
+SDRAM[3].EmcPdEx2Rd = 0x00000003;
+SDRAM[3].EmcPChg2Pden = 0x00000005;
+SDRAM[3].EmcAct2Pden = 0x00000005;
+SDRAM[3].EmcAr2Pden = 0x00000001;
+SDRAM[3].EmcRw2Pden = 0x0000000e;
+SDRAM[3].EmcTxsr = 0x000000c8;
+SDRAM[3].EmcTcke = 0x00000003;
+SDRAM[3].EmcTfaw = 0x00000011;
+SDRAM[3].EmcTrpab = 0x00000006;
+SDRAM[3].EmcTClkStable = 0x00000006;
+SDRAM[3].EmcTClkStop = 0x00000002;
+SDRAM[3].EmcTRefBw = 0x00000000;
+SDRAM[3].EmcQUseExtra = 0x00000000;
+SDRAM[3].EmcFbioCfg1 = 0x00000000;
+SDRAM[3].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[3].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[3].EmcFbioQuseDly = 0x74747474;
+SDRAM[3].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[3].EmcFbioCfg5 = 0x00000083;
+SDRAM[3].EmcFbioCfg6 = 0x00000002;
+SDRAM[3].EmcFbioSpare = 0x00000000;
+SDRAM[3].EmcMrs = 0x0000085a;
+SDRAM[3].EmcEmrs = 0x00100002;
+SDRAM[3].EmcMrw1 = 0x00000000;
+SDRAM[3].EmcMrw2 = 0x00000000;
+SDRAM[3].EmcMrw3 = 0x00000000;
+SDRAM[3].EmcMrwResetCommand = 0x00000000;
+SDRAM[3].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[3].EmcAdrCfg = 0x00060303;
+SDRAM[3].EmcAdrCfg1 = 0x00060303;
+SDRAM[3].McEmemCfg = 0x00040000;
+SDRAM[3].McLowLatencyConfig = 0x80000003;
+SDRAM[3].EmcCfg = 0x0301ff00;
+SDRAM[3].EmcCfg2 = 0x00000405;
+SDRAM[3].EmcDbg = 0x01000400;
+SDRAM[3].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[3].EmcCfgDigDll = 0xf0000313;
+SDRAM[3].EmcDllXformDqs = 0x00000010;
+SDRAM[3].EmcDllXformQUse = 0x00000008;
+SDRAM[3].WarmBootWait = 0x00000002;
+SDRAM[3].EmcCttTermCtrl = 0x00000802;
+SDRAM[3].EmcOdtWrite = 0x00000000;
+SDRAM[3].EmcOdtRead = 0x00000000;
+SDRAM[3].EmcZcalRefCnt = 0x00000000;
+SDRAM[3].EmcZcalWaitCnt = 0x00000000;
+SDRAM[3].EmcZcalMrwCmd = 0x00000000;
+SDRAM[3].EmcMrsResetDll = 0x00000000;
+SDRAM[3].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[3].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[3].EmcMrwZqInitWait = 0x00000000;
+SDRAM[3].EmcMrsResetDllWait = 0x00000000;
+SDRAM[3].EmcEmrsEmr2 = 0x00200000;
+SDRAM[3].EmcEmrsEmr3 = 0x00300000;
+SDRAM[3].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[3].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[3].EmcDdr2Wait = 0x00000002;
+SDRAM[3].EmcCfgClktrim0 = 0x00000000;
+SDRAM[3].EmcCfgClktrim1 = 0x00000000;
+SDRAM[3].EmcCfgClktrim2 = 0x00000000;
+SDRAM[3].PmcDdrPwr = 0x00000001;
+SDRAM[3].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[3].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[3].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[3].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[3].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[3].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[3].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[3].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
diff --git a/arch/arm/boards/toradex-colibri-t20/colibri-t20_512_hsmmc.bct.cfg b/arch/arm/boards/toradex-colibri-t20/colibri-t20_512_hsmmc.bct.cfg
new file mode 100644
index 0000000000..3bbce031cd
--- /dev/null
+++ b/arch/arm/boards/toradex-colibri-t20/colibri-t20_512_hsmmc.bct.cfg
@@ -0,0 +1,451 @@
+# Copyright (c) 2013, Toradex AG. All rights reserved.
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+# claim that you wrote the original software. If you use this software
+# in a product, an acknowledgment in the product documentation would be
+# appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+# misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+Version = 0x00020001;
+PartitionSize = 16777216;
+BlockSize = 16384;
+PageSize = 512;
+OdmData = 0x200C0000;
+
+DevType[0] = Sdmmc;
+DeviceParam[0].SdmmcParams.ClockDivider = 12; # 432/24 = 18MHz.
+DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit;
+DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0;
+
+DevType[1] = Sdmmc;
+DeviceParam[1].SdmmcParams.ClockDivider = 12; # 432/24 = 18MHz.
+DeviceParam[1].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit;
+DeviceParam[1].SdmmcParams.MaxPowerClassSupported = 0;
+
+DevType[2] = Sdmmc;
+DeviceParam[2].SdmmcParams.ClockDivider = 12; # 432/24 = 18MHz.
+DeviceParam[2].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit;
+DeviceParam[2].SdmmcParams.MaxPowerClassSupported = 0;
+
+DevType[3] = Sdmmc;
+DeviceParam[3].SdmmcParams.ClockDivider = 12; # 432/24 = 18MHz.
+DeviceParam[3].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_4Bit;
+DeviceParam[3].SdmmcParams.MaxPowerClassSupported = 0;
+
+SDRAM[0].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[0].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[0].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[0].PllMInputDivider = 0x0000000d;
+SDRAM[0].PllMFeedbackDivider = 0x0000029a;
+SDRAM[0].PllMPostDivider = 0x00000000;
+SDRAM[0].PllMStableTime = 0x0000012c;
+SDRAM[0].EmcClockDivider = 0x00000001;
+SDRAM[0].EmcAutoCalInterval = 0x00000000;
+SDRAM[0].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[0].EmcAutoCalWait = 0x00000000;
+SDRAM[0].EmcPinProgramWait = 0x00000000;
+SDRAM[0].EmcRc = 0x00000014;
+SDRAM[0].EmcRfc = 0x00000041;
+SDRAM[0].EmcRas = 0x0000000f;
+SDRAM[0].EmcRp = 0x00000005;
+SDRAM[0].EmcR2w = 0x00000004;
+SDRAM[0].EmcW2r = 0x00000005;
+SDRAM[0].EmcR2p = 0x00000003;
+SDRAM[0].EmcW2p = 0x0000000a;
+SDRAM[0].EmcRdRcd = 0x00000005;
+SDRAM[0].EmcWrRcd = 0x00000005;
+SDRAM[0].EmcRrd = 0x00000004;
+SDRAM[0].EmcRext = 0x00000001;
+SDRAM[0].EmcWdv = 0x00000003;
+SDRAM[0].EmcQUse = 0x00000004;
+SDRAM[0].EmcQRst = 0x00000003;
+SDRAM[0].EmcQSafe = 0x00000009;
+SDRAM[0].EmcRdv = 0x0000000c;
+SDRAM[0].EmcRefresh = 0x000009ff;
+SDRAM[0].EmcBurstRefreshNum = 0x00000000;
+SDRAM[0].EmcPdEx2Wr = 0x00000003;
+SDRAM[0].EmcPdEx2Rd = 0x00000003;
+SDRAM[0].EmcPChg2Pden = 0x00000005;
+SDRAM[0].EmcAct2Pden = 0x00000005;
+SDRAM[0].EmcAr2Pden = 0x00000001;
+SDRAM[0].EmcRw2Pden = 0x0000000e;
+SDRAM[0].EmcTxsr = 0x000000c8;
+SDRAM[0].EmcTcke = 0x00000003;
+SDRAM[0].EmcTfaw = 0x00000011;
+SDRAM[0].EmcTrpab = 0x00000006;
+SDRAM[0].EmcTClkStable = 0x0000000c;
+SDRAM[0].EmcTClkStop = 0x00000002;
+SDRAM[0].EmcTRefBw = 0x00000000;
+SDRAM[0].EmcQUseExtra = 0x00000000;
+SDRAM[0].EmcFbioCfg1 = 0x00000000;
+SDRAM[0].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[0].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[0].EmcFbioQuseDly = 0x74747474;
+SDRAM[0].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[0].EmcFbioCfg5 = 0x00000083;
+SDRAM[0].EmcFbioCfg6 = 0x00000002;
+SDRAM[0].EmcFbioSpare = 0x00000000;
+SDRAM[0].EmcMrs = 0x0000085a;
+SDRAM[0].EmcEmrs = 0x00100002;
+SDRAM[0].EmcMrw1 = 0x00000000;
+SDRAM[0].EmcMrw2 = 0x00000000;
+SDRAM[0].EmcMrw3 = 0x00000000;
+SDRAM[0].EmcMrwResetCommand = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[0].EmcAdrCfg = 0x00070303;
+SDRAM[0].EmcAdrCfg1 = 0x00070303;
+SDRAM[0].McEmemCfg = 0x00080000;
+SDRAM[0].McLowLatencyConfig = 0x80000003;
+SDRAM[0].EmcCfg = 0x0301ff00;
+SDRAM[0].EmcCfg2 = 0x00000405;
+SDRAM[0].EmcDbg = 0x01000400;
+SDRAM[0].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[0].EmcCfgDigDll = 0xf0000313;
+SDRAM[0].EmcDllXformDqs = 0x00000010;
+SDRAM[0].EmcDllXformQUse = 0x00000008;
+SDRAM[0].WarmBootWait = 0x00000002;
+SDRAM[0].EmcCttTermCtrl = 0x00000802;
+SDRAM[0].EmcOdtWrite = 0x00000000;
+SDRAM[0].EmcOdtRead = 0x00000000;
+SDRAM[0].EmcZcalRefCnt = 0x00000000;
+SDRAM[0].EmcZcalWaitCnt = 0x00000000;
+SDRAM[0].EmcZcalMrwCmd = 0x00000000;
+SDRAM[0].EmcMrsResetDll = 0x00000000;
+SDRAM[0].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[0].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[0].EmcMrwZqInitWait = 0x00000000;
+SDRAM[0].EmcMrsResetDllWait = 0x00000000;
+SDRAM[0].EmcEmrsEmr2 = 0x00200000;
+SDRAM[0].EmcEmrsEmr3 = 0x00300000;
+SDRAM[0].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[0].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[0].EmcDdr2Wait = 0x00000002;
+SDRAM[0].EmcCfgClktrim0 = 0x00000000;
+SDRAM[0].EmcCfgClktrim1 = 0x00000000;
+SDRAM[0].EmcCfgClktrim2 = 0x00000000;
+SDRAM[0].PmcDdrPwr = 0x00000001;
+SDRAM[0].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[0].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[0].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[0].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[0].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[1].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[1].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[1].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[1].PllMInputDivider = 0x0000000d;
+SDRAM[1].PllMFeedbackDivider = 0x0000029a;
+SDRAM[1].PllMPostDivider = 0x00000000;
+SDRAM[1].PllMStableTime = 0x0000012c;
+SDRAM[1].EmcClockDivider = 0x00000001;
+SDRAM[1].EmcAutoCalInterval = 0x00000000;
+SDRAM[1].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[1].EmcAutoCalWait = 0x00000000;
+SDRAM[1].EmcPinProgramWait = 0x00000000;
+SDRAM[1].EmcRc = 0x00000014;
+SDRAM[1].EmcRfc = 0x00000041;
+SDRAM[1].EmcRas = 0x0000000f;
+SDRAM[1].EmcRp = 0x00000005;
+SDRAM[1].EmcR2w = 0x00000004;
+SDRAM[1].EmcW2r = 0x00000005;
+SDRAM[1].EmcR2p = 0x00000003;
+SDRAM[1].EmcW2p = 0x0000000a;
+SDRAM[1].EmcRdRcd = 0x00000005;
+SDRAM[1].EmcWrRcd = 0x00000005;
+SDRAM[1].EmcRrd = 0x00000004;
+SDRAM[1].EmcRext = 0x00000001;
+SDRAM[1].EmcWdv = 0x00000003;
+SDRAM[1].EmcQUse = 0x00000004;
+SDRAM[1].EmcQRst = 0x00000003;
+SDRAM[1].EmcQSafe = 0x00000009;
+SDRAM[1].EmcRdv = 0x0000000c;
+SDRAM[1].EmcRefresh = 0x000009ff;
+SDRAM[1].EmcBurstRefreshNum = 0x00000000;
+SDRAM[1].EmcPdEx2Wr = 0x00000003;
+SDRAM[1].EmcPdEx2Rd = 0x00000003;
+SDRAM[1].EmcPChg2Pden = 0x00000005;
+SDRAM[1].EmcAct2Pden = 0x00000005;
+SDRAM[1].EmcAr2Pden = 0x00000001;
+SDRAM[1].EmcRw2Pden = 0x0000000e;
+SDRAM[1].EmcTxsr = 0x000000c8;
+SDRAM[1].EmcTcke = 0x00000003;
+SDRAM[1].EmcTfaw = 0x00000011;
+SDRAM[1].EmcTrpab = 0x00000006;
+SDRAM[1].EmcTClkStable = 0x0000000c;
+SDRAM[1].EmcTClkStop = 0x00000002;
+SDRAM[1].EmcTRefBw = 0x00000000;
+SDRAM[1].EmcQUseExtra = 0x00000000;
+SDRAM[1].EmcFbioCfg1 = 0x00000000;
+SDRAM[1].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[1].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[1].EmcFbioQuseDly = 0x74747474;
+SDRAM[1].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[1].EmcFbioCfg5 = 0x00000083;
+SDRAM[1].EmcFbioCfg6 = 0x00000002;
+SDRAM[1].EmcFbioSpare = 0x00000000;
+SDRAM[1].EmcMrs = 0x0000085a;
+SDRAM[1].EmcEmrs = 0x00100002;
+SDRAM[1].EmcMrw1 = 0x00000000;
+SDRAM[1].EmcMrw2 = 0x00000000;
+SDRAM[1].EmcMrw3 = 0x00000000;
+SDRAM[1].EmcMrwResetCommand = 0x00000000;
+SDRAM[1].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[1].EmcAdrCfg = 0x00070303;
+SDRAM[1].EmcAdrCfg1 = 0x00070303;
+SDRAM[1].McEmemCfg = 0x00080000;
+SDRAM[1].McLowLatencyConfig = 0x80000003;
+SDRAM[1].EmcCfg = 0x0301ff00;
+SDRAM[1].EmcCfg2 = 0x00000405;
+SDRAM[1].EmcDbg = 0x01000400;
+SDRAM[1].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[1].EmcCfgDigDll = 0xf0000313;
+SDRAM[1].EmcDllXformDqs = 0x00000010;
+SDRAM[1].EmcDllXformQUse = 0x00000008;
+SDRAM[1].WarmBootWait = 0x00000002;
+SDRAM[1].EmcCttTermCtrl = 0x00000802;
+SDRAM[1].EmcOdtWrite = 0x00000000;
+SDRAM[1].EmcOdtRead = 0x00000000;
+SDRAM[1].EmcZcalRefCnt = 0x00000000;
+SDRAM[1].EmcZcalWaitCnt = 0x00000000;
+SDRAM[1].EmcZcalMrwCmd = 0x00000000;
+SDRAM[1].EmcMrsResetDll = 0x00000000;
+SDRAM[1].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[1].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[1].EmcMrwZqInitWait = 0x00000000;
+SDRAM[1].EmcMrsResetDllWait = 0x00000000;
+SDRAM[1].EmcEmrsEmr2 = 0x00200000;
+SDRAM[1].EmcEmrsEmr3 = 0x00300000;
+SDRAM[1].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[1].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[1].EmcDdr2Wait = 0x00000002;
+SDRAM[1].EmcCfgClktrim0 = 0x00000000;
+SDRAM[1].EmcCfgClktrim1 = 0x00000000;
+SDRAM[1].EmcCfgClktrim2 = 0x00000000;
+SDRAM[1].PmcDdrPwr = 0x00000001;
+SDRAM[1].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[1].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[1].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[1].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[1].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[1].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[1].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[1].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[2].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[2].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[2].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[2].PllMInputDivider = 0x0000000d;
+SDRAM[2].PllMFeedbackDivider = 0x0000029a;
+SDRAM[2].PllMPostDivider = 0x00000000;
+SDRAM[2].PllMStableTime = 0x0000012c;
+SDRAM[2].EmcClockDivider = 0x00000001;
+SDRAM[2].EmcAutoCalInterval = 0x00000000;
+SDRAM[2].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[2].EmcAutoCalWait = 0x00000000;
+SDRAM[2].EmcPinProgramWait = 0x00000000;
+SDRAM[2].EmcRc = 0x00000014;
+SDRAM[2].EmcRfc = 0x00000041;
+SDRAM[2].EmcRas = 0x0000000f;
+SDRAM[2].EmcRp = 0x00000005;
+SDRAM[2].EmcR2w = 0x00000004;
+SDRAM[2].EmcW2r = 0x00000005;
+SDRAM[2].EmcR2p = 0x00000003;
+SDRAM[2].EmcW2p = 0x0000000a;
+SDRAM[2].EmcRdRcd = 0x00000005;
+SDRAM[2].EmcWrRcd = 0x00000005;
+SDRAM[2].EmcRrd = 0x00000004;
+SDRAM[2].EmcRext = 0x00000001;
+SDRAM[2].EmcWdv = 0x00000003;
+SDRAM[2].EmcQUse = 0x00000004;
+SDRAM[2].EmcQRst = 0x00000003;
+SDRAM[2].EmcQSafe = 0x00000009;
+SDRAM[2].EmcRdv = 0x0000000c;
+SDRAM[2].EmcRefresh = 0x000009ff;
+SDRAM[2].EmcBurstRefreshNum = 0x00000000;
+SDRAM[2].EmcPdEx2Wr = 0x00000003;
+SDRAM[2].EmcPdEx2Rd = 0x00000003;
+SDRAM[2].EmcPChg2Pden = 0x00000005;
+SDRAM[2].EmcAct2Pden = 0x00000005;
+SDRAM[2].EmcAr2Pden = 0x00000001;
+SDRAM[2].EmcRw2Pden = 0x0000000e;
+SDRAM[2].EmcTxsr = 0x000000c8;
+SDRAM[2].EmcTcke = 0x00000003;
+SDRAM[2].EmcTfaw = 0x00000011;
+SDRAM[2].EmcTrpab = 0x00000006;
+SDRAM[2].EmcTClkStable = 0x0000000c;
+SDRAM[2].EmcTClkStop = 0x00000002;
+SDRAM[2].EmcTRefBw = 0x00000000;
+SDRAM[2].EmcQUseExtra = 0x00000000;
+SDRAM[2].EmcFbioCfg1 = 0x00000000;
+SDRAM[2].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[2].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[2].EmcFbioQuseDly = 0x74747474;
+SDRAM[2].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[2].EmcFbioCfg5 = 0x00000083;
+SDRAM[2].EmcFbioCfg6 = 0x00000002;
+SDRAM[2].EmcFbioSpare = 0x00000000;
+SDRAM[2].EmcMrs = 0x0000085a;
+SDRAM[2].EmcEmrs = 0x00100002;
+SDRAM[2].EmcMrw1 = 0x00000000;
+SDRAM[2].EmcMrw2 = 0x00000000;
+SDRAM[2].EmcMrw3 = 0x00000000;
+SDRAM[2].EmcMrwResetCommand = 0x00000000;
+SDRAM[2].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[2].EmcAdrCfg = 0x00070303;
+SDRAM[2].EmcAdrCfg1 = 0x00070303;
+SDRAM[2].McEmemCfg = 0x00080000;
+SDRAM[2].McLowLatencyConfig = 0x80000003;
+SDRAM[2].EmcCfg = 0x0301ff00;
+SDRAM[2].EmcCfg2 = 0x00000405;
+SDRAM[2].EmcDbg = 0x01000400;
+SDRAM[2].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[2].EmcCfgDigDll = 0xf0000313;
+SDRAM[2].EmcDllXformDqs = 0x00000010;
+SDRAM[2].EmcDllXformQUse = 0x00000008;
+SDRAM[2].WarmBootWait = 0x00000002;
+SDRAM[2].EmcCttTermCtrl = 0x00000802;
+SDRAM[2].EmcOdtWrite = 0x00000000;
+SDRAM[2].EmcOdtRead = 0x00000000;
+SDRAM[2].EmcZcalRefCnt = 0x00000000;
+SDRAM[2].EmcZcalWaitCnt = 0x00000000;
+SDRAM[2].EmcZcalMrwCmd = 0x00000000;
+SDRAM[2].EmcMrsResetDll = 0x00000000;
+SDRAM[2].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[2].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[2].EmcMrwZqInitWait = 0x00000000;
+SDRAM[2].EmcMrsResetDllWait = 0x00000000;
+SDRAM[2].EmcEmrsEmr2 = 0x00200000;
+SDRAM[2].EmcEmrsEmr3 = 0x00300000;
+SDRAM[2].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[2].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[2].EmcDdr2Wait = 0x00000002;
+SDRAM[2].EmcCfgClktrim0 = 0x00000000;
+SDRAM[2].EmcCfgClktrim1 = 0x00000000;
+SDRAM[2].EmcCfgClktrim2 = 0x00000000;
+SDRAM[2].PmcDdrPwr = 0x00000001;
+SDRAM[2].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[2].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[2].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[2].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[2].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[2].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[2].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[2].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[3].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[3].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[3].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[3].PllMInputDivider = 0x0000000d;
+SDRAM[3].PllMFeedbackDivider = 0x0000029a;
+SDRAM[3].PllMPostDivider = 0x00000000;
+SDRAM[3].PllMStableTime = 0x0000012c;
+SDRAM[3].EmcClockDivider = 0x00000001;
+SDRAM[3].EmcAutoCalInterval = 0x00000000;
+SDRAM[3].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[3].EmcAutoCalWait = 0x00000000;
+SDRAM[3].EmcPinProgramWait = 0x00000000;
+SDRAM[3].EmcRc = 0x00000014;
+SDRAM[3].EmcRfc = 0x00000041;
+SDRAM[3].EmcRas = 0x0000000f;
+SDRAM[3].EmcRp = 0x00000005;
+SDRAM[3].EmcR2w = 0x00000004;
+SDRAM[3].EmcW2r = 0x00000005;
+SDRAM[3].EmcR2p = 0x00000003;
+SDRAM[3].EmcW2p = 0x0000000a;
+SDRAM[3].EmcRdRcd = 0x00000005;
+SDRAM[3].EmcWrRcd = 0x00000005;
+SDRAM[3].EmcRrd = 0x00000004;
+SDRAM[3].EmcRext = 0x00000001;
+SDRAM[3].EmcWdv = 0x00000003;
+SDRAM[3].EmcQUse = 0x00000004;
+SDRAM[3].EmcQRst = 0x00000003;
+SDRAM[3].EmcQSafe = 0x00000009;
+SDRAM[3].EmcRdv = 0x0000000c;
+SDRAM[3].EmcRefresh = 0x000009ff;
+SDRAM[3].EmcBurstRefreshNum = 0x00000000;
+SDRAM[3].EmcPdEx2Wr = 0x00000003;
+SDRAM[3].EmcPdEx2Rd = 0x00000003;
+SDRAM[3].EmcPChg2Pden = 0x00000005;
+SDRAM[3].EmcAct2Pden = 0x00000005;
+SDRAM[3].EmcAr2Pden = 0x00000001;
+SDRAM[3].EmcRw2Pden = 0x0000000e;
+SDRAM[3].EmcTxsr = 0x000000c8;
+SDRAM[3].EmcTcke = 0x00000003;
+SDRAM[3].EmcTfaw = 0x00000011;
+SDRAM[3].EmcTrpab = 0x00000006;
+SDRAM[3].EmcTClkStable = 0x0000000c;
+SDRAM[3].EmcTClkStop = 0x00000002;
+SDRAM[3].EmcTRefBw = 0x00000000;
+SDRAM[3].EmcQUseExtra = 0x00000000;
+SDRAM[3].EmcFbioCfg1 = 0x00000000;
+SDRAM[3].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[3].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[3].EmcFbioQuseDly = 0x74747474;
+SDRAM[3].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[3].EmcFbioCfg5 = 0x00000083;
+SDRAM[3].EmcFbioCfg6 = 0x00000002;
+SDRAM[3].EmcFbioSpare = 0x00000000;
+SDRAM[3].EmcMrs = 0x0000085a;
+SDRAM[3].EmcEmrs = 0x00100002;
+SDRAM[3].EmcMrw1 = 0x00000000;
+SDRAM[3].EmcMrw2 = 0x00000000;
+SDRAM[3].EmcMrw3 = 0x00000000;
+SDRAM[3].EmcMrwResetCommand = 0x00000000;
+SDRAM[3].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[3].EmcAdrCfg = 0x00070303;
+SDRAM[3].EmcAdrCfg1 = 0x00070303;
+SDRAM[3].McEmemCfg = 0x00080000;
+SDRAM[3].McLowLatencyConfig = 0x80000003;
+SDRAM[3].EmcCfg = 0x0301ff00;
+SDRAM[3].EmcCfg2 = 0x00000405;
+SDRAM[3].EmcDbg = 0x01000400;
+SDRAM[3].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[3].EmcCfgDigDll = 0xf0000313;
+SDRAM[3].EmcDllXformDqs = 0x00000010;
+SDRAM[3].EmcDllXformQUse = 0x00000008;
+SDRAM[3].WarmBootWait = 0x00000002;
+SDRAM[3].EmcCttTermCtrl = 0x00000802;
+SDRAM[3].EmcOdtWrite = 0x00000000;
+SDRAM[3].EmcOdtRead = 0x00000000;
+SDRAM[3].EmcZcalRefCnt = 0x00000000;
+SDRAM[3].EmcZcalWaitCnt = 0x00000000;
+SDRAM[3].EmcZcalMrwCmd = 0x00000000;
+SDRAM[3].EmcMrsResetDll = 0x00000000;
+SDRAM[3].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[3].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[3].EmcMrwZqInitWait = 0x00000000;
+SDRAM[3].EmcMrsResetDllWait = 0x00000000;
+SDRAM[3].EmcEmrsEmr2 = 0x00200000;
+SDRAM[3].EmcEmrsEmr3 = 0x00300000;
+SDRAM[3].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[3].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[3].EmcDdr2Wait = 0x00000002;
+SDRAM[3].EmcCfgClktrim0 = 0x00000000;
+SDRAM[3].EmcCfgClktrim1 = 0x00000000;
+SDRAM[3].EmcCfgClktrim2 = 0x00000000;
+SDRAM[3].PmcDdrPwr = 0x00000001;
+SDRAM[3].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[3].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[3].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[3].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[3].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[3].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[3].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[3].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
diff --git a/arch/arm/boards/toradex-colibri-t20/colibri-t20_512_v11_nand.bct.cfg b/arch/arm/boards/toradex-colibri-t20/colibri-t20_512_v11_nand.bct.cfg
new file mode 100644
index 0000000000..a8d0e58bac
--- /dev/null
+++ b/arch/arm/boards/toradex-colibri-t20/colibri-t20_512_v11_nand.bct.cfg
@@ -0,0 +1,459 @@
+# Copyright (c) 2013, Toradex AG. All rights reserved.
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+# claim that you wrote the original software. If you use this software
+# in a product, an acknowledgment in the product documentation would be
+# appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+# misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+Version = 0x00020001;
+PartitionSize = 8388608;
+BlockSize = 524288;
+PageSize = 4096;
+OdmData = 0x200C0000;
+
+DevType[0] = Nand;
+DeviceParam[0].NandParams.ClockDivider = 0x4; # Clock source of 108MHz
+DeviceParam[0].NandParams.NandTiming2 = 0xA; # For 108MHz clock
+DeviceParam[0].NandParams.NandTiming = 0x3B269213; # For 108MHz clock
+DeviceParam[0].NandParams.BlockSizeLog2 = 0;
+DeviceParam[0].NandParams.PageSizeLog2 = 0;
+
+DevType[1] = Nand;
+DeviceParam[1].NandParams.ClockDivider = 0x4; # Clock source of 108MHz
+DeviceParam[1].NandParams.NandTiming2 = 0xA; # For 108MHz clock
+DeviceParam[1].NandParams.NandTiming = 0x3B269213; # For 108MHz clock
+DeviceParam[1].NandParams.BlockSizeLog2 = 0;
+DeviceParam[1].NandParams.PageSizeLog2 = 0;
+
+DevType[2] = Nand;
+DeviceParam[2].NandParams.ClockDivider = 0x4; # Clock source of 108MHz
+DeviceParam[2].NandParams.NandTiming2 = 0xA; # For 108MHz clock
+DeviceParam[2].NandParams.NandTiming = 0x3B269213; # For 108MHz clock
+DeviceParam[2].NandParams.BlockSizeLog2 = 0;
+DeviceParam[2].NandParams.PageSizeLog2 = 0;
+
+DevType[3] = Nand;
+DeviceParam[3].NandParams.ClockDivider = 0x4; # Clock source of 108MHz
+DeviceParam[3].NandParams.NandTiming2 = 0xA; # For 108MHz clock
+DeviceParam[3].NandParams.NandTiming = 0x3B269213; # For 108MHz clock
+DeviceParam[3].NandParams.BlockSizeLog2 = 0;
+DeviceParam[3].NandParams.PageSizeLog2 = 0;
+
+SDRAM[0].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[0].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[0].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[0].PllMInputDivider = 0x0000000d;
+SDRAM[0].PllMFeedbackDivider = 0x0000029a;
+SDRAM[0].PllMPostDivider = 0x00000000;
+SDRAM[0].PllMStableTime = 0x0000012c;
+SDRAM[0].EmcClockDivider = 0x00000001;
+SDRAM[0].EmcAutoCalInterval = 0x00000000;
+SDRAM[0].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[0].EmcAutoCalWait = 0x00000000;
+SDRAM[0].EmcPinProgramWait = 0x00000000;
+SDRAM[0].EmcRc = 0x00000014;
+SDRAM[0].EmcRfc = 0x00000041;
+SDRAM[0].EmcRas = 0x0000000f;
+SDRAM[0].EmcRp = 0x00000005;
+SDRAM[0].EmcR2w = 0x00000004;
+SDRAM[0].EmcW2r = 0x00000005;
+SDRAM[0].EmcR2p = 0x00000003;
+SDRAM[0].EmcW2p = 0x0000000a;
+SDRAM[0].EmcRdRcd = 0x00000005;
+SDRAM[0].EmcWrRcd = 0x00000005;
+SDRAM[0].EmcRrd = 0x00000004;
+SDRAM[0].EmcRext = 0x00000001;
+SDRAM[0].EmcWdv = 0x00000003;
+SDRAM[0].EmcQUse = 0x00000004;
+SDRAM[0].EmcQRst = 0x00000003;
+SDRAM[0].EmcQSafe = 0x00000009;
+SDRAM[0].EmcRdv = 0x0000000c;
+SDRAM[0].EmcRefresh = 0x000009ff;
+SDRAM[0].EmcBurstRefreshNum = 0x00000000;
+SDRAM[0].EmcPdEx2Wr = 0x00000003;
+SDRAM[0].EmcPdEx2Rd = 0x00000003;
+SDRAM[0].EmcPChg2Pden = 0x00000005;
+SDRAM[0].EmcAct2Pden = 0x00000005;
+SDRAM[0].EmcAr2Pden = 0x00000001;
+SDRAM[0].EmcRw2Pden = 0x0000000e;
+SDRAM[0].EmcTxsr = 0x000000c8;
+SDRAM[0].EmcTcke = 0x00000003;
+SDRAM[0].EmcTfaw = 0x00000011;
+SDRAM[0].EmcTrpab = 0x00000006;
+SDRAM[0].EmcTClkStable = 0x0000000c;
+SDRAM[0].EmcTClkStop = 0x00000002;
+SDRAM[0].EmcTRefBw = 0x00000000;
+SDRAM[0].EmcQUseExtra = 0x00000000;
+SDRAM[0].EmcFbioCfg1 = 0x00000000;
+SDRAM[0].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[0].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[0].EmcFbioQuseDly = 0x74747474;
+SDRAM[0].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[0].EmcFbioCfg5 = 0x00000083;
+SDRAM[0].EmcFbioCfg6 = 0x00000002;
+SDRAM[0].EmcFbioSpare = 0x00000000;
+SDRAM[0].EmcMrs = 0x0000085a;
+SDRAM[0].EmcEmrs = 0x00100002;
+SDRAM[0].EmcMrw1 = 0x00000000;
+SDRAM[0].EmcMrw2 = 0x00000000;
+SDRAM[0].EmcMrw3 = 0x00000000;
+SDRAM[0].EmcMrwResetCommand = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[0].EmcAdrCfg = 0x00070303;
+SDRAM[0].EmcAdrCfg1 = 0x00070303;
+SDRAM[0].McEmemCfg = 0x00080000;
+SDRAM[0].McLowLatencyConfig = 0x80000003;
+SDRAM[0].EmcCfg = 0x0301ff00;
+SDRAM[0].EmcCfg2 = 0x00000405;
+SDRAM[0].EmcDbg = 0x01000400;
+SDRAM[0].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[0].EmcCfgDigDll = 0xf0000313;
+SDRAM[0].EmcDllXformDqs = 0x00000010;
+SDRAM[0].EmcDllXformQUse = 0x00000008;
+SDRAM[0].WarmBootWait = 0x00000002;
+SDRAM[0].EmcCttTermCtrl = 0x00000802;
+SDRAM[0].EmcOdtWrite = 0x00000000;
+SDRAM[0].EmcOdtRead = 0x00000000;
+SDRAM[0].EmcZcalRefCnt = 0x00000000;
+SDRAM[0].EmcZcalWaitCnt = 0x00000000;
+SDRAM[0].EmcZcalMrwCmd = 0x00000000;
+SDRAM[0].EmcMrsResetDll = 0x00000000;
+SDRAM[0].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[0].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[0].EmcMrwZqInitWait = 0x00000000;
+SDRAM[0].EmcMrsResetDllWait = 0x00000000;
+SDRAM[0].EmcEmrsEmr2 = 0x00200000;
+SDRAM[0].EmcEmrsEmr3 = 0x00300000;
+SDRAM[0].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[0].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[0].EmcDdr2Wait = 0x00000002;
+SDRAM[0].EmcCfgClktrim0 = 0x00000000;
+SDRAM[0].EmcCfgClktrim1 = 0x00000000;
+SDRAM[0].EmcCfgClktrim2 = 0x00000000;
+SDRAM[0].PmcDdrPwr = 0x00000001;
+SDRAM[0].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[0].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[0].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[0].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[0].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[1].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[1].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[1].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[1].PllMInputDivider = 0x0000000d;
+SDRAM[1].PllMFeedbackDivider = 0x0000029a;
+SDRAM[1].PllMPostDivider = 0x00000000;
+SDRAM[1].PllMStableTime = 0x0000012c;
+SDRAM[1].EmcClockDivider = 0x00000001;
+SDRAM[1].EmcAutoCalInterval = 0x00000000;
+SDRAM[1].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[1].EmcAutoCalWait = 0x00000000;
+SDRAM[1].EmcPinProgramWait = 0x00000000;
+SDRAM[1].EmcRc = 0x00000014;
+SDRAM[1].EmcRfc = 0x00000041;
+SDRAM[1].EmcRas = 0x0000000f;
+SDRAM[1].EmcRp = 0x00000005;
+SDRAM[1].EmcR2w = 0x00000004;
+SDRAM[1].EmcW2r = 0x00000005;
+SDRAM[1].EmcR2p = 0x00000003;
+SDRAM[1].EmcW2p = 0x0000000a;
+SDRAM[1].EmcRdRcd = 0x00000005;
+SDRAM[1].EmcWrRcd = 0x00000005;
+SDRAM[1].EmcRrd = 0x00000004;
+SDRAM[1].EmcRext = 0x00000001;
+SDRAM[1].EmcWdv = 0x00000003;
+SDRAM[1].EmcQUse = 0x00000004;
+SDRAM[1].EmcQRst = 0x00000003;
+SDRAM[1].EmcQSafe = 0x00000009;
+SDRAM[1].EmcRdv = 0x0000000c;
+SDRAM[1].EmcRefresh = 0x000009ff;
+SDRAM[1].EmcBurstRefreshNum = 0x00000000;
+SDRAM[1].EmcPdEx2Wr = 0x00000003;
+SDRAM[1].EmcPdEx2Rd = 0x00000003;
+SDRAM[1].EmcPChg2Pden = 0x00000005;
+SDRAM[1].EmcAct2Pden = 0x00000005;
+SDRAM[1].EmcAr2Pden = 0x00000001;
+SDRAM[1].EmcRw2Pden = 0x0000000e;
+SDRAM[1].EmcTxsr = 0x000000c8;
+SDRAM[1].EmcTcke = 0x00000003;
+SDRAM[1].EmcTfaw = 0x00000011;
+SDRAM[1].EmcTrpab = 0x00000006;
+SDRAM[1].EmcTClkStable = 0x0000000c;
+SDRAM[1].EmcTClkStop = 0x00000002;
+SDRAM[1].EmcTRefBw = 0x00000000;
+SDRAM[1].EmcQUseExtra = 0x00000000;
+SDRAM[1].EmcFbioCfg1 = 0x00000000;
+SDRAM[1].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[1].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[1].EmcFbioQuseDly = 0x74747474;
+SDRAM[1].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[1].EmcFbioCfg5 = 0x00000083;
+SDRAM[1].EmcFbioCfg6 = 0x00000002;
+SDRAM[1].EmcFbioSpare = 0x00000000;
+SDRAM[1].EmcMrs = 0x0000085a;
+SDRAM[1].EmcEmrs = 0x00100002;
+SDRAM[1].EmcMrw1 = 0x00000000;
+SDRAM[1].EmcMrw2 = 0x00000000;
+SDRAM[1].EmcMrw3 = 0x00000000;
+SDRAM[1].EmcMrwResetCommand = 0x00000000;
+SDRAM[1].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[1].EmcAdrCfg = 0x00070303;
+SDRAM[1].EmcAdrCfg1 = 0x00070303;
+SDRAM[1].McEmemCfg = 0x00080000;
+SDRAM[1].McLowLatencyConfig = 0x80000003;
+SDRAM[1].EmcCfg = 0x0301ff00;
+SDRAM[1].EmcCfg2 = 0x00000405;
+SDRAM[1].EmcDbg = 0x01000400;
+SDRAM[1].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[1].EmcCfgDigDll = 0xf0000313;
+SDRAM[1].EmcDllXformDqs = 0x00000010;
+SDRAM[1].EmcDllXformQUse = 0x00000008;
+SDRAM[1].WarmBootWait = 0x00000002;
+SDRAM[1].EmcCttTermCtrl = 0x00000802;
+SDRAM[1].EmcOdtWrite = 0x00000000;
+SDRAM[1].EmcOdtRead = 0x00000000;
+SDRAM[1].EmcZcalRefCnt = 0x00000000;
+SDRAM[1].EmcZcalWaitCnt = 0x00000000;
+SDRAM[1].EmcZcalMrwCmd = 0x00000000;
+SDRAM[1].EmcMrsResetDll = 0x00000000;
+SDRAM[1].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[1].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[1].EmcMrwZqInitWait = 0x00000000;
+SDRAM[1].EmcMrsResetDllWait = 0x00000000;
+SDRAM[1].EmcEmrsEmr2 = 0x00200000;
+SDRAM[1].EmcEmrsEmr3 = 0x00300000;
+SDRAM[1].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[1].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[1].EmcDdr2Wait = 0x00000002;
+SDRAM[1].EmcCfgClktrim0 = 0x00000000;
+SDRAM[1].EmcCfgClktrim1 = 0x00000000;
+SDRAM[1].EmcCfgClktrim2 = 0x00000000;
+SDRAM[1].PmcDdrPwr = 0x00000001;
+SDRAM[1].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[1].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[1].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[1].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[1].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[1].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[1].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[1].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[2].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[2].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[2].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[2].PllMInputDivider = 0x0000000d;
+SDRAM[2].PllMFeedbackDivider = 0x0000029a;
+SDRAM[2].PllMPostDivider = 0x00000000;
+SDRAM[2].PllMStableTime = 0x0000012c;
+SDRAM[2].EmcClockDivider = 0x00000001;
+SDRAM[2].EmcAutoCalInterval = 0x00000000;
+SDRAM[2].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[2].EmcAutoCalWait = 0x00000000;
+SDRAM[2].EmcPinProgramWait = 0x00000000;
+SDRAM[2].EmcRc = 0x00000014;
+SDRAM[2].EmcRfc = 0x00000041;
+SDRAM[2].EmcRas = 0x0000000f;
+SDRAM[2].EmcRp = 0x00000005;
+SDRAM[2].EmcR2w = 0x00000004;
+SDRAM[2].EmcW2r = 0x00000005;
+SDRAM[2].EmcR2p = 0x00000003;
+SDRAM[2].EmcW2p = 0x0000000a;
+SDRAM[2].EmcRdRcd = 0x00000005;
+SDRAM[2].EmcWrRcd = 0x00000005;
+SDRAM[2].EmcRrd = 0x00000004;
+SDRAM[2].EmcRext = 0x00000001;
+SDRAM[2].EmcWdv = 0x00000003;
+SDRAM[2].EmcQUse = 0x00000004;
+SDRAM[2].EmcQRst = 0x00000003;
+SDRAM[2].EmcQSafe = 0x00000009;
+SDRAM[2].EmcRdv = 0x0000000c;
+SDRAM[2].EmcRefresh = 0x000009ff;
+SDRAM[2].EmcBurstRefreshNum = 0x00000000;
+SDRAM[2].EmcPdEx2Wr = 0x00000003;
+SDRAM[2].EmcPdEx2Rd = 0x00000003;
+SDRAM[2].EmcPChg2Pden = 0x00000005;
+SDRAM[2].EmcAct2Pden = 0x00000005;
+SDRAM[2].EmcAr2Pden = 0x00000001;
+SDRAM[2].EmcRw2Pden = 0x0000000e;
+SDRAM[2].EmcTxsr = 0x000000c8;
+SDRAM[2].EmcTcke = 0x00000003;
+SDRAM[2].EmcTfaw = 0x00000011;
+SDRAM[2].EmcTrpab = 0x00000006;
+SDRAM[2].EmcTClkStable = 0x0000000c;
+SDRAM[2].EmcTClkStop = 0x00000002;
+SDRAM[2].EmcTRefBw = 0x00000000;
+SDRAM[2].EmcQUseExtra = 0x00000000;
+SDRAM[2].EmcFbioCfg1 = 0x00000000;
+SDRAM[2].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[2].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[2].EmcFbioQuseDly = 0x74747474;
+SDRAM[2].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[2].EmcFbioCfg5 = 0x00000083;
+SDRAM[2].EmcFbioCfg6 = 0x00000002;
+SDRAM[2].EmcFbioSpare = 0x00000000;
+SDRAM[2].EmcMrs = 0x0000085a;
+SDRAM[2].EmcEmrs = 0x00100002;
+SDRAM[2].EmcMrw1 = 0x00000000;
+SDRAM[2].EmcMrw2 = 0x00000000;
+SDRAM[2].EmcMrw3 = 0x00000000;
+SDRAM[2].EmcMrwResetCommand = 0x00000000;
+SDRAM[2].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[2].EmcAdrCfg = 0x00070303;
+SDRAM[2].EmcAdrCfg1 = 0x00070303;
+SDRAM[2].McEmemCfg = 0x00080000;
+SDRAM[2].McLowLatencyConfig = 0x80000003;
+SDRAM[2].EmcCfg = 0x0301ff00;
+SDRAM[2].EmcCfg2 = 0x00000405;
+SDRAM[2].EmcDbg = 0x01000400;
+SDRAM[2].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[2].EmcCfgDigDll = 0xf0000313;
+SDRAM[2].EmcDllXformDqs = 0x00000010;
+SDRAM[2].EmcDllXformQUse = 0x00000008;
+SDRAM[2].WarmBootWait = 0x00000002;
+SDRAM[2].EmcCttTermCtrl = 0x00000802;
+SDRAM[2].EmcOdtWrite = 0x00000000;
+SDRAM[2].EmcOdtRead = 0x00000000;
+SDRAM[2].EmcZcalRefCnt = 0x00000000;
+SDRAM[2].EmcZcalWaitCnt = 0x00000000;
+SDRAM[2].EmcZcalMrwCmd = 0x00000000;
+SDRAM[2].EmcMrsResetDll = 0x00000000;
+SDRAM[2].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[2].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[2].EmcMrwZqInitWait = 0x00000000;
+SDRAM[2].EmcMrsResetDllWait = 0x00000000;
+SDRAM[2].EmcEmrsEmr2 = 0x00200000;
+SDRAM[2].EmcEmrsEmr3 = 0x00300000;
+SDRAM[2].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[2].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[2].EmcDdr2Wait = 0x00000002;
+SDRAM[2].EmcCfgClktrim0 = 0x00000000;
+SDRAM[2].EmcCfgClktrim1 = 0x00000000;
+SDRAM[2].EmcCfgClktrim2 = 0x00000000;
+SDRAM[2].PmcDdrPwr = 0x00000001;
+SDRAM[2].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[2].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[2].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[2].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[2].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[2].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[2].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[2].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[3].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[3].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[3].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[3].PllMInputDivider = 0x0000000d;
+SDRAM[3].PllMFeedbackDivider = 0x0000029a;
+SDRAM[3].PllMPostDivider = 0x00000000;
+SDRAM[3].PllMStableTime = 0x0000012c;
+SDRAM[3].EmcClockDivider = 0x00000001;
+SDRAM[3].EmcAutoCalInterval = 0x00000000;
+SDRAM[3].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[3].EmcAutoCalWait = 0x00000000;
+SDRAM[3].EmcPinProgramWait = 0x00000000;
+SDRAM[3].EmcRc = 0x00000014;
+SDRAM[3].EmcRfc = 0x00000041;
+SDRAM[3].EmcRas = 0x0000000f;
+SDRAM[3].EmcRp = 0x00000005;
+SDRAM[3].EmcR2w = 0x00000004;
+SDRAM[3].EmcW2r = 0x00000005;
+SDRAM[3].EmcR2p = 0x00000003;
+SDRAM[3].EmcW2p = 0x0000000a;
+SDRAM[3].EmcRdRcd = 0x00000005;
+SDRAM[3].EmcWrRcd = 0x00000005;
+SDRAM[3].EmcRrd = 0x00000004;
+SDRAM[3].EmcRext = 0x00000001;
+SDRAM[3].EmcWdv = 0x00000003;
+SDRAM[3].EmcQUse = 0x00000004;
+SDRAM[3].EmcQRst = 0x00000003;
+SDRAM[3].EmcQSafe = 0x00000009;
+SDRAM[3].EmcRdv = 0x0000000c;
+SDRAM[3].EmcRefresh = 0x000009ff;
+SDRAM[3].EmcBurstRefreshNum = 0x00000000;
+SDRAM[3].EmcPdEx2Wr = 0x00000003;
+SDRAM[3].EmcPdEx2Rd = 0x00000003;
+SDRAM[3].EmcPChg2Pden = 0x00000005;
+SDRAM[3].EmcAct2Pden = 0x00000005;
+SDRAM[3].EmcAr2Pden = 0x00000001;
+SDRAM[3].EmcRw2Pden = 0x0000000e;
+SDRAM[3].EmcTxsr = 0x000000c8;
+SDRAM[3].EmcTcke = 0x00000003;
+SDRAM[3].EmcTfaw = 0x00000011;
+SDRAM[3].EmcTrpab = 0x00000006;
+SDRAM[3].EmcTClkStable = 0x0000000c;
+SDRAM[3].EmcTClkStop = 0x00000002;
+SDRAM[3].EmcTRefBw = 0x00000000;
+SDRAM[3].EmcQUseExtra = 0x00000000;
+SDRAM[3].EmcFbioCfg1 = 0x00000000;
+SDRAM[3].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[3].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[3].EmcFbioQuseDly = 0x74747474;
+SDRAM[3].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[3].EmcFbioCfg5 = 0x00000083;
+SDRAM[3].EmcFbioCfg6 = 0x00000002;
+SDRAM[3].EmcFbioSpare = 0x00000000;
+SDRAM[3].EmcMrs = 0x0000085a;
+SDRAM[3].EmcEmrs = 0x00100002;
+SDRAM[3].EmcMrw1 = 0x00000000;
+SDRAM[3].EmcMrw2 = 0x00000000;
+SDRAM[3].EmcMrw3 = 0x00000000;
+SDRAM[3].EmcMrwResetCommand = 0x00000000;
+SDRAM[3].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[3].EmcAdrCfg = 0x00070303;
+SDRAM[3].EmcAdrCfg1 = 0x00070303;
+SDRAM[3].McEmemCfg = 0x00080000;
+SDRAM[3].McLowLatencyConfig = 0x80000003;
+SDRAM[3].EmcCfg = 0x0301ff00;
+SDRAM[3].EmcCfg2 = 0x00000405;
+SDRAM[3].EmcDbg = 0x01000400;
+SDRAM[3].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[3].EmcCfgDigDll = 0xf0000313;
+SDRAM[3].EmcDllXformDqs = 0x00000010;
+SDRAM[3].EmcDllXformQUse = 0x00000008;
+SDRAM[3].WarmBootWait = 0x00000002;
+SDRAM[3].EmcCttTermCtrl = 0x00000802;
+SDRAM[3].EmcOdtWrite = 0x00000000;
+SDRAM[3].EmcOdtRead = 0x00000000;
+SDRAM[3].EmcZcalRefCnt = 0x00000000;
+SDRAM[3].EmcZcalWaitCnt = 0x00000000;
+SDRAM[3].EmcZcalMrwCmd = 0x00000000;
+SDRAM[3].EmcMrsResetDll = 0x00000000;
+SDRAM[3].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[3].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[3].EmcMrwZqInitWait = 0x00000000;
+SDRAM[3].EmcMrsResetDllWait = 0x00000000;
+SDRAM[3].EmcEmrsEmr2 = 0x00200000;
+SDRAM[3].EmcEmrsEmr3 = 0x00300000;
+SDRAM[3].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[3].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[3].EmcDdr2Wait = 0x00000002;
+SDRAM[3].EmcCfgClktrim0 = 0x00000000;
+SDRAM[3].EmcCfgClktrim1 = 0x00000000;
+SDRAM[3].EmcCfgClktrim2 = 0x00000000;
+SDRAM[3].PmcDdrPwr = 0x00000001;
+SDRAM[3].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[3].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[3].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[3].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[3].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[3].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[3].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[3].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
diff --git a/arch/arm/boards/toradex-colibri-t20/colibri-t20_512_v12_nand.bct.cfg b/arch/arm/boards/toradex-colibri-t20/colibri-t20_512_v12_nand.bct.cfg
new file mode 100644
index 0000000000..a37ea65cea
--- /dev/null
+++ b/arch/arm/boards/toradex-colibri-t20/colibri-t20_512_v12_nand.bct.cfg
@@ -0,0 +1,459 @@
+# Copyright (c) 2013, Toradex AG. All rights reserved.
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+# claim that you wrote the original software. If you use this software
+# in a product, an acknowledgment in the product documentation would be
+# appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+# misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+Version = 0x00020001;
+PartitionSize = 8388608;
+BlockSize = 262144;
+PageSize = 4096;
+OdmData = 0x200C0000;
+
+DevType[0] = Nand;
+DeviceParam[0].NandParams.ClockDivider = 0x4; # Clock source of 108MHz
+DeviceParam[0].NandParams.NandTiming2 = 0xA; # For 108MHz clock
+DeviceParam[0].NandParams.NandTiming = 0x3B269213; # For 108MHz clock
+DeviceParam[0].NandParams.BlockSizeLog2 = 0;
+DeviceParam[0].NandParams.PageSizeLog2 = 0;
+
+DevType[1] = Nand;
+DeviceParam[1].NandParams.ClockDivider = 0x4; # Clock source of 108MHz
+DeviceParam[1].NandParams.NandTiming2 = 0xA; # For 108MHz clock
+DeviceParam[1].NandParams.NandTiming = 0x3B269213; # For 108MHz clock
+DeviceParam[1].NandParams.BlockSizeLog2 = 0;
+DeviceParam[1].NandParams.PageSizeLog2 = 0;
+
+DevType[2] = Nand;
+DeviceParam[2].NandParams.ClockDivider = 0x4; # Clock source of 108MHz
+DeviceParam[2].NandParams.NandTiming2 = 0xA; # For 108MHz clock
+DeviceParam[2].NandParams.NandTiming = 0x3B269213; # For 108MHz clock
+DeviceParam[2].NandParams.BlockSizeLog2 = 0;
+DeviceParam[2].NandParams.PageSizeLog2 = 0;
+
+DevType[3] = Nand;
+DeviceParam[3].NandParams.ClockDivider = 0x4; # Clock source of 108MHz
+DeviceParam[3].NandParams.NandTiming2 = 0xA; # For 108MHz clock
+DeviceParam[3].NandParams.NandTiming = 0x3B269213; # For 108MHz clock
+DeviceParam[3].NandParams.BlockSizeLog2 = 0;
+DeviceParam[3].NandParams.PageSizeLog2 = 0;
+
+SDRAM[0].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[0].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[0].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[0].PllMInputDivider = 0x0000000d;
+SDRAM[0].PllMFeedbackDivider = 0x0000029a;
+SDRAM[0].PllMPostDivider = 0x00000000;
+SDRAM[0].PllMStableTime = 0x0000012c;
+SDRAM[0].EmcClockDivider = 0x00000001;
+SDRAM[0].EmcAutoCalInterval = 0x00000000;
+SDRAM[0].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[0].EmcAutoCalWait = 0x00000000;
+SDRAM[0].EmcPinProgramWait = 0x00000000;
+SDRAM[0].EmcRc = 0x00000014;
+SDRAM[0].EmcRfc = 0x00000041;
+SDRAM[0].EmcRas = 0x0000000f;
+SDRAM[0].EmcRp = 0x00000005;
+SDRAM[0].EmcR2w = 0x00000004;
+SDRAM[0].EmcW2r = 0x00000005;
+SDRAM[0].EmcR2p = 0x00000003;
+SDRAM[0].EmcW2p = 0x0000000a;
+SDRAM[0].EmcRdRcd = 0x00000005;
+SDRAM[0].EmcWrRcd = 0x00000005;
+SDRAM[0].EmcRrd = 0x00000004;
+SDRAM[0].EmcRext = 0x00000001;
+SDRAM[0].EmcWdv = 0x00000003;
+SDRAM[0].EmcQUse = 0x00000004;
+SDRAM[0].EmcQRst = 0x00000003;
+SDRAM[0].EmcQSafe = 0x00000009;
+SDRAM[0].EmcRdv = 0x0000000c;
+SDRAM[0].EmcRefresh = 0x000009ff;
+SDRAM[0].EmcBurstRefreshNum = 0x00000000;
+SDRAM[0].EmcPdEx2Wr = 0x00000003;
+SDRAM[0].EmcPdEx2Rd = 0x00000003;
+SDRAM[0].EmcPChg2Pden = 0x00000005;
+SDRAM[0].EmcAct2Pden = 0x00000005;
+SDRAM[0].EmcAr2Pden = 0x00000001;
+SDRAM[0].EmcRw2Pden = 0x0000000e;
+SDRAM[0].EmcTxsr = 0x000000c8;
+SDRAM[0].EmcTcke = 0x00000003;
+SDRAM[0].EmcTfaw = 0x00000011;
+SDRAM[0].EmcTrpab = 0x00000006;
+SDRAM[0].EmcTClkStable = 0x0000000c;
+SDRAM[0].EmcTClkStop = 0x00000002;
+SDRAM[0].EmcTRefBw = 0x00000000;
+SDRAM[0].EmcQUseExtra = 0x00000000;
+SDRAM[0].EmcFbioCfg1 = 0x00000000;
+SDRAM[0].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[0].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[0].EmcFbioQuseDly = 0x74747474;
+SDRAM[0].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[0].EmcFbioCfg5 = 0x00000083;
+SDRAM[0].EmcFbioCfg6 = 0x00000002;
+SDRAM[0].EmcFbioSpare = 0x00000000;
+SDRAM[0].EmcMrs = 0x0000085a;
+SDRAM[0].EmcEmrs = 0x00100002;
+SDRAM[0].EmcMrw1 = 0x00000000;
+SDRAM[0].EmcMrw2 = 0x00000000;
+SDRAM[0].EmcMrw3 = 0x00000000;
+SDRAM[0].EmcMrwResetCommand = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[0].EmcAdrCfg = 0x00070303;
+SDRAM[0].EmcAdrCfg1 = 0x00070303;
+SDRAM[0].McEmemCfg = 0x00080000;
+SDRAM[0].McLowLatencyConfig = 0x80000003;
+SDRAM[0].EmcCfg = 0x0301ff00;
+SDRAM[0].EmcCfg2 = 0x00000405;
+SDRAM[0].EmcDbg = 0x01000400;
+SDRAM[0].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[0].EmcCfgDigDll = 0xf0000313;
+SDRAM[0].EmcDllXformDqs = 0x00000010;
+SDRAM[0].EmcDllXformQUse = 0x00000008;
+SDRAM[0].WarmBootWait = 0x00000002;
+SDRAM[0].EmcCttTermCtrl = 0x00000802;
+SDRAM[0].EmcOdtWrite = 0x00000000;
+SDRAM[0].EmcOdtRead = 0x00000000;
+SDRAM[0].EmcZcalRefCnt = 0x00000000;
+SDRAM[0].EmcZcalWaitCnt = 0x00000000;
+SDRAM[0].EmcZcalMrwCmd = 0x00000000;
+SDRAM[0].EmcMrsResetDll = 0x00000000;
+SDRAM[0].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[0].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[0].EmcMrwZqInitWait = 0x00000000;
+SDRAM[0].EmcMrsResetDllWait = 0x00000000;
+SDRAM[0].EmcEmrsEmr2 = 0x00200000;
+SDRAM[0].EmcEmrsEmr3 = 0x00300000;
+SDRAM[0].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[0].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[0].EmcDdr2Wait = 0x00000002;
+SDRAM[0].EmcCfgClktrim0 = 0x00000000;
+SDRAM[0].EmcCfgClktrim1 = 0x00000000;
+SDRAM[0].EmcCfgClktrim2 = 0x00000000;
+SDRAM[0].PmcDdrPwr = 0x00000001;
+SDRAM[0].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[0].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[0].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[0].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[0].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[1].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[1].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[1].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[1].PllMInputDivider = 0x0000000d;
+SDRAM[1].PllMFeedbackDivider = 0x0000029a;
+SDRAM[1].PllMPostDivider = 0x00000000;
+SDRAM[1].PllMStableTime = 0x0000012c;
+SDRAM[1].EmcClockDivider = 0x00000001;
+SDRAM[1].EmcAutoCalInterval = 0x00000000;
+SDRAM[1].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[1].EmcAutoCalWait = 0x00000000;
+SDRAM[1].EmcPinProgramWait = 0x00000000;
+SDRAM[1].EmcRc = 0x00000014;
+SDRAM[1].EmcRfc = 0x00000041;
+SDRAM[1].EmcRas = 0x0000000f;
+SDRAM[1].EmcRp = 0x00000005;
+SDRAM[1].EmcR2w = 0x00000004;
+SDRAM[1].EmcW2r = 0x00000005;
+SDRAM[1].EmcR2p = 0x00000003;
+SDRAM[1].EmcW2p = 0x0000000a;
+SDRAM[1].EmcRdRcd = 0x00000005;
+SDRAM[1].EmcWrRcd = 0x00000005;
+SDRAM[1].EmcRrd = 0x00000004;
+SDRAM[1].EmcRext = 0x00000001;
+SDRAM[1].EmcWdv = 0x00000003;
+SDRAM[1].EmcQUse = 0x00000004;
+SDRAM[1].EmcQRst = 0x00000003;
+SDRAM[1].EmcQSafe = 0x00000009;
+SDRAM[1].EmcRdv = 0x0000000c;
+SDRAM[1].EmcRefresh = 0x000009ff;
+SDRAM[1].EmcBurstRefreshNum = 0x00000000;
+SDRAM[1].EmcPdEx2Wr = 0x00000003;
+SDRAM[1].EmcPdEx2Rd = 0x00000003;
+SDRAM[1].EmcPChg2Pden = 0x00000005;
+SDRAM[1].EmcAct2Pden = 0x00000005;
+SDRAM[1].EmcAr2Pden = 0x00000001;
+SDRAM[1].EmcRw2Pden = 0x0000000e;
+SDRAM[1].EmcTxsr = 0x000000c8;
+SDRAM[1].EmcTcke = 0x00000003;
+SDRAM[1].EmcTfaw = 0x00000011;
+SDRAM[1].EmcTrpab = 0x00000006;
+SDRAM[1].EmcTClkStable = 0x0000000c;
+SDRAM[1].EmcTClkStop = 0x00000002;
+SDRAM[1].EmcTRefBw = 0x00000000;
+SDRAM[1].EmcQUseExtra = 0x00000000;
+SDRAM[1].EmcFbioCfg1 = 0x00000000;
+SDRAM[1].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[1].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[1].EmcFbioQuseDly = 0x74747474;
+SDRAM[1].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[1].EmcFbioCfg5 = 0x00000083;
+SDRAM[1].EmcFbioCfg6 = 0x00000002;
+SDRAM[1].EmcFbioSpare = 0x00000000;
+SDRAM[1].EmcMrs = 0x0000085a;
+SDRAM[1].EmcEmrs = 0x00100002;
+SDRAM[1].EmcMrw1 = 0x00000000;
+SDRAM[1].EmcMrw2 = 0x00000000;
+SDRAM[1].EmcMrw3 = 0x00000000;
+SDRAM[1].EmcMrwResetCommand = 0x00000000;
+SDRAM[1].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[1].EmcAdrCfg = 0x00070303;
+SDRAM[1].EmcAdrCfg1 = 0x00070303;
+SDRAM[1].McEmemCfg = 0x00080000;
+SDRAM[1].McLowLatencyConfig = 0x80000003;
+SDRAM[1].EmcCfg = 0x0301ff00;
+SDRAM[1].EmcCfg2 = 0x00000405;
+SDRAM[1].EmcDbg = 0x01000400;
+SDRAM[1].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[1].EmcCfgDigDll = 0xf0000313;
+SDRAM[1].EmcDllXformDqs = 0x00000010;
+SDRAM[1].EmcDllXformQUse = 0x00000008;
+SDRAM[1].WarmBootWait = 0x00000002;
+SDRAM[1].EmcCttTermCtrl = 0x00000802;
+SDRAM[1].EmcOdtWrite = 0x00000000;
+SDRAM[1].EmcOdtRead = 0x00000000;
+SDRAM[1].EmcZcalRefCnt = 0x00000000;
+SDRAM[1].EmcZcalWaitCnt = 0x00000000;
+SDRAM[1].EmcZcalMrwCmd = 0x00000000;
+SDRAM[1].EmcMrsResetDll = 0x00000000;
+SDRAM[1].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[1].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[1].EmcMrwZqInitWait = 0x00000000;
+SDRAM[1].EmcMrsResetDllWait = 0x00000000;
+SDRAM[1].EmcEmrsEmr2 = 0x00200000;
+SDRAM[1].EmcEmrsEmr3 = 0x00300000;
+SDRAM[1].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[1].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[1].EmcDdr2Wait = 0x00000002;
+SDRAM[1].EmcCfgClktrim0 = 0x00000000;
+SDRAM[1].EmcCfgClktrim1 = 0x00000000;
+SDRAM[1].EmcCfgClktrim2 = 0x00000000;
+SDRAM[1].PmcDdrPwr = 0x00000001;
+SDRAM[1].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[1].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[1].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[1].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[1].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[1].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[1].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[1].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[2].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[2].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[2].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[2].PllMInputDivider = 0x0000000d;
+SDRAM[2].PllMFeedbackDivider = 0x0000029a;
+SDRAM[2].PllMPostDivider = 0x00000000;
+SDRAM[2].PllMStableTime = 0x0000012c;
+SDRAM[2].EmcClockDivider = 0x00000001;
+SDRAM[2].EmcAutoCalInterval = 0x00000000;
+SDRAM[2].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[2].EmcAutoCalWait = 0x00000000;
+SDRAM[2].EmcPinProgramWait = 0x00000000;
+SDRAM[2].EmcRc = 0x00000014;
+SDRAM[2].EmcRfc = 0x00000041;
+SDRAM[2].EmcRas = 0x0000000f;
+SDRAM[2].EmcRp = 0x00000005;
+SDRAM[2].EmcR2w = 0x00000004;
+SDRAM[2].EmcW2r = 0x00000005;
+SDRAM[2].EmcR2p = 0x00000003;
+SDRAM[2].EmcW2p = 0x0000000a;
+SDRAM[2].EmcRdRcd = 0x00000005;
+SDRAM[2].EmcWrRcd = 0x00000005;
+SDRAM[2].EmcRrd = 0x00000004;
+SDRAM[2].EmcRext = 0x00000001;
+SDRAM[2].EmcWdv = 0x00000003;
+SDRAM[2].EmcQUse = 0x00000004;
+SDRAM[2].EmcQRst = 0x00000003;
+SDRAM[2].EmcQSafe = 0x00000009;
+SDRAM[2].EmcRdv = 0x0000000c;
+SDRAM[2].EmcRefresh = 0x000009ff;
+SDRAM[2].EmcBurstRefreshNum = 0x00000000;
+SDRAM[2].EmcPdEx2Wr = 0x00000003;
+SDRAM[2].EmcPdEx2Rd = 0x00000003;
+SDRAM[2].EmcPChg2Pden = 0x00000005;
+SDRAM[2].EmcAct2Pden = 0x00000005;
+SDRAM[2].EmcAr2Pden = 0x00000001;
+SDRAM[2].EmcRw2Pden = 0x0000000e;
+SDRAM[2].EmcTxsr = 0x000000c8;
+SDRAM[2].EmcTcke = 0x00000003;
+SDRAM[2].EmcTfaw = 0x00000011;
+SDRAM[2].EmcTrpab = 0x00000006;
+SDRAM[2].EmcTClkStable = 0x0000000c;
+SDRAM[2].EmcTClkStop = 0x00000002;
+SDRAM[2].EmcTRefBw = 0x00000000;
+SDRAM[2].EmcQUseExtra = 0x00000000;
+SDRAM[2].EmcFbioCfg1 = 0x00000000;
+SDRAM[2].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[2].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[2].EmcFbioQuseDly = 0x74747474;
+SDRAM[2].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[2].EmcFbioCfg5 = 0x00000083;
+SDRAM[2].EmcFbioCfg6 = 0x00000002;
+SDRAM[2].EmcFbioSpare = 0x00000000;
+SDRAM[2].EmcMrs = 0x0000085a;
+SDRAM[2].EmcEmrs = 0x00100002;
+SDRAM[2].EmcMrw1 = 0x00000000;
+SDRAM[2].EmcMrw2 = 0x00000000;
+SDRAM[2].EmcMrw3 = 0x00000000;
+SDRAM[2].EmcMrwResetCommand = 0x00000000;
+SDRAM[2].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[2].EmcAdrCfg = 0x00070303;
+SDRAM[2].EmcAdrCfg1 = 0x00070303;
+SDRAM[2].McEmemCfg = 0x00080000;
+SDRAM[2].McLowLatencyConfig = 0x80000003;
+SDRAM[2].EmcCfg = 0x0301ff00;
+SDRAM[2].EmcCfg2 = 0x00000405;
+SDRAM[2].EmcDbg = 0x01000400;
+SDRAM[2].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[2].EmcCfgDigDll = 0xf0000313;
+SDRAM[2].EmcDllXformDqs = 0x00000010;
+SDRAM[2].EmcDllXformQUse = 0x00000008;
+SDRAM[2].WarmBootWait = 0x00000002;
+SDRAM[2].EmcCttTermCtrl = 0x00000802;
+SDRAM[2].EmcOdtWrite = 0x00000000;
+SDRAM[2].EmcOdtRead = 0x00000000;
+SDRAM[2].EmcZcalRefCnt = 0x00000000;
+SDRAM[2].EmcZcalWaitCnt = 0x00000000;
+SDRAM[2].EmcZcalMrwCmd = 0x00000000;
+SDRAM[2].EmcMrsResetDll = 0x00000000;
+SDRAM[2].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[2].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[2].EmcMrwZqInitWait = 0x00000000;
+SDRAM[2].EmcMrsResetDllWait = 0x00000000;
+SDRAM[2].EmcEmrsEmr2 = 0x00200000;
+SDRAM[2].EmcEmrsEmr3 = 0x00300000;
+SDRAM[2].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[2].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[2].EmcDdr2Wait = 0x00000002;
+SDRAM[2].EmcCfgClktrim0 = 0x00000000;
+SDRAM[2].EmcCfgClktrim1 = 0x00000000;
+SDRAM[2].EmcCfgClktrim2 = 0x00000000;
+SDRAM[2].PmcDdrPwr = 0x00000001;
+SDRAM[2].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[2].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[2].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[2].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[2].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[2].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[2].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[2].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
+
+SDRAM[3].MemoryType = NvBootMemoryType_Ddr2;
+SDRAM[3].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[3].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[3].PllMInputDivider = 0x0000000d;
+SDRAM[3].PllMFeedbackDivider = 0x0000029a;
+SDRAM[3].PllMPostDivider = 0x00000000;
+SDRAM[3].PllMStableTime = 0x0000012c;
+SDRAM[3].EmcClockDivider = 0x00000001;
+SDRAM[3].EmcAutoCalInterval = 0x00000000;
+SDRAM[3].EmcAutoCalConfig = 0xe0a61111;
+SDRAM[3].EmcAutoCalWait = 0x00000000;
+SDRAM[3].EmcPinProgramWait = 0x00000000;
+SDRAM[3].EmcRc = 0x00000014;
+SDRAM[3].EmcRfc = 0x00000041;
+SDRAM[3].EmcRas = 0x0000000f;
+SDRAM[3].EmcRp = 0x00000005;
+SDRAM[3].EmcR2w = 0x00000004;
+SDRAM[3].EmcW2r = 0x00000005;
+SDRAM[3].EmcR2p = 0x00000003;
+SDRAM[3].EmcW2p = 0x0000000a;
+SDRAM[3].EmcRdRcd = 0x00000005;
+SDRAM[3].EmcWrRcd = 0x00000005;
+SDRAM[3].EmcRrd = 0x00000004;
+SDRAM[3].EmcRext = 0x00000001;
+SDRAM[3].EmcWdv = 0x00000003;
+SDRAM[3].EmcQUse = 0x00000004;
+SDRAM[3].EmcQRst = 0x00000003;
+SDRAM[3].EmcQSafe = 0x00000009;
+SDRAM[3].EmcRdv = 0x0000000c;
+SDRAM[3].EmcRefresh = 0x000009ff;
+SDRAM[3].EmcBurstRefreshNum = 0x00000000;
+SDRAM[3].EmcPdEx2Wr = 0x00000003;
+SDRAM[3].EmcPdEx2Rd = 0x00000003;
+SDRAM[3].EmcPChg2Pden = 0x00000005;
+SDRAM[3].EmcAct2Pden = 0x00000005;
+SDRAM[3].EmcAr2Pden = 0x00000001;
+SDRAM[3].EmcRw2Pden = 0x0000000e;
+SDRAM[3].EmcTxsr = 0x000000c8;
+SDRAM[3].EmcTcke = 0x00000003;
+SDRAM[3].EmcTfaw = 0x00000011;
+SDRAM[3].EmcTrpab = 0x00000006;
+SDRAM[3].EmcTClkStable = 0x0000000c;
+SDRAM[3].EmcTClkStop = 0x00000002;
+SDRAM[3].EmcTRefBw = 0x00000000;
+SDRAM[3].EmcQUseExtra = 0x00000000;
+SDRAM[3].EmcFbioCfg1 = 0x00000000;
+SDRAM[3].EmcFbioDqsibDly = 0x1c1c1c1c;
+SDRAM[3].EmcFbioDqsibDlyMsb = 0x00000000;
+SDRAM[3].EmcFbioQuseDly = 0x74747474;
+SDRAM[3].EmcFbioQuseDlyMsb = 0x00000000;
+SDRAM[3].EmcFbioCfg5 = 0x00000083;
+SDRAM[3].EmcFbioCfg6 = 0x00000002;
+SDRAM[3].EmcFbioSpare = 0x00000000;
+SDRAM[3].EmcMrs = 0x0000085a;
+SDRAM[3].EmcEmrs = 0x00100002;
+SDRAM[3].EmcMrw1 = 0x00000000;
+SDRAM[3].EmcMrw2 = 0x00000000;
+SDRAM[3].EmcMrw3 = 0x00000000;
+SDRAM[3].EmcMrwResetCommand = 0x00000000;
+SDRAM[3].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[3].EmcAdrCfg = 0x00070303;
+SDRAM[3].EmcAdrCfg1 = 0x00070303;
+SDRAM[3].McEmemCfg = 0x00080000;
+SDRAM[3].McLowLatencyConfig = 0x80000003;
+SDRAM[3].EmcCfg = 0x0301ff00;
+SDRAM[3].EmcCfg2 = 0x00000405;
+SDRAM[3].EmcDbg = 0x01000400;
+SDRAM[3].AhbArbitrationXbarCtrl = 0x00010000;
+SDRAM[3].EmcCfgDigDll = 0xf0000313;
+SDRAM[3].EmcDllXformDqs = 0x00000010;
+SDRAM[3].EmcDllXformQUse = 0x00000008;
+SDRAM[3].WarmBootWait = 0x00000002;
+SDRAM[3].EmcCttTermCtrl = 0x00000802;
+SDRAM[3].EmcOdtWrite = 0x00000000;
+SDRAM[3].EmcOdtRead = 0x00000000;
+SDRAM[3].EmcZcalRefCnt = 0x00000000;
+SDRAM[3].EmcZcalWaitCnt = 0x00000000;
+SDRAM[3].EmcZcalMrwCmd = 0x00000000;
+SDRAM[3].EmcMrsResetDll = 0x00000000;
+SDRAM[3].EmcMrwZqInitDev0 = 0x00000000;
+SDRAM[3].EmcMrwZqInitDev1 = 0x00000000;
+SDRAM[3].EmcMrwZqInitWait = 0x00000000;
+SDRAM[3].EmcMrsResetDllWait = 0x00000000;
+SDRAM[3].EmcEmrsEmr2 = 0x00200000;
+SDRAM[3].EmcEmrsEmr3 = 0x00300000;
+SDRAM[3].EmcEmrsDdr2DllEnable = 0x00100000;
+SDRAM[3].EmcMrsDdr2DllReset = 0x00000100;
+SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00100386;
+SDRAM[3].EmcDdr2Wait = 0x00000002;
+SDRAM[3].EmcCfgClktrim0 = 0x00000000;
+SDRAM[3].EmcCfgClktrim1 = 0x00000000;
+SDRAM[3].EmcCfgClktrim2 = 0x00000000;
+SDRAM[3].PmcDdrPwr = 0x00000001;
+SDRAM[3].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
+SDRAM[3].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
+SDRAM[3].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
+SDRAM[3].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
+SDRAM[3].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
+SDRAM[3].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
+SDRAM[3].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
+SDRAM[3].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
diff --git a/arch/arm/boards/toradex-colibri-t20/entry.c b/arch/arm/boards/toradex-colibri-t20/entry.c
index 886613f13d..695862cfd3 100644
--- a/arch/arm/boards/toradex-colibri-t20/entry.c
+++ b/arch/arm/boards/toradex-colibri-t20/entry.c
@@ -22,7 +22,7 @@
extern char __dtb_tegra20_colibri_iris_start[];
-ENTRY_FUNCTION(start_toradex_colibri_t20_iris, r0, r1, r2)
+static void common_toradex_colibri_t20_iris_start(void)
{
uint32_t fdt;
@@ -32,3 +32,43 @@ ENTRY_FUNCTION(start_toradex_colibri_t20_iris, r0, r1, r2)
tegra_avp_reset_vector(fdt);
}
+
+ENTRY_FUNCTION(start_colibri_t20_256_usbload, r0, r1, r2)
+{
+ common_toradex_colibri_t20_iris_start();
+}
+
+ENTRY_FUNCTION(start_colibri_t20_256_hsmmc, r0, r1, r2)
+{
+ common_toradex_colibri_t20_iris_start();
+}
+
+ENTRY_FUNCTION(start_colibri_t20_256_v11_nand, r0, r1, r2)
+{
+ common_toradex_colibri_t20_iris_start();
+}
+
+ENTRY_FUNCTION(start_colibri_t20_256_v12_nand, r0, r1, r2)
+{
+ common_toradex_colibri_t20_iris_start();
+}
+
+ENTRY_FUNCTION(start_colibri_t20_512_usbload, r0, r1, r2)
+{
+ common_toradex_colibri_t20_iris_start();
+}
+
+ENTRY_FUNCTION(start_colibri_t20_512_hsmmc, r0, r1, r2)
+{
+ common_toradex_colibri_t20_iris_start();
+}
+
+ENTRY_FUNCTION(start_colibri_t20_512_v11_nand, r0, r1, r2)
+{
+ common_toradex_colibri_t20_iris_start();
+}
+
+ENTRY_FUNCTION(start_colibri_t20_512_v12_nand, r0, r1, r2)
+{
+ common_toradex_colibri_t20_iris_start();
+}
diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts
index 1110b89749..35b4d7e43c 100644
--- a/arch/arm/dts/tegra30-beaver.dts
+++ b/arch/arm/dts/tegra30-beaver.dts
@@ -191,6 +191,15 @@
"pex_l1_clkreq_n_pdd6";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
};
+ sdio1 {
+ nvidia,pins = "drive_sdio1";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <46>;
+ nvidia,pull-up-strength = <42>;
+ nvidia,slew-rate-rising = <1>;
+ nvidia,slew-rate-falling = <1>;
+ };
sdio3 {
nvidia,pins = "drive_sdio3";
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
@@ -325,6 +334,7 @@
"vi_hsync_pd7";
nvidia,function = "ddr";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
ddr_up {
nvidia,pins = "vi_d11_pt3";
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 1bbe6ce5e1..5e2b4cb16d 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -63,6 +63,8 @@ config MACH_TOSHIBA_AC100
config MACH_NVIDIA_BEAVER
bool "NVIDIA Beaver"
select ARCH_TEGRA_3x_SOC
+ select I2C
+ select I2C_TEGRA
endmenu
diff --git a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
index 32f10d7838..9ae8784efd 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
@@ -59,7 +59,7 @@ void tegra_dvc_write_data(u32 data, u32 config)
writel(config, TEGRA_DVC_BASE + TEGRA_I2C_CNFG);
}
-static inline __attribute__((always_inline))
+static __always_inline
void tegra30_tps65911_cpu_rail_enable(void)
{
tegra_dvc_write_addr(0x5a, 2);
@@ -71,7 +71,7 @@ void tegra30_tps65911_cpu_rail_enable(void)
tegra_ll_delay_usec(10 * 1000);
}
-static inline __attribute__((always_inline))
+static __always_inline
void tegra30_tps62366a_ramp_vddcore(void)
{
tegra_dvc_write_addr(0xc0, 2);
@@ -80,7 +80,7 @@ void tegra30_tps62366a_ramp_vddcore(void)
tegra_ll_delay_usec(1000);
}
-static inline __attribute__((always_inline))
+static __always_inline
void tegra30_tps62361b_ramp_vddcore(void)
{
tegra_dvc_write_addr(0xc0, 2);
diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h
index 52b405d5f8..10265183c1 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -70,6 +70,12 @@ enum tegra_chiptype {
};
static __always_inline
+u32 tegra_read_chipid(void)
+{
+ return readl(TEGRA_APB_MISC_BASE + APB_MISC_HIDREV);
+}
+
+static __always_inline
enum tegra_chiptype tegra_get_chiptype(void)
{
u32 hidrev;
diff --git a/arch/arm/mach-tegra/include/mach/tegra30-car.h b/arch/arm/mach-tegra/include/mach/tegra30-car.h
index ce110602fc..286a2a613a 100644
--- a/arch/arm/mach-tegra/include/mach/tegra30-car.h
+++ b/arch/arm/mach-tegra/include/mach/tegra30-car.h
@@ -25,6 +25,8 @@
#define CRC_CLK_SOURCE_MSEL_SRC_PLLM 2
#define CRC_CLK_SOURCE_MSEL_SRC_CLKM 3
+#define CRC_CLK_SOURCE_I2C4 0x3c4
+
#define CRC_RST_DEV_V_SET 0x430
#define CRC_RST_DEV_V_MSELECT (1 << 3)
diff --git a/arch/arm/mach-tegra/tegra20-pmc.c b/arch/arm/mach-tegra/tegra20-pmc.c
index b7d84d89ba..1069df9405 100644
--- a/arch/arm/mach-tegra/tegra20-pmc.c
+++ b/arch/arm/mach-tegra/tegra20-pmc.c
@@ -51,6 +51,8 @@ static __maybe_unused struct of_device_id tegra20_pmc_dt_ids[] = {
{
.compatible = "nvidia,tegra20-pmc",
}, {
+ .compatible = "nvidia,tegra30-pmc",
+ }, {
/* sentinel */
}
};