Merge branch 'for-next/kbuild'

35 files changed, 229 insertions, 237 deletions

diff --git a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c
index a199e4da1c..9777d15dfe 100644
--- a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c
@@ -29,7 +29,7 @@
 
 #include <mach/cyclone5-scan-manager.h>
 
-static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]
+static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]
     = {
 	0x00000000,
 	0x00000000,
@@ -57,7 +57,7 @@ static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCAN
 	0x00001000,
 };
 
-static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)]
+static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)]
     = {
 	0x000C0300,
 	0x10040000,
@@ -115,7 +115,7 @@ static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCAN
 	0x00000080,
 };
 
-static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)]
+static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)]
     = {
 	0x80040100,
 	0x00000000,
@@ -149,7 +149,7 @@ static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCAN
 	0x00000800,
 };
 
-static const unsigned long SECT(iocsr_scan_chain3_table)[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)]
+static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)]
     = {
 	0x0C420D80,
 	0x082000FF,
diff --git a/arch/arm/boards/altera-socdk/lowlevel.c b/arch/arm/boards/altera-socdk/lowlevel.c
index 36dbc55b96..822c3d8ee6 100644
--- a/arch/arm/boards/altera-socdk/lowlevel.c
+++ b/arch/arm/boards/altera-socdk/lowlevel.c
@@ -1,5 +1,3 @@
-#define SECT(name) __attribute__((section("socfpga_socdk_" #name))) name
-
 #include "sdram_config.h"
 #include "pinmux_config.c"
 #include "pll_config.h"
diff --git a/arch/arm/boards/altera-socdk/pinmux_config.c b/arch/arm/boards/altera-socdk/pinmux_config.c
index 8bdaaedb80..ff784bbecf 100644
--- a/arch/arm/boards/altera-socdk/pinmux_config.c
+++ b/arch/arm/boards/altera-socdk/pinmux_config.c
@@ -30,7 +30,7 @@
 #include <common.h>
 
 /* pin MUX configuration data */
-static unsigned long SECT(sys_mgr_init_table)[] = {
+static unsigned long sys_mgr_init_table[] = {
 	0,			/* EMACIO0 */
 	2,			/* EMACIO1 */
 	2,			/* EMACIO2 */
diff --git a/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c b/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c
index c9011b2e21..6531383807 100644
--- a/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c
+++ b/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c
@@ -28,7 +28,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 static const uint32_t ac_rom_init_size = 36;
-static const uint32_t SECT(ac_rom_init)[36] = {
+static const uint32_t ac_rom_init[36] = {
 	0x20700000,
 	0x20780000,
 	0x10080431,
diff --git a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c
index 6153de9005..9a814cba79 100644
--- a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c
@@ -29,7 +29,7 @@
 
 #include <mach/cyclone5-scan-manager.h>
 
-static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
+static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
 	0x00000000,
 	0x00000000,
 	0x0FF00000,
@@ -56,7 +56,7 @@ static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCAN
 	0x00001000,
 };
 
-static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
+static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
 	0x000C0300,
 	0x300C0000,
 	0x300000C0,
@@ -113,7 +113,7 @@ static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCAN
 	0x00000080,
 };
 
-static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
+static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
 	0x300C0300,
 	0x00000000,
 	0x0FF00000,
@@ -146,7 +146,7 @@ static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCAN
 	0x00000800,
 };
 
-static const unsigned long SECT(iocsr_scan_chain3_table)[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
+static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
 	0x0CC20D80,
 	0x0C3000FF,
 	0x0A804001,
diff --git a/arch/arm/boards/ebv-socrates/lowlevel.c b/arch/arm/boards/ebv-socrates/lowlevel.c
index ed2d4a72a5..3f12ae806f 100644
--- a/arch/arm/boards/ebv-socrates/lowlevel.c
+++ b/arch/arm/boards/ebv-socrates/lowlevel.c
@@ -1,5 +1,3 @@
-#define SECT(name) __attribute__((section("ebv_socrates_" #name))) name
-
 #include "sdram_config.h"
 #include "pinmux_config.c"
 #include "pll_config.h"
diff --git a/arch/arm/boards/ebv-socrates/pinmux_config.c b/arch/arm/boards/ebv-socrates/pinmux_config.c
index 89e6b33c86..faa3122466 100644
--- a/arch/arm/boards/ebv-socrates/pinmux_config.c
+++ b/arch/arm/boards/ebv-socrates/pinmux_config.c
@@ -30,7 +30,7 @@
 #include <common.h>
 
 /* pin MUX configuration data */
-static unsigned long SECT(sys_mgr_init_table)[] = {
+static unsigned long sys_mgr_init_table[] = {
 	0, /* EMACIO0 */
 	2, /* EMACIO1 */
 	2, /* EMACIO2 */
@@ -238,4 +238,4 @@ static unsigned long SECT(sys_mgr_init_table)[] = {
 	0, /* SPIM1USEFPGA */
 	0, /* USB0USEFPGA */
 	0 /* SPIM0USEFPGA */
-};
+};
\ No newline at end of file
diff --git a/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c b/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c
index c52da56b79..5b5196ad77 100644
--- a/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c
+++ b/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c
@@ -1,5 +1,5 @@
 static const uint32_t ac_rom_init_size = 36;
-static const uint32_t SECT(ac_rom_init)[36] =
+static const uint32_t ac_rom_init[36] =
 {
 	0x20700000,
 	0x20780000,
diff --git a/arch/arm/boards/nvidia-beaver/Makefile b/arch/arm/boards/nvidia-beaver/Makefile
index f0eb7b2de0..1b90eb13fd 100644
--- a/arch/arm/boards/nvidia-beaver/Makefile
+++ b/arch/arm/boards/nvidia-beaver/Makefile
@@ -1,4 +1,4 @@
-CFLAGS_pbl-entry.o := -mcpu=arm7tdmi -march=armv4t
+CFLAGS_entry.pbl.o := -mcpu=arm7tdmi -march=armv4t
 soc := tegra30
 lwl-y += entry.o
 obj-y += board.o
diff --git a/arch/arm/boards/nvidia-jetson-tk1/Makefile b/arch/arm/boards/nvidia-jetson-tk1/Makefile
index 5487f0289a..d38001c158 100644
--- a/arch/arm/boards/nvidia-jetson-tk1/Makefile
+++ b/arch/arm/boards/nvidia-jetson-tk1/Makefile
@@ -1,4 +1,4 @@
-CFLAGS_pbl-entry.o := -mcpu=arm7tdmi -march=armv4t
+CFLAGS_entry.pbl.o := -mcpu=arm7tdmi -march=armv4t
 soc := tegra124
 lwl-y += entry.o
 obj-y += board.o
diff --git a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
index 80cb270313..1458e76ba8 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
@@ -29,7 +29,7 @@
 
 #include <mach/cyclone5-scan-manager.h>
 
-static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
+static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
 	0x00000000,
 	0x00000000,
 	0x0FF00000,
@@ -56,7 +56,7 @@ static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCAN
 	0x00001000,
 };
 
-static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
+static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
 	0x00100000,
 	0x300C0000,
 	0x300000C0,
@@ -113,7 +113,7 @@ static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCAN
 	0x00000080,
 };
 
-static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
+static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
 	0x300C0300,
 	0x00000000,
 	0x0FF00000,
@@ -146,7 +146,7 @@ static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCAN
 	0x00000800,
 };
 
-static const unsigned long SECT(iocsr_scan_chain3_table)[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
+static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
 	0x0C420D80,
 	0x082000FF,
 	0x0A804001,
diff --git a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
index 46f6477a0f..deac0e9cb2 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
@@ -1,5 +1,3 @@
-#define SECT(name) __attribute__((section("terasic_de0_nano_soc_" #name))) name
-
 #include "sdram_config.h"
 #include "pinmux_config.c"
 #include "pll_config.h"
diff --git a/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c b/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c
index c061901814..9c5c7f18ba 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c
@@ -29,7 +29,7 @@
 
 #include <common.h>
 
-static unsigned long SECT(sys_mgr_init_table)[] = {
+static unsigned long sys_mgr_init_table[] = {
 	0, /* EMACIO0 */
 	2, /* EMACIO1 */
 	2, /* EMACIO2 */
diff --git a/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c b/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c
index 1efe4f99c2..52be44f897 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c
@@ -27,7 +27,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 static const uint32_t ac_rom_init_size = 36;
-static const uint32_t SECT(ac_rom_init)[36] =
+static const uint32_t ac_rom_init[36] =
 {
 	0x20700000,
 	0x20780000,
diff --git a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c
index c2ccc46d9b..9367b0d110 100644
--- a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c
@@ -29,7 +29,7 @@
 
 #include <mach/cyclone5-scan-manager.h>
 
-static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
+static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
 	0x00000000,
 	0x00000000,
 	0x0FF00000,
@@ -56,7 +56,7 @@ static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCAN
 	0x00001000,
 };
 
-static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
+static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
 	0x00100000,
 	0x300C0000,
 	0x300000C0,
@@ -113,7 +113,7 @@ static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCAN
 	0x00000080,
 };
 
-static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
+static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
 	0x300C0300,
 	0x00000000,
 	0x0FF00000,
@@ -146,7 +146,7 @@ static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCAN
 	0x00000800,
 };
 
-static const unsigned long SECT(iocsr_scan_chain3_table)[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
+static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
 	0x0C420D80,
 	0x082000FF,
 	0x0A804001,
diff --git a/arch/arm/boards/terasic-sockit/lowlevel.c b/arch/arm/boards/terasic-sockit/lowlevel.c
index 585c786598..1dd7940aeb 100644
--- a/arch/arm/boards/terasic-sockit/lowlevel.c
+++ b/arch/arm/boards/terasic-sockit/lowlevel.c
@@ -1,5 +1,3 @@
-#define SECT(name) __attribute__((section("terasic_sockit_" #name))) name
-
 #include "sdram_config.h"
 #include "pinmux_config.c"
 #include "pll_config.h"
diff --git a/arch/arm/boards/terasic-sockit/pinmux_config.c b/arch/arm/boards/terasic-sockit/pinmux_config.c
index 9a1316d0df..bcf27dbe1e 100644
--- a/arch/arm/boards/terasic-sockit/pinmux_config.c
+++ b/arch/arm/boards/terasic-sockit/pinmux_config.c
@@ -29,7 +29,7 @@
 
 #include <common.h>
 
-static unsigned long SECT(sys_mgr_init_table)[] = {
+static unsigned long sys_mgr_init_table[] = {
 	0, /* EMACIO0 */
 	2, /* EMACIO1 */
 	2, /* EMACIO2 */
diff --git a/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c b/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c
index 8044477e01..fe0764b0ce 100644
--- a/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c
+++ b/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c
@@ -28,7 +28,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 static const uint32_t ac_rom_init_size = 36;
-static const uint32_t SECT(ac_rom_init)[36] =
+static const uint32_t ac_rom_init[36] =
 {
 	0x20700000,
 	0x20780000,
diff --git a/arch/arm/boards/toradex-colibri-t20/Makefile b/arch/arm/boards/toradex-colibri-t20/Makefile
index 644a8e5269..cdce48d1f8 100644
--- a/arch/arm/boards/toradex-colibri-t20/Makefile
+++ b/arch/arm/boards/toradex-colibri-t20/Makefile
@@ -1,4 +1,4 @@
-CFLAGS_pbl-entry.o := -mcpu=arm7tdmi -march=armv4t
+CFLAGS_entry.pbl.o := -mcpu=arm7tdmi -march=armv4t
 soc := tegra20
 lwl-y += entry.o
 obj-y += board.o
diff --git a/arch/arm/boards/toshiba-ac100/Makefile b/arch/arm/boards/toshiba-ac100/Makefile
index 4ef18c0ce9..e8158cb253 100644
--- a/arch/arm/boards/toshiba-ac100/Makefile
+++ b/arch/arm/boards/toshiba-ac100/Makefile
@@ -1,3 +1,3 @@
-CFLAGS_pbl-entry.o := -mcpu=arm7tdmi -march=armv4t
+CFLAGS_entry.pbl.o := -mcpu=arm7tdmi -march=armv4t
 lwl-y += entry.o
 obj-y += board.o
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index 63cf35c299..f7f9c30415 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -6,7 +6,7 @@ obj-pbl-y += lowlevel$(S64).o
 obj-pbl-$(CONFIG_MMU) += mmu-early$(S64).o
 obj-pbl-$(CONFIG_CPU_32v7) += hyp.o
 AFLAGS_hyp.o :=-Wa,-march=armv7-a -Wa,-mcpu=all
-AFLAGS_pbl-hyp.o :=-Wa,-march=armv7-a -Wa,-mcpu=all
+AFLAGS_hyp.pbl.o :=-Wa,-march=armv7-a -Wa,-mcpu=all
 
 obj-y += start.o entry.o entry_ll$(S64).o
 
@@ -32,20 +32,20 @@ obj-$(CONFIG_ARM_PSCI) += psci.o
 obj-$(CONFIG_ARM_PSCI_OF) += psci-of.o
 obj-pbl-$(CONFIG_ARM_SMCCC) += smccc-call$(S64).o
 AFLAGS_smccc-call$(S64).o :=-Wa,-march=armv$(if $(S64),8,7)-a
-AFLAGS_pbl-smccc-call$(S64).o :=-Wa,-march=armv$(if $(S64),8,7)-a
+AFLAGS_smccc-call$(S64).pbl.o :=-Wa,-march=armv$(if $(S64),8,7)-a
 obj-$(CONFIG_ARM_SECURE_MONITOR) += sm.o sm_as.o
 AFLAGS_sm_as.o		:=-Wa,-march=armv7-a
 
 obj-pbl-$(CONFIG_CPU_32v4T) += cache-armv4.o
 obj-pbl-$(CONFIG_CPU_32v5) += cache-armv5.o
 obj-pbl-$(CONFIG_CPU_32v6) += cache-armv6.o
-AFLAGS_cache-armv7.o       :=-Wa,-march=armv7-a
 obj-pbl-$(CONFIG_CPU_32v7) += cache-armv7.o
-AFLAGS_pbl-cache-armv7.o       :=-Wa,-march=armv7-a
+AFLAGS_cache-armv7.o       :=-Wa,-march=armv7-a
+AFLAGS_cache-armv7.pbl.o   :=-Wa,-march=armv7-a
 obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
-AFLAGS_cache-armv8.o       :=-Wa,-march=armv8-a
 obj-pbl-$(CONFIG_CPU_64v8) += cache-armv8.o
-AFLAGS_pbl-cache-armv8.o       :=-Wa,-march=armv8-a
+AFLAGS_cache-armv8.o       :=-Wa,-march=armv8-a
+AFLAGS-cache-armv8.pbl.o   :=-Wa,-march=armv8-a
 
 pbl-y += entry.o entry_ll$(S64).o
 pbl-y += uncompress.o
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1aeaa61e01..d61a052310 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -2,49 +2,49 @@
 # created.
 obj- += dummy.o
 
-lwl-dtb-$(CONFIG_MACH_ADVANTECH_ROM_742X) += imx6dl-advantech-rom-7421.dtb.o
-lwl-dtb-$(CONFIG_MACH_AFI_GF) += am335x-afi-gf.dtb.o
-lwl-dtb-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o
-lwl-dtb-$(CONFIG_MACH_CANON_A1100) += canon-a1100.dtb.o
-lwl-dtb-$(CONFIG_MACH_CM_FX6) += imx6dl-cm-fx6.dtb.o imx6q-cm-fx6.dtb.o imx6q-utilite.dtb.o
-lwl-dtb-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o
-lwl-dtb-$(CONFIG_MACH_DUCKBILL) += imx28-duckbill.dtb.o
-lwl-dtb-$(CONFIG_MACH_KINDLE_MX50) += imx50-kindle-d01100.dtb.o imx50-kindle-d01200.dtb.o imx50-kindle-ey21.dtb.o
-lwl-dtb-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o
-lwl-dtb-$(CONFIG_MACH_ELTEC_HIPERCAM) += imx6dl-eltec-hipercam.dtb.o
-lwl-dtb-$(CONFIG_MACH_EMBEST_MARSBOARD) += imx6q-marsboard.dtb.o
-lwl-dtb-$(CONFIG_MACH_EMBEST_RIOTBOARD) += imx6s-riotboard.dtb.o
-lwl-dtb-$(CONFIG_MACH_EMBEDSKY_E9) += imx6q-embedsky-e9.dtb.o
-lwl-dtb-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o
-lwl-dtb-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o
-lwl-dtb-$(CONFIG_MACH_TX53) += imx53-tx53-xx30.dtb.o imx53-tx53-1011.dtb.o
-lwl-dtb-$(CONFIG_MACH_CCMX51) += imx51-ccxmx51.dtb.o
-lwl-dtb-$(CONFIG_MACH_CCMX53) += imx53-ccxmx53.dtb.o
-lwl-dtb-$(CONFIG_MACH_DIGI_CCIMX6ULSBCPRO) += imx6ul-ccimx6ulsbcpro.dtb.o
-lwl-dtb-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o
-lwl-dtb-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += imx7d-sdb.dtb.o
-lwl-dtb-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
-lwl-dtb-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.dtb.o
-lwl-dtb-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o
-lwl-dtb-$(CONFIG_MACH_GRINN_LITEBOARD) += imx6ul-liteboard.dtb.o
-lwl-dtb-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o
-lwl-dtb-$(CONFIG_MACH_GUF_VINCELL) += imx53-guf-vincell.dtb.o imx53-guf-vincell-lt.dtb.o
-lwl-dtb-$(CONFIG_MACH_GW_VENTANA) += imx6q-gw54xx.dtb.o
-lwl-dtb-$(CONFIG_MACH_KONTRON_SAMX6I) += imx6q-samx6i.dtb.o \
+lwl-$(CONFIG_MACH_ADVANTECH_ROM_742X) += imx6dl-advantech-rom-7421.dtb.o
+lwl-$(CONFIG_MACH_AFI_GF) += am335x-afi-gf.dtb.o
+lwl-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o
+lwl-$(CONFIG_MACH_CANON_A1100) += canon-a1100.dtb.o
+lwl-$(CONFIG_MACH_CM_FX6) += imx6dl-cm-fx6.dtb.o imx6q-cm-fx6.dtb.o imx6q-utilite.dtb.o
+lwl-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o
+lwl-$(CONFIG_MACH_DUCKBILL) += imx28-duckbill.dtb.o
+lwl-$(CONFIG_MACH_KINDLE_MX50) += imx50-kindle-d01100.dtb.o imx50-kindle-d01200.dtb.o imx50-kindle-ey21.dtb.o
+lwl-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o
+lwl-$(CONFIG_MACH_ELTEC_HIPERCAM) += imx6dl-eltec-hipercam.dtb.o
+lwl-$(CONFIG_MACH_EMBEST_MARSBOARD) += imx6q-marsboard.dtb.o
+lwl-$(CONFIG_MACH_EMBEST_RIOTBOARD) += imx6s-riotboard.dtb.o
+lwl-$(CONFIG_MACH_EMBEDSKY_E9) += imx6q-embedsky-e9.dtb.o
+lwl-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o
+lwl-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o
+lwl-$(CONFIG_MACH_TX53) += imx53-tx53-xx30.dtb.o imx53-tx53-1011.dtb.o
+lwl-$(CONFIG_MACH_CCMX51) += imx51-ccxmx51.dtb.o
+lwl-$(CONFIG_MACH_CCMX53) += imx53-ccxmx53.dtb.o
+lwl-$(CONFIG_MACH_DIGI_CCIMX6ULSBCPRO) += imx6ul-ccimx6ulsbcpro.dtb.o
+lwl-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o
+lwl-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += imx7d-sdb.dtb.o
+lwl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
+lwl-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.dtb.o
+lwl-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o
+lwl-$(CONFIG_MACH_GRINN_LITEBOARD) += imx6ul-liteboard.dtb.o
+lwl-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o
+lwl-$(CONFIG_MACH_GUF_VINCELL) += imx53-guf-vincell.dtb.o imx53-guf-vincell-lt.dtb.o
+lwl-$(CONFIG_MACH_GW_VENTANA) += imx6q-gw54xx.dtb.o
+lwl-$(CONFIG_MACH_KONTRON_SAMX6I) += imx6q-samx6i.dtb.o \
 					imx6dl-samx6i.dtb.o
-lwl-dtb-$(CONFIG_MACH_LENOVO_IX4_300D) += armada-xp-lenovo-ix4-300d-bb.dtb.o
-lwl-dtb-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o
-lwl-dtb-$(CONFIG_MACH_MARVELL_ARMADA_XP_DB) += armada-xp-db-bb.dtb.o
-lwl-dtb-$(CONFIG_MACH_MB7707) += module-mb7707.dtb.o
-lwl-dtb-$(CONFIG_MACH_MX28EVK) += imx28-evk.dtb.o
-lwl-dtb-$(CONFIG_MACH_NETGEAR_RN104) += armada-370-rn104-bb.dtb.o
-lwl-dtb-$(CONFIG_MACH_NETGEAR_RN2120) += armada-xp-rn2120-bb.dtb.o
-lwl-dtb-$(CONFIG_MACH_NITROGEN6) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o imx6qp-nitrogen6_max.dtb.o
-lwl-dtb-$(CONFIG_MACH_NVIDIA_BEAVER) += tegra30-beaver.dtb.o
-lwl-dtb-$(CONFIG_MACH_NVIDIA_JETSON) += tegra124-jetson-tk1.dtb.o
-lwl-dtb-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o
-lwl-dtb-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o
-lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += am335x-phytec-phyflex-som.dtb.o am335x-phytec-phyflex-som-mlo.dtb.o \
+lwl-$(CONFIG_MACH_LENOVO_IX4_300D) += armada-xp-lenovo-ix4-300d-bb.dtb.o
+lwl-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o
+lwl-$(CONFIG_MACH_MARVELL_ARMADA_XP_DB) += armada-xp-db-bb.dtb.o
+lwl-$(CONFIG_MACH_MB7707) += module-mb7707.dtb.o
+lwl-$(CONFIG_MACH_MX28EVK) += imx28-evk.dtb.o
+lwl-$(CONFIG_MACH_NETGEAR_RN104) += armada-370-rn104-bb.dtb.o
+lwl-$(CONFIG_MACH_NETGEAR_RN2120) += armada-xp-rn2120-bb.dtb.o
+lwl-$(CONFIG_MACH_NITROGEN6) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o imx6qp-nitrogen6_max.dtb.o
+lwl-$(CONFIG_MACH_NVIDIA_BEAVER) += tegra30-beaver.dtb.o
+lwl-$(CONFIG_MACH_NVIDIA_JETSON) += tegra124-jetson-tk1.dtb.o
+lwl-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o
+lwl-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o
+lwl-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += am335x-phytec-phyflex-som.dtb.o am335x-phytec-phyflex-som-mlo.dtb.o \
 	am335x-phytec-phyflex-som-no-spi.dtb.o am335x-phytec-phyflex-som-no-eeprom.dtb.o \
 	am335x-phytec-phyflex-som-no-spi-no-eeprom.dtb.o \
 	am335x-phytec-phycore-som-mlo.dtb.o \
@@ -52,7 +52,7 @@ lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += am335x-phytec-phyflex-som.dtb.o am33
 	am335x-phytec-phycore-som-nand-no-eeprom.dtb.o am335x-phytec-phycore-som-nand-no-spi-no-eeprom.dtb.o \
 	am335x-phytec-phycore-som-emmc.dtb.o \
 	am335x-phytec-phycard-som.dtb.o am335x-phytec-phycard-som-mlo.dtb.o
-lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-phycard.dtb.o \
+lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-phycard.dtb.o \
 				imx6s-phytec-pbab01.dtb.o \
 				imx6dl-phytec-pbab01.dtb.o \
 				imx6q-phytec-pbab01.dtb.o \
@@ -70,65 +70,65 @@ lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-phycard.dtb.o \
 				imx6ull-phytec-phycore-som-lc-nand.dtb.o \
 				imx6ull-phytec-phycore-som-nand.dtb.o \
 				imx6ull-phytec-phycore-som-emmc.dtb.o
-lwl-dtb-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o
-lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o
-lwl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
-lwl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o
-lwl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o
-lwl-dtb-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o
-lwl-dtb-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o
-lwl-dtb-$(CONFIG_MACH_RPI) += bcm2835-rpi.dtb.o
-lwl-dtb-$(CONFIG_MACH_RPI2) += bcm2836-rpi-2.dtb.o
-lwl-dtb-$(CONFIG_MACH_RPI3) += bcm2837-rpi-3.dtb.o
-lwl-dtb-$(CONFIG_MACH_RPI_CM3) += bcm2837-rpi-cm3.dtb.o
-lwl-dtb-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o
-lwl-dtb-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o
-lwl-dtb-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o
-lwl-dtb-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o
-lwl-dtb-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
-lwl-dtb-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += socfpga_arria10_achilles.dtb.o
-lwl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += socfpga_cyclone5_de0_nano_soc.dtb.o
-lwl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
-lwl-dtb-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o
-lwl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingboard.dtb.o \
+lwl-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o
+lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o
+lwl-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
+lwl-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o
+lwl-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o
+lwl-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o
+lwl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o
+lwl-$(CONFIG_MACH_RPI) += bcm2835-rpi.dtb.o
+lwl-$(CONFIG_MACH_RPI2) += bcm2836-rpi-2.dtb.o
+lwl-$(CONFIG_MACH_RPI3) += bcm2837-rpi-3.dtb.o
+lwl-$(CONFIG_MACH_RPI_CM3) += bcm2837-rpi-cm3.dtb.o
+lwl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o
+lwl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o
+lwl-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o
+lwl-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o
+lwl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
+lwl-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += socfpga_arria10_achilles.dtb.o
+lwl-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += socfpga_cyclone5_de0_nano_soc.dtb.o
+lwl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
+lwl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o
+lwl-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingboard.dtb.o \
 				imx6dl-hummingboard2.dtb.o imx6q-hummingboard2.dtb.o \
 				imx6q-h100.dtb.o
-lwl-dtb-$(CONFIG_MACH_STM32MP157C_DK2) += stm32mp157c-dk2.dtb.o
-lwl-dtb-$(CONFIG_MACH_LXA_MC1) += stm32mp157c-lxa-mc1.dtb.o
-lwl-dtb-$(CONFIG_MACH_SCB9328) += imx1-scb9328.dtb.o
-lwl-dtb-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o
-lwl-dtb-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += imx6ul-pico-hobbit.dtb.o
-lwl-dtb-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += imx6ull-14x14-evk.dtb.o
-lwl-dtb-$(CONFIG_MACH_NXP_IMX8MM_EVK) += imx8mm-evk.dtb.o
-lwl-dtb-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += imx8mq-evk.dtb.o
-lwl-dtb-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o
-lwl-dtb-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
-lwl-dtb-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o
-lwl-dtb-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o
-lwl-dtb-$(CONFIG_MACH_TX25) += imx25-karo-tx25.dtb.o
-lwl-dtb-$(CONFIG_MACH_TX6X) += imx6dl-tx6u.dtb.o
-lwl-dtb-$(CONFIG_MACH_TX6X) += imx6q-tx6q.dtb.o
-lwl-dtb-$(CONFIG_MACH_TURRIS_OMNIA) += armada-385-turris-omnia-bb.dtb.o
-lwl-dtb-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o
-lwl-dtb-$(CONFIG_MACH_UDOO_NEO) += imx6sx-udoo-neo-full.dtb.o
-lwl-dtb-$(CONFIG_MACH_USI_TOPKICK) += kirkwood-topkick-bb.dtb.o
-lwl-dtb-$(CONFIG_MACH_VARISCITE_MX6) += imx6q-var-custom.dtb.o
-lwl-dtb-$(CONFIG_MACH_VERSATILEPB) += versatile-pb.dtb.o
-lwl-dtb-$(CONFIG_MACH_VEXPRESS) += vexpress-v2p-ca9.dtb.o
-lwl-dtb-$(CONFIG_MACH_VEXPRESS) += vexpress-v2p-ca15.dtb.o
-lwl-dtb-$(CONFIG_MACH_VIRT2REAL) += virt2real.dtb.o
-lwl-dtb-$(CONFIG_MACH_VSCOM_BALTOS) += am335x-baltos-minimal.dtb.o
-lwl-dtb-$(CONFIG_MACH_WARP7) += imx7s-warp.dtb.o
-lwl-dtb-$(CONFIG_MACH_VF610_TWR) += vf610-twr.dtb.o
-lwl-dtb-$(CONFIG_MACH_ZII_RDU1) +=	\
+lwl-$(CONFIG_MACH_STM32MP157C_DK2) += stm32mp157c-dk2.dtb.o
+lwl-$(CONFIG_MACH_LXA_MC1) += stm32mp157c-lxa-mc1.dtb.o
+lwl-$(CONFIG_MACH_SCB9328) += imx1-scb9328.dtb.o
+lwl-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o
+lwl-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += imx6ul-pico-hobbit.dtb.o
+lwl-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += imx6ull-14x14-evk.dtb.o
+lwl-$(CONFIG_MACH_NXP_IMX8MM_EVK) += imx8mm-evk.dtb.o
+lwl-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += imx8mq-evk.dtb.o
+lwl-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o
+lwl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
+lwl-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o
+lwl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o
+lwl-$(CONFIG_MACH_TX25) += imx25-karo-tx25.dtb.o
+lwl-$(CONFIG_MACH_TX6X) += imx6dl-tx6u.dtb.o
+lwl-$(CONFIG_MACH_TX6X) += imx6q-tx6q.dtb.o
+lwl-$(CONFIG_MACH_TURRIS_OMNIA) += armada-385-turris-omnia-bb.dtb.o
+lwl-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o
+lwl-$(CONFIG_MACH_UDOO_NEO) += imx6sx-udoo-neo-full.dtb.o
+lwl-$(CONFIG_MACH_USI_TOPKICK) += kirkwood-topkick-bb.dtb.o
+lwl-$(CONFIG_MACH_VARISCITE_MX6) += imx6q-var-custom.dtb.o
+lwl-$(CONFIG_MACH_VERSATILEPB) += versatile-pb.dtb.o
+lwl-$(CONFIG_MACH_VEXPRESS) += vexpress-v2p-ca9.dtb.o
+lwl-$(CONFIG_MACH_VEXPRESS) += vexpress-v2p-ca15.dtb.o
+lwl-$(CONFIG_MACH_VIRT2REAL) += virt2real.dtb.o
+lwl-$(CONFIG_MACH_VSCOM_BALTOS) += am335x-baltos-minimal.dtb.o
+lwl-$(CONFIG_MACH_WARP7) += imx7s-warp.dtb.o
+lwl-$(CONFIG_MACH_VF610_TWR) += vf610-twr.dtb.o
+lwl-$(CONFIG_MACH_ZII_RDU1) +=	\
 	imx51-zii-rdu1.dtb.o		\
 	imx51-zii-scu2-mezz.dtb.o	\
 	imx51-zii-scu3-esb.dtb.o
-lwl-dtb-$(CONFIG_MACH_ZII_RDU2) += imx6q-zii-rdu2.dtb.o imx6qp-zii-rdu2.dtb.o
-lwl-dtb-$(CONFIG_MACH_ZII_IMX8MQ_DEV) +=	\
+lwl-$(CONFIG_MACH_ZII_RDU2) += imx6q-zii-rdu2.dtb.o imx6qp-zii-rdu2.dtb.o
+lwl-$(CONFIG_MACH_ZII_IMX8MQ_DEV) +=	\
 	imx8mq-zii-ultra-rmb3.dtb.o		\
 	imx8mq-zii-ultra-zest.dtb.o
-lwl-dtb-$(CONFIG_MACH_ZII_VF610_DEV) += \
+lwl-$(CONFIG_MACH_ZII_VF610_DEV) += \
 	vf610-zii-dev-rev-b.dtb.o 	\
 	vf610-zii-dev-rev-c.dtb.o 	\
 	vf610-zii-cfu1.dtb.o		\
@@ -136,17 +136,17 @@ lwl-dtb-$(CONFIG_MACH_ZII_VF610_DEV) += \
 	vf610-zii-scu4-aib.dtb.o	\
 	vf610-zii-spb4.dtb.o		\
 	vf610-zii-ssmb-dtu.dtb.o
-lwl-dtb-$(CONFIG_MACH_AT91SAM9263EK_DT) += at91sam9263ek.dtb.o
-lwl-dtb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += at91-microchip-ksz9477-evb.dtb.o
-lwl-dtb-$(CONFIG_MACH_SAMA5D27_SOM1) += at91-sama5d27_som1_ek.dtb.o
-lwl-dtb-$(CONFIG_MACH_SAMA5D27_GIANTBOARD) += at91-sama5d27_giantboard.dtb.o
-lwl-dtb-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o
-lwl-dtb-$(CONFIG_MACH_XILINX_ZCU104) += zynqmp-zcu104-revA.dtb.o
+lwl-$(CONFIG_MACH_AT91SAM9263EK_DT) += at91sam9263ek.dtb.o
+lwl-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += at91-microchip-ksz9477-evb.dtb.o
+lwl-$(CONFIG_MACH_SAMA5D27_SOM1) += at91-sama5d27_som1_ek.dtb.o
+lwl-$(CONFIG_MACH_SAMA5D27_GIANTBOARD) += at91-sama5d27_giantboard.dtb.o
+lwl-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o
+lwl-$(CONFIG_MACH_XILINX_ZCU104) += zynqmp-zcu104-revA.dtb.o
 
-lwl-dtb-$(CONFIG_MACH_ZII_IMX7D_DEV) += imx7d-zii-rpu2.dtb.o imx7d-zii-rmu2.dtb.o
-lwl-dtb-$(CONFIG_MACH_WAGO_PFC_AM35XX) += am35xx-pfc-750_820x.dtb.o
-lwl-dtb-$(CONFIG_MACH_LS1046ARDB) += fsl-ls1046a-rdb.dtb.o
-lwl-dtb-$(CONFIG_MACH_TQMLS1046A) += fsl-tqmls1046a-mbls10xxa.dtb.o
-lwl-dtb-$(CONFIG_MACH_ZEDBOARD) += zynq-zed.dtb.o
+lwl-$(CONFIG_MACH_ZII_IMX7D_DEV) += imx7d-zii-rpu2.dtb.o imx7d-zii-rmu2.dtb.o
+lwl-$(CONFIG_MACH_WAGO_PFC_AM35XX) += am35xx-pfc-750_820x.dtb.o
+lwl-$(CONFIG_MACH_LS1046ARDB) += fsl-ls1046a-rdb.dtb.o
+lwl-$(CONFIG_MACH_TQMLS1046A) += fsl-tqmls1046a-mbls10xxa.dtb.o
+lwl-$(CONFIG_MACH_ZEDBOARD) += zynq-zed.dtb.o
 
 clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo
diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c
index 9b58c452d4..e5ecb0f1b8 100644
--- a/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c
@@ -221,7 +221,7 @@ static int check_test_mem(int start)
 
 #endif // TEST_SIZE
 
-static void SECT(set_failing_group_stage)(uint32_t group, uint32_t stage, uint32_t substage)
+static void set_failing_group_stage(uint32_t group, uint32_t stage, uint32_t substage)
 {
 	if (gbl->error_stage == CAL_STAGE_NIL) {
 		gbl->error_substage = substage;
@@ -313,7 +313,7 @@ static void initialize(void)
 	}
 }
 
-static void SECT(set_rank_and_odt_mask)(uint32_t rank, uint32_t odt_mode)
+static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
 {
 	uint32_t odt_mask_0 = 0;
 	uint32_t odt_mask_1 = 0;
@@ -485,7 +485,7 @@ static inline void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
 
 }
 
-static void SECT(scc_mgr_set_dqs_en_phase_all_ranks)(uint32_t read_group, uint32_t phase)
+static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group, uint32_t phase)
 {
 	uint32_t r;
 	uint32_t update_scan_chains;
@@ -513,7 +513,7 @@ static inline void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t
 
 }
 
-static void SECT(scc_mgr_set_dqdqs_output_phase_all_ranks)(uint32_t write_group, uint32_t phase)
+static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group, uint32_t phase)
 {
 	uint32_t r;
 	uint32_t update_scan_chains;
@@ -541,7 +541,7 @@ static inline void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
 
 }
 
-static void SECT(scc_mgr_set_dqs_en_delay_all_ranks)(uint32_t read_group, uint32_t delay)
+static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group, uint32_t delay)
 {
 	uint32_t r;
 
@@ -562,7 +562,7 @@ static void SECT(scc_mgr_set_dqs_en_delay_all_ranks)(uint32_t read_group, uint32
 	}
 }
 
-static void SECT(scc_mgr_set_oct_out1_delay)(uint32_t write_group, uint32_t delay)
+static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
 {
 	uint32_t read_group;
 
@@ -581,7 +581,7 @@ static void SECT(scc_mgr_set_oct_out1_delay)(uint32_t write_group, uint32_t dela
 
 }
 
-static void SECT(scc_mgr_set_oct_out2_delay)(uint32_t write_group, uint32_t delay)
+static void scc_mgr_set_oct_out2_delay(uint32_t write_group, uint32_t delay)
 {
 	uint32_t read_group;
 
@@ -692,7 +692,7 @@ static inline void scc_mgr_set_dm_in_delay(uint32_t write_group, uint32_t dm, ui
 	WRITE_SCC_DM_IO_IN_DELAY(dm, delay);
 }
 
-static inline void SECT(scc_mgr_set_dm_bypass)(uint32_t write_group, uint32_t dm, uint32_t bypass)
+static inline void scc_mgr_set_dm_bypass(uint32_t write_group, uint32_t dm, uint32_t bypass)
 {
 	// Load the setting in the SCC manager
 	WRITE_SCC_DM_BYPASS(dm, bypass);
@@ -700,7 +700,7 @@ static inline void SECT(scc_mgr_set_dm_bypass)(uint32_t write_group, uint32_t dm
 
 //USER Zero all DQS config
 // TODO: maybe rename to scc_mgr_zero_dqs_config (or something)
-static void SECT(scc_mgr_zero_all)(void)
+static void scc_mgr_zero_all(void)
 {
 	uint32_t i, r;
 
@@ -735,7 +735,7 @@ static void SECT(scc_mgr_zero_all)(void)
 	}
 }
 
-static void SECT(scc_set_bypass_mode)(uint32_t write_group, uint32_t mode)
+static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
 {
 	// mode = 0 : Do NOT bypass - Half Rate Mode
 	// mode = 1 : Bypass - Full Rate Mode
@@ -763,7 +763,7 @@ static void SECT(scc_set_bypass_mode)(uint32_t write_group, uint32_t mode)
 }
 
 // Moving up to avoid warnings
-static void SECT(scc_mgr_load_dqs_for_write_group)(uint32_t write_group)
+static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
 {
 	uint32_t read_group;
 
@@ -780,7 +780,7 @@ static void SECT(scc_mgr_load_dqs_for_write_group)(uint32_t write_group)
 	}
 }
 
-static void SECT(scc_mgr_zero_group)(uint32_t write_group, uint32_t test_begin, int32_t out_only)
+static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin, int32_t out_only)
 {
 	uint32_t i, r;
 
@@ -861,7 +861,7 @@ static void scc_mgr_load_dm(uint32_t dm)
 //USER apply and load a particular input delay for the DQ pins in a group
 //USER group_bgn is the index of the first dq pin (in the write group)
 
-static void SECT(scc_mgr_apply_group_dq_in_delay)(uint32_t write_group, uint32_t group_bgn,
+static void scc_mgr_apply_group_dq_in_delay(uint32_t write_group, uint32_t group_bgn,
 					    uint32_t delay)
 {
 	uint32_t i, p;
@@ -874,7 +874,7 @@ static void SECT(scc_mgr_apply_group_dq_in_delay)(uint32_t write_group, uint32_t
 
 //USER apply and load a particular output delay for the DQ pins in a group
 
-static void SECT(scc_mgr_apply_group_dq_out1_delay)(uint32_t write_group, uint32_t group_bgn,
+static void scc_mgr_apply_group_dq_out1_delay(uint32_t write_group, uint32_t group_bgn,
 					      uint32_t delay1)
 {
 	uint32_t i, p;
@@ -887,7 +887,7 @@ static void SECT(scc_mgr_apply_group_dq_out1_delay)(uint32_t write_group, uint32
 
 //USER apply and load a particular output delay for the DM pins in a group
 
-static void SECT(scc_mgr_apply_group_dm_out1_delay)(uint32_t write_group, uint32_t delay1)
+static void scc_mgr_apply_group_dm_out1_delay(uint32_t write_group, uint32_t delay1)
 {
 	uint32_t i;
 
@@ -898,7 +898,7 @@ static void SECT(scc_mgr_apply_group_dm_out1_delay)(uint32_t write_group, uint32
 }
 
 //USER apply and load delay on both DQS and OCT out1
-static void SECT(scc_mgr_apply_group_dqs_io_and_oct_out1)(uint32_t write_group, uint32_t delay)
+static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group, uint32_t delay)
 {
 	scc_mgr_set_dqs_out1_delay(write_group, delay);
 	scc_mgr_load_dqs_io();
@@ -910,7 +910,7 @@ static void SECT(scc_mgr_apply_group_dqs_io_and_oct_out1)(uint32_t write_group,
 //USER set delay on both DQS and OCT out1 by incrementally changing
 //USER the settings one dtap at a time towards the target value, to avoid
 //USER breaking the lock of the DLL/PLL on the memory device.
-static void SECT(scc_mgr_set_group_dqs_io_and_oct_out1_gradual)(uint32_t write_group, uint32_t delay)
+static void scc_mgr_set_group_dqs_io_and_oct_out1_gradual(uint32_t write_group, uint32_t delay)
 {
 	uint32_t d = READ_SCC_DQS_IO_OUT1_DELAY();
 
@@ -934,7 +934,7 @@ static void SECT(scc_mgr_set_group_dqs_io_and_oct_out1_gradual)(uint32_t write_g
 
 //USER apply a delay to the entire output side: DQ, DM, DQS, OCT
 
-static void SECT(scc_mgr_apply_group_all_out_delay)(uint32_t write_group, uint32_t group_bgn,
+static void scc_mgr_apply_group_all_out_delay(uint32_t write_group, uint32_t group_bgn,
 					      uint32_t delay)
 {
 	//USER dq shift
@@ -951,7 +951,7 @@ static void SECT(scc_mgr_apply_group_all_out_delay)(uint32_t write_group, uint32
 }
 
 //USER apply a delay to the entire output side (DQ, DM, DQS, OCT) and to all ranks
-static void SECT(scc_mgr_apply_group_all_out_delay_all_ranks)(uint32_t write_group, uint32_t group_bgn,
+static void scc_mgr_apply_group_all_out_delay_all_ranks(uint32_t write_group, uint32_t group_bgn,
 							uint32_t delay)
 {
 	uint32_t r;
@@ -968,7 +968,7 @@ static void SECT(scc_mgr_apply_group_all_out_delay_all_ranks)(uint32_t write_gro
 
 //USER apply a delay to the entire output side: DQ, DM, DQS, OCT
 
-static void SECT(scc_mgr_apply_group_all_out_delay_add)(uint32_t write_group, uint32_t group_bgn,
+static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group, uint32_t group_bgn,
 						  uint32_t delay)
 {
 	uint32_t i, p, new_delay;
@@ -1046,7 +1046,7 @@ static void SECT(scc_mgr_apply_group_all_out_delay_add)(uint32_t write_group, ui
 }
 
 //USER apply a delay to the entire output side (DQ, DM, DQS, OCT) and to all ranks
-static void SECT(scc_mgr_apply_group_all_out_delay_add_all_ranks)(uint32_t write_group,
+static void scc_mgr_apply_group_all_out_delay_add_all_ranks(uint32_t write_group,
 							    uint32_t group_bgn, uint32_t delay)
 {
 	uint32_t r;
@@ -1067,7 +1067,7 @@ static inline void scc_mgr_spread_out2_delay_all_ranks(uint32_t write_group, uin
 
 // optimization used to recover some slots in ddr3 inst_rom
 // could be applied to other protocols if we wanted to
-static void SECT(set_jump_as_return)(void)
+static void set_jump_as_return(void)
 {
 	// to save space, we replace return with jump to special shared RETURN instruction
 	// so we set the counter to large value so that we always jump
@@ -1077,7 +1077,7 @@ static void SECT(set_jump_as_return)(void)
 }
 
 // should always use constants as argument to ensure all computations are performed at compile time
-static inline void SECT(delay_for_n_mem_clocks)(const uint32_t clocks)
+static inline void delay_for_n_mem_clocks(const uint32_t clocks)
 {
 	uint32_t afi_clocks;
 	uint8_t inner;
@@ -1145,7 +1145,7 @@ static inline void SECT(delay_for_n_mem_clocks)(const uint32_t clocks)
 }
 
 // should always use constants as argument to ensure all computations are performed at compile time
-static inline void SECT(delay_for_n_ns)(const uint32_t nanoseconds)
+static inline void delay_for_n_ns(const uint32_t nanoseconds)
 {
 	delay_for_n_mem_clocks((1000 * nanoseconds) / (1000000 / AFI_CLK_FREQ) * AFI_RATE_RATIO);
 }
@@ -1161,7 +1161,7 @@ static void rw_mgr_rdimm_initialize(void)
 {
 }
 
-static void SECT(rw_mgr_mem_initialize)(void)
+static void rw_mgr_mem_initialize(void)
 {
 	uint32_t r;
 
@@ -1273,7 +1273,7 @@ static void rw_mgr_mem_dll_lock_wait(void)
 //USER  At the end of calibration we have to program the user settings in, and
 //USER  hand off the memory to the user.
 
-static void SECT(rw_mgr_mem_handoff)(void)
+static void rw_mgr_mem_handoff(void)
 {
 	uint32_t r;
 
@@ -1325,7 +1325,7 @@ static void SECT(rw_mgr_mem_handoff)(void)
 }
 
 //USER performs a guaranteed read on the patterns we are going to use during a read test to ensure memory works
-static uint32_t SECT(rw_mgr_mem_calibrate_read_test_patterns)(uint32_t rank_bgn, uint32_t group,
+static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn, uint32_t group,
 							uint32_t num_tries, t_btfld * bit_chk,
 							uint32_t all_ranks)
 {
@@ -1387,7 +1387,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_read_test_patterns)(uint32_t rank_bgn,
 	return (*bit_chk == param->read_correct_mask);
 }
 
-static uint32_t SECT(rw_mgr_mem_calibrate_read_test_patterns_all_ranks)(uint32_t group,
+static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks(uint32_t group,
 								  uint32_t num_tries,
 								  t_btfld * bit_chk)
 {
@@ -1410,7 +1410,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_read_test_patterns_all_ranks)(uint32_t
 }
 
 //USER load up the patterns we are going to use during a read test
-static void SECT(rw_mgr_mem_calibrate_read_load_patterns)(uint32_t rank_bgn, uint32_t all_ranks)
+static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn, uint32_t all_ranks)
 {
 	uint32_t r;
 	uint32_t rank_end =
@@ -1445,7 +1445,7 @@ static void SECT(rw_mgr_mem_calibrate_read_load_patterns)(uint32_t rank_bgn, uin
 	set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
 }
 
-static inline void SECT(rw_mgr_mem_calibrate_read_load_patterns_all_ranks)(void)
+static inline void rw_mgr_mem_calibrate_read_load_patterns_all_ranks(void)
 {
 	rw_mgr_mem_calibrate_read_load_patterns(0, 1);
 }
@@ -1564,7 +1564,7 @@ static inline void SECT(rw_mgr_mem_calibrate_read_load_patterns_all_ranks)(void)
 //USER  try a read and see if it returns correct data back. has dummy reads inserted into the mix
 //USER  used to align dqs enable. has more thorough checks than the regular read test.
 
-static uint32_t SECT(rw_mgr_mem_calibrate_read_test)(uint32_t rank_bgn, uint32_t group,
+static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
 					       uint32_t num_tries, uint32_t all_correct,
 					       t_btfld * bit_chk, uint32_t all_groups,
 					       uint32_t all_ranks)
@@ -1651,7 +1651,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_read_test)(uint32_t rank_bgn, uint32_t
 	}
 }
 
-static inline uint32_t SECT(rw_mgr_mem_calibrate_read_test_all_ranks)(uint32_t group, uint32_t num_tries,
+static inline uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group, uint32_t num_tries,
 								uint32_t all_correct,
 								t_btfld * bit_chk,
 								uint32_t all_groups)
@@ -1660,7 +1660,7 @@ static inline uint32_t SECT(rw_mgr_mem_calibrate_read_test_all_ranks)(uint32_t g
 					      1);
 }
 
-static void SECT(rw_mgr_incr_vfifo)(uint32_t grp, uint32_t * v)
+static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t * v)
 {
 	//USER fiddle with FIFO
 	if (HARD_PHY) {
@@ -1691,7 +1691,7 @@ static void SECT(rw_mgr_incr_vfifo)(uint32_t grp, uint32_t * v)
 }
 
 //Used in quick cal to properly loop through the duplicated VFIFOs in AV QDRII/RLDRAM
-static inline void SECT(rw_mgr_incr_vfifo_all)(uint32_t grp, uint32_t * v)
+static inline void rw_mgr_incr_vfifo_all(uint32_t grp, uint32_t * v)
 {
 #if VFIFO_CONTROL_WIDTH_PER_DQS == 1
 	rw_mgr_incr_vfifo(grp, v);
@@ -1706,7 +1706,7 @@ static inline void SECT(rw_mgr_incr_vfifo_all)(uint32_t grp, uint32_t * v)
 #endif
 }
 
-static void SECT(rw_mgr_decr_vfifo)(uint32_t grp, uint32_t * v)
+static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t * v)
 {
 
 	uint32_t i;
@@ -1722,7 +1722,7 @@ static void SECT(rw_mgr_decr_vfifo)(uint32_t grp, uint32_t * v)
 
 // Navid's version
 
-static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase)(uint32_t grp)
+static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
 {
 	uint32_t i, d, v, p;
 	uint32_t max_working_cnt;
@@ -2415,7 +2415,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
 #else
 // Val's original version
 
-static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase)(uint32_t grp)
+static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
 {
 	uint32_t i, j, v, d;
 	uint32_t min_working_d, max_working_cnt;
@@ -2532,7 +2532,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase)(uint32_t grp)
 #endif
 
 // Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different dq_in_delay values
-static inline uint32_t SECT(rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay)(uint32_t
+static inline uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay(uint32_t
 										      write_group,
 										      uint32_t
 										      read_group,
@@ -2584,7 +2584,7 @@ static inline uint32_t SECT(rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_d
 
 #if NEWVERSION_RDDESKEW
 
-static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_center)(uint32_t rank_bgn, uint32_t write_group,
+static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t write_group,
 						  uint32_t read_group, uint32_t test_bgn,
 						  uint32_t use_read_test, uint32_t update_fom)
 {
@@ -2902,7 +2902,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_center)(uint32_t rank_bgn, uint3
 
 #else
 
-static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_center)(uint32_t rank_bgn, uint32_t grp,
+static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t grp,
 						  uint32_t test_bgn, uint32_t use_read_test)
 {
 	uint32_t i, p, d;
@@ -3037,7 +3037,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_center)(uint32_t rank_bgn, uint3
 #if NEWVERSION_GW
 
 //USER VFIFO Calibration -- Full Calibration
-static uint32_t SECT(rw_mgr_mem_calibrate_vfifo)(uint32_t read_group, uint32_t test_bgn)
+static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group, uint32_t test_bgn)
 {
 	uint32_t p, d, rank_bgn, sr;
 	uint32_t dtaps_per_ptap;
@@ -3201,7 +3201,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_vfifo)(uint32_t read_group, uint32_t t
 #else
 
 //USER VFIFO Calibration -- Full Calibration
-static uint32_t SECT(rw_mgr_mem_calibrate_vfifo)(uint32_t g, uint32_t test_bgn)
+static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t g, uint32_t test_bgn)
 {
 	uint32_t p, rank_bgn, sr;
 	uint32_t grp_calibrated;
@@ -3272,7 +3272,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_vfifo)(uint32_t g, uint32_t test_bgn)
 #endif
 
 //USER VFIFO Calibration -- Read Deskew Calibration after write deskew
-static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_end)(uint32_t read_group, uint32_t test_bgn)
+static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group, uint32_t test_bgn)
 {
 	uint32_t rank_bgn, sr;
 	uint32_t grp_calibrated;
@@ -3323,7 +3323,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_end)(uint32_t read_group, uint32
 
 //USER Calibrate LFIFO to find smallest read latency
 
-static uint32_t SECT(rw_mgr_mem_calibrate_lfifo)(void)
+static uint32_t rw_mgr_mem_calibrate_lfifo(void)
 {
 	uint32_t found_one;
 	t_btfld bit_chk;
@@ -3381,7 +3381,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_lfifo)(void)
 //USER two variants are provided. one that just tests a write pattern and another that
 //USER tests datamask functionality.
 
-static void SECT(rw_mgr_mem_calibrate_write_test_issue)(uint32_t group, uint32_t test_dm)
+static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group, uint32_t test_dm)
 {
 	uint32_t mcc_instruction;
 	uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES)
@@ -3486,7 +3486,7 @@ static void SECT(rw_mgr_mem_calibrate_write_test_issue)(uint32_t group, uint32_t
 
 //USER Test writes, can check for a single bit pass or multiple bit pass
 
-static uint32_t SECT(rw_mgr_mem_calibrate_write_test)(uint32_t rank_bgn, uint32_t write_group,
+static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn, uint32_t write_group,
 						uint32_t use_dm, uint32_t all_correct,
 						t_btfld * bit_chk, uint32_t all_ranks)
 {
@@ -3552,7 +3552,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_write_test)(uint32_t rank_bgn, uint32_
 	}
 }
 
-static inline uint32_t SECT(rw_mgr_mem_calibrate_write_test_all_ranks)(uint32_t write_group,
+static inline uint32_t rw_mgr_mem_calibrate_write_test_all_ranks(uint32_t write_group,
 								 uint32_t use_dm,
 								 uint32_t all_correct,
 								 t_btfld * bit_chk)
@@ -3565,7 +3565,7 @@ static inline uint32_t SECT(rw_mgr_mem_calibrate_write_test_all_ranks)(uint32_t
 #if NEWVERSION_WL
 
 //USER Write Levelling -- Full Calibration
-static uint32_t SECT(rw_mgr_mem_calibrate_wlevel)(uint32_t g, uint32_t test_bgn)
+static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn)
 {
 	uint32_t p, d;
 
@@ -3805,7 +3805,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_wlevel)(uint32_t g, uint32_t test_bgn)
 #else
 
 //USER Write Levelling -- Full Calibration
-static uint32_t SECT(rw_mgr_mem_calibrate_wlevel)(uint32_t g, uint32_t test_bgn)
+static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn)
 {
 	uint32_t p, d;
 	t_btfld bit_chk;
@@ -3934,7 +3934,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_wlevel)(uint32_t g, uint32_t test_bgn)
 
 #if NEWVERSION_WRDESKEW
 
-static uint32_t SECT(rw_mgr_mem_calibrate_writes_center)(uint32_t rank_bgn, uint32_t write_group,
+static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t write_group,
 						   uint32_t test_bgn)
 {
 	uint32_t i, p, min_index;
@@ -4307,7 +4307,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_writes_center)(uint32_t rank_bgn, uint
 
 #else // !NEWVERSION_WRDESKEW
 
-static uint32_t SECT(rw_mgr_mem_calibrate_writes_center)(uint32_t rank_bgn, uint32_t write_group,
+static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t write_group,
 						   uint32_t test_bgn)
 {
 	uint32_t i, p, d;
@@ -4488,7 +4488,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_writes_center)(uint32_t rank_bgn, uint
 
 //USER calibrate the write operations
 
-static uint32_t SECT(rw_mgr_mem_calibrate_writes)(uint32_t rank_bgn, uint32_t g, uint32_t test_bgn)
+static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g, uint32_t test_bgn)
 {
 
 	reg_file_set_stage(CAL_STAGE_WRITES);
@@ -4509,7 +4509,7 @@ static uint32_t SECT(rw_mgr_mem_calibrate_writes)(uint32_t rank_bgn, uint32_t g,
 }
 
 //USER precharge all banks and activate row 0 in bank "000..." and bank "111..."
-static void SECT(mem_precharge_and_activate)(void)
+static void mem_precharge_and_activate(void)
 {
 	uint32_t r;
 
@@ -4540,7 +4540,7 @@ static void SECT(mem_precharge_and_activate)(void)
 
 //USER Configure various memory related parameters.
 
-static void SECT(mem_config)(void)
+static void mem_config(void)
 {
 	uint32_t rlat, wlat;
 	uint32_t rw_wl_nop_cycles;
@@ -4629,7 +4629,7 @@ static void SECT(mem_config)(void)
 
 //USER Set VFIFO and LFIFO to instant-on settings in skip calibration mode
 
-static void SECT(mem_skip_calibrate)(void)
+static void mem_skip_calibrate(void)
 {
 	uint32_t vfifo_offset;
 	uint32_t i, j, r;
@@ -4707,7 +4707,7 @@ static void SECT(mem_skip_calibrate)(void)
 
 //USER Memory calibration entry point
 
-static uint32_t SECT(mem_calibrate)(void)
+static uint32_t mem_calibrate(void)
 {
 	uint32_t i;
 	uint32_t rank_bgn, sr;
@@ -4914,7 +4914,7 @@ static uint32_t SECT(mem_calibrate)(void)
 	return 1;
 }
 
-static uint32_t SECT(run_mem_calibrate)(void)
+static uint32_t run_mem_calibrate(void)
 {
 
 	uint32_t pass;
@@ -5011,7 +5011,7 @@ static uint32_t SECT(run_mem_calibrate)(void)
 
 }
 
-static void SECT(hc_initialize_rom_data)(void)
+static void hc_initialize_rom_data(void)
 {
 	uint32_t i;
 
@@ -5026,7 +5026,7 @@ static void SECT(hc_initialize_rom_data)(void)
 	}
 }
 
-static void SECT(initialize_reg_file)(void)
+static void initialize_reg_file(void)
 {
 	// Initialize the register file with the correct data
 	IOWR_32DIRECT(REG_FILE_SIGNATURE, 0, REG_FILE_INIT_SEQ_SIGNATURE);
@@ -5038,7 +5038,7 @@ static void SECT(initialize_reg_file)(void)
 	IOWR_32DIRECT(REG_FILE_DEBUG2, 0, 0);
 }
 
-static void SECT(initialize_hps_phy)(void)
+static void initialize_hps_phy(void)
 {
 	// These may need to be included also:
 	// wrap_back_en (false)
@@ -5131,7 +5131,7 @@ static void initialize_tracking(void)
 	IOWR_32DIRECT(REG_FILE_TRK_RFSH, 0, concatenated_refresh);
 }
 
-static int SECT(socfpga_mem_calibration)(void)
+static int socfpga_mem_calibration(void)
 {
 	param_t my_param;
 	gbl_t my_gbl;
diff --git a/arch/arm/mach-socfpga/include/mach/lowlevel.h b/arch/arm/mach-socfpga/include/mach/lowlevel.h
index 657e07a881..8134a02357 100644
--- a/arch/arm/mach-socfpga/include/mach/lowlevel.h
+++ b/arch/arm/mach-socfpga/include/mach/lowlevel.h
@@ -13,7 +13,7 @@
 #include <mach/pll_config.h>
 #include <mach/cyclone5-sequencer.c>
 
-static noinline void SECT(start_socfpga_c5_common)(uint32_t size, void *fdt_blob)
+static void __noreturn start_socfpga_c5_common(uint32_t size, void *fdt_blob)
 {
 	void *fdt;
 
@@ -32,7 +32,7 @@ static noinline void SECT(start_socfpga_c5_common)(uint32_t size, void *fdt_blob
 		start_socfpga_c5_common(memory_size, __dtb_##fdt_name##_start); \
 	}
 
-static noinline void SECT(start_socfpga_c5_xload_common)(uint32_t size)
+static noinline void start_socfpga_c5_xload_common(uint32_t size)
 {
 	struct socfpga_io_config io_config;
 	int ret;
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 7547951752..60aae41ea0 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,5 +1,5 @@
 CFLAGS_tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t
-CFLAGS_pbl-tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t
+CFLAGS_tegra_avp_init.pbl.o := -mcpu=arm7tdmi -march=armv4t
 lwl-y += tegra_avp_init.o
 lwl-y += tegra_maincomplex_init.o
 obj-y += tegra20.o
diff --git a/arch/kvx/Makefile b/arch/kvx/Makefile
index c97cff3456..643ef28553 100644
--- a/arch/kvx/Makefile
+++ b/arch/kvx/Makefile
@@ -32,6 +32,6 @@ lds-y += arch/kvx/cpu/barebox.lds
 
 cmd_barebox__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_barebox) -o $@ \
       -T $(BAREBOX_LDS) \
-      --start-group $(BAREBOX_OBJS) --end-group \
+      --whole-archive $(BAREBOX_OBJS) --no-while-archive \
       -L$(LIBGCC_PATH) -lgcc \
       $(filter-out $(BAREBOX_LDS) $(BAREBOX_OBJS) FORCE ,$^)
diff --git a/arch/kvx/dts/Makefile b/arch/kvx/dts/Makefile
index 9d5e94ae10..391783c1ea 100644
--- a/arch/kvx/dts/Makefile
+++ b/arch/kvx/dts/Makefile
@@ -4,10 +4,10 @@ obj- += dummy.o
 
 BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME))
 ifneq ($(BUILTIN_DTB),)
-obj-dtb-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
+obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
 endif
 
-obj-dtb-$(CONFIG_BOARD_K200) += k200.dtb.o
+obj-$(CONFIG_BOARD_K200) += k200.dtb.o
 
 always := $(dtb-y)
 clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 5604a0a10d..4eb6ba7721 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -102,7 +102,7 @@ lds-$(CONFIG_GENERIC_LINKER_SCRIPT)   := arch/mips/lib/barebox.lds
 
 cmd_barebox__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_barebox) -o $@ \
       -T $(BAREBOX_LDS)                         \
-      --start-group $(BAREBOX_OBJS) --end-group                  \
+      --whole-archive $(BAREBOX_OBJS) --no-whole-archive        \
       $(filter-out $(BAREBOX_LDS) $(BAREBOX_OBJS) FORCE ,$^);	\
 	$(objtree)/scripts/mips-relocs $@
 
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 9e8a6a6aaf..b0ad25ecfa 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -1,18 +1,18 @@
 BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME))
 ifneq ($(BUILTIN_DTB),)
-obj-dtb-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
+obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
 endif
 
-pbl-dtb-$(CONFIG_BOARD_8DEVICES_LIMA) += qca4531-8devices-lima.dtb.o
-pbl-dtb-$(CONFIG_BOARD_BLACK_SWIFT) += black-swift.dtb.o
-pbl-dtb-$(CONFIG_BOARD_CI20) += img-ci20.dtb.o
-pbl-dtb-$(CONFIG_BOARD_DLINK_DIR320) += dlink-dir-320.dtb.o
-pbl-dtb-$(CONFIG_BOARD_DPTECHNICS_DPT_MODULE) += ar9331-dptechnics-dpt-module.dtb.o
-pbl-dtb-$(CONFIG_BOARD_OPENEMBEDED_SOM9331) += ar9331-openembed-som9331-board.dtb.o
-pbl-dtb-$(CONFIG_BOARD_LOONGSON_TECH_LS1B) += loongson-ls1b.dtb.o
-pbl-dtb-$(CONFIG_BOARD_QEMU_MALTA) += qemu-malta.dtb.o
-pbl-dtb-$(CONFIG_BOARD_RZX50) += rzx50.dtb.o
-pbl-dtb-$(CONFIG_BOARD_TPLINK_MR3020) += ar9331_tl_mr3020.dtb.o
-pbl-dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += ar9344-tl-wdr4300-v1.7.dtb.o
+pbl-$(CONFIG_BOARD_8DEVICES_LIMA) += qca4531-8devices-lima.dtb.o
+pbl-$(CONFIG_BOARD_BLACK_SWIFT) += black-swift.dtb.o
+pbl-$(CONFIG_BOARD_CI20) += img-ci20.dtb.o
+pbl-$(CONFIG_BOARD_DLINK_DIR320) += dlink-dir-320.dtb.o
+pbl-$(CONFIG_BOARD_DPTECHNICS_DPT_MODULE) += ar9331-dptechnics-dpt-module.dtb.o
+pbl-$(CONFIG_BOARD_OPENEMBEDED_SOM9331) += ar9331-openembed-som9331-board.dtb.o
+pbl-$(CONFIG_BOARD_LOONGSON_TECH_LS1B) += loongson-ls1b.dtb.o
+pbl-$(CONFIG_BOARD_QEMU_MALTA) += qemu-malta.dtb.o
+pbl-$(CONFIG_BOARD_RZX50) += rzx50.dtb.o
+pbl-$(CONFIG_BOARD_TPLINK_MR3020) += ar9331_tl_mr3020.dtb.o
+pbl-$(CONFIG_BOARD_TPLINK_WDR4300) += ar9344-tl-wdr4300-v1.7.dtb.o
 
 clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo
diff --git a/arch/mips/pbl/Makefile b/arch/mips/pbl/Makefile
index 535bb4bf55..3bd0df165d 100644
--- a/arch/mips/pbl/Makefile
+++ b/arch/mips/pbl/Makefile
@@ -31,7 +31,7 @@ zbarebox-lds := $(obj)/zbarebox.lds
 quiet_cmd_zbarebox__ ?= LD      $@
       cmd_zbarebox__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_zbarebox) -o $@ \
       -T $(zbarebox-lds)                                           \
-      --start-group $(zbarebox-common) --end-group                 \
+      --whole-archive $(zbarebox-common) --no-while-archive        \
       $(filter-out $(zbarebox-lds) $(zbarebox-common) FORCE ,$^)
 
 $(obj)/zbarebox: $(zbarebox-lds) $(zbarebox-common) FORCE
diff --git a/arch/powerpc/Kbuild b/arch/powerpc/Kbuild
index 503ce631c0..65e2493386 100644
--- a/arch/powerpc/Kbuild
+++ b/arch/powerpc/Kbuild
@@ -1,2 +1,4 @@
 obj-$(CONFIG_ARCH_MPC85XX) += cpu-85xx/
 obj-y += lib/
+obj-$(CONFIG_FSL_DDR2) += ddr-8xxx/
+obj-$(CONFIG_FSL_DDR3) += ddr-8xxx/
diff --git a/arch/powerpc/mach-mpc85xx/Makefile b/arch/powerpc/mach-mpc85xx/Makefile
index de4f5efde2..9886c7da45 100644
--- a/arch/powerpc/mach-mpc85xx/Makefile
+++ b/arch/powerpc/mach-mpc85xx/Makefile
@@ -9,6 +9,4 @@ obj-y			+= fsl_i2c.o
 obj-$(CONFIG_MP)	+= mp.o
 obj-$(CONFIG_OFTREE)	+= fdt.o
 obj-$(CONFIG_DRIVER_NET_GIANFAR) += eth-devices.o
-obj-$(CONFIG_FSL_DDR2) += ../ddr-8xxx/
-obj-$(CONFIG_FSL_DDR3) += ../ddr-8xxx/
 extra-y += barebox.lds
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 903fe8ff34..509f236cc0 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,9 +1,9 @@
 BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME))
 ifneq ($(BUILTIN_DTB),)
-obj-dtb-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
+obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
 endif
 
-obj-dtb-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo-generic.dtb.o
+obj-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo-generic.dtb.o
 
 # just to build a built-in.o. Otherwise compilation fails when no devicetree is
 # created.
diff --git a/arch/sandbox/Makefile b/arch/sandbox/Makefile
index 3d2eb5bc11..3917cade94 100644
--- a/arch/sandbox/Makefile
+++ b/arch/sandbox/Makefile
@@ -53,7 +53,7 @@ SANITIZER_LIBS += -fsanitize=undefined
 endif
 
 cmd_barebox__ = $(CC) -o $@ -Wl,-T,$(BAREBOX_LDS) \
-	-Wl,--start-group $(BAREBOX_OBJS) -Wl,--end-group \
+	-Wl,--whole-archive $(BAREBOX_OBJS) -Wl,--no-whole-archive \
 	-lrt -lpthread $(SDL_LIBS) $(FTDI1_LIBS) \
 	$(SANITIZER_LIBS)
 
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 97f6d85f2f..61e51abc71 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -73,8 +73,8 @@ lds-$(CONFIG_X86_64)   := arch/x86/mach-efi/elf_x86_64_efi.lds
 cmd_barebox__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_barebox) -o $@	\
 		-T $(lds-y)					\
 		-shared -Bsymbolic -nostdlib -znocombreloc	\
-		--start-group $(BAREBOX_OBJS)			\
-		--end-group					\
+		--whole-archive $(BAREBOX_OBJS)			\
+		--no-whole-archive				\
 		$(filter-out $(BAREBOX_LDS) $(BAREBOX_OBJS) FORCE ,$^)
 
 quiet_cmd_efi_image = EFI-IMG $@