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authorAhmad Fatoum <a.fatoum@pengutronix.de>2022-02-20 13:47:22 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2022-02-23 11:15:44 +0100
commit2261d05cc0412695f6816303b9be7de390d6e551 (patch)
tree4617038de2be92ebcb26527ba5f57c4e90263e4f /drivers/reset
parent41a1b37ec18f321e5d1b9e431c0301f9b654af4d (diff)
downloadbarebox-2261d05cc0412695f6816303b9be7de390d6e551.tar.gz
reset: move stm32 reset code to drivers/power/reset
We will gut the STM32 reset controller parts in a follow-up commit, because that will be handled together with clocking in a single RCC driver. This will leave only restart and reset reason support in the driver, so move it to drivers/power/reset, so it's not out-of-place. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220220124736.3052502-11-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/reset')
-rw-r--r--drivers/reset/Kconfig6
-rw-r--r--drivers/reset/Makefile1
-rw-r--r--drivers/reset/reset-stm32.c178
3 files changed, 0 insertions, 185 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index b12159094d..21a6e1a50d 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -39,12 +39,6 @@ config RESET_IMX7
help
This enables the reset controller driver for i.MX7 SoCs.
-config RESET_STM32
- bool "STM32 Reset Driver"
- depends on ARCH_STM32MP || COMPILE_TEST
- help
- This enables the reset controller driver for STM32MP1.
-
config RESET_STARFIVE
bool "StarFive Controller Driver" if COMPILE_TEST
default SOC_STARFIVE
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index b4270411fd..6d0cd51f86 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -3,5 +3,4 @@ obj-$(CONFIG_RESET_CONTROLLER) += core.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
-obj-$(CONFIG_RESET_STM32) += reset-stm32.o
obj-$(CONFIG_RESET_STARFIVE) += reset-starfive-vic.o
diff --git a/drivers/reset/reset-stm32.c b/drivers/reset/reset-stm32.c
deleted file mode 100644
index e625ba27ff..0000000000
--- a/drivers/reset/reset-stm32.c
+++ /dev/null
@@ -1,178 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Copyright (C) 2019, Ahmad Fatoum, Pengutronix
- * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
- */
-
-#include <common.h>
-#include <init.h>
-#include <linux/err.h>
-#include <linux/reset-controller.h>
-#include <restart.h>
-#include <reset_source.h>
-#include <asm/io.h>
-
-#define RCC_CL 0x4
-
-#define RCC_MP_GRSTCSETR 0x404
-#define RCC_MP_RSTSCLRR 0x408
-
-#define STM32MP_RCC_RSTF_POR BIT(0)
-#define STM32MP_RCC_RSTF_BOR BIT(1)
-#define STM32MP_RCC_RSTF_PAD BIT(2)
-#define STM32MP_RCC_RSTF_HCSS BIT(3)
-#define STM32MP_RCC_RSTF_VCORE BIT(4)
-
-#define STM32MP_RCC_RSTF_MPSYS BIT(6)
-#define STM32MP_RCC_RSTF_MCSYS BIT(7)
-#define STM32MP_RCC_RSTF_IWDG1 BIT(8)
-#define STM32MP_RCC_RSTF_IWDG2 BIT(9)
-
-#define STM32MP_RCC_RSTF_STDBY BIT(11)
-#define STM32MP_RCC_RSTF_CSTDBY BIT(12)
-#define STM32MP_RCC_RSTF_MPUP0 BIT(13)
-#define STM32MP_RCC_RSTF_MPUP1 BIT(14)
-
-struct stm32_reset_reason {
- uint32_t mask;
- enum reset_src_type type;
- int instance;
-};
-
-struct stm32_reset {
- void __iomem *base;
- struct reset_controller_dev rcdev;
- struct restart_handler restart;
-};
-
-static struct stm32_reset *to_stm32_reset(struct reset_controller_dev *rcdev)
-{
- return container_of(rcdev, struct stm32_reset, rcdev);
-}
-
-static u32 stm32_reset_status(struct stm32_reset *priv, unsigned long bank)
-{
- return readl(priv->base + bank);
-}
-
-static void stm32_reset(struct stm32_reset *priv, unsigned long id, bool assert)
-{
- int bank = (id / 32) * 4;
- int offset = id % 32;
- void __iomem *reg = priv->base + bank;
-
- if (!assert)
- reg += RCC_CL;
-
- writel(BIT(offset), reg);
-}
-
-static void __noreturn stm32mp_rcc_restart_handler(struct restart_handler *rst)
-{
- struct stm32_reset *priv = container_of(rst, struct stm32_reset, restart);
-
- stm32_reset(priv, RCC_MP_GRSTCSETR * BITS_PER_BYTE, true);
-
- mdelay(1000);
- hang();
-}
-
-static const struct stm32_reset_reason stm32mp_reset_reasons[] = {
- { STM32MP_RCC_RSTF_POR, RESET_POR, 0 },
- { STM32MP_RCC_RSTF_BOR, RESET_BROWNOUT, 0 },
- { STM32MP_RCC_RSTF_STDBY, RESET_WKE, 0 },
- { STM32MP_RCC_RSTF_CSTDBY, RESET_WKE, 1 },
- { STM32MP_RCC_RSTF_MPSYS, RESET_RST, 2 },
- { STM32MP_RCC_RSTF_MPUP0, RESET_RST, 0 },
- { STM32MP_RCC_RSTF_MPUP1, RESET_RST, 1 },
- { STM32MP_RCC_RSTF_IWDG1, RESET_WDG, 0 },
- { STM32MP_RCC_RSTF_IWDG2, RESET_WDG, 1 },
- { STM32MP_RCC_RSTF_PAD, RESET_EXT, 1 },
- { /* sentinel */ }
-};
-
-static void stm32_set_reset_reason(struct stm32_reset *priv,
- const struct stm32_reset_reason *reasons)
-{
- enum reset_src_type type = RESET_UKWN;
- u32 reg;
- int i, instance = 0;
-
- reg = stm32_reset_status(priv, RCC_MP_RSTSCLRR);
-
- for (i = 0; reasons[i].mask; i++) {
- if (reg & reasons[i].mask) {
- type = reasons[i].type;
- instance = reasons[i].instance;
- break;
- }
- }
-
- reset_source_set_prinst(type, RESET_SOURCE_DEFAULT_PRIORITY, instance);
-
- pr_info("STM32 RCC reset reason %s (MP_RSTSR: 0x%08x)\n",
- reset_source_to_string(type), reg);
-}
-
-static int stm32_reset_assert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- stm32_reset(to_stm32_reset(rcdev), id, true);
- return 0;
-}
-
-static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- stm32_reset(to_stm32_reset(rcdev), id, false);
- return 0;
-}
-
-static const struct reset_control_ops stm32_reset_ops = {
- .assert = stm32_reset_assert,
- .deassert = stm32_reset_deassert,
-};
-
-static int stm32_reset_probe(struct device_d *dev)
-{
- struct stm32_reset *priv;
- struct resource *iores;
- int ret;
-
- priv = xzalloc(sizeof(*priv));
-
- iores = dev_request_mem_resource(dev, 0);
- if (IS_ERR(iores))
- return PTR_ERR(iores);
-
- priv->base = IOMEM(iores->start);
- priv->rcdev.nr_resets = (iores->end - iores->start) * BITS_PER_BYTE;
- priv->rcdev.ops = &stm32_reset_ops;
- priv->rcdev.of_node = dev->device_node;
-
- priv->restart.name = "stm32-rcc";
- priv->restart.restart = stm32mp_rcc_restart_handler;
- priv->restart.priority = 200;
-
- ret = restart_handler_register(&priv->restart);
- if (ret)
- dev_warn(dev, "Cannot register restart handler\n");
-
- stm32_set_reset_reason(priv, stm32mp_reset_reasons);
-
- return reset_controller_register(&priv->rcdev);
-}
-
-static const struct of_device_id stm32_rcc_reset_dt_ids[] = {
- { .compatible = "st,stm32mp1-rcc" },
- { /* sentinel */ },
-};
-
-static struct driver_d stm32_rcc_reset_driver = {
- .name = "stm32mp_rcc_reset",
- .probe = stm32_reset_probe,
- .of_compatible = DRV_OF_COMPAT(stm32_rcc_reset_dt_ids),
-};
-
-postcore_platform_driver(stm32_rcc_reset_driver);