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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2022-10-17 15:49:29 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-10-18 10:56:29 +0200 |
| commit | 924101c81d6ec2f1b351a073f2c96eec65295b17 (patch) | |
| tree | e7fa42372a365823f00998415345e26bddb1ec00 /drivers/soc | |
| parent | 9011bf7b7fe8109b39e458c7522c544062a8bcff (diff) | |
| download | barebox-924101c81d6ec2f1b351a073f2c96eec65295b17.tar.gz | |
ARM: i.MX8MP: add feature controller support for Plus
Plus has lots of peripherals that need be disabled, depending on fusebox
settings. Some of these are already described in the upstream device tree,
so reference them in the barebox DT and add the necessary glue for
disabling them like we already do on i.MX8MM/N.
We omit CPU fusing for now. These are handled by tester3 and would need
a bit more rework.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20221017134929.622022-4-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/soc')
| -rw-r--r-- | drivers/soc/imx/imx8m-featctrl.c | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/drivers/soc/imx/imx8m-featctrl.c b/drivers/soc/imx/imx8m-featctrl.c index 1798d0fc28..f2c57ac136 100644 --- a/drivers/soc/imx/imx8m-featctrl.c +++ b/drivers/soc/imx/imx8m-featctrl.c @@ -53,13 +53,19 @@ int imx8m_feat_ctrl_init(struct device_d *dev, u32 tester4, clear_bit(IMX8M_FEAT_VPU, features); if (is_fused(tester4, data->gpu_bitmask)) clear_bit(IMX8M_FEAT_GPU, features); - - switch (tester4 & 3) { - case 0b11: - clear_bit(IMX8M_FEAT_CPU_DUAL, features); - fallthrough; - case 0b10: - clear_bit(IMX8M_FEAT_CPU_QUAD, features); + if (is_fused(tester4, data->mipi_dsi_bitmask)) + clear_bit(IMX8M_FEAT_MIPI_DSI, features); + if (is_fused(tester4, data->isp_bitmask)) + clear_bit(IMX8M_FEAT_ISP, features); + + if (data->check_cpus) { + switch (tester4 & 3) { + case 0b11: + clear_bit(IMX8M_FEAT_CPU_DUAL, features); + fallthrough; + case 0b10: + clear_bit(IMX8M_FEAT_CPU_QUAD, features); + } } priv->feat.dev = dev; |