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authorPhilipp Zabel <p.zabel@pengutronix.de>2023-04-03 13:53:37 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2023-04-11 13:58:09 +0200
commita28e290780b36e4ddf9c0afd2043b6c3ffe8156f (patch)
tree57910097d48ffc1bc311c8f1eaec9cbee099cb1b /include
parent3698477e339a902f31f2181805e1026e56612188 (diff)
downloadbarebox-a28e290780b36e4ddf9c0afd2043b6c3ffe8156f.tar.gz
spi: add per-driver bits-per-word mask
Allow SPI hosts to signal per-transfer bits-per-word switching support and drivers to query it with spi_is_bpw_supported(). Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.barebox.org/20230403115340.3416720-1-p.zabel@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'include')
-rw-r--r--include/spi/spi.h32
1 files changed, 32 insertions, 0 deletions
diff --git a/include/spi/spi.h b/include/spi/spi.h
index fa9329b08c..6a5c0e32cf 100644
--- a/include/spi/spi.h
+++ b/include/spi/spi.h
@@ -6,6 +6,7 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/string.h>
+#include <linux/bitops.h>
struct spi_controller_mem_ops;
@@ -131,6 +132,11 @@ struct spi_message;
* SPI slaves, and are numbered from zero to num_chipselects.
* each slave has a chipselect signal, but it's common that not
* every chipselect is connected to a slave.
+ * @bits_per_word_mask: A mask indicating which values of bits_per_word are
+ * supported by the driver. Bit n indicates that a bits_per_word n+1 is
+ * supported. If set, the SPI core will reject any transfer with an
+ * unsupported bits_per_word. If not set, this value is simply ignored,
+ * and it's up to the individual driver to perform any validation.
* @max_speed_hz: Highest supported transfer speed
* @setup: updates the device mode and clocking records used by a
* device's SPI controller; protocol code may call this. This
@@ -165,6 +171,12 @@ struct spi_controller {
/* Optimized handlers for SPI memory-like operations */
const struct spi_controller_mem_ops *mem_ops;
+
+ /* Bitmask of supported bits_per_word for transfers */
+ u32 bits_per_word_mask;
+#define SPI_BPW_MASK(bits) BIT((bits) - 1)
+#define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1)
+
/*
* on some hardware transfer size may be constrained
* the limit may depend on device transfer settings
@@ -435,6 +447,26 @@ spi_transfer_del(struct spi_transfer *t)
list_del(&t->transfer_list);
}
+/**
+ * spi_is_bpw_supported - Check if bits per word is supported
+ * @spi: SPI device
+ * @bpw: Bits per word
+ *
+ * This function checks to see if the SPI controller supports @bpw.
+ *
+ * Returns:
+ * True if @bpw is supported, false otherwise.
+ */
+static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw)
+{
+ u32 bpw_mask = spi->master->bits_per_word_mask;
+
+ if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw)))
+ return true;
+
+ return false;
+}
+
/* All these synchronous SPI transfer routines are utilities layered
* over the core async transfer primitive. Here, "synchronous" means
* they will sleep uninterruptibly until the async transfer completes.