| Commit message (Collapse) | Author | Age | Files | Lines |
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The buf8 variable was never used so remove it.
Fixes: 2f1fc1c92 ("ddr_spd: Add function to read eeprom")
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.barebox.org/20230125124840.3386338-1-m.felsch@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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DDR4 splits the read in two pages while other DDR types do not.
Introduce a new parameter to indicate how to read the SPD.
Signed-off-by: John Watts <contact@jookia.org>
Link: https://lore.barebox.org/20230121144429.3524905-8-contact@jookia.org
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Using signed char type for computed CRC bytes leads to them being sign
extended on comparison with unsigned char values from SPD EEPROM struct.
This happens as when being compared those values undergo integer
promotion that converts them into ints, sign extending signed types.
Having most significant byte set for any of computed CRC bytes thus
results in the mismatch being erroneously detected.
While at it, also remove redundant type casts.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
Link: https://lore.barebox.org/20230113140648.31572-1-denorl2009@gmail.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The prebootloader is inherently board-specific, so it's natural to
hardcode the i2c driver used and we only support fsl_i2c at the moment
anyway. For abstractions used by different prebootloaders though
(e.g. PMIC writing, SPD EEPROM decoding), it would be good for generic
code to use a pbl_i2c abstraction, so it can be reused across PBLs using
different I2C controllers. Add such an abstraction and use it where
appropriate.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.barebox.org/20220805125413.1046239-8-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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For all files in common/ that already have a license text:
- Replace with appropriate SPDX-License-Identifier
- Remove empty comment lines around replacement
- remove comment completely if only thing remaining is name
of file without description
Reviewed-by: Roland Hieber <rhi@pengutronix.de>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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((x & 0x10) == 1) can never be true. Test for the bit at 0x10 instead.
Signed-off-by: 张忠山 <zzs213@126.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This updates the ddr_spd.h header file from U-Boot-2019.01 with some
small changes:
- typedefs are removed
- "_s" suffix from struct types removed
- remove unnecessary "extern" from function declarations
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Our cyc_crc16() function is the same function as crc_itu_t() in the
Linux kernel. Import and use crc_itu_t() from the Kernel for
consistency.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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---=== SPD EEPROM Information ===---
EEPROM Checksum of bytes 0-62 OK (0xDF)
Total number of bytes in EEPROM 256
Fundamental Memory type DDR2 SDRAM
SPD Revision 1.2
---=== Memory Characteristics ===---
Maximum module speed 800 MHz (PC2-6400)
Size 2048 MB
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64
Ranks 2
SDRAM Device Width 8 bits
Module Height 30.0 mm
Module Type SO-DIMM (67.6 mm)
DRAM Package Planar
Voltage Interface Level SSTL 1.8V
Module Configuration Type No Parity
Refresh Rate Reduced (7.8 us) - Self Refresh
Supported Burst Lengths 4, 8
Supported CAS Latencies (tCL) 6T
tCL-tRCD-tRP-tRAS 6-6-6-18 as DDR2-800
Minimum Cycle Time 2.5 ns at CAS 6
Maximum Access Time 0.40 ns at CAS 6
Maximum Cycle Time (tCK max) 8 ns
---=== Timing Parameters ===---
Address/Command Setup Time Before Clock (tIS) 0.17 ns
Address/Command Hold Time After Clock (tIH) 0.25 ns
Data Input Setup Time Before Strobe (tDS) 0.05 ns
Data Input Hold Time After Strobe (tDH) 0.12 ns
Minimum Row Precharge Delay (tRP) 15.00 ns
Minimum Row Active to Row Active Delay (tRRD) 7.50 ns
Minimum RAS# to CAS# Delay (tRCD) 15.00 ns
Minimum RAS# Pulse Width (tRAS) 45.00 ns
Write Recovery Time (tWR) 15.00 ns
Minimum Write to Read CMD Delay (tWTR) 7.50 ns
Minimum Read to Pre-charge CMD Delay (tRTP) 7.50 ns
Minimum Active to Auto-refresh Delay (tRC) 60.00 ns
Minimum Recovery Delay (tRFC) 127 ns
Maximum DQS to DQ Skew (tDQSQ) 0.20 ns
Maximum Read Data Hold Skew (tQHS) 0.30 ns
---=== Manufacturing Information ===---
Manufacturer JEDEC ID 7f 98 00 00 00 00 00 00
Manufacturing Location Code 0x05
Part Number
Manufacturing Date 2014-W47
Assembly Serial Number 0x43266892
Signed-off-by: Alexander Smirnov <alllecs@yandex.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add DDR3 SPD verification support for use by the PPC 8xxx DDR driver.
This is based on the equivalent files from U-Boot version git-be937b5.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The code calculates the DDR2 SPD checksum as per JEDEC standard
No 21-C Appendix X (revision 1.2)
The code is based on the equivalent files from U-Boot version
git-a71d45d.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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