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| author | Zhigang Gong <zhigang.gong@intel.com> | 2015-04-13 10:36:37 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2015-04-13 16:16:10 +0800 |
| commit | 152b100ce9bcf9d4d8599be31366a9df0ccc616f (patch) | |
| tree | 2e12410ef70a0fc49ab3b5b293934a3e1312acc6 | |
| parent | b4fe645e17f998420e8acdc60b1b9b6187a6db94 (diff) | |
| download | beignet-152b100ce9bcf9d4d8599be31366a9df0ccc616f.tar.gz | |
GBE: fix a bug in byte scatter write.
In uniform mode, we should set simd width to 1 and set noMask bit.
Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Reviewed-by: "Yang, Rong R" <rong.r.yang@intel.com>
| -rw-r--r-- | backend/src/backend/gen_insn_selection.cpp | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 9a665937..7d7a8c35 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -3350,11 +3350,17 @@ namespace gbe const GenRegister value = sel.selReg(insn.getValue(0)); GBE_ASSERT(insn.getValueNum() == 1); const GenRegister tmp = sel.selReg(sel.reg(FAMILY_DWORD, isUniform), ir::TYPE_U32); - if (elemSize == GEN_BYTE_SCATTER_WORD) { - sel.MOV(tmp, GenRegister::retype(value, GEN_TYPE_UW)); - } else if (elemSize == GEN_BYTE_SCATTER_BYTE) { - sel.MOV(tmp, GenRegister::retype(value, GEN_TYPE_UB)); - } + sel.push(); + if (isUniform) { + sel.curr.noMask = 1; + sel.curr.execWidth = 1; + } + + if (elemSize == GEN_BYTE_SCATTER_WORD) + sel.MOV(tmp, GenRegister::retype(value, GEN_TYPE_UW)); + else if (elemSize == GEN_BYTE_SCATTER_BYTE) + sel.MOV(tmp, GenRegister::retype(value, GEN_TYPE_UB)); + sel.pop(); sel.BYTE_SCATTER(addr, tmp, elemSize, bti); } } |