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| author | Pan Xiuli <xiuli.pan@intel.com> | 2016-05-26 08:22:36 +0800 |
|---|---|---|
| committer | Yang Rong <rong.r.yang@intel.com> | 2016-06-13 17:02:36 +0800 |
| commit | 15dfc20b396210f27c59b5512f256f3628230721 (patch) | |
| tree | 943ff494536d9c78d5eefc67d8d092eb274ec1d6 /kernels | |
| parent | 5c7a23b65cd9222fb12c230ab55c8790691684ca (diff) | |
| download | beignet-15dfc20b396210f27c59b5512f256f3628230721.tar.gz | |
Backend: Add intel_sub_group_block_read/write form image
Using meida block read/write to read data in block. In simd16 mode the
need some reg relocation for later use.
GEN7 has some different data port.
V2: Refine block read simd16 with tmp reg to avoide MOVs
V3: Fix build bug with clang.
V4: Resize the tmp vector size of block write
Signed-off-by: Pan Xiuli <xiuli.pan@intel.com>
Reviewed-by: Yang Rong <rong.r.yang@intel.com>
Diffstat (limited to 'kernels')
0 files changed, 0 insertions, 0 deletions