sim: fully merge sim_cpu_base into sim_cpu

Now that all ports have migrated to the new framework, drop support
for the old sim_cpu_base layout.  There's a lot of noise here, so
it's been split into a dedicated commit.

1 files changed, 19 insertions, 26 deletions

diff --git a/sim/common/sim-cpu.h b/sim/common/sim-cpu.h
index 83244e09c9e..90e294eb3c6 100644
--- a/sim/common/sim-cpu.h
+++ b/sim/common/sim-cpu.h
@@ -46,39 +46,38 @@ typedef void (PC_STORE_FN) (sim_cpu *, sim_cia);
 
 /* Pseudo baseclass for each cpu.  */
 
-typedef struct {
-
+struct _sim_cpu {
   /* Backlink to main state struct.  */
   SIM_DESC state;
-#define CPU_STATE(cpu) ((cpu)->base.state)
+#define CPU_STATE(cpu) ((cpu)->state)
 
   /* Processor index within the SD_DESC */
   int index;
-#define CPU_INDEX(cpu) ((cpu)->base.index)
+#define CPU_INDEX(cpu) ((cpu)->index)
 
   /* The name of the cpu.  */
   const char *name;
-#define CPU_NAME(cpu) ((cpu)->base.name)
+#define CPU_NAME(cpu) ((cpu)->name)
 
   /* Options specific to this cpu.  */
   struct option_list *options;
-#define CPU_OPTIONS(cpu) ((cpu)->base.options)
+#define CPU_OPTIONS(cpu) ((cpu)->options)
 
   /* Processor specific core data */
   sim_cpu_core core;
-#define CPU_CORE(cpu) (& (cpu)->base.core)
+#define CPU_CORE(cpu) (& (cpu)->core)
 
   /* Number of instructions (used to iterate over CPU_INSN_NAME).  */
   unsigned int max_insns;
-#define CPU_MAX_INSNS(cpu) ((cpu)->base.max_insns)
+#define CPU_MAX_INSNS(cpu) ((cpu)->max_insns)
 
   /* Function to return the name of an insn.  */
   CPU_INSN_NAME_FN *insn_name;
-#define CPU_INSN_NAME(cpu) ((cpu)->base.insn_name)
+#define CPU_INSN_NAME(cpu) ((cpu)->insn_name)
 
   /* Trace data.  See sim-trace.h.  */
   TRACE_DATA trace_data;
-#define CPU_TRACE_DATA(cpu) (& (cpu)->base.trace_data)
+#define CPU_TRACE_DATA(cpu) (& (cpu)->trace_data)
 
   /* Maximum number of debuggable entities.
      This debugging is not intended for normal use.
@@ -90,7 +89,7 @@ typedef struct {
 
   /* Boolean array of specified debugging flags.  */
   char debug_flags[MAX_DEBUG_VALUES];
-#define CPU_DEBUG_FLAGS(cpu) ((cpu)->base.debug_flags)
+#define CPU_DEBUG_FLAGS(cpu) ((cpu)->debug_flags)
   /* Standard values.  */
 #define DEBUG_INSN_IDX 0
 #define DEBUG_NEXT_IDX 2 /* simulator specific debug bits begin here */
@@ -98,37 +97,31 @@ typedef struct {
   /* Debugging output goes to this or stderr if NULL.
      We can't store `stderr' here as stderr goes through a callback.  */
   FILE *debug_file;
-#define CPU_DEBUG_FILE(cpu) ((cpu)->base.debug_file)
+#define CPU_DEBUG_FILE(cpu) ((cpu)->debug_file)
 
   /* Profile data.  See sim-profile.h.  */
   PROFILE_DATA profile_data;
-#define CPU_PROFILE_DATA(cpu) (& (cpu)->base.profile_data)
+#define CPU_PROFILE_DATA(cpu) (& (cpu)->profile_data)
 
   /* Machine tables for this cpu.  See sim-model.h.  */
   const SIM_MACH *mach;
-#define CPU_MACH(cpu) ((cpu)->base.mach)
+#define CPU_MACH(cpu) ((cpu)->mach)
   /* The selected model.  */
   const SIM_MODEL *model;
-#define CPU_MODEL(cpu) ((cpu)->base.model)
+#define CPU_MODEL(cpu) ((cpu)->model)
   /* Model data (profiling state, etc.).  */
   void *model_data;
-#define CPU_MODEL_DATA(cpu) ((cpu)->base.model_data)
+#define CPU_MODEL_DATA(cpu) ((cpu)->model_data)
 
   /* Routines to fetch/store registers.  */
   CPUREG_FETCH_FN *reg_fetch;
-#define CPU_REG_FETCH(c) ((c)->base.reg_fetch)
+#define CPU_REG_FETCH(c) ((c)->reg_fetch)
   CPUREG_STORE_FN *reg_store;
-#define CPU_REG_STORE(c) ((c)->base.reg_store)
+#define CPU_REG_STORE(c) ((c)->reg_store)
   PC_FETCH_FN *pc_fetch;
-#define CPU_PC_FETCH(c) ((c)->base.pc_fetch)
+#define CPU_PC_FETCH(c) ((c)->pc_fetch)
   PC_STORE_FN *pc_store;
-#define CPU_PC_STORE(c) ((c)->base.pc_store)
-
-} sim_cpu_base;
-
-struct _sim_cpu {
-  /* All the common state.  */
-  sim_cpu_base base;
+#define CPU_PC_STORE(c) ((c)->pc_store)
 
 #ifdef CGEN_ARCH
   /* Static parts of cgen.  */