opcodes/

* ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle PPC_OPERANDS_GPR_0. * ppc-opc.c (RA0): Define. (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0. (RAOPT): Rename from RAO. Update all uses. (powerpc_opcodes): Use RA0 as appropriate. Add "lsdx", "lsdi", "stsdx", "stsdi", "lmd" and "stmd" insns. include/opcode/ * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. gas/testsuite/ Update gas/ppc/. ld/testsuite/ Update ld-powerpc/.
author: Alan Modra <amodra@gmail.com> 2004-03-16 00:59:35 +0000
committer: Alan Modra <amodra@gmail.com> 2004-03-16 00:59:35 +0000
commit: 974a217561b92209b973f8f06ac35b3cf6502a86 (patch)
tree: 47b64ba7f50ef41611dc62324400aaca2a08ab16
parent: 443600310d5b32102bfaa0495b4ee6a227933bb7 (diff)
download: binutils-gdb-974a217561b92209b973f8f06ac35b3cf6502a86.tar.gz
31 files changed, 1012 insertions, 946 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index bd964528572..5f7c30fad12 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,21 @@
+2004-03-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/ppc/altivec.d: Update.
+	* gas/ppc/altivec_xcoff.d: Update.
+	* gas/ppc/altivec_xcoff64.d: Update.
+	* gas/ppc/astest.d: Update.
+	* gas/ppc/astest2.d: Update.
+	* gas/ppc/astest2_64.d: Update.
+	* gas/ppc/astest64.d: Update.
+	* gas/ppc/booke.d: Update.
+	* gas/ppc/booke_xcoff.d: Update.
+	* gas/ppc/booke_xcoff64.d: Update.
+	* gas/ppc/e500.d: Update.
+	* gas/ppc/power4.d: Update.
+	* gas/ppc/test1elf32.d: Update.
+	* gas/ppc/test1elf64.d: Update.
+	* gas/ppc/test1xcoff32.d: Update.
+
 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 
 	* gas/i386/padlock.s: Pad with .p2align.
diff --git a/gas/testsuite/gas/ppc/altivec.d b/gas/testsuite/gas/ppc/altivec.d
index 72533cbcc82..ca234b1e632 100644
--- a/gas/testsuite/gas/ppc/altivec.d
+++ b/gas/testsuite/gas/ppc/altivec.d
@@ -7,9 +7,9 @@
 Disassembly of section \.text:
 
 00000000 <start>:
-   0:	7c 60 06 6c 	dss	3
+   0:	7c 60 06 6c 	dss     3
    4:	7e 00 06 6c 	dssall
-   8:	7c 25 22 ac 	dst	r5,r4,1
-   c:	7e 08 3a ac 	dstt	r8,r7,0
-  10:	7c 65 32 ec 	dstst	r5,r6,3
-  14:	7e 44 2a ec 	dststt	r4,r5,2
+   8:	7c 25 22 ac 	dst     r5,r4,1
+   c:	7e 08 3a ac 	dstt    r8,r7,0
+  10:	7c 65 32 ec 	dstst   r5,r6,3
+  14:	7e 44 2a ec 	dststt  r4,r5,2
diff --git a/gas/testsuite/gas/ppc/altivec_xcoff.d b/gas/testsuite/gas/ppc/altivec_xcoff.d
index 80626551b69..e8f0a33ed44 100644
--- a/gas/testsuite/gas/ppc/altivec_xcoff.d
+++ b/gas/testsuite/gas/ppc/altivec_xcoff.d
@@ -7,9 +7,9 @@
 Disassembly of section .text:
 
 0000000000000000 <.text>:
-   0:	7c 60 06 6c 	dss	3
+   0:	7c 60 06 6c 	dss     3
    4:	7e 00 06 6c 	dssall
-   8:	7c 25 22 ac 	dst	r5,r4,1
-   c:	7e 08 3a ac 	dstt	r8,r7,0
-  10:	7c 65 32 ec 	dstst	r5,r6,3
-  14:	7e 44 2a ec 	dststt	r4,r5,2
+   8:	7c 25 22 ac 	dst     r5,r4,1
+   c:	7e 08 3a ac 	dstt    r8,r7,0
+  10:	7c 65 32 ec 	dstst   r5,r6,3
+  14:	7e 44 2a ec 	dststt  r4,r5,2
diff --git a/gas/testsuite/gas/ppc/altivec_xcoff64.d b/gas/testsuite/gas/ppc/altivec_xcoff64.d
index 241cd86675c..af7fea46bbc 100644
--- a/gas/testsuite/gas/ppc/altivec_xcoff64.d
+++ b/gas/testsuite/gas/ppc/altivec_xcoff64.d
@@ -7,9 +7,9 @@
 Disassembly of section .text:
 
 0000000000000000 <.text>:
-   0:	7c 60 06 6c 	dss	3
+   0:	7c 60 06 6c 	dss     3
    4:	7e 00 06 6c 	dssall
-   8:	7c 25 22 ac 	dst	r5,r4,1
-   c:	7e 08 3a ac 	dstt	r8,r7,0
-  10:	7c 65 32 ec 	dstst	r5,r6,3
-  14:	7e 44 2a ec 	dststt	r4,r5,2
+   8:	7c 25 22 ac 	dst     r5,r4,1
+   c:	7e 08 3a ac 	dstt    r8,r7,0
+  10:	7c 65 32 ec 	dstst   r5,r6,3
+  14:	7e 44 2a ec 	dststt  r4,r5,2
diff --git a/gas/testsuite/gas/ppc/astest.d b/gas/testsuite/gas/ppc/astest.d
index 68aab554dff..758f9ce84c6 100644
--- a/gas/testsuite/gas/ppc/astest.d
+++ b/gas/testsuite/gas/ppc/astest.d
@@ -11,28 +11,28 @@ Disassembly of section \.text:
    8:	60 00 00 00 	nop
 
 0+000000c <a>:
-   c:	48 00 00 04 	b	10 <apfour>
+   c:	48 00 00 04 	b       10 <apfour>
 
 0+0000010 <apfour>:
-  10:	48 00 00 08 	b	18 <apfour\+0x8>
-  14:	48 00 00 00 	b	14 <apfour\+0x4>
+  10:	48 00 00 08 	b       18 <apfour\+0x8>
+  14:	48 00 00 00 	b       14 <apfour\+0x4>
 			14: R_PPC_REL24	x
-  18:	48 00 00 04 	b	1c <apfour\+0xc>
+  18:	48 00 00 04 	b       1c <apfour\+0xc>
 			18: R_PPC_REL24	\.data\+0x4
-  1c:	48 00 00 00 	b	1c <apfour\+0xc>
+  1c:	48 00 00 00 	b       1c <apfour\+0xc>
 			1c: R_PPC_REL24	z
-  20:	48 00 00 14 	b	34 <apfour\+0x24>
+  20:	48 00 00 14 	b       34 <apfour\+0x24>
 			20: R_PPC_REL24	z\+0x14
-  24:	48 00 00 04 	b	28 <apfour\+0x18>
-  28:	48 00 00 00 	b	28 <apfour\+0x18>
+  24:	48 00 00 04 	b       28 <apfour\+0x18>
+  28:	48 00 00 00 	b       28 <apfour\+0x18>
 			28: R_PPC_REL24	a
-  2c:	4b ff ff e4 	b	10 <apfour>
-  30:	48 00 00 04 	b	34 <apfour\+0x24>
+  2c:	4b ff ff e4 	b       10 <apfour>
+  30:	48 00 00 04 	b       34 <apfour\+0x24>
 			30: R_PPC_REL24	a\+0x4
-  34:	4b ff ff e0 	b	14 <apfour\+0x4>
-  38:	48 00 00 00 	b	38 <apfour\+0x28>
+  34:	4b ff ff e0 	b       14 <apfour\+0x4>
+  38:	48 00 00 00 	b       38 <apfour\+0x28>
 			38: R_PPC_LOCAL24PC	a
-  3c:	4b ff ff d4 	b	10 <apfour>
+  3c:	4b ff ff d4 	b       10 <apfour>
 
   40:	00 00 00 40 	\.long 0x40
 			40: R_PPC_ADDR32	\.text\+0x40
@@ -49,11 +49,11 @@ Disassembly of section \.text:
 			58: R_PPC_ADDR32	x
 			5c: R_PPC_ADDR32	y
 			60: R_PPC_ADDR32	z
-  64:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  64:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			64: R_PPC_ADDR32	x\+0xf+ffffffc
-  68:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  68:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			68: R_PPC_ADDR32	y\+0xf+ffffffc
-  6c:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  6c:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			6c: R_PPC_ADDR32	z\+0xf+ffffffc
   70:	ff ff ff 9c 	\.long 0xffffff9c
   74:	ff ff ff 9c 	\.long 0xffffff9c
@@ -61,7 +61,7 @@ Disassembly of section \.text:
 			78: R_PPC_ADDR32	a
 			7c: R_PPC_ADDR32	b
 			80: R_PPC_ADDR32	apfour
-  84:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  84:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
   88:	00 00 00 02 	\.long 0x2
 			88: R_PPC_ADDR32	apfour\+0x2
   8c:	00 00 00 00 	\.long 0x0
diff --git a/gas/testsuite/gas/ppc/astest2.d b/gas/testsuite/gas/ppc/astest2.d
index f46a1e194c5..273ca57bf85 100644
--- a/gas/testsuite/gas/ppc/astest2.d
+++ b/gas/testsuite/gas/ppc/astest2.d
@@ -9,26 +9,26 @@ Disassembly of section \.text:
    0:	60 00 00 00 	nop
    4:	60 00 00 00 	nop
    8:	60 00 00 00 	nop
-   c:	48 00 00 04 	b	10 <foo\+0x10>
-  10:	48 00 00 08 	b	18 <foo\+0x18>
-  14:	48 00 00 00 	b	14 <foo\+0x14>
+   c:	48 00 00 04 	b       10 <foo\+0x10>
+  10:	48 00 00 08 	b       18 <foo\+0x18>
+  14:	48 00 00 00 	b       14 <foo\+0x14>
 			14: R_PPC_REL24	x
-  18:	48 00 00 04 	b	1c <foo\+0x1c>
+  18:	48 00 00 04 	b       1c <foo\+0x1c>
 			18: R_PPC_REL24	\.data\+0x4
-  1c:	48 00 00 00 	b	1c <foo\+0x1c>
+  1c:	48 00 00 00 	b       1c <foo\+0x1c>
 			1c: R_PPC_REL24	z
-  20:	48 00 00 14 	b	34 <foo\+0x34>
+  20:	48 00 00 14 	b       34 <foo\+0x34>
 			20: R_PPC_REL24	z\+0x14
-  24:	48 00 00 04 	b	28 <foo\+0x28>
-  28:	48 00 00 00 	b	28 <foo\+0x28>
+  24:	48 00 00 04 	b       28 <foo\+0x28>
+  28:	48 00 00 00 	b       28 <foo\+0x28>
 			28: R_PPC_REL24	a
-  2c:	48 00 00 50 	b	7c <apfour>
-  30:	48 00 00 04 	b	34 <foo\+0x34>
+  2c:	48 00 00 50 	b       7c <apfour>
+  30:	48 00 00 04 	b       34 <foo\+0x34>
 			30: R_PPC_REL24	a\+0x4
-  34:	48 00 00 4c 	b	80 <apfour\+0x4>
-  38:	48 00 00 00 	b	38 <foo\+0x38>
+  34:	48 00 00 4c 	b       80 <apfour\+0x4>
+  38:	48 00 00 00 	b       38 <foo\+0x38>
 			38: R_PPC_LOCAL24PC	a
-  3c:	48 00 00 40 	b	7c <apfour>
+  3c:	48 00 00 40 	b       7c <apfour>
 
   40:	00 00 00 40 	\.long 0x40
 			40: R_PPC_ADDR32	\.text\+0x40
@@ -45,11 +45,11 @@ Disassembly of section \.text:
 			58: R_PPC_ADDR32	x
 			5c: R_PPC_ADDR32	y
 			60: R_PPC_ADDR32	z
-  64:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  64:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			64: R_PPC_ADDR32	x\+0xf+ffffffc
-  68:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  68:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			68: R_PPC_ADDR32	y\+0xf+ffffffc
-  6c:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  6c:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			6c: R_PPC_ADDR32	z\+0xf+ffffffc
   70:	00 00 00 08 	\.long 0x8
   74:	00 00 00 08 	\.long 0x8
@@ -62,19 +62,19 @@ Disassembly of section \.text:
 	\.\.\.
 			7c: R_PPC_ADDR32	b
 			80: R_PPC_ADDR32	apfour
-  84:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  84:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
   88:	00 00 00 02 	\.long 0x2
 			88: R_PPC_ADDR32	apfour\+0x2
   8c:	00 00 00 00 	\.long 0x0
   90:	60 00 00 00 	nop
-  94:	40 a5 ff fc 	ble-	cr1,90 <apfour\+0x14>
-  98:	41 a9 ff f8 	bgt-	cr2,90 <apfour\+0x14>
-  9c:	40 8d ff f4 	ble\+	cr3,90 <apfour\+0x14>
-  a0:	41 91 ff f0 	bgt\+	cr4,90 <apfour\+0x14>
-  a4:	40 95 00 10 	ble-	cr5,b4 <nop>
-  a8:	41 99 00 0c 	bgt-	cr6,b4 <nop>
-  ac:	40 bd 00 08 	ble\+	cr7,b4 <nop>
-  b0:	41 a1 00 04 	bgt\+	b4 <nop>
+  94:	40 a5 ff fc 	ble-    cr1,90 <apfour\+0x14>
+  98:	41 a9 ff f8 	bgt-    cr2,90 <apfour\+0x14>
+  9c:	40 8d ff f4 	ble\+    cr3,90 <apfour\+0x14>
+  a0:	41 91 ff f0 	bgt\+    cr4,90 <apfour\+0x14>
+  a4:	40 95 00 10 	ble-    cr5,b4 <nop>
+  a8:	41 99 00 0c 	bgt-    cr6,b4 <nop>
+  ac:	40 bd 00 08 	ble\+    cr7,b4 <nop>
+  b0:	41 a1 00 04 	bgt\+    b4 <nop>
 Disassembly of section \.data:
 
 0+0000000 <x>:
diff --git a/gas/testsuite/gas/ppc/astest2_64.d b/gas/testsuite/gas/ppc/astest2_64.d
index 3a3d7dbc207..bc3cddf22e2 100644
--- a/gas/testsuite/gas/ppc/astest2_64.d
+++ b/gas/testsuite/gas/ppc/astest2_64.d
@@ -9,23 +9,23 @@ Disassembly of section \.text:
    0:	60 00 00 00 	nop
    4:	60 00 00 00 	nop
    8:	60 00 00 00 	nop
-   c:	48 00 00 04 	b	10 <foo\+0x10>
-  10:	48 00 00 08 	b	18 <foo\+0x18>
-  14:	48 00 00 00 	b	14 <foo\+0x14>
+   c:	48 00 00 04 	b       10 <foo\+0x10>
+  10:	48 00 00 08 	b       18 <foo\+0x18>
+  14:	48 00 00 00 	b       14 <foo\+0x14>
 			14: R_PPC64_REL24	x
-  18:	48 00 00 04 	b	1c <foo\+0x1c>
+  18:	48 00 00 04 	b       1c <foo\+0x1c>
 			18: R_PPC64_REL24	\.data\+0x4
-  1c:	48 00 00 00 	b	1c <foo\+0x1c>
+  1c:	48 00 00 00 	b       1c <foo\+0x1c>
 			1c: R_PPC64_REL24	z
-  20:	48 00 00 14 	b	34 <foo\+0x34>
+  20:	48 00 00 14 	b       34 <foo\+0x34>
 			20: R_PPC64_REL24	z\+0x14
-  24:	48 00 00 04 	b	28 <foo\+0x28>
-  28:	48 00 00 00 	b	28 <foo\+0x28>
+  24:	48 00 00 04 	b       28 <foo\+0x28>
+  28:	48 00 00 00 	b       28 <foo\+0x28>
 			28: R_PPC64_REL24	a
-  2c:	48 00 00 48 	b	74 <apfour>
-  30:	48 00 00 04 	b	34 <foo\+0x34>
+  2c:	48 00 00 48 	b       74 <apfour>
+  30:	48 00 00 04 	b       34 <foo\+0x34>
 			30: R_PPC64_REL24	a\+0x4
-  34:	48 00 00 44 	b	78 <apfour\+0x4>
+  34:	48 00 00 44 	b       78 <apfour\+0x4>
   38:	00 00 00 38 	\.long 0x38
 			38: R_PPC64_ADDR32	\.text\+0x38
   3c:	00 00 00 44 	\.long 0x44
@@ -40,11 +40,11 @@ Disassembly of section \.text:
 			50: R_PPC64_ADDR32	x
 			54: R_PPC64_ADDR32	y
 			58: R_PPC64_ADDR32	z
-  5c:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  5c:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			5c: R_PPC64_ADDR32	x\+0xfffffffffffffffc
-  60:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  60:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			60: R_PPC64_ADDR32	y\+0xfffffffffffffffc
-  64:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  64:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			64: R_PPC64_ADDR32	z\+0xfffffffffffffffc
   68:	00 00 00 08 	\.long 0x8
   6c:	00 00 00 08 	\.long 0x8
@@ -57,7 +57,7 @@ Disassembly of section \.text:
 	\.\.\.
 			74: R_PPC64_ADDR32	b
 			78: R_PPC64_ADDR32	apfour
-  7c:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  7c:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
   80:	00 00 00 02 	\.long 0x2
 			80: R_PPC64_ADDR32	apfour\+0x2
   84:	00 00 00 00 	\.long 0x0
diff --git a/gas/testsuite/gas/ppc/astest64.d b/gas/testsuite/gas/ppc/astest64.d
index a87415a2bef..d66e72c1be1 100644
--- a/gas/testsuite/gas/ppc/astest64.d
+++ b/gas/testsuite/gas/ppc/astest64.d
@@ -11,25 +11,25 @@ Disassembly of section \.text:
    8:	60 00 00 00 	nop
 
 000000000000000c <a>:
-   c:	48 00 00 04 	b	10 <apfour>
+   c:	48 00 00 04 	b       10 <apfour>
 
 0000000000000010 <apfour>:
-  10:	48 00 00 08 	b	18 <apfour\+0x8>
-  14:	48 00 00 00 	b	14 <apfour\+0x4>
+  10:	48 00 00 08 	b       18 <apfour\+0x8>
+  14:	48 00 00 00 	b       14 <apfour\+0x4>
 			14: R_PPC64_REL24	x
-  18:	48 00 00 04 	b	1c <apfour\+0xc>
+  18:	48 00 00 04 	b       1c <apfour\+0xc>
 			18: R_PPC64_REL24	\.data\+0x4
-  1c:	48 00 00 00 	b	1c <apfour\+0xc>
+  1c:	48 00 00 00 	b       1c <apfour\+0xc>
 			1c: R_PPC64_REL24	z
-  20:	48 00 00 14 	b	34 <apfour\+0x24>
+  20:	48 00 00 14 	b       34 <apfour\+0x24>
 			20: R_PPC64_REL24	z\+0x14
-  24:	48 00 00 04 	b	28 <apfour\+0x18>
-  28:	48 00 00 00 	b	28 <apfour\+0x18>
+  24:	48 00 00 04 	b       28 <apfour\+0x18>
+  28:	48 00 00 00 	b       28 <apfour\+0x18>
 			28: R_PPC64_REL24	a
-  2c:	4b ff ff e4 	b	10 <apfour>
-  30:	48 00 00 04 	b	34 <apfour\+0x24>
+  2c:	4b ff ff e4 	b       10 <apfour>
+  30:	48 00 00 04 	b       34 <apfour\+0x24>
 			30: R_PPC64_REL24	a\+0x4
-  34:	4b ff ff e0 	b	14 <apfour\+0x4>
+  34:	4b ff ff e0 	b       14 <apfour\+0x4>
   38:	00 00 00 38 	\.long 0x38
 			38: R_PPC64_ADDR32	\.text\+0x38
   3c:	00 00 00 44 	\.long 0x44
@@ -44,11 +44,11 @@ Disassembly of section \.text:
 			50: R_PPC64_ADDR32	x
 			54: R_PPC64_ADDR32	y
 			58: R_PPC64_ADDR32	z
-  5c:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  5c:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			5c: R_PPC64_ADDR32	x\+0xfffffffffffffffc
-  60:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  60:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			60: R_PPC64_ADDR32	y\+0xfffffffffffffffc
-  64:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  64:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			64: R_PPC64_ADDR32	z\+0xfffffffffffffffc
   68:	ff ff ff a4 	\.long 0xffffffa4
   6c:	ff ff ff a4 	\.long 0xffffffa4
@@ -56,7 +56,7 @@ Disassembly of section \.text:
 			70: R_PPC64_ADDR32	a
 			74: R_PPC64_ADDR32	b
 			78: R_PPC64_ADDR32	apfour
-  7c:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  7c:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
   80:	00 00 00 02 	\.long 0x2
 			80: R_PPC64_ADDR32	apfour\+0x2
   84:	00 00 00 00 	\.long 0x0
diff --git a/gas/testsuite/gas/ppc/booke.d b/gas/testsuite/gas/ppc/booke.d
index 595424c18f4..a8d5c57202d 100644
--- a/gas/testsuite/gas/ppc/booke.d
+++ b/gas/testsuite/gas/ppc/booke.d
@@ -7,138 +7,138 @@
 Disassembly of section \.text:
 
 0+0000000 <start>:
-   0:	24 25 00 30 	bce	1,4\*cr1\+gt,30 <branch_target_1>
-   4:	24 46 00 3d 	bcel	2,4\*cr1\+eq,40 <branch_target_2>
-   8:	24 67 00 02 	bcea	3,4\*cr1\+so,0 <start>
+   0:	24 25 00 30 	bce     1,4\*cr1\+gt,30 <branch_target_1>
+   4:	24 46 00 3d 	bcel    2,4\*cr1\+eq,40 <branch_target_2>
+   8:	24 67 00 02 	bcea    3,4\*cr1\+so,0 <start>
 			8: R_PPC(64)?_ADDR14	branch_target_3
-   c:	24 88 00 03 	bcela	4,4\*cr2\+lt,0 <start>
+   c:	24 88 00 03 	bcela   4,4\*cr2\+lt,0 <start>
 			c: R_PPC(64)?_ADDR14	branch_target_4
-  10:	4c a9 00 22 	bclre	5,4\*cr2\+gt
-  14:	4c aa 00 23 	bclrel	5,4\*cr2\+eq
-  18:	4d 0b 04 22 	bcctre	8,4\*cr2\+so
-  1c:	4d 0c 04 23 	bcctrel	8,4\*cr3\+lt
-  20:	58 00 00 74 	be	94 <branch_target_5>
-  24:	58 00 00 89 	bel	ac <branch_target_6>
-  28:	58 00 00 02 	bea	0 <start>
+  10:	4c a9 00 22 	bclre   5,4\*cr2\+gt
+  14:	4c aa 00 23 	bclrel  5,4\*cr2\+eq
+  18:	4d 0b 04 22 	bcctre  8,4\*cr2\+so
+  1c:	4d 0c 04 23 	bcctrel 8,4\*cr3\+lt
+  20:	58 00 00 74 	be      94 <branch_target_5>
+  24:	58 00 00 89 	bel     ac <branch_target_6>
+  28:	58 00 00 02 	bea     0 <start>
 			28: R_PPC(64)?_ADDR24	branch_target_7
-  2c:	58 00 00 03 	bela	0 <start>
+  2c:	58 00 00 03 	bela    0 <start>
 			2c: R_PPC(64)?_ADDR24	branch_target_8
 
 0+0000030 <branch_target_1>:
-  30:	e9 09 00 80 	lbze	r8,8\(r9\)
-  34:	e9 8f 00 41 	lbzue	r12,4\(r15\)
-  38:	7c 86 40 fe 	lbzuxe	r4,r6,r8
-  3c:	7c 65 38 be 	lbzxe	r3,r5,r7
+  30:	e9 09 00 80 	lbze    r8,8\(r9\)
+  34:	e9 8f 00 41 	lbzue   r12,4\(r15\)
+  38:	7c 86 40 fe 	lbzuxe  r4,r6,r8
+  3c:	7c 65 38 be 	lbzxe   r3,r5,r7
 
 0+0000040 <branch_target_2>:
-  40:	f8 a6 06 40 	lde	r5,400\(r6\)
-  44:	f8 c7 07 11 	ldue	r6,452\(r7\)
-  48:	7c e8 4e 3e 	ldxe	r7,r8,r9
-  4c:	7d 4b 66 7e 	lduxe	r10,r11,r12
+  40:	f8 a6 06 40 	lde     r5,400\(r6\)
+  44:	f8 c7 07 11 	ldue    r6,452\(r7\)
+  48:	7c e8 4e 3e 	ldxe    r7,r8,r9
+  4c:	7d 4b 66 7e 	lduxe   r10,r11,r12
 
 0+0000050 <branch_target_3>:
-  50:	f9 81 02 06 	lfde	f12,128\(r1\)
-  54:	f8 25 00 47 	lfdue	f1,16\(r5\)
-  58:	7c a1 1c be 	lfdxe	f5,r1,r3
-  5c:	7c c2 24 fe 	lfduxe	f6,r2,r4
-  60:	f9 09 00 c4 	lfse	f8,48\(r9\)
-  64:	f9 2a 01 15 	lfsue	f9,68\(r10\)
-  68:	7d 44 44 7e 	lfsuxe	f10,r4,r8
-  6c:	7d 23 3c 3e 	lfsxe	f9,r3,r7
+  50:	f9 81 02 06 	lfde    f12,128\(r1\)
+  54:	f8 25 00 47 	lfdue   f1,16\(r5\)
+  58:	7c a1 1c be 	lfdxe   f5,r1,r3
+  5c:	7c c2 24 fe 	lfduxe  f6,r2,r4
+  60:	f9 09 00 c4 	lfse    f8,48\(r9\)
+  64:	f9 2a 01 15 	lfsue   f9,68\(r10\)
+  68:	7d 44 44 7e 	lfsuxe  f10,r4,r8
+  6c:	7d 23 3c 3e 	lfsxe   f9,r3,r7
 
 0+0000070 <branch_target_4>:
-  70:	e9 45 03 24 	lhae	r10,50\(r5\)
-  74:	e8 23 00 55 	lhaue	r1,5\(r3\)
-  78:	7c a1 1a fe 	lhauxe	r5,r1,r3
-  7c:	7f be fa be 	lhaxe	r29,r30,r31
-  80:	7c 22 1e 3c 	lhbrxe	r1,r2,r3
-  84:	e8 83 01 22 	lhze	r4,18\(r3\)
-  88:	e8 c9 01 43 	lhzue	r6,20\(r9\)
-  8c:	7c a7 4a 7e 	lhzuxe	r5,r7,r9
-  90:	7d 27 2a 3e 	lhzxe	r9,r7,r5
+  70:	e9 45 03 24 	lhae    r10,50\(r5\)
+  74:	e8 23 00 55 	lhaue   r1,5\(r3\)
+  78:	7c a1 1a fe 	lhauxe  r5,r1,r3
+  7c:	7f be fa be 	lhaxe   r29,r30,r31
+  80:	7c 22 1e 3c 	lhbrxe  r1,r2,r3
+  84:	e8 83 01 22 	lhze    r4,18\(r3\)
+  88:	e8 c9 01 43 	lhzue   r6,20\(r9\)
+  8c:	7c a7 4a 7e 	lhzuxe  r5,r7,r9
+  90:	7d 27 2a 3e 	lhzxe   r9,r7,r5
 
 0+0000094 <branch_target_5>:
-  94:	7d 4f a0 fc 	lwarxe	r10,r15,r20
-  98:	7c aa 94 3c 	lwbrxe	r5,r10,r18
-  9c:	eb 9d 00 46 	lwze	r28,4\(r29\)
-  a0:	e9 0a 02 87 	lwzue	r8,40\(r10\)
-  a4:	7c 66 48 7e 	lwzuxe	r3,r6,r9
-  a8:	7f dd e0 3e 	lwzxe	r30,r29,r28
+  94:	7d 4f a0 fc 	lwarxe  r10,r15,r20
+  98:	7c aa 94 3c 	lwbrxe  r5,r10,r18
+  9c:	eb 9d 00 46 	lwze    r28,4\(r29\)
+  a0:	e9 0a 02 87 	lwzue   r8,40\(r10\)
+  a4:	7c 66 48 7e 	lwzuxe  r3,r6,r9
+  a8:	7f dd e0 3e 	lwzxe   r30,r29,r28
 
 0+00000ac <branch_target_6>:
-  ac:	7c 06 3d fc 	dcbae	r6,r7
-  b0:	7c 08 48 bc 	dcbfe	r8,r9
-  b4:	7c 0a 5b bc 	dcbie	r10,r11
-  b8:	7c 08 f0 7c 	dcbste	r8,r30
-  bc:	7c c3 0a 3c 	dcbte	6,r3,r1
-  c0:	7c a4 11 fa 	dcbtste	5,r4,r2
-  c4:	7c 0f 77 fc 	dcbze	r15,r14
-  c8:	7c 03 27 bc 	icbie	r3,r4
-  cc:	7c a8 48 2c 	icbt	5,r8,r9
-  d0:	7c ca 78 3c 	icbte	6,r10,r15
-  d4:	7c a6 02 26 	mfapidi	r5,r6
-  d8:	7c 07 46 24 	tlbivax	r7,r8
-  dc:	7c 09 56 26 	tlbivaxe	r9,r10
-  e0:	7c 0b 67 24 	tlbsx	r11,r12
-  e4:	7c 0d 77 26 	tlbsxe	r13,r14
-  e8:	7c 00 07 a4 	tlbwe	
-  ec:	7c 00 07 a4 	tlbwe	
-  f0:	7c 21 0f a4 	tlbwe	r1,r1,1
+  ac:	7c 06 3d fc 	dcbae   r6,r7
+  b0:	7c 08 48 bc 	dcbfe   r8,r9
+  b4:	7c 0a 5b bc 	dcbie   r10,r11
+  b8:	7c 08 f0 7c 	dcbste  r8,r30
+  bc:	7c c3 0a 3c 	dcbte   6,r3,r1
+  c0:	7c a4 11 fa 	dcbtste 5,r4,r2
+  c4:	7c 0f 77 fc 	dcbze   r15,r14
+  c8:	7c 03 27 bc 	icbie   r3,r4
+  cc:	7c a8 48 2c 	icbt    5,r8,r9
+  d0:	7c ca 78 3c 	icbte   6,r10,r15
+  d4:	7c a6 02 26 	mfapidi r5,r6
+  d8:	7c 07 46 24 	tlbivax r7,r8
+  dc:	7c 09 56 26 	tlbivaxe r9,r10
+  e0:	7c 0b 67 24 	tlbsx   r11,r12
+  e4:	7c 0d 77 26 	tlbsxe  r13,r14
+  e8:	7c 00 07 a4 	tlbwe   
+  ec:	7c 00 07 a4 	tlbwe   
+  f0:	7c 21 0f a4 	tlbwe   r1,r1,1
 
 0+00000f4 <branch_target_7>:
-  f4:	7c 22 1b 14 	adde64	r1,r2,r3
-  f8:	7c 85 37 14 	adde64o	r4,r5,r6
-  fc:	7c e8 03 d4 	addme64	r7,r8
- 100:	7d 2a 07 d4 	addme64o	r9,r10
- 104:	7d 6c 03 94 	addze64	r11,r12
- 108:	7d ae 07 94 	addze64o	r13,r14
- 10c:	7e 80 04 40 	mcrxr64	cr5
- 110:	7d f0 8b 10 	subfe64	r15,r16,r17
- 114:	7e 53 a7 10 	subfe64o	r18,r19,r20
- 118:	7e b6 03 d0 	subfme64	r21,r22
- 11c:	7e f8 07 d0 	subfme64o	r23,r24
- 120:	7f 3a 03 90 	subfze64	r25,r26
- 124:	7f 7c 07 90 	subfze64o	r27,r28
+  f4:	7c 22 1b 14 	adde64  r1,r2,r3
+  f8:	7c 85 37 14 	adde64o r4,r5,r6
+  fc:	7c e8 03 d4 	addme64 r7,r8
+ 100:	7d 2a 07 d4 	addme64o r9,r10
+ 104:	7d 6c 03 94 	addze64 r11,r12
+ 108:	7d ae 07 94 	addze64o r13,r14
+ 10c:	7e 80 04 40 	mcrxr64 cr5
+ 110:	7d f0 8b 10 	subfe64 r15,r16,r17
+ 114:	7e 53 a7 10 	subfe64o r18,r19,r20
+ 118:	7e b6 03 d0 	subfme64 r21,r22
+ 11c:	7e f8 07 d0 	subfme64o r23,r24
+ 120:	7f 3a 03 90 	subfze64 r25,r26
+ 124:	7f 7c 07 90 	subfze64o r27,r28
 
 0+0000128 <branch_target_8>:
- 128:	e8 22 03 28 	stbe	r1,50\(r2\)
- 12c:	e8 64 02 89 	stbue	r3,40\(r4\)
- 130:	7c a6 39 fe 	stbuxe	r5,r6,r7
- 134:	7d 09 51 be 	stbxe	r8,r9,r10
- 138:	7d 6c 6b ff 	stdcxe\.	r11,r12,r13
- 13c:	f9 cf 00 78 	stde	r14,28\(r15\)
- 140:	fa 11 00 59 	stdue	r16,20\(r17\)
- 144:	7e 53 a7 3e 	stdxe	r18,r19,r20
- 148:	7e b6 bf 7e 	stduxe	r21,r22,r23
- 14c:	f8 38 00 3e 	stfde	f1,12\(r24\)
- 150:	f8 59 00 0f 	stfdue	f2,0\(r25\)
- 154:	7c 7a dd be 	stfdxe	f3,r26,r27
- 158:	7c 9c ed fe 	stfduxe	f4,r28,r29
- 15c:	7c be ff be 	stfiwxe	f5,r30,r31
- 160:	f8 de 00 6c 	stfse	f6,24\(r30\)
- 164:	f8 fd 00 5d 	stfsue	f7,20\(r29\)
- 168:	7d 1c dd 3e 	stfsxe	f8,r28,r27
- 16c:	7d 3a cd 7e 	stfsuxe	f9,r26,r25
- 170:	7f 17 b7 3c 	sthbrxe	r24,r23,r22
- 174:	ea b4 01 ea 	sthe	r21,30\(r20\)
- 178:	ea 72 02 8b 	sthue	r19,40\(r18\)
- 17c:	7e 30 7b 7e 	sthuxe	r17,r16,r15
- 180:	7d cd 63 3e 	sthxe	r14,r13,r12
- 184:	7d 6a 4d 3c 	stwbrxe	r11,r10,r9
- 188:	7d 07 31 3d 	stwcxe\.	r8,r7,r6
- 18c:	e8 a4 03 2e 	stwe	r5,50\(r4\)
- 190:	e8 62 02 8f 	stwue	r3,40\(r2\)
- 194:	7c 22 19 7e 	stwuxe	r1,r2,r3
- 198:	7c 85 31 3e 	stwxe	r4,r5,r6
+ 128:	e8 22 03 28 	stbe    r1,50\(r2\)
+ 12c:	e8 64 02 89 	stbue   r3,40\(r4\)
+ 130:	7c a6 39 fe 	stbuxe  r5,r6,r7
+ 134:	7d 09 51 be 	stbxe   r8,r9,r10
+ 138:	7d 6c 6b ff 	stdcxe\. r11,r12,r13
+ 13c:	f9 cf 00 78 	stde    r14,28\(r15\)
+ 140:	fa 11 00 59 	stdue   r16,20\(r17\)
+ 144:	7e 53 a7 3e 	stdxe   r18,r19,r20
+ 148:	7e b6 bf 7e 	stduxe  r21,r22,r23
+ 14c:	f8 38 00 3e 	stfde   f1,12\(r24\)
+ 150:	f8 59 00 0f 	stfdue  f2,0\(r25\)
+ 154:	7c 7a dd be 	stfdxe  f3,r26,r27
+ 158:	7c 9c ed fe 	stfduxe f4,r28,r29
+ 15c:	7c be ff be 	stfiwxe f5,r30,r31
+ 160:	f8 de 00 6c 	stfse   f6,24\(r30\)
+ 164:	f8 fd 00 5d 	stfsue  f7,20\(r29\)
+ 168:	7d 1c dd 3e 	stfsxe  f8,r28,r27
+ 16c:	7d 3a cd 7e 	stfsuxe f9,r26,r25
+ 170:	7f 17 b7 3c 	sthbrxe r24,r23,r22
+ 174:	ea b4 01 ea 	sthe    r21,30\(r20\)
+ 178:	ea 72 02 8b 	sthue   r19,40\(r18\)
+ 17c:	7e 30 7b 7e 	sthuxe  r17,r16,r15
+ 180:	7d cd 63 3e 	sthxe   r14,r13,r12
+ 184:	7d 6a 4d 3c 	stwbrxe r11,r10,r9
+ 188:	7d 07 31 3d 	stwcxe\. r8,r7,r6
+ 18c:	e8 a4 03 2e 	stwe    r5,50\(r4\)
+ 190:	e8 62 02 8f 	stwue   r3,40\(r2\)
+ 194:	7c 22 19 7e 	stwuxe  r1,r2,r3
+ 198:	7c 85 31 3e 	stwxe   r4,r5,r6
  19c:	4c 00 00 66 	rfci
- 1a0:	7c 60 01 06 	wrtee	r3
- 1a4:	7c 00 81 46 	wrteei	1
- 1a8:	7c 85 02 06 	mfdcrx	r4,r5
- 1ac:	7c aa 3a 86 	mfdcr	r5,234
- 1b0:	7c e6 03 06 	mtdcrx	r6,r7
- 1b4:	7d 10 6b 86 	mtdcr	432,r8
+ 1a0:	7c 60 01 06 	wrtee   r3
+ 1a4:	7c 00 81 46 	wrteei  1
+ 1a8:	7c 85 02 06 	mfdcrx  r4,r5
+ 1ac:	7c aa 3a 86 	mfdcr   r5,234
+ 1b0:	7c e6 03 06 	mtdcrx  r6,r7
+ 1b4:	7d 10 6b 86 	mtdcr   432,r8
  1b8:	7c 00 04 ac 	msync
- 1bc:	7c 09 55 ec 	dcba	r9,r10
- 1c0:	7c 00 06 ac 	mbar	
- 1c4:	7c 00 06 ac 	mbar	
- 1c8:	7c 20 06 ac 	mbar	1
+ 1bc:	7c 09 55 ec 	dcba    r9,r10
+ 1c0:	7c 00 06 ac 	mbar    
+ 1c4:	7c 00 06 ac 	mbar    
+ 1c8:	7c 20 06 ac 	mbar    1
diff --git a/gas/testsuite/gas/ppc/booke_xcoff.d b/gas/testsuite/gas/ppc/booke_xcoff.d
index 50bbf9a1a8e..30a594ba484 100644
--- a/gas/testsuite/gas/ppc/booke_xcoff.d
+++ b/gas/testsuite/gas/ppc/booke_xcoff.d
@@ -7,22 +7,22 @@
 Disassembly of section .text:
 
 0000000000000000 <.text>:
-   0:	7c 22 3f 64 	tlbre	r1,r2,7
-   4:	7c be 1f a4 	tlbwe	r5,r30,3
-   8:	7c a8 48 2c 	icbt	5,r8,r9
-   c:	7c a6 02 26 	mfapidi	r5,r6
-  10:	7c 07 46 24 	tlbivax	r7,r8
-  14:	7c 09 56 26 	tlbivaxe	r9,r10
-  18:	7c 0b 67 24 	tlbsx	r11,r12
-  1c:	7c 0d 77 26 	tlbsxe	r13,r14
-  20:	7e 80 04 40 	mcrxr64	cr5
+   0:	7c 22 3f 64 	tlbre   r1,r2,7
+   4:	7c be 1f a4 	tlbwe   r5,r30,3
+   8:	7c a8 48 2c 	icbt    5,r8,r9
+   c:	7c a6 02 26 	mfapidi r5,r6
+  10:	7c 07 46 24 	tlbivax r7,r8
+  14:	7c 09 56 26 	tlbivaxe r9,r10
+  18:	7c 0b 67 24 	tlbsx   r11,r12
+  1c:	7c 0d 77 26 	tlbsxe  r13,r14
+  20:	7e 80 04 40 	mcrxr64 cr5
   24:	4c 00 00 66 	rfci
-  28:	7c 60 01 06 	wrtee	r3
-  2c:	7c 00 81 46 	wrteei	1
-  30:	7c 85 02 06 	mfdcrx	r4,r5
-  34:	7c aa 3a 86 	mfdcr	r5,234
-  38:	7c e6 03 06 	mtdcrx	r6,r7
-  3c:	7d 10 6b 86 	mtdcr	432,r8
-  40:	7c 00 04 ac 	sync	
-  44:	7c 09 55 ec 	dcba	r9,r10
+  28:	7c 60 01 06 	wrtee   r3
+  2c:	7c 00 81 46 	wrteei  1
+  30:	7c 85 02 06 	mfdcrx  r4,r5
+  34:	7c aa 3a 86 	mfdcr   r5,234
+  38:	7c e6 03 06 	mtdcrx  r6,r7
+  3c:	7d 10 6b 86 	mtdcr   432,r8
+  40:	7c 00 04 ac 	sync    
+  44:	7c 09 55 ec 	dcba    r9,r10
   48:	7c 00 06 ac 	eieio
diff --git a/gas/testsuite/gas/ppc/booke_xcoff64.d b/gas/testsuite/gas/ppc/booke_xcoff64.d
index 803fa57552d..646ce9df92b 100644
--- a/gas/testsuite/gas/ppc/booke_xcoff64.d
+++ b/gas/testsuite/gas/ppc/booke_xcoff64.d
@@ -7,119 +7,119 @@
 Disassembly of section .text:
 
 0000000000000000 <.text>:
-   0:	7c 22 3f 64 	tlbre	r1,r2,7
-   4:	7c be 1f a4 	tlbwe	r5,r30,3
-   8:	24 25 00 30 	bce	1,4\*cr1\+gt,38 <.text\+0x38>
-   c:	24 46 00 3d 	bcel	2,4\*cr1\+eq,48 <.text\+0x48>
-  10:	24 67 00 5a 	bcea	3,4\*cr1\+so,58 <.text\+0x58>
+   0:	7c 22 3f 64 	tlbre   r1,r2,7
+   4:	7c be 1f a4 	tlbwe   r5,r30,3
+   8:	24 25 00 30 	bce     1,4\*cr1\+gt,38 <.text\+0x38>
+   c:	24 46 00 3d 	bcel    2,4\*cr1\+eq,48 <.text\+0x48>
+  10:	24 67 00 5a 	bcea    3,4\*cr1\+so,58 <.text\+0x58>
 			12: R_BA_16	.text
-  14:	24 88 00 7b 	bcela	4,4\*cr2,78 <.text\+0x78>
+  14:	24 88 00 7b 	bcela   4,4\*cr2,78 <.text\+0x78>
 			16: R_BA_16	.text
-  18:	4c a9 00 22 	bclre	5,4\*cr2\+gt
-  1c:	4c aa 00 23 	bclrel	5,4\*cr2\+eq
-  20:	4d 0b 04 22 	bcctre	8,4\*cr2\+so
-  24:	4d 0c 04 23 	bcctrel	8,4\*cr3
-  28:	58 00 00 74 	be	9c <.text\+0x9c>
-  2c:	58 00 00 89 	bel	b4 <.text\+0xb4>
-  30:	58 00 00 f2 	bea	f0 <.text\+0xf0>
+  18:	4c a9 00 22 	bclre   5,4\*cr2\+gt
+  1c:	4c aa 00 23 	bclrel  5,4\*cr2\+eq
+  20:	4d 0b 04 22 	bcctre  8,4\*cr2\+so
+  24:	4d 0c 04 23 	bcctrel 8,4\*cr3
+  28:	58 00 00 74 	be      9c <.text\+0x9c>
+  2c:	58 00 00 89 	bel     b4 <.text\+0xb4>
+  30:	58 00 00 f2 	bea     f0 <.text\+0xf0>
 			30: R_BA_26	.text
-  34:	58 00 01 27 	bela	124 <.text\+0x124>
+  34:	58 00 01 27 	bela    124 <.text\+0x124>
 			34: R_BA_26	.text
-  38:	e9 09 00 80 	lbze	r8,8\(r9\)
-  3c:	e9 8f 00 41 	lbzue	r12,4\(r15\)
-  40:	7c 86 40 fe 	lbzuxe	r4,r6,r8
-  44:	7c 65 38 be 	lbzxe	r3,r5,r7
-  48:	f8 a6 06 40 	lde	r5,400\(r6\)
-  4c:	f8 c7 07 11 	ldue	r6,452\(r7\)
-  50:	7c e8 4e 3e 	ldxe	r7,r8,r9
-  54:	7d 4b 66 7e 	lduxe	r10,r11,r12
-  58:	f9 81 02 06 	lfde	f12,128\(r1\)
-  5c:	f8 25 00 47 	lfdue	f1,16\(r5\)
-  60:	7c a1 1c be 	lfdxe	f5,r1,r3
-  64:	7c c2 24 fe 	lfduxe	f6,r2,r4
-  68:	f9 09 00 c4 	lfse	f8,48\(r9\)
-  6c:	f9 2a 01 15 	lfsue	f9,68\(r10\)
-  70:	7d 44 44 7e 	lfsuxe	f10,r4,r8
-  74:	7d 23 3c 3e 	lfsxe	f9,r3,r7
-  78:	e9 45 03 24 	lhae	r10,50\(r5\)
-  7c:	e8 23 00 55 	lhaue	r1,5\(r3\)
-  80:	7c a1 1a fe 	lhauxe	r5,r1,r3
-  84:	7f be fa be 	lhaxe	r29,r30,r31
-  88:	7c 22 1e 3c 	lhbrxe	r1,r2,r3
-  8c:	e8 83 01 22 	lhze	r4,18\(r3\)
-  90:	e8 c9 01 43 	lhzue	r6,20\(r9\)
-  94:	7c a7 4a 7e 	lhzuxe	r5,r7,r9
-  98:	7d 27 2a 3e 	lhzxe	r9,r7,r5
-  9c:	7d 4f a0 fc 	lwarxe	r10,r15,r20
-  a0:	7c aa 94 3c 	lwbrxe	r5,r10,r18
-  a4:	eb 9d 00 46 	lwze	r28,4\(r29\)
-  a8:	e9 0a 02 87 	lwzue	r8,40\(r10\)
-  ac:	7c 66 48 7e 	lwzuxe	r3,r6,r9
-  b0:	7f dd e0 3e 	lwzxe	r30,r29,r28
-  b4:	7c 06 3d fc 	dcbae	r6,r7
-  b8:	7c 08 48 bc 	dcbfe	r8,r9
-  bc:	7c 0a 5b bc 	dcbie	r10,r11
-  c0:	7c 08 f0 7c 	dcbste	r8,r30
-  c4:	7c c3 0a 3c 	dcbte	6,r3,r1
-  c8:	7c a4 11 fa 	dcbtste	5,r4,r2
-  cc:	7c 0f 77 fc 	dcbze	r15,r14
-  d0:	7c 03 27 bc 	icbie	r3,r4
-  d4:	7c a8 48 2c 	icbt	5,r8,r9
-  d8:	7c ca 78 3c 	icbte	6,r10,r15
-  dc:	7c a6 02 26 	mfapidi	r5,r6
-  e0:	7c 07 46 24 	tlbivax	r7,r8
-  e4:	7c 09 56 26 	tlbivaxe	r9,r10
-  e8:	7c 0b 67 24 	tlbsx	r11,r12
-  ec:	7c 0d 77 26 	tlbsxe	r13,r14
-  f0:	7c 22 1b 14 	adde64	r1,r2,r3
-  f4:	7c 85 37 14 	adde64o	r4,r5,r6
-  f8:	7c e8 03 d4 	addme64	r7,r8
-  fc:	7d 2a 07 d4 	addme64o	r9,r10
- 100:	7d 6c 03 94 	addze64	r11,r12
- 104:	7d ae 07 94 	addze64o	r13,r14
- 108:	7e 80 04 40 	mcrxr64	cr5
- 10c:	7d f0 8b 10 	subfe64	r15,r16,r17
- 110:	7e 53 a7 10 	subfe64o	r18,r19,r20
- 114:	7e b6 03 d0 	subfme64	r21,r22
- 118:	7e f8 07 d0 	subfme64o	r23,r24
- 11c:	7f 3a 03 90 	subfze64	r25,r26
- 120:	7f 7c 07 90 	subfze64o	r27,r28
- 124:	e8 22 03 28 	stbe	r1,50\(r2\)
- 128:	e8 64 02 89 	stbue	r3,40\(r4\)
- 12c:	7c a6 39 fe 	stbuxe	r5,r6,r7
- 130:	7d 09 51 be 	stbxe	r8,r9,r10
- 134:	7d 6c 6b ff 	stdcxe.	r11,r12,r13
- 138:	f9 cf 00 78 	stde	r14,28\(r15\)
- 13c:	fa 11 00 59 	stdue	r16,20\(r17\)
- 140:	7e 53 a7 3e 	stdxe	r18,r19,r20
- 144:	7e b6 bf 7e 	stduxe	r21,r22,r23
- 148:	f8 38 00 3e 	stfde	f1,12\(r24\)
- 14c:	f8 59 00 0f 	stfdue	f2,0\(r25\)
- 150:	7c 7a dd be 	stfdxe	f3,r26,r27
- 154:	7c 9c ed fe 	stfduxe	f4,r28,r29
- 158:	7c be ff be 	stfiwxe	f5,r30,r31
- 15c:	f8 de 00 6c 	stfse	f6,24\(r30\)
- 160:	f8 fd 00 5d 	stfsue	f7,20\(r29\)
- 164:	7d 1c dd 3e 	stfsxe	f8,r28,r27
- 168:	7d 3a cd 7e 	stfsuxe	f9,r26,r25
- 16c:	7f 17 b7 3c 	sthbrxe	r24,r23,r22
- 170:	ea b4 01 ea 	sthe	r21,30\(r20\)
- 174:	ea 72 02 8b 	sthue	r19,40\(r18\)
- 178:	7e 30 7b 7e 	sthuxe	r17,r16,r15
- 17c:	7d cd 63 3e 	sthxe	r14,r13,r12
- 180:	7d 6a 4d 3c 	stwbrxe	r11,r10,r9
- 184:	7d 07 31 3d 	stwcxe.	r8,r7,r6
- 188:	e8 a4 03 2e 	stwe	r5,50\(r4\)
- 18c:	e8 62 02 8f 	stwue	r3,40\(r2\)
- 190:	7c 22 19 7e 	stwuxe	r1,r2,r3
- 194:	7c 85 31 3e 	stwxe	r4,r5,r6
+  38:	e9 09 00 80 	lbze    r8,8\(r9\)
+  3c:	e9 8f 00 41 	lbzue   r12,4\(r15\)
+  40:	7c 86 40 fe 	lbzuxe  r4,r6,r8
+  44:	7c 65 38 be 	lbzxe   r3,r5,r7
+  48:	f8 a6 06 40 	lde     r5,400\(r6\)
+  4c:	f8 c7 07 11 	ldue    r6,452\(r7\)
+  50:	7c e8 4e 3e 	ldxe    r7,r8,r9
+  54:	7d 4b 66 7e 	lduxe   r10,r11,r12
+  58:	f9 81 02 06 	lfde    f12,128\(r1\)
+  5c:	f8 25 00 47 	lfdue   f1,16\(r5\)
+  60:	7c a1 1c be 	lfdxe   f5,r1,r3
+  64:	7c c2 24 fe 	lfduxe  f6,r2,r4
+  68:	f9 09 00 c4 	lfse    f8,48\(r9\)
+  6c:	f9 2a 01 15 	lfsue   f9,68\(r10\)
+  70:	7d 44 44 7e 	lfsuxe  f10,r4,r8
+  74:	7d 23 3c 3e 	lfsxe   f9,r3,r7
+  78:	e9 45 03 24 	lhae    r10,50\(r5\)
+  7c:	e8 23 00 55 	lhaue   r1,5\(r3\)
+  80:	7c a1 1a fe 	lhauxe  r5,r1,r3
+  84:	7f be fa be 	lhaxe   r29,r30,r31
+  88:	7c 22 1e 3c 	lhbrxe  r1,r2,r3
+  8c:	e8 83 01 22 	lhze    r4,18\(r3\)
+  90:	e8 c9 01 43 	lhzue   r6,20\(r9\)
+  94:	7c a7 4a 7e 	lhzuxe  r5,r7,r9
+  98:	7d 27 2a 3e 	lhzxe   r9,r7,r5
+  9c:	7d 4f a0 fc 	lwarxe  r10,r15,r20
+  a0:	7c aa 94 3c 	lwbrxe  r5,r10,r18
+  a4:	eb 9d 00 46 	lwze    r28,4\(r29\)
+  a8:	e9 0a 02 87 	lwzue   r8,40\(r10\)
+  ac:	7c 66 48 7e 	lwzuxe  r3,r6,r9
+  b0:	7f dd e0 3e 	lwzxe   r30,r29,r28
+  b4:	7c 06 3d fc 	dcbae   r6,r7
+  b8:	7c 08 48 bc 	dcbfe   r8,r9
+  bc:	7c 0a 5b bc 	dcbie   r10,r11
+  c0:	7c 08 f0 7c 	dcbste  r8,r30
+  c4:	7c c3 0a 3c 	dcbte   6,r3,r1
+  c8:	7c a4 11 fa 	dcbtste 5,r4,r2
+  cc:	7c 0f 77 fc 	dcbze   r15,r14
+  d0:	7c 03 27 bc 	icbie   r3,r4
+  d4:	7c a8 48 2c 	icbt    5,r8,r9
+  d8:	7c ca 78 3c 	icbte   6,r10,r15
+  dc:	7c a6 02 26 	mfapidi r5,r6
+  e0:	7c 07 46 24 	tlbivax r7,r8
+  e4:	7c 09 56 26 	tlbivaxe r9,r10
+  e8:	7c 0b 67 24 	tlbsx   r11,r12
+  ec:	7c 0d 77 26 	tlbsxe  r13,r14
+  f0:	7c 22 1b 14 	adde64  r1,r2,r3
+  f4:	7c 85 37 14 	adde64o r4,r5,r6
+  f8:	7c e8 03 d4 	addme64 r7,r8
+  fc:	7d 2a 07 d4 	addme64o r9,r10
+ 100:	7d 6c 03 94 	addze64 r11,r12
+ 104:	7d ae 07 94 	addze64o r13,r14
+ 108:	7e 80 04 40 	mcrxr64 cr5
+ 10c:	7d f0 8b 10 	subfe64 r15,r16,r17
+ 110:	7e 53 a7 10 	subfe64o r18,r19,r20
+ 114:	7e b6 03 d0 	subfme64 r21,r22
+ 118:	7e f8 07 d0 	subfme64o r23,r24
+ 11c:	7f 3a 03 90 	subfze64 r25,r26
+ 120:	7f 7c 07 90 	subfze64o r27,r28
+ 124:	e8 22 03 28 	stbe    r1,50\(r2\)
+ 128:	e8 64 02 89 	stbue   r3,40\(r4\)
+ 12c:	7c a6 39 fe 	stbuxe  r5,r6,r7
+ 130:	7d 09 51 be 	stbxe   r8,r9,r10
+ 134:	7d 6c 6b ff 	stdcxe. r11,r12,r13
+ 138:	f9 cf 00 78 	stde    r14,28\(r15\)
+ 13c:	fa 11 00 59 	stdue   r16,20\(r17\)
+ 140:	7e 53 a7 3e 	stdxe   r18,r19,r20
+ 144:	7e b6 bf 7e 	stduxe  r21,r22,r23
+ 148:	f8 38 00 3e 	stfde   f1,12\(r24\)
+ 14c:	f8 59 00 0f 	stfdue  f2,0\(r25\)
+ 150:	7c 7a dd be 	stfdxe  f3,r26,r27
+ 154:	7c 9c ed fe 	stfduxe f4,r28,r29
+ 158:	7c be ff be 	stfiwxe f5,r30,r31
+ 15c:	f8 de 00 6c 	stfse   f6,24\(r30\)
+ 160:	f8 fd 00 5d 	stfsue  f7,20\(r29\)
+ 164:	7d 1c dd 3e 	stfsxe  f8,r28,r27
+ 168:	7d 3a cd 7e 	stfsuxe f9,r26,r25
+ 16c:	7f 17 b7 3c 	sthbrxe r24,r23,r22
+ 170:	ea b4 01 ea 	sthe    r21,30\(r20\)
+ 174:	ea 72 02 8b 	sthue   r19,40\(r18\)
+ 178:	7e 30 7b 7e 	sthuxe  r17,r16,r15
+ 17c:	7d cd 63 3e 	sthxe   r14,r13,r12
+ 180:	7d 6a 4d 3c 	stwbrxe r11,r10,r9
+ 184:	7d 07 31 3d 	stwcxe. r8,r7,r6
+ 188:	e8 a4 03 2e 	stwe    r5,50\(r4\)
+ 18c:	e8 62 02 8f 	stwue   r3,40\(r2\)
+ 190:	7c 22 19 7e 	stwuxe  r1,r2,r3
+ 194:	7c 85 31 3e 	stwxe   r4,r5,r6
  198:	4c 00 00 66 	rfci
- 19c:	7c 60 01 06 	wrtee	r3
- 1a0:	7c 00 81 46 	wrteei	1
- 1a4:	7c 85 02 06 	mfdcrx	r4,r5
- 1a8:	7c aa 3a 86 	mfdcr	r5,234
- 1ac:	7c e6 03 06 	mtdcrx	r6,r7
- 1b0:	7d 10 6b 86 	mtdcr	432,r8
- 1b4:	7c 00 04 ac 	sync	
- 1b8:	7c 09 55 ec 	dcba	r9,r10
+ 19c:	7c 60 01 06 	wrtee   r3
+ 1a0:	7c 00 81 46 	wrteei  1
+ 1a4:	7c 85 02 06 	mfdcrx  r4,r5
+ 1a8:	7c aa 3a 86 	mfdcr   r5,234
+ 1ac:	7c e6 03 06 	mtdcrx  r6,r7
+ 1b0:	7d 10 6b 86 	mtdcr   432,r8
+ 1b4:	7c 00 04 ac 	sync    
+ 1b8:	7c 09 55 ec 	dcba    r9,r10
  1bc:	7c 00 06 ac 	eieio
diff --git a/gas/testsuite/gas/ppc/e500.d b/gas/testsuite/gas/ppc/e500.d
index 6b74285ba2b..b48502060da 100644
--- a/gas/testsuite/gas/ppc/e500.d
+++ b/gas/testsuite/gas/ppc/e500.d
@@ -7,15 +7,15 @@
 Disassembly of section \.text:
 
 0+0000000 <start>:
-   0:	7c 43 25 de 	isel	r2,r3,r4,23
-   4:	7c 85 33 0c 	dcblc	4,r5,r6
-   8:	7c e8 49 4c 	dcbtls	7,r8,r9
-   c:	7d 4b 61 0c 	dcbtstls	10,r11,r12
-  10:	7d ae 7b cc 	icbtls	13,r14,r15
-  14:	7e 11 91 cc 	icblc	16,r17,r18
-  18:	7c 89 33 9c 	mtpmr	201,r4
-  1c:	7c ab 32 9c 	mfpmr	r5,203
+   0:	7c 43 25 de 	isel    r2,r3,r4,23
+   4:	7c 85 33 0c 	dcblc   4,r5,r6
+   8:	7c e8 49 4c 	dcbtls  7,r8,r9
+   c:	7d 4b 61 0c 	dcbtstls 10,r11,r12
+  10:	7d ae 7b cc 	icbtls  13,r14,r15
+  14:	7e 11 91 cc 	icblc   16,r17,r18
+  18:	7c 89 33 9c 	mtpmr   201,r4
+  1c:	7c ab 32 9c 	mfpmr   r5,203
   20:	7c 00 04 0c 	bblels
   24:	7c 00 04 4c 	bbelr
-  28:	7d 00 83 a6 	mtspefscr	r8
-  2c:	7d 20 82 a6 	mfspefscr	r9
+  28:	7d 00 83 a6 	mtspefscr r8
+  2c:	7d 20 82 a6 	mfspefscr r9
diff --git a/gas/testsuite/gas/ppc/power4.d b/gas/testsuite/gas/ppc/power4.d
index e42a81b8ce6..6094848ee5d 100644
--- a/gas/testsuite/gas/ppc/power4.d
+++ b/gas/testsuite/gas/ppc/power4.d
@@ -34,68 +34,68 @@ SYMBOL TABLE:
 Disassembly of section \.text:
 
 0+ <\.text>:
- +0:	e0 83 00 00 	lq	r4,0\(r3\)
+ +0:	e0 83 00 00 	lq      r4,0\(r3\)
 			2: R_PPC64_ADDR16_LO_DS	dsym0
- +4:	e0 83 00 00 	lq	r4,0\(r3\)
+ +4:	e0 83 00 00 	lq      r4,0\(r3\)
 			6: R_PPC64_ADDR16_LO_DS	dsym1
- +8:	e0 83 00 00 	lq	r4,0\(r3\)
+ +8:	e0 83 00 00 	lq      r4,0\(r3\)
 			a: R_PPC64_ADDR16_LO_DS	usym0
- +c:	e0 83 00 00 	lq	r4,0\(r3\)
+ +c:	e0 83 00 00 	lq      r4,0\(r3\)
 			e: R_PPC64_ADDR16_LO_DS	usym1
- +10:	e0 83 00 00 	lq	r4,0\(r3\)
+ +10:	e0 83 00 00 	lq      r4,0\(r3\)
 			12: R_PPC64_ADDR16_LO_DS	esym0
- +14:	e0 83 00 00 	lq	r4,0\(r3\)
+ +14:	e0 83 00 00 	lq      r4,0\(r3\)
 			16: R_PPC64_ADDR16_LO_DS	esym1
- +18:	e0 82 00 00 	lq	r4,0\(r2\)
+ +18:	e0 82 00 00 	lq      r4,0\(r2\)
 			1a: R_PPC64_TOC16_DS	\.toc
- +1c:	e0 82 00 00 	lq	r4,0\(r2\)
+ +1c:	e0 82 00 00 	lq      r4,0\(r2\)
 			1e: R_PPC64_TOC16_DS	\.toc\+0x8
- +20:	e0 82 00 10 	lq	r4,16\(r2\)
+ +20:	e0 82 00 10 	lq      r4,16\(r2\)
 			22: R_PPC64_TOC16_DS	\.toc\+0x10
- +24:	e0 82 00 10 	lq	r4,16\(r2\)
+ +24:	e0 82 00 10 	lq      r4,16\(r2\)
 			26: R_PPC64_TOC16_DS	\.toc\+0x18
- +28:	e0 82 00 20 	lq	r4,32\(r2\)
+ +28:	e0 82 00 20 	lq      r4,32\(r2\)
 			2a: R_PPC64_TOC16_DS	\.toc\+0x20
- +2c:	e0 82 00 20 	lq	r4,32\(r2\)
+ +2c:	e0 82 00 20 	lq      r4,32\(r2\)
 			2e: R_PPC64_TOC16_DS	\.toc\+0x28
- +30:	e0 c2 00 20 	lq	r6,32\(r2\)
+ +30:	e0 c2 00 20 	lq      r6,32\(r2\)
 			32: R_PPC64_TOC16_LO_DS	\.toc\+0x28
- +34:	e0 80 00 00 	lq	r4,0\(r0\)
+ +34:	e0 80 00 00 	lq      r4,0\(0\)
 			36: R_PPC64_ADDR16_LO_DS	\.text
- +38:	e0 c3 00 00 	lq	r6,0\(r3\)
+ +38:	e0 c3 00 00 	lq      r6,0\(r3\)
 			3a: R_PPC64_GOT16_DS	dsym0
- +3c:	e0 c3 00 00 	lq	r6,0\(r3\)
+ +3c:	e0 c3 00 00 	lq      r6,0\(r3\)
 			3e: R_PPC64_GOT16_LO_DS	dsym0
- +40:	e0 c3 00 00 	lq	r6,0\(r3\)
+ +40:	e0 c3 00 00 	lq      r6,0\(r3\)
 			42: R_PPC64_PLT16_LO_DS	dsym0
- +44:	e0 c3 00 00 	lq	r6,0\(r3\)
+ +44:	e0 c3 00 00 	lq      r6,0\(r3\)
 			46: R_PPC64_SECTOFF_DS	dsym1
- +48:	e0 c3 00 00 	lq	r6,0\(r3\)
+ +48:	e0 c3 00 00 	lq      r6,0\(r3\)
 			4a: R_PPC64_SECTOFF_LO_DS	dsym1
- +4c:	e0 c4 00 10 	lq	r6,16\(r4\)
- +50:	f8 c7 00 02 	stq	r6,0\(r7\)
- +54:	f8 c7 00 12 	stq	r6,16\(r7\)
- +58:	f8 c7 ff f2 	stq	r6,-16\(r7\)
- +5c:	f8 c7 80 02 	stq	r6,-32768\(r7\)
- +60:	f8 c7 7f f2 	stq	r6,32752\(r7\)
+ +4c:	e0 c4 00 10 	lq      r6,16\(r4\)
+ +50:	f8 c7 00 02 	stq     r6,0\(r7\)
+ +54:	f8 c7 00 12 	stq     r6,16\(r7\)
+ +58:	f8 c7 ff f2 	stq     r6,-16\(r7\)
+ +5c:	f8 c7 80 02 	stq     r6,-32768\(r7\)
+ +60:	f8 c7 7f f2 	stq     r6,32752\(r7\)
  +64:	00 00 02 00 	attn
- +68:	7c 6f f1 20 	mtcr	r3
- +6c:	7c 6f f1 20 	mtcr	r3
- +70:	7c 68 11 20 	mtcrf	129,r3
- +74:	7c 70 11 20 	mtcrf	1,r3
- +78:	7c 70 21 20 	mtcrf	2,r3
- +7c:	7c 70 41 20 	mtcrf	4,r3
- +80:	7c 70 81 20 	mtcrf	8,r3
- +84:	7c 71 01 20 	mtcrf	16,r3
- +88:	7c 72 01 20 	mtcrf	32,r3
- +8c:	7c 74 01 20 	mtcrf	64,r3
- +90:	7c 78 01 20 	mtcrf	128,r3
- +94:	7c 60 00 26 	mfcr	r3
- +98:	7c 70 10 26 	mfcr	r3,1
- +9c:	7c 70 20 26 	mfcr	r3,2
- +a0:	7c 70 40 26 	mfcr	r3,4
- +a4:	7c 70 80 26 	mfcr	r3,8
- +a8:	7c 71 00 26 	mfcr	r3,16
- +ac:	7c 72 00 26 	mfcr	r3,32
- +b0:	7c 74 00 26 	mfcr	r3,64
- +b4:	7c 78 00 26 	mfcr	r3,128
+ +68:	7c 6f f1 20 	mtcr    r3
+ +6c:	7c 6f f1 20 	mtcr    r3
+ +70:	7c 68 11 20 	mtcrf   129,r3
+ +74:	7c 70 11 20 	mtcrf   1,r3
+ +78:	7c 70 21 20 	mtcrf   2,r3
+ +7c:	7c 70 41 20 	mtcrf   4,r3
+ +80:	7c 70 81 20 	mtcrf   8,r3
+ +84:	7c 71 01 20 	mtcrf   16,r3
+ +88:	7c 72 01 20 	mtcrf   32,r3
+ +8c:	7c 74 01 20 	mtcrf   64,r3
+ +90:	7c 78 01 20 	mtcrf   128,r3
+ +94:	7c 60 00 26 	mfcr    r3
+ +98:	7c 70 10 26 	mfcr    r3,1
+ +9c:	7c 70 20 26 	mfcr    r3,2
+ +a0:	7c 70 40 26 	mfcr    r3,4
+ +a4:	7c 70 80 26 	mfcr    r3,8
+ +a8:	7c 71 00 26 	mfcr    r3,16
+ +ac:	7c 72 00 26 	mfcr    r3,32
+ +b0:	7c 74 00 26 	mfcr    r3,64
+ +b4:	7c 78 00 26 	mfcr    r3,128
diff --git a/gas/testsuite/gas/ppc/test1elf32.d b/gas/testsuite/gas/ppc/test1elf32.d
index e7f2da61811..5654282b396 100644
--- a/gas/testsuite/gas/ppc/test1elf32.d
+++ b/gas/testsuite/gas/ppc/test1elf32.d
@@ -35,50 +35,50 @@ SYMBOL TABLE:
 Disassembly of section \.text:
 
 0+0000 <\.text>:
-   0:	80 63 00 00 	lwz	r3,0\(r3\)
+   0:	80 63 00 00 	lwz     r3,0\(r3\)
 			2: R_PPC_ADDR16_LO	dsym0
-   4:	80 63 00 00 	lwz	r3,0\(r3\)
+   4:	80 63 00 00 	lwz     r3,0\(r3\)
 			6: R_PPC_ADDR16_LO	dsym1
-   8:	80 63 00 00 	lwz	r3,0\(r3\)
+   8:	80 63 00 00 	lwz     r3,0\(r3\)
 			a: R_PPC_ADDR16_LO	usym0
-   c:	80 63 00 00 	lwz	r3,0\(r3\)
+   c:	80 63 00 00 	lwz     r3,0\(r3\)
 			e: R_PPC_ADDR16_LO	usym1
-  10:	80 63 00 00 	lwz	r3,0\(r3\)
+  10:	80 63 00 00 	lwz     r3,0\(r3\)
 			12: R_PPC_ADDR16_LO	esym0
-  14:	80 63 00 00 	lwz	r3,0\(r3\)
+  14:	80 63 00 00 	lwz     r3,0\(r3\)
 			16: R_PPC_ADDR16_LO	esym1
-  18:	38 60 00 04 	li	r3,4
-  1c:	38 60 ff fc 	li	r3,-4
-  20:	38 60 00 04 	li	r3,4
-  24:	38 60 ff fc 	li	r3,-4
-  28:	38 60 ff fc 	li	r3,-4
-  2c:	38 60 00 04 	li	r3,4
-  30:	38 60 00 00 	li	r3,0
+  18:	38 60 00 04 	li      r3,4
+  1c:	38 60 ff fc 	li      r3,-4
+  20:	38 60 00 04 	li      r3,4
+  24:	38 60 ff fc 	li      r3,-4
+  28:	38 60 ff fc 	li      r3,-4
+  2c:	38 60 00 04 	li      r3,4
+  30:	38 60 00 00 	li      r3,0
 			32: R_PPC_ADDR16_LO	dsym0
-  34:	38 60 00 00 	li	r3,0
+  34:	38 60 00 00 	li      r3,0
 			36: R_PPC_ADDR16_HI	dsym0
-  38:	38 60 00 00 	li	r3,0
+  38:	38 60 00 00 	li      r3,0
 			3a: R_PPC_ADDR16_HA	dsym0
-  3c:	38 60 ff fc 	li	r3,-4
-  40:	38 60 ff ff 	li	r3,-1
-  44:	38 60 00 00 	li	r3,0
-  48:	80 64 00 04 	lwz	r3,4\(r4\)
-  4c:	80 60 00 00 	lwz	r3,0\(r0\)
+  3c:	38 60 ff fc 	li      r3,-4
+  40:	38 60 ff ff 	li      r3,-1
+  44:	38 60 00 00 	li      r3,0
+  48:	80 64 00 04 	lwz     r3,4\(r4\)
+  4c:	80 60 00 00 	lwz     r3,0\(0\)
 			4e: R_PPC_ADDR16_LO	\.text
 Disassembly of section \.data:
 
 0+0000 <dsym0>:
-   0:	de ad be ef 	stfdu	f21,-16657\(r13\)
+   0:	de ad be ef 	stfdu   f21,-16657\(r13\)
 
 0+0004 <dsym1>:
-   4:	ca fe ba be 	lfd	f23,-17730\(r30\)
+   4:	ca fe ba be 	lfd     f23,-17730\(r30\)
 
 0+0008 <datpt>:
    8:	00 98 96 80 	\.long 0x989680
 			8: R_PPC_REL32	jk\+0x989680
 
 0+000c <dat0>:
-   c:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+   c:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			c: R_PPC_REL32	jk\+0xf+fffc
 
 0+0010 <dat1>:
diff --git a/gas/testsuite/gas/ppc/test1elf64.d b/gas/testsuite/gas/ppc/test1elf64.d
index bd8ae9f3ee1..bfdd4e86222 100644
--- a/gas/testsuite/gas/ppc/test1elf64.d
+++ b/gas/testsuite/gas/ppc/test1elf64.d
@@ -40,80 +40,80 @@ SYMBOL TABLE:
 Disassembly of section \.text:
 
 0000000000000000 <\.text>:
-   0:	e8 63 00 00 	ld	r3,0\(r3\)
+   0:	e8 63 00 00 	ld      r3,0\(r3\)
 			2: R_PPC64_ADDR16_LO_DS	dsym0
-   4:	e8 63 00 00 	ld	r3,0\(r3\)
+   4:	e8 63 00 00 	ld      r3,0\(r3\)
 			6: R_PPC64_ADDR16_LO_DS	dsym1
-   8:	e8 63 00 00 	ld	r3,0\(r3\)
+   8:	e8 63 00 00 	ld      r3,0\(r3\)
 			a: R_PPC64_ADDR16_LO_DS	usym0
-   c:	e8 63 00 00 	ld	r3,0\(r3\)
+   c:	e8 63 00 00 	ld      r3,0\(r3\)
 			e: R_PPC64_ADDR16_LO_DS	usym1
-  10:	e8 63 00 00 	ld	r3,0\(r3\)
+  10:	e8 63 00 00 	ld      r3,0\(r3\)
 			12: R_PPC64_ADDR16_LO_DS	esym0
-  14:	e8 63 00 00 	ld	r3,0\(r3\)
+  14:	e8 63 00 00 	ld      r3,0\(r3\)
 			16: R_PPC64_ADDR16_LO_DS	esym1
-  18:	e8 62 00 00 	ld	r3,0\(r2\)
+  18:	e8 62 00 00 	ld      r3,0\(r2\)
 			1a: R_PPC64_TOC16_DS	\.toc
-  1c:	e8 62 00 08 	ld	r3,8\(r2\)
+  1c:	e8 62 00 08 	ld      r3,8\(r2\)
 			1e: R_PPC64_TOC16_DS	\.toc\+0x8
-  20:	e8 62 00 10 	ld	r3,16\(r2\)
+  20:	e8 62 00 10 	ld      r3,16\(r2\)
 			22: R_PPC64_TOC16_DS	\.toc\+0x10
-  24:	e8 62 00 18 	ld	r3,24\(r2\)
+  24:	e8 62 00 18 	ld      r3,24\(r2\)
 			26: R_PPC64_TOC16_DS	\.toc\+0x18
-  28:	e8 62 00 20 	ld	r3,32\(r2\)
+  28:	e8 62 00 20 	ld      r3,32\(r2\)
 			2a: R_PPC64_TOC16_DS	\.toc\+0x20
-  2c:	e8 62 00 28 	ld	r3,40\(r2\)
+  2c:	e8 62 00 28 	ld      r3,40\(r2\)
 			2e: R_PPC64_TOC16_DS	\.toc\+0x28
-  30:	3c 80 00 28 	lis	r4,40
+  30:	3c 80 00 28 	lis     r4,40
 			32: R_PPC64_TOC16_HA	\.toc\+0x28
-  34:	e8 62 00 28 	ld	r3,40\(r2\)
+  34:	e8 62 00 28 	ld      r3,40\(r2\)
 			36: R_PPC64_TOC16_LO_DS	\.toc\+0x28
-  38:	38 60 00 08 	li	r3,8
-  3c:	38 60 ff f8 	li	r3,-8
-  40:	38 60 00 08 	li	r3,8
-  44:	38 60 ff f8 	li	r3,-8
-  48:	38 60 ff f8 	li	r3,-8
-  4c:	38 60 00 08 	li	r3,8
-  50:	38 60 00 00 	li	r3,0
+  38:	38 60 00 08 	li      r3,8
+  3c:	38 60 ff f8 	li      r3,-8
+  40:	38 60 00 08 	li      r3,8
+  44:	38 60 ff f8 	li      r3,-8
+  48:	38 60 ff f8 	li      r3,-8
+  4c:	38 60 00 08 	li      r3,8
+  50:	38 60 00 00 	li      r3,0
 			52: R_PPC64_ADDR16_LO	dsym0
-  54:	38 60 00 00 	li	r3,0
+  54:	38 60 00 00 	li      r3,0
 			56: R_PPC64_ADDR16_HI	dsym0
-  58:	38 60 00 00 	li	r3,0
+  58:	38 60 00 00 	li      r3,0
 			5a: R_PPC64_ADDR16_HA	dsym0
-  5c:	38 60 00 00 	li	r3,0
+  5c:	38 60 00 00 	li      r3,0
 			5e: R_PPC64_ADDR16_HIGHER	dsym0
-  60:	38 60 00 00 	li	r3,0
+  60:	38 60 00 00 	li      r3,0
 			62: R_PPC64_ADDR16_HIGHERA	dsym0
-  64:	38 60 00 00 	li	r3,0
+  64:	38 60 00 00 	li      r3,0
 			66: R_PPC64_ADDR16_HIGHEST	dsym0
-  68:	38 60 00 00 	li	r3,0
+  68:	38 60 00 00 	li      r3,0
 			6a: R_PPC64_ADDR16_HIGHESTA	dsym0
-  6c:	38 60 ff f8 	li	r3,-8
-  70:	38 60 ff ff 	li	r3,-1
-  74:	38 60 00 00 	li	r3,0
-  78:	38 60 ff ff 	li	r3,-1
-  7c:	38 60 00 00 	li	r3,0
-  80:	38 60 ff ff 	li	r3,-1
-  84:	38 60 00 00 	li	r3,0
-  88:	e8 64 00 08 	ld	r3,8\(r4\)
-  8c:	e8 60 00 00 	ld	r3,0\(r0\)
+  6c:	38 60 ff f8 	li      r3,-8
+  70:	38 60 ff ff 	li      r3,-1
+  74:	38 60 00 00 	li      r3,0
+  78:	38 60 ff ff 	li      r3,-1
+  7c:	38 60 00 00 	li      r3,0
+  80:	38 60 ff ff 	li      r3,-1
+  84:	38 60 00 00 	li      r3,0
+  88:	e8 64 00 08 	ld      r3,8\(r4\)
+  8c:	e8 60 00 00 	ld      r3,0\(0\)
 			8e: R_PPC64_ADDR16_LO_DS	\.text
 Disassembly of section \.data:
 
 0000000000000000 <dsym0>:
    0:	00 00 00 00 	\.long 0x0
-   4:	de ad be ef 	stfdu	f21,-16657\(r13\)
+   4:	de ad be ef 	stfdu   f21,-16657\(r13\)
 
 0000000000000008 <dsym1>:
    8:	00 00 00 00 	\.long 0x0
-   c:	ca fe ba be 	lfd	f23,-17730\(r30\)
+   c:	ca fe ba be 	lfd     f23,-17730\(r30\)
 
 0000000000000010 <datpt>:
   10:	00 98 96 80 	\.long 0x989680
 			10: R_PPC64_REL32	jk\+0x989680
 
 0000000000000014 <dat0>:
-  14:	ff ff ff fc 	fnmsub	f31,f31,f31,f31
+  14:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			14: R_PPC64_REL32	jk\+0xfffffffffffffffc
 
 0000000000000018 <dat1>:
diff --git a/gas/testsuite/gas/ppc/test1xcoff32.d b/gas/testsuite/gas/ppc/test1xcoff32.d
index e720587b6c5..7e7a7a73686 100644
--- a/gas/testsuite/gas/ppc/test1xcoff32.d
+++ b/gas/testsuite/gas/ppc/test1xcoff32.d
@@ -64,50 +64,50 @@ Disassembly of section \.text:
    4:	00 be ef ed 	\.long 0xbeefed
 
 0+0008 <reference_csect_relative_symbols>:
-   8:	80 63 00 00 	l	r3,0\(r3\)
-   c:	80 63 00 04 	l	r3,4\(r3\)
-  10:	80 63 00 04 	l	r3,4\(r3\)
-  14:	80 63 00 00 	l	r3,0\(r3\)
+   8:	80 63 00 00 	l       r3,0\(r3\)
+   c:	80 63 00 04 	l       r3,4\(r3\)
+  10:	80 63 00 04 	l       r3,4\(r3\)
+  14:	80 63 00 00 	l       r3,0\(r3\)
 
 0+0018 <dubious_references_to_default_RW_csect>:
-  18:	80 63 00 00 	l	r3,0\(r3\)
-  1c:	80 63 00 04 	l	r3,4\(r3\)
-  20:	80 63 00 04 	l	r3,4\(r3\)
-  24:	80 63 00 08 	l	r3,8\(r3\)
+  18:	80 63 00 00 	l       r3,0\(r3\)
+  1c:	80 63 00 04 	l       r3,4\(r3\)
+  20:	80 63 00 04 	l       r3,4\(r3\)
+  24:	80 63 00 08 	l       r3,8\(r3\)
 
 0+0028 <reference_via_toc>:
-  28:	80 62 00 0c 	l	r3,12\(r2\)
+  28:	80 62 00 0c 	l       r3,12\(r2\)
 			2a: R_TOC	ignored0\+0xf+ff8c
-  2c:	80 62 00 10 	l	r3,16\(r2\)
+  2c:	80 62 00 10 	l       r3,16\(r2\)
 			2e: R_TOC	ignored1\+0xf+ff88
-  30:	80 62 00 14 	l	r3,20\(r2\)
+  30:	80 62 00 14 	l       r3,20\(r2\)
 			32: R_TOC	ignored2\+0xf+ff84
-  34:	80 62 00 18 	l	r3,24\(r2\)
+  34:	80 62 00 18 	l       r3,24\(r2\)
 			36: R_TOC	ignored3\+0xf+ff80
-  38:	80 62 00 1c 	l	r3,28\(r2\)
+  38:	80 62 00 1c 	l       r3,28\(r2\)
 			3a: R_TOC	ignored4\+0xf+ff7c
-  3c:	80 62 00 20 	l	r3,32\(r2\)
+  3c:	80 62 00 20 	l       r3,32\(r2\)
 			3e: R_TOC	ignored5\+0xf+ff78
 
 0+0040 <subtract_symbols>:
-  40:	38 60 00 04 	lil	r3,4
-  44:	38 60 ff fc 	lil	r3,-4
-  48:	38 60 00 04 	lil	r3,4
-  4c:	38 60 ff fc 	lil	r3,-4
-  50:	38 60 ff fc 	lil	r3,-4
-  54:	38 60 00 04 	lil	r3,4
-  58:	80 64 00 04 	l	r3,4\(r4\)
+  40:	38 60 00 04 	lil     r3,4
+  44:	38 60 ff fc 	lil     r3,-4
+  48:	38 60 00 04 	lil     r3,4
+  4c:	38 60 ff fc 	lil     r3,-4
+  50:	38 60 ff fc 	lil     r3,-4
+  54:	38 60 00 04 	lil     r3,4
+  58:	80 64 00 04 	l       r3,4\(r4\)
 
 0+005c <load_addresses>:
-  5c:	38 60 00 00 	lil	r3,0
-  60:	38 60 00 04 	lil	r3,4
-  64:	38 62 00 24 	cal	r3,36\(r2\)
+  5c:	38 60 00 00 	lil     r3,0
+  60:	38 60 00 04 	lil     r3,4
+  64:	38 62 00 24 	cal     r3,36\(r2\)
 			66: R_TOC	ignored6\+0xf+ff74
 Disassembly of section \.data:
 
 0+0068 <TOC-0xc>:
-  68:	de ad be ef 	stfdu	f21,-16657\(r13\)
-  6c:	ca fe ba be 	lfd	f23,-17730\(r30\)
+  68:	de ad be ef 	stfdu   f21,-16657\(r13\)
+  6c:	ca fe ba be 	lfd     f23,-17730\(r30\)
   70:	00 00 ba ad 	\.long 0xbaad
 
 0+0074 <TOC>:
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index aafdb414b03..d5bc8ac458b 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2004-03-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
+
 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 
 	* i386.h (i386_optab): Added xstore as an alias for xstorerng.
@@ -11,7 +15,7 @@
 	* h8300.h (32bit ldc/stc): Add relaxing support.
 
 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
-	
+
 	* h8300.h (BITOP): Pass MEMRELAX flag.
 
 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 342237e8dd6..d55caa7568f 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -1,5 +1,5 @@
 /* ppc.h -- Header file for PowerPC opcode table
-   Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003
+   Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004
    Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 
@@ -151,7 +151,7 @@ struct powerpc_operand
      operand value into an instruction, check this field.
 
      If it is NULL, execute
-         i |= (op & ((1 << o->bits) - 1)) << o->shift;
+	 i |= (op & ((1 << o->bits) - 1)) << o->shift;
      (i is the instruction which we are filling in, o is a pointer to
      this structure, and op is the opcode value; this assumes twos
      complement arithmetic).
@@ -170,7 +170,7 @@ struct powerpc_operand
      extract this operand type from an instruction, check this field.
 
      If it is NULL, compute
-         op = ((i) >> o->shift) & ((1 << o->bits) - 1);
+	 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 	 if ((o->flags & PPC_OPERAND_SIGNED) != 0
 	     && (op & (1 << (o->bits - 1))) != 0)
 	   op -= 1 << o->bits;
@@ -233,17 +233,20 @@ extern const struct powerpc_operand powerpc_operands[];
    register names with a leading 'r'.  */
 #define PPC_OPERAND_GPR (040)
 
+/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
+#define PPC_OPERAND_GPR_0 (0100)
+
 /* This operand names a floating point register.  The disassembler
    prints these with a leading 'f'.  */
-#define PPC_OPERAND_FPR (0100)
+#define PPC_OPERAND_FPR (0200)
 
 /* This operand is a relative branch displacement.  The disassembler
    prints these symbolically if possible.  */
-#define PPC_OPERAND_RELATIVE (0200)
+#define PPC_OPERAND_RELATIVE (0400)
 
 /* This operand is an absolute branch address.  The disassembler
    prints these symbolically if possible.  */
-#define PPC_OPERAND_ABSOLUTE (0400)
+#define PPC_OPERAND_ABSOLUTE (01000)
 
 /* This operand is optional, and is zero if omitted.  This is used for
    the optional BF and L fields in the comparison instructions.  The
@@ -251,7 +254,7 @@ extern const struct powerpc_operand powerpc_operands[];
    and the number of operands remaining for the opcode, and decide
    whether this operand is present or not.  The disassembler should
    print this operand out only if it is not zero.  */
-#define PPC_OPERAND_OPTIONAL (01000)
+#define PPC_OPERAND_OPTIONAL (02000)
 
 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
    is omitted, then for the next operand use this operand value plus
@@ -259,24 +262,24 @@ extern const struct powerpc_operand powerpc_operands[];
    hack is needed because the Power rotate instructions can take
    either 4 or 5 operands.  The disassembler should print this operand
    out regardless of the PPC_OPERAND_OPTIONAL field.  */
-#define PPC_OPERAND_NEXT (02000)
+#define PPC_OPERAND_NEXT (04000)
 
 /* This operand should be regarded as a negative number for the
    purposes of overflow checking (i.e., the normal most negative
    number is disallowed and one more than the normal most positive
    number is allowed).  This flag will only be set for a signed
    operand.  */
-#define PPC_OPERAND_NEGATIVE (04000)
+#define PPC_OPERAND_NEGATIVE (010000)
 
 /* This operand names a vector unit register.  The disassembler
    prints these with a leading 'v'.  */
-#define PPC_OPERAND_VR (010000)
+#define PPC_OPERAND_VR (020000)
 
 /* This operand is for the DS field in a DS form instruction.  */
-#define PPC_OPERAND_DS (020000)
+#define PPC_OPERAND_DS (040000)
 
 /* This operand is for the DQ field in a DQ form instruction.  */
-#define PPC_OPERAND_DQ (040000)
+#define PPC_OPERAND_DQ (0100000)
 
 /* The POWER and PowerPC assemblers use a few macros.  We keep them
    with the operands table for simplicity.  The macro table is an
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index 5358d33df23..807c08bfb1c 100644
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,15 @@
+2004-03-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tls.d: Update.
+	* ld-powerpc/tls32.d: Update.
+	* ld-powerpc/tlsexe.d: Update.
+	* ld-powerpc/tlsexe32.d: Update.
+	* ld-powerpc/tlsexetoc.d: Update.
+	* ld-powerpc/tlsso.d: Update.
+	* ld-powerpc/tlsso32.d: Update.
+	* ld-powerpc/tlstoc.d: Update.
+	* ld-powerpc/tlstocso.d: Update.
+
 2004-03-05  Nathan Sidwell  <nathan@codesourcery.com>
 
 	* ld-scripts/size.exp: New.
@@ -29,7 +41,7 @@
 	relocations.
 
 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
-	
+
 	* ld-h8300/relax-5.s: New file: Source for relax-5 test.
 	* ld-h8300/relax-5.d: New file: Expected output and commands for
 	assembling and linking the relax-5 test.
@@ -54,7 +66,7 @@
 	ld-arm/arm-static-app.r: New files.
 
 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
-	
+
 	* ld-h8300/h8300-exp:  Run the relax-4 test.
 	* ld-h8300/relax-4.s: New file: Source for relax-4 test.
 	* ld-h8300/relax-4.d: New file: Expected output and commands for
diff --git a/ld/testsuite/ld-powerpc/tls.d b/ld/testsuite/ld-powerpc/tls.d
index 621fcb0893a..abae98ad23c 100644
--- a/ld/testsuite/ld-powerpc/tls.d
+++ b/ld/testsuite/ld-powerpc/tls.d
@@ -10,44 +10,44 @@
 Disassembly of section \.text:
 
 0+100000e8 <_start>:
-    100000e8:	3c 6d 00 00 	addis	r3,r13,0
+    100000e8:	3c 6d 00 00 	addis   r3,r13,0
     100000ec:	60 00 00 00 	nop
-    100000f0:	38 63 90 78 	addi	r3,r3,-28552
-    100000f4:	3c 6d 00 00 	addis	r3,r13,0
+    100000f0:	38 63 90 78 	addi    r3,r3,-28552
+    100000f4:	3c 6d 00 00 	addis   r3,r13,0
     100000f8:	60 00 00 00 	nop
-    100000fc:	38 63 10 00 	addi	r3,r3,4096
-    10000100:	3c 6d 00 00 	addis	r3,r13,0
+    100000fc:	38 63 10 00 	addi    r3,r3,4096
+    10000100:	3c 6d 00 00 	addis   r3,r13,0
     10000104:	60 00 00 00 	nop
-    10000108:	38 63 90 40 	addi	r3,r3,-28608
-    1000010c:	3c 6d 00 00 	addis	r3,r13,0
+    10000108:	38 63 90 40 	addi    r3,r3,-28608
+    1000010c:	3c 6d 00 00 	addis   r3,r13,0
     10000110:	60 00 00 00 	nop
-    10000114:	38 63 10 00 	addi	r3,r3,4096
-    10000118:	39 23 80 48 	addi	r9,r3,-32696
-    1000011c:	3d 23 00 00 	addis	r9,r3,0
-    10000120:	81 49 80 50 	lwz	r10,-32688\(r9\)
-    10000124:	e9 22 80 10 	ld	r9,-32752\(r2\)
-    10000128:	7d 49 18 2a 	ldx	r10,r9,r3
-    1000012c:	3d 2d 00 00 	addis	r9,r13,0
-    10000130:	a1 49 90 60 	lhz	r10,-28576\(r9\)
-    10000134:	89 4d 90 68 	lbz	r10,-28568\(r13\)
-    10000138:	3d 2d 00 00 	addis	r9,r13,0
-    1000013c:	99 49 90 70 	stb	r10,-28560\(r9\)
-    10000140:	3c 6d 00 00 	addis	r3,r13,0
+    10000114:	38 63 10 00 	addi    r3,r3,4096
+    10000118:	39 23 80 48 	addi    r9,r3,-32696
+    1000011c:	3d 23 00 00 	addis   r9,r3,0
+    10000120:	81 49 80 50 	lwz     r10,-32688\(r9\)
+    10000124:	e9 22 80 10 	ld      r9,-32752\(r2\)
+    10000128:	7d 49 18 2a 	ldx     r10,r9,r3
+    1000012c:	3d 2d 00 00 	addis   r9,r13,0
+    10000130:	a1 49 90 60 	lhz     r10,-28576\(r9\)
+    10000134:	89 4d 90 68 	lbz     r10,-28568\(r13\)
+    10000138:	3d 2d 00 00 	addis   r9,r13,0
+    1000013c:	99 49 90 70 	stb     r10,-28560\(r9\)
+    10000140:	3c 6d 00 00 	addis   r3,r13,0
     10000144:	60 00 00 00 	nop
-    10000148:	38 63 90 00 	addi	r3,r3,-28672
-    1000014c:	3c 6d 00 00 	addis	r3,r13,0
+    10000148:	38 63 90 00 	addi    r3,r3,-28672
+    1000014c:	3c 6d 00 00 	addis   r3,r13,0
     10000150:	60 00 00 00 	nop
-    10000154:	38 63 10 00 	addi	r3,r3,4096
-    10000158:	f9 43 80 08 	std	r10,-32760\(r3\)
-    1000015c:	3d 23 00 00 	addis	r9,r3,0
-    10000160:	91 49 80 10 	stw	r10,-32752\(r9\)
-    10000164:	e9 22 80 08 	ld	r9,-32760\(r2\)
-    10000168:	7d 49 19 2a 	stdx	r10,r9,r3
-    1000016c:	3d 2d 00 00 	addis	r9,r13,0
-    10000170:	b1 49 90 60 	sth	r10,-28576\(r9\)
-    10000174:	e9 4d 90 2a 	lwa	r10,-28632\(r13\)
-    10000178:	3d 2d 00 00 	addis	r9,r13,0
-    1000017c:	a9 49 90 30 	lha	r10,-28624\(r9\)
+    10000154:	38 63 10 00 	addi    r3,r3,4096
+    10000158:	f9 43 80 08 	std     r10,-32760\(r3\)
+    1000015c:	3d 23 00 00 	addis   r9,r3,0
+    10000160:	91 49 80 10 	stw     r10,-32752\(r9\)
+    10000164:	e9 22 80 08 	ld      r9,-32760\(r2\)
+    10000168:	7d 49 19 2a 	stdx    r10,r9,r3
+    1000016c:	3d 2d 00 00 	addis   r9,r13,0
+    10000170:	b1 49 90 60 	sth     r10,-28576\(r9\)
+    10000174:	e9 4d 90 2a 	lwa     r10,-28632\(r13\)
+    10000178:	3d 2d 00 00 	addis   r9,r13,0
+    1000017c:	a9 49 90 30 	lha     r10,-28624\(r9\)
 
 0+10000180 <\.__tls_get_addr>:
     10000180:	4e 80 00 20 	blr
diff --git a/ld/testsuite/ld-powerpc/tls32.d b/ld/testsuite/ld-powerpc/tls32.d
index b2e384d7f53..86fe04abfa3 100644
--- a/ld/testsuite/ld-powerpc/tls32.d
+++ b/ld/testsuite/ld-powerpc/tls32.d
@@ -10,34 +10,34 @@
 Disassembly of section \.text:
 
 0+1800094 <_start>:
- 1800094:	3c 62 00 00 	addis	r3,r2,0
- 1800098:	38 63 90 3c 	addi	r3,r3,-28612
- 180009c:	3c 62 00 00 	addis	r3,r2,0
- 18000a0:	38 63 10 00 	addi	r3,r3,4096
- 18000a4:	3c 62 00 00 	addis	r3,r2,0
- 18000a8:	38 63 90 20 	addi	r3,r3,-28640
- 18000ac:	3c 62 00 00 	addis	r3,r2,0
- 18000b0:	38 63 10 00 	addi	r3,r3,4096
- 18000b4:	39 23 80 24 	addi	r9,r3,-32732
- 18000b8:	3d 23 00 00 	addis	r9,r3,0
- 18000bc:	81 49 80 28 	lwz	r10,-32728\(r9\)
- 18000c0:	3d 22 00 00 	addis	r9,r2,0
- 18000c4:	a1 49 90 30 	lhz	r10,-28624\(r9\)
- 18000c8:	89 42 90 34 	lbz	r10,-28620\(r2\)
- 18000cc:	3d 22 00 00 	addis	r9,r2,0
- 18000d0:	99 49 90 38 	stb	r10,-28616\(r9\)
- 18000d4:	3c 62 00 00 	addis	r3,r2,0
- 18000d8:	38 63 90 00 	addi	r3,r3,-28672
- 18000dc:	3c 62 00 00 	addis	r3,r2,0
- 18000e0:	38 63 10 00 	addi	r3,r3,4096
- 18000e4:	91 43 80 04 	stw	r10,-32764\(r3\)
- 18000e8:	3d 23 00 00 	addis	r9,r3,0
- 18000ec:	91 49 80 08 	stw	r10,-32760\(r9\)
- 18000f0:	3d 22 00 00 	addis	r9,r2,0
- 18000f4:	b1 49 90 30 	sth	r10,-28624\(r9\)
- 18000f8:	a1 42 90 14 	lhz	r10,-28652\(r2\)
- 18000fc:	3d 22 00 00 	addis	r9,r2,0
- 1800100:	a9 49 90 18 	lha	r10,-28648\(r9\)
+ 1800094:	3c 62 00 00 	addis   r3,r2,0
+ 1800098:	38 63 90 3c 	addi    r3,r3,-28612
+ 180009c:	3c 62 00 00 	addis   r3,r2,0
+ 18000a0:	38 63 10 00 	addi    r3,r3,4096
+ 18000a4:	3c 62 00 00 	addis   r3,r2,0
+ 18000a8:	38 63 90 20 	addi    r3,r3,-28640
+ 18000ac:	3c 62 00 00 	addis   r3,r2,0
+ 18000b0:	38 63 10 00 	addi    r3,r3,4096
+ 18000b4:	39 23 80 24 	addi    r9,r3,-32732
+ 18000b8:	3d 23 00 00 	addis   r9,r3,0
+ 18000bc:	81 49 80 28 	lwz     r10,-32728\(r9\)
+ 18000c0:	3d 22 00 00 	addis   r9,r2,0
+ 18000c4:	a1 49 90 30 	lhz     r10,-28624\(r9\)
+ 18000c8:	89 42 90 34 	lbz     r10,-28620\(r2\)
+ 18000cc:	3d 22 00 00 	addis   r9,r2,0
+ 18000d0:	99 49 90 38 	stb     r10,-28616\(r9\)
+ 18000d4:	3c 62 00 00 	addis   r3,r2,0
+ 18000d8:	38 63 90 00 	addi    r3,r3,-28672
+ 18000dc:	3c 62 00 00 	addis   r3,r2,0
+ 18000e0:	38 63 10 00 	addi    r3,r3,4096
+ 18000e4:	91 43 80 04 	stw     r10,-32764\(r3\)
+ 18000e8:	3d 23 00 00 	addis   r9,r3,0
+ 18000ec:	91 49 80 08 	stw     r10,-32760\(r9\)
+ 18000f0:	3d 22 00 00 	addis   r9,r2,0
+ 18000f4:	b1 49 90 30 	sth     r10,-28624\(r9\)
+ 18000f8:	a1 42 90 14 	lhz     r10,-28652\(r2\)
+ 18000fc:	3d 22 00 00 	addis   r9,r2,0
+ 1800100:	a9 49 90 18 	lha     r10,-28648\(r9\)
 
 0+1800104 <__tls_get_addr>:
  1800104:	4e 80 00 20 	blr
diff --git a/ld/testsuite/ld-powerpc/tlsexe.d b/ld/testsuite/ld-powerpc/tlsexe.d
index 6dac928aa6b..546daf3defd 100644
--- a/ld/testsuite/ld-powerpc/tlsexe.d
+++ b/ld/testsuite/ld-powerpc/tlsexe.d
@@ -9,68 +9,68 @@
 Disassembly of section \.text:
 
 .* <_start-0x1c>:
-.*	3d 82 00 00 	addis	r12,r2,0
-.*	f8 41 00 28 	std	r2,40\(r1\)
-.*	e9 6c 80 48 	ld	r11,-32696\(r12\)
-.*	e8 4c 80 50 	ld	r2,-32688\(r12\)
-.*	7d 69 03 a6 	mtctr	r11
-.*	e9 6c 80 58 	ld	r11,-32680\(r12\)
+.*	3d 82 00 00 	addis   r12,r2,0
+.*	f8 41 00 28 	std     r2,40\(r1\)
+.*	e9 6c 80 48 	ld      r11,-32696\(r12\)
+.*	e8 4c 80 50 	ld      r2,-32688\(r12\)
+.*	7d 69 03 a6 	mtctr   r11
+.*	e9 6c 80 58 	ld      r11,-32680\(r12\)
 .*	4e 80 04 20 	bctr
 
 .* <_start>:
-.*	e8 62 80 10 	ld	r3,-32752\(r2\)
+.*	e8 62 80 10 	ld      r3,-32752\(r2\)
 .*	60 00 00 00 	nop
-.*	7c 63 6a 14 	add	r3,r3,r13
-.*	38 62 80 18 	addi	r3,r2,-32744
-.*	4b ff ff d5 	bl	.*
-.*	e8 41 00 28 	ld	r2,40\(r1\)
-.*	3c 6d 00 00 	addis	r3,r13,0
+.*	7c 63 6a 14 	add     r3,r3,r13
+.*	38 62 80 18 	addi    r3,r2,-32744
+.*	4b ff ff d5 	bl      .*
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	3c 6d 00 00 	addis   r3,r13,0
 .*	60 00 00 00 	nop
-.*	38 63 90 38 	addi	r3,r3,-28616
-.*	3c 6d 00 00 	addis	r3,r13,0
+.*	38 63 90 38 	addi    r3,r3,-28616
+.*	3c 6d 00 00 	addis   r3,r13,0
 .*	60 00 00 00 	nop
-.*	38 63 10 00 	addi	r3,r3,4096
-.*	39 23 80 40 	addi	r9,r3,-32704
-.*	3d 23 00 00 	addis	r9,r3,0
-.*	81 49 80 48 	lwz	r10,-32696\(r9\)
-.*	e9 22 80 28 	ld	r9,-32728\(r2\)
-.*	7d 49 18 2a 	ldx	r10,r9,r3
-.*	3d 2d 00 00 	addis	r9,r13,0
-.*	a1 49 90 58 	lhz	r10,-28584\(r9\)
-.*	89 4d 90 60 	lbz	r10,-28576\(r13\)
-.*	3d 2d 00 00 	addis	r9,r13,0
-.*	99 49 90 68 	stb	r10,-28568\(r9\)
-.*	3c 6d 00 00 	addis	r3,r13,0
+.*	38 63 10 00 	addi    r3,r3,4096
+.*	39 23 80 40 	addi    r9,r3,-32704
+.*	3d 23 00 00 	addis   r9,r3,0
+.*	81 49 80 48 	lwz     r10,-32696\(r9\)
+.*	e9 22 80 28 	ld      r9,-32728\(r2\)
+.*	7d 49 18 2a 	ldx     r10,r9,r3
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	a1 49 90 58 	lhz     r10,-28584\(r9\)
+.*	89 4d 90 60 	lbz     r10,-28576\(r13\)
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	99 49 90 68 	stb     r10,-28568\(r9\)
+.*	3c 6d 00 00 	addis   r3,r13,0
 .*	60 00 00 00 	nop
-.*	38 63 90 00 	addi	r3,r3,-28672
-.*	3c 6d 00 00 	addis	r3,r13,0
+.*	38 63 90 00 	addi    r3,r3,-28672
+.*	3c 6d 00 00 	addis   r3,r13,0
 .*	60 00 00 00 	nop
-.*	38 63 10 00 	addi	r3,r3,4096
-.*	f9 43 80 08 	std	r10,-32760\(r3\)
-.*	3d 23 00 00 	addis	r9,r3,0
-.*	91 49 80 10 	stw	r10,-32752\(r9\)
-.*	e9 22 80 08 	ld	r9,-32760\(r2\)
-.*	7d 49 19 2a 	stdx	r10,r9,r3
-.*	3d 2d 00 00 	addis	r9,r13,0
-.*	b1 49 90 58 	sth	r10,-28584\(r9\)
-.*	e9 4d 90 2a 	lwa	r10,-28632\(r13\)
-.*	3d 2d 00 00 	addis	r9,r13,0
-.*	a9 49 90 30 	lha	r10,-28624\(r9\)
-.*	7d 89 02 a6 	mfctr	r12
-.*	78 0b 1f 24 	rldicr	r11,r0,3,60
-.*	34 40 80 00 	addic\.	r2,r0,-32768
-.*	7d 8b 60 50 	subf	r12,r11,r12
-.*	7c 42 fe 76 	sradi	r2,r2,63
-.*	78 0b 17 64 	rldicr	r11,r0,2,61
-.*	7c 42 58 38 	and	r2,r2,r11
-.*	7d 8b 60 50 	subf	r12,r11,r12
-.*	7d 8c 12 14 	add	r12,r12,r2
-.*	3d 8c 00 01 	addis	r12,r12,1
-.*	e9 6c 01 c4 	ld	r11,452\(r12\)
-.*	39 8c 01 c4 	addi	r12,r12,452
-.*	e8 4c 00 08 	ld	r2,8\(r12\)
-.*	7d 69 03 a6 	mtctr	r11
-.*	e9 6c 00 10 	ld	r11,16\(r12\)
+.*	38 63 10 00 	addi    r3,r3,4096
+.*	f9 43 80 08 	std     r10,-32760\(r3\)
+.*	3d 23 00 00 	addis   r9,r3,0
+.*	91 49 80 10 	stw     r10,-32752\(r9\)
+.*	e9 22 80 08 	ld      r9,-32760\(r2\)
+.*	7d 49 19 2a 	stdx    r10,r9,r3
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	b1 49 90 58 	sth     r10,-28584\(r9\)
+.*	e9 4d 90 2a 	lwa     r10,-28632\(r13\)
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	a9 49 90 30 	lha     r10,-28624\(r9\)
+.*	7d 89 02 a6 	mfctr   r12
+.*	78 0b 1f 24 	rldicr  r11,r0,3,60
+.*	34 40 80 00 	addic\.  r2,r0,-32768
+.*	7d 8b 60 50 	subf    r12,r11,r12
+.*	7c 42 fe 76 	sradi   r2,r2,63
+.*	78 0b 17 64 	rldicr  r11,r0,2,61
+.*	7c 42 58 38 	and     r2,r2,r11
+.*	7d 8b 60 50 	subf    r12,r11,r12
+.*	7d 8c 12 14 	add     r12,r12,r2
+.*	3d 8c 00 01 	addis   r12,r12,1
+.*	e9 6c 01 c4 	ld      r11,452\(r12\)
+.*	39 8c 01 c4 	addi    r12,r12,452
+.*	e8 4c 00 08 	ld      r2,8\(r12\)
+.*	7d 69 03 a6 	mtctr   r11
+.*	e9 6c 00 10 	ld      r11,16\(r12\)
 .*	4e 80 04 20 	bctr
-.*	38 00 00 00 	li	r0,0
-.*	4b ff ff bc 	b	.*
+.*	38 00 00 00 	li      r0,0
+.*	4b ff ff bc 	b       .*
diff --git a/ld/testsuite/ld-powerpc/tlsexe32.d b/ld/testsuite/ld-powerpc/tlsexe32.d
index 9bd8221f22a..4aea8f061c2 100644
--- a/ld/testsuite/ld-powerpc/tlsexe32.d
+++ b/ld/testsuite/ld-powerpc/tlsexe32.d
@@ -9,34 +9,34 @@
 Disassembly of section \.text:
 
 0180028c <_start>:
- 180028c:	80 7f 00 0c 	lwz	r3,12\(r31\)
- 1800290:	7c 63 12 14 	add	r3,r3,r2
- 1800294:	38 7f 00 10 	addi	r3,r31,16
- 1800298:	48 01 01 85 	bl	181041c .*
- 180029c:	3c 62 00 00 	addis	r3,r2,0
- 18002a0:	38 63 90 1c 	addi	r3,r3,-28644
- 18002a4:	3c 62 00 00 	addis	r3,r2,0
- 18002a8:	38 63 10 00 	addi	r3,r3,4096
- 18002ac:	39 23 80 20 	addi	r9,r3,-32736
- 18002b0:	3d 23 00 00 	addis	r9,r3,0
- 18002b4:	81 49 80 24 	lwz	r10,-32732\(r9\)
- 18002b8:	3d 22 00 00 	addis	r9,r2,0
- 18002bc:	a1 49 90 2c 	lhz	r10,-28628\(r9\)
- 18002c0:	89 42 90 30 	lbz	r10,-28624\(r2\)
- 18002c4:	3d 22 00 00 	addis	r9,r2,0
- 18002c8:	99 49 90 34 	stb	r10,-28620\(r9\)
- 18002cc:	3c 62 00 00 	addis	r3,r2,0
- 18002d0:	38 63 90 00 	addi	r3,r3,-28672
- 18002d4:	3c 62 00 00 	addis	r3,r2,0
- 18002d8:	38 63 10 00 	addi	r3,r3,4096
- 18002dc:	91 43 80 04 	stw	r10,-32764\(r3\)
- 18002e0:	3d 23 00 00 	addis	r9,r3,0
- 18002e4:	91 49 80 08 	stw	r10,-32760\(r9\)
- 18002e8:	3d 22 00 00 	addis	r9,r2,0
- 18002ec:	b1 49 90 2c 	sth	r10,-28628\(r9\)
- 18002f0:	a1 42 90 14 	lhz	r10,-28652\(r2\)
- 18002f4:	3d 22 00 00 	addis	r9,r2,0
- 18002f8:	a9 49 90 18 	lha	r10,-28648\(r9\)
+ 180028c:	80 7f 00 0c 	lwz     r3,12\(r31\)
+ 1800290:	7c 63 12 14 	add     r3,r3,r2
+ 1800294:	38 7f 00 10 	addi    r3,r31,16
+ 1800298:	48 01 01 85 	bl      181041c .*
+ 180029c:	3c 62 00 00 	addis   r3,r2,0
+ 18002a0:	38 63 90 1c 	addi    r3,r3,-28644
+ 18002a4:	3c 62 00 00 	addis   r3,r2,0
+ 18002a8:	38 63 10 00 	addi    r3,r3,4096
+ 18002ac:	39 23 80 20 	addi    r9,r3,-32736
+ 18002b0:	3d 23 00 00 	addis   r9,r3,0
+ 18002b4:	81 49 80 24 	lwz     r10,-32732\(r9\)
+ 18002b8:	3d 22 00 00 	addis   r9,r2,0
+ 18002bc:	a1 49 90 2c 	lhz     r10,-28628\(r9\)
+ 18002c0:	89 42 90 30 	lbz     r10,-28624\(r2\)
+ 18002c4:	3d 22 00 00 	addis   r9,r2,0
+ 18002c8:	99 49 90 34 	stb     r10,-28620\(r9\)
+ 18002cc:	3c 62 00 00 	addis   r3,r2,0
+ 18002d0:	38 63 90 00 	addi    r3,r3,-28672
+ 18002d4:	3c 62 00 00 	addis   r3,r2,0
+ 18002d8:	38 63 10 00 	addi    r3,r3,4096
+ 18002dc:	91 43 80 04 	stw     r10,-32764\(r3\)
+ 18002e0:	3d 23 00 00 	addis   r9,r3,0
+ 18002e4:	91 49 80 08 	stw     r10,-32760\(r9\)
+ 18002e8:	3d 22 00 00 	addis   r9,r2,0
+ 18002ec:	b1 49 90 2c 	sth     r10,-28628\(r9\)
+ 18002f0:	a1 42 90 14 	lhz     r10,-28652\(r2\)
+ 18002f4:	3d 22 00 00 	addis   r9,r2,0
+ 18002f8:	a9 49 90 18 	lha     r10,-28648\(r9\)
 Disassembly of section \.got:
 
 018103b8 <\.got>:
diff --git a/ld/testsuite/ld-powerpc/tlsexetoc.d b/ld/testsuite/ld-powerpc/tlsexetoc.d
index 7947149ce43..7ec07d2389e 100644
--- a/ld/testsuite/ld-powerpc/tlsexetoc.d
+++ b/ld/testsuite/ld-powerpc/tlsexetoc.d
@@ -9,52 +9,52 @@
 Disassembly of section \.text:
 
 .* <_start-0x1c>:
-.*	3d 82 00 00 	addis	r12,r2,0
-.*	f8 41 00 28 	std	r2,40\(r1\)
-.*	e9 6c 80 70 	ld	r11,-32656\(r12\)
-.*	e8 4c 80 78 	ld	r2,-32648\(r12\)
-.*	7d 69 03 a6 	mtctr	r11
-.*	e9 6c 80 80 	ld	r11,-32640\(r12\)
+.*	3d 82 00 00 	addis   r12,r2,0
+.*	f8 41 00 28 	std     r2,40\(r1\)
+.*	e9 6c 80 70 	ld      r11,-32656\(r12\)
+.*	e8 4c 80 78 	ld      r2,-32648\(r12\)
+.*	7d 69 03 a6 	mtctr   r11
+.*	e9 6c 80 80 	ld      r11,-32640\(r12\)
 .*	4e 80 04 20 	bctr
 
 .* <_start>:
-.*	38 62 80 08 	addi	r3,r2,-32760
-.*	4b ff ff e1 	bl	.*
-.*	e8 41 00 28 	ld	r2,40\(r1\)
-.*	38 62 80 18 	addi	r3,r2,-32744
-.*	4b ff ff d5 	bl	.*
-.*	e8 41 00 28 	ld	r2,40\(r1\)
-.*	3c 6d 00 00 	addis	r3,r13,0
+.*	38 62 80 08 	addi    r3,r2,-32760
+.*	4b ff ff e1 	bl      .*
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	38 62 80 18 	addi    r3,r2,-32744
+.*	4b ff ff d5 	bl      .*
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	3c 6d 00 00 	addis   r3,r13,0
 .*	60 00 00 00 	nop
-.*	38 63 90 38 	addi	r3,r3,-28616
-.*	3c 6d 00 00 	addis	r3,r13,0
+.*	38 63 90 38 	addi    r3,r3,-28616
+.*	3c 6d 00 00 	addis   r3,r13,0
 .*	60 00 00 00 	nop
-.*	38 63 10 00 	addi	r3,r3,4096
-.*	39 23 80 40 	addi	r9,r3,-32704
-.*	3d 23 00 00 	addis	r9,r3,0
-.*	81 49 80 48 	lwz	r10,-32696\(r9\)
-.*	e9 22 80 48 	ld	r9,-32696\(r2\)
-.*	7d 49 18 2a 	ldx	r10,r9,r3
-.*	3d 2d 00 00 	addis	r9,r13,0
-.*	a1 49 90 58 	lhz	r10,-28584\(r9\)
-.*	89 4d 90 60 	lbz	r10,-28576\(r13\)
-.*	3d 2d 00 00 	addis	r9,r13,0
-.*	99 49 90 68 	stb	r10,-28568\(r9\)
-.*	7d 89 02 a6 	mfctr	r12
-.*	78 0b 1f 24 	rldicr	r11,r0,3,60
-.*	34 40 80 00 	addic\.	r2,r0,-32768
-.*	7d 8b 60 50 	subf	r12,r11,r12
-.*	7c 42 fe 76 	sradi	r2,r2,63
-.*	78 0b 17 64 	rldicr	r11,r0,2,61
-.*	7c 42 58 38 	and	r2,r2,r11
-.*	7d 8b 60 50 	subf	r12,r11,r12
-.*	7d 8c 12 14 	add	r12,r12,r2
-.*	3d 8c 00 01 	addis	r12,r12,1
-.*	e9 6c 01 ec 	ld	r11,492\(r12\)
-.*	39 8c 01 ec 	addi	r12,r12,492
-.*	e8 4c 00 08 	ld	r2,8\(r12\)
-.*	7d 69 03 a6 	mtctr	r11
-.*	e9 6c 00 10 	ld	r11,16\(r12\)
+.*	38 63 10 00 	addi    r3,r3,4096
+.*	39 23 80 40 	addi    r9,r3,-32704
+.*	3d 23 00 00 	addis   r9,r3,0
+.*	81 49 80 48 	lwz     r10,-32696\(r9\)
+.*	e9 22 80 48 	ld      r9,-32696\(r2\)
+.*	7d 49 18 2a 	ldx     r10,r9,r3
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	a1 49 90 58 	lhz     r10,-28584\(r9\)
+.*	89 4d 90 60 	lbz     r10,-28576\(r13\)
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	99 49 90 68 	stb     r10,-28568\(r9\)
+.*	7d 89 02 a6 	mfctr   r12
+.*	78 0b 1f 24 	rldicr  r11,r0,3,60
+.*	34 40 80 00 	addic\.  r2,r0,-32768
+.*	7d 8b 60 50 	subf    r12,r11,r12
+.*	7c 42 fe 76 	sradi   r2,r2,63
+.*	78 0b 17 64 	rldicr  r11,r0,2,61
+.*	7c 42 58 38 	and     r2,r2,r11
+.*	7d 8b 60 50 	subf    r12,r11,r12
+.*	7d 8c 12 14 	add     r12,r12,r2
+.*	3d 8c 00 01 	addis   r12,r12,1
+.*	e9 6c 01 ec 	ld      r11,492\(r12\)
+.*	39 8c 01 ec 	addi    r12,r12,492
+.*	e8 4c 00 08 	ld      r2,8\(r12\)
+.*	7d 69 03 a6 	mtctr   r11
+.*	e9 6c 00 10 	ld      r11,16\(r12\)
 .*	4e 80 04 20 	bctr
-.*	38 00 00 00 	li	r0,0
-.*	4b ff ff bc 	b	.*
+.*	38 00 00 00 	li      r0,0
+.*	4b ff ff bc 	b       .*
diff --git a/ld/testsuite/ld-powerpc/tlsso.d b/ld/testsuite/ld-powerpc/tlsso.d
index 5f13b0415c4..dc4ae18256b 100644
--- a/ld/testsuite/ld-powerpc/tlsso.d
+++ b/ld/testsuite/ld-powerpc/tlsso.d
@@ -9,68 +9,68 @@
 Disassembly of section \.text:
 
 .* <\.__tls_get_addr>:
-.*	3d 82 00 00 	addis	r12,r2,0
-.*	f8 41 00 28 	std	r2,40\(r1\)
-.*	e9 6c 80 78 	ld	r11,-32648\(r12\)
-.*	e8 4c 80 80 	ld	r2,-32640\(r12\)
-.*	7d 69 03 a6 	mtctr	r11
-.*	e9 6c 80 88 	ld	r11,-32632\(r12\)
+.*	3d 82 00 00 	addis   r12,r2,0
+.*	f8 41 00 28 	std     r2,40\(r1\)
+.*	e9 6c 80 78 	ld      r11,-32648\(r12\)
+.*	e8 4c 80 80 	ld      r2,-32640\(r12\)
+.*	7d 69 03 a6 	mtctr   r11
+.*	e9 6c 80 88 	ld      r11,-32632\(r12\)
 .*	4e 80 04 20 	bctr
 
 .* <_start>:
-.*	38 62 80 30 	addi	r3,r2,-32720
-.*	4b ff ff e1 	bl	.* <\.__tls_get_addr>
-.*	e8 41 00 28 	ld	r2,40\(r1\)
-.*	38 62 80 08 	addi	r3,r2,-32760
-.*	4b ff ff d5 	bl	.* <\.__tls_get_addr>
-.*	e8 41 00 28 	ld	r2,40\(r1\)
-.*	38 62 80 48 	addi	r3,r2,-32696
-.*	4b ff ff c9 	bl	.* <\.__tls_get_addr>
-.*	e8 41 00 28 	ld	r2,40\(r1\)
-.*	38 62 80 08 	addi	r3,r2,-32760
-.*	4b ff ff bd 	bl	.* <\.__tls_get_addr>
-.*	e8 41 00 28 	ld	r2,40\(r1\)
-.*	39 23 80 40 	addi	r9,r3,-32704
-.*	3d 23 00 00 	addis	r9,r3,0
-.*	81 49 80 48 	lwz	r10,-32696\(r9\)
-.*	e9 22 80 40 	ld	r9,-32704\(r2\)
-.*	7d 49 18 2a 	ldx	r10,r9,r3
-.*	e9 22 80 58 	ld	r9,-32680\(r2\)
-.*	7d 49 6a 2e 	lhzx	r10,r9,r13
-.*	89 4d 00 00 	lbz	r10,0\(r13\)
-.*	3d 2d 00 00 	addis	r9,r13,0
-.*	99 49 00 00 	stb	r10,0\(r9\)
-.*	38 62 80 18 	addi	r3,r2,-32744
-.*	4b ff ff 89 	bl	.* <\.__tls_get_addr>
-.*	e8 41 00 28 	ld	r2,40\(r1\)
-.*	38 62 80 08 	addi	r3,r2,-32760
-.*	4b ff ff 7d 	bl	.* <\.__tls_get_addr>
-.*	e8 41 00 28 	ld	r2,40\(r1\)
-.*	f9 43 80 08 	std	r10,-32760\(r3\)
-.*	3d 23 00 00 	addis	r9,r3,0
-.*	91 49 80 10 	stw	r10,-32752\(r9\)
-.*	e9 22 80 28 	ld	r9,-32728\(r2\)
-.*	7d 49 19 2a 	stdx	r10,r9,r3
-.*	e9 22 80 58 	ld	r9,-32680\(r2\)
-.*	7d 49 6b 2e 	sthx	r10,r9,r13
-.*	e9 4d 00 02 	lwa	r10,0\(r13\)
-.*	3d 2d 00 00 	addis	r9,r13,0
-.*	a9 49 00 00 	lha	r10,0\(r9\)
-.*	7d 89 02 a6 	mfctr	r12
-.*	78 0b 1f 24 	rldicr	r11,r0,3,60
-.*	34 40 80 00 	addic\.	r2,r0,-32768
-.*	7d 8b 60 50 	subf	r12,r11,r12
-.*	7c 42 fe 76 	sradi	r2,r2,63
-.*	78 0b 17 64 	rldicr	r11,r0,2,61
-.*	7c 42 58 38 	and	r2,r2,r11
-.*	7d 8b 60 50 	subf	r12,r11,r12
-.*	7d 8c 12 14 	add	r12,r12,r2
-.*	3d 8c 00 01 	addis	r12,r12,1
-.*	e9 6c 01 f4 	ld	r11,500\(r12\)
-.*	39 8c 01 f4 	addi	r12,r12,500
-.*	e8 4c 00 08 	ld	r2,8\(r12\)
-.*	7d 69 03 a6 	mtctr	r11
-.*	e9 6c 00 10 	ld	r11,16\(r12\)
+.*	38 62 80 30 	addi    r3,r2,-32720
+.*	4b ff ff e1 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	38 62 80 08 	addi    r3,r2,-32760
+.*	4b ff ff d5 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	38 62 80 48 	addi    r3,r2,-32696
+.*	4b ff ff c9 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	38 62 80 08 	addi    r3,r2,-32760
+.*	4b ff ff bd 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	39 23 80 40 	addi    r9,r3,-32704
+.*	3d 23 00 00 	addis   r9,r3,0
+.*	81 49 80 48 	lwz     r10,-32696\(r9\)
+.*	e9 22 80 40 	ld      r9,-32704\(r2\)
+.*	7d 49 18 2a 	ldx     r10,r9,r3
+.*	e9 22 80 58 	ld      r9,-32680\(r2\)
+.*	7d 49 6a 2e 	lhzx    r10,r9,r13
+.*	89 4d 00 00 	lbz     r10,0\(r13\)
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	99 49 00 00 	stb     r10,0\(r9\)
+.*	38 62 80 18 	addi    r3,r2,-32744
+.*	4b ff ff 89 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	38 62 80 08 	addi    r3,r2,-32760
+.*	4b ff ff 7d 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	f9 43 80 08 	std     r10,-32760\(r3\)
+.*	3d 23 00 00 	addis   r9,r3,0
+.*	91 49 80 10 	stw     r10,-32752\(r9\)
+.*	e9 22 80 28 	ld      r9,-32728\(r2\)
+.*	7d 49 19 2a 	stdx    r10,r9,r3
+.*	e9 22 80 58 	ld      r9,-32680\(r2\)
+.*	7d 49 6b 2e 	sthx    r10,r9,r13
+.*	e9 4d 00 02 	lwa     r10,0\(r13\)
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	a9 49 00 00 	lha     r10,0\(r9\)
+.*	7d 89 02 a6 	mfctr   r12
+.*	78 0b 1f 24 	rldicr  r11,r0,3,60
+.*	34 40 80 00 	addic\.  r2,r0,-32768
+.*	7d 8b 60 50 	subf    r12,r11,r12
+.*	7c 42 fe 76 	sradi   r2,r2,63
+.*	78 0b 17 64 	rldicr  r11,r0,2,61
+.*	7c 42 58 38 	and     r2,r2,r11
+.*	7d 8b 60 50 	subf    r12,r11,r12
+.*	7d 8c 12 14 	add     r12,r12,r2
+.*	3d 8c 00 01 	addis   r12,r12,1
+.*	e9 6c 01 f4 	ld      r11,500\(r12\)
+.*	39 8c 01 f4 	addi    r12,r12,500
+.*	e8 4c 00 08 	ld      r2,8\(r12\)
+.*	7d 69 03 a6 	mtctr   r11
+.*	e9 6c 00 10 	ld      r11,16\(r12\)
 .*	4e 80 04 20 	bctr
-.*	38 00 00 00 	li	r0,0
-.*	4b ff ff bc 	b	.*
+.*	38 00 00 00 	li      r0,0
+.*	4b ff ff bc 	b       .*
diff --git a/ld/testsuite/ld-powerpc/tlsso32.d b/ld/testsuite/ld-powerpc/tlsso32.d
index 1e9ba31a0ac..3cf6a76d13e 100644
--- a/ld/testsuite/ld-powerpc/tlsso32.d
+++ b/ld/testsuite/ld-powerpc/tlsso32.d
@@ -9,34 +9,34 @@
 Disassembly of section \.text:
 
 0+538 <_start>:
- 538:	38 7f 00 1c 	addi	r3,r31,28
- 53c:	48 00 00 01 	bl	53c .*
- 540:	38 7f 00 0c 	addi	r3,r31,12
- 544:	48 00 00 01 	bl	544 .*
- 548:	38 7f 00 24 	addi	r3,r31,36
- 54c:	48 01 01 95 	bl	106e0 .*
- 550:	38 7f 00 0c 	addi	r3,r31,12
- 554:	48 01 01 8d 	bl	106e0 .*
- 558:	39 23 80 20 	addi	r9,r3,-32736
- 55c:	3d 23 00 00 	addis	r9,r3,0
- 560:	81 49 80 24 	lwz	r10,-32732\(r9\)
- 564:	81 3f 00 2c 	lwz	r9,44\(r31\)
- 568:	7d 49 12 2e 	lhzx	r10,r9,r2
- 56c:	89 42 00 00 	lbz	r10,0\(r2\)
- 570:	3d 22 00 00 	addis	r9,r2,0
- 574:	99 49 00 00 	stb	r10,0\(r9\)
- 578:	38 7e 00 14 	addi	r3,r30,20
- 57c:	48 00 00 01 	bl	57c .*
- 580:	38 7e 00 0c 	addi	r3,r30,12
- 584:	48 00 00 01 	bl	584 .*
- 588:	91 43 80 04 	stw	r10,-32764\(r3\)
- 58c:	3d 23 00 00 	addis	r9,r3,0
- 590:	91 49 80 08 	stw	r10,-32760\(r9\)
- 594:	81 3e 00 2c 	lwz	r9,44\(r30\)
- 598:	7d 49 13 2e 	sthx	r10,r9,r2
- 59c:	a1 42 00 00 	lhz	r10,0\(r2\)
- 5a0:	3d 22 00 00 	addis	r9,r2,0
- 5a4:	a9 49 00 00 	lha	r10,0\(r9\)
+ 538:	38 7f 00 1c 	addi    r3,r31,28
+ 53c:	48 00 00 01 	bl      53c .*
+ 540:	38 7f 00 0c 	addi    r3,r31,12
+ 544:	48 00 00 01 	bl      544 .*
+ 548:	38 7f 00 24 	addi    r3,r31,36
+ 54c:	48 01 01 95 	bl      106e0 .*
+ 550:	38 7f 00 0c 	addi    r3,r31,12
+ 554:	48 01 01 8d 	bl      106e0 .*
+ 558:	39 23 80 20 	addi    r9,r3,-32736
+ 55c:	3d 23 00 00 	addis   r9,r3,0
+ 560:	81 49 80 24 	lwz     r10,-32732\(r9\)
+ 564:	81 3f 00 2c 	lwz     r9,44\(r31\)
+ 568:	7d 49 12 2e 	lhzx    r10,r9,r2
+ 56c:	89 42 00 00 	lbz     r10,0\(r2\)
+ 570:	3d 22 00 00 	addis   r9,r2,0
+ 574:	99 49 00 00 	stb     r10,0\(r9\)
+ 578:	38 7e 00 14 	addi    r3,r30,20
+ 57c:	48 00 00 01 	bl      57c .*
+ 580:	38 7e 00 0c 	addi    r3,r30,12
+ 584:	48 00 00 01 	bl      584 .*
+ 588:	91 43 80 04 	stw     r10,-32764\(r3\)
+ 58c:	3d 23 00 00 	addis   r9,r3,0
+ 590:	91 49 80 08 	stw     r10,-32760\(r9\)
+ 594:	81 3e 00 2c 	lwz     r9,44\(r30\)
+ 598:	7d 49 13 2e 	sthx    r10,r9,r2
+ 59c:	a1 42 00 00 	lhz     r10,0\(r2\)
+ 5a0:	3d 22 00 00 	addis   r9,r2,0
+ 5a4:	a9 49 00 00 	lha     r10,0\(r9\)
 Disassembly of section \.got:
 
 00010664 <\.got>:
diff --git a/ld/testsuite/ld-powerpc/tlstoc.d b/ld/testsuite/ld-powerpc/tlstoc.d
index c111a5d3dbd..cfa8abab208 100644
--- a/ld/testsuite/ld-powerpc/tlstoc.d
+++ b/ld/testsuite/ld-powerpc/tlstoc.d
@@ -13,25 +13,25 @@ Disassembly of section \.text:
 .*	4e 80 00 20 	blr
 
 .* <_start>:
-.*	3c 6d 00 00 	addis	r3,r13,0
+.*	3c 6d 00 00 	addis   r3,r13,0
 .*	60 00 00 00 	nop
-.*	38 63 90 40 	addi	r3,r3,-28608
-.*	3c 6d 00 00 	addis	r3,r13,0
+.*	38 63 90 40 	addi    r3,r3,-28608
+.*	3c 6d 00 00 	addis   r3,r13,0
 .*	60 00 00 00 	nop
-.*	38 63 10 00 	addi	r3,r3,4096
-.*	3c 6d 00 00 	addis	r3,r13,0
+.*	38 63 10 00 	addi    r3,r3,4096
+.*	3c 6d 00 00 	addis   r3,r13,0
 .*	60 00 00 00 	nop
-.*	38 63 90 48 	addi	r3,r3,-28600
-.*	3c 6d 00 00 	addis	r3,r13,0
+.*	38 63 90 48 	addi    r3,r3,-28600
+.*	3c 6d 00 00 	addis   r3,r13,0
 .*	60 00 00 00 	nop
-.*	38 63 10 00 	addi	r3,r3,4096
-.*	39 23 80 50 	addi	r9,r3,-32688
-.*	3d 23 00 00 	addis	r9,r3,0
-.*	81 49 80 58 	lwz	r10,-32680\(r9\)
-.*	e9 22 80 40 	ld	r9,-32704\(r2\)
-.*	7d 49 18 2a 	ldx	r10,r9,r3
-.*	3d 2d 00 00 	addis	r9,r13,0
-.*	a1 49 90 68 	lhz	r10,-28568\(r9\)
-.*	89 4d 90 70 	lbz	r10,-28560\(r13\)
-.*	3d 2d 00 00 	addis	r9,r13,0
-.*	99 49 90 78 	stb	r10,-28552\(r9\)
+.*	38 63 10 00 	addi    r3,r3,4096
+.*	39 23 80 50 	addi    r9,r3,-32688
+.*	3d 23 00 00 	addis   r9,r3,0
+.*	81 49 80 58 	lwz     r10,-32680\(r9\)
+.*	e9 22 80 40 	ld      r9,-32704\(r2\)
+.*	7d 49 18 2a 	ldx     r10,r9,r3
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	a1 49 90 68 	lhz     r10,-28568\(r9\)
+.*	89 4d 90 70 	lbz     r10,-28560\(r13\)
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	99 49 90 78 	stb     r10,-28552\(r9\)
diff --git a/ld/testsuite/ld-powerpc/tlstocso.d b/ld/testsuite/ld-powerpc/tlstocso.d
index 8ea7627c1cd..0534b3bccc5 100644
--- a/ld/testsuite/ld-powerpc/tlstocso.d
+++ b/ld/testsuite/ld-powerpc/tlstocso.d
@@ -9,52 +9,52 @@
 Disassembly of section \.text:
 
 .* <\.__tls_get_addr>:
-.*	3d 82 00 00 	addis	r12,r2,0
-.*	f8 41 00 28 	std	r2,40\(r1\)
-.*	e9 6c 80 70 	ld	r11,-32656\(r12\)
-.*	e8 4c 80 78 	ld	r2,-32648\(r12\)
-.*	7d 69 03 a6 	mtctr	r11
-.*	e9 6c 80 80 	ld	r11,-32640\(r12\)
+.*	3d 82 00 00 	addis   r12,r2,0
+.*	f8 41 00 28 	std     r2,40\(r1\)
+.*	e9 6c 80 70 	ld      r11,-32656\(r12\)
+.*	e8 4c 80 78 	ld      r2,-32648\(r12\)
+.*	7d 69 03 a6 	mtctr   r11
+.*	e9 6c 80 80 	ld      r11,-32640\(r12\)
 .*	4e 80 04 20 	bctr
 
 .* <_start>:
-.*	38 62 80 08 	addi	r3,r2,-32760
-.*	4b ff ff e1 	bl	.* <\.__tls_get_addr>
-.*	e8 41 00 28 	ld	r2,40\(r1\)
-.*	38 62 80 18 	addi	r3,r2,-32744
-.*	4b ff ff d5 	bl	.* <\.__tls_get_addr>
-.*	e8 41 00 28 	ld	r2,40\(r1\)
-.*	38 62 80 28 	addi	r3,r2,-32728
-.*	4b ff ff c9 	bl	.* <\.__tls_get_addr>
-.*	e8 41 00 28 	ld	r2,40\(r1\)
-.*	38 62 80 38 	addi	r3,r2,-32712
-.*	4b ff ff bd 	bl	.* <\.__tls_get_addr>
-.*	e8 41 00 28 	ld	r2,40\(r1\)
-.*	39 23 80 40 	addi	r9,r3,-32704
-.*	3d 23 00 00 	addis	r9,r3,0
-.*	81 49 80 48 	lwz	r10,-32696\(r9\)
-.*	e9 22 80 48 	ld	r9,-32696\(r2\)
-.*	7d 49 18 2a 	ldx	r10,r9,r3
-.*	e9 22 80 50 	ld	r9,-32688\(r2\)
-.*	7d 49 6a 2e 	lhzx	r10,r9,r13
-.*	89 4d 00 00 	lbz	r10,0\(r13\)
-.*	3d 2d 00 00 	addis	r9,r13,0
-.*	99 49 00 00 	stb	r10,0\(r9\)
-.*	7d 89 02 a6 	mfctr	r12
-.*	78 0b 1f 24 	rldicr	r11,r0,3,60
-.*	34 40 80 00 	addic\.	r2,r0,-32768
-.*	7d 8b 60 50 	subf	r12,r11,r12
-.*	7c 42 fe 76 	sradi	r2,r2,63
-.*	78 0b 17 64 	rldicr	r11,r0,2,61
-.*	7c 42 58 38 	and	r2,r2,r11
-.*	7d 8b 60 50 	subf	r12,r11,r12
-.*	7d 8c 12 14 	add	r12,r12,r2
-.*	3d 8c 00 01 	addis	r12,r12,1
-.*	e9 6c 01 ec 	ld	r11,492\(r12\)
-.*	39 8c 01 ec 	addi	r12,r12,492
-.*	e8 4c 00 08 	ld	r2,8\(r12\)
-.*	7d 69 03 a6 	mtctr	r11
-.*	e9 6c 00 10 	ld	r11,16\(r12\)
+.*	38 62 80 08 	addi    r3,r2,-32760
+.*	4b ff ff e1 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	38 62 80 18 	addi    r3,r2,-32744
+.*	4b ff ff d5 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	38 62 80 28 	addi    r3,r2,-32728
+.*	4b ff ff c9 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	38 62 80 38 	addi    r3,r2,-32712
+.*	4b ff ff bd 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	39 23 80 40 	addi    r9,r3,-32704
+.*	3d 23 00 00 	addis   r9,r3,0
+.*	81 49 80 48 	lwz     r10,-32696\(r9\)
+.*	e9 22 80 48 	ld      r9,-32696\(r2\)
+.*	7d 49 18 2a 	ldx     r10,r9,r3
+.*	e9 22 80 50 	ld      r9,-32688\(r2\)
+.*	7d 49 6a 2e 	lhzx    r10,r9,r13
+.*	89 4d 00 00 	lbz     r10,0\(r13\)
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	99 49 00 00 	stb     r10,0\(r9\)
+.*	7d 89 02 a6 	mfctr   r12
+.*	78 0b 1f 24 	rldicr  r11,r0,3,60
+.*	34 40 80 00 	addic\.  r2,r0,-32768
+.*	7d 8b 60 50 	subf    r12,r11,r12
+.*	7c 42 fe 76 	sradi   r2,r2,63
+.*	78 0b 17 64 	rldicr  r11,r0,2,61
+.*	7c 42 58 38 	and     r2,r2,r11
+.*	7d 8b 60 50 	subf    r12,r11,r12
+.*	7d 8c 12 14 	add     r12,r12,r2
+.*	3d 8c 00 01 	addis   r12,r12,1
+.*	e9 6c 01 ec 	ld      r11,492\(r12\)
+.*	39 8c 01 ec 	addi    r12,r12,492
+.*	e8 4c 00 08 	ld      r2,8\(r12\)
+.*	7d 69 03 a6 	mtctr   r11
+.*	e9 6c 00 10 	ld      r11,16\(r12\)
 .*	4e 80 04 20 	bctr
-.*	38 00 00 00 	li	r0,0
-.*	4b ff ff bc 	b	.*
+.*	38 00 00 00 	li      r0,0
+.*	4b ff ff bc 	b       .*
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c953d140f02..925b6abd356 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2004-03-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
+	PPC_OPERANDS_GPR_0.
+	* ppc-opc.c (RA0): Define.
+	(RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
+	(RAOPT): Rename from RAO.  Update all uses.
+	(powerpc_opcodes): Use RA0 as appropriate.  Add "lsdx", "lsdi",
+	"stsdx", "stsdi", "lmd" and "stmd" insns.
+
 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 
 	* sparc-dis.c (print_insn_sparc): Update getword prototype.
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 76af4e7af12..4d48b9d4b70 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -1,5 +1,5 @@
 /* ppc-dis.c -- Disassemble PowerPC instructions
-   Copyright 1994, 1995, 2000, 2001, 2002, 2003
+   Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004
    Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 
@@ -191,9 +191,10 @@ print_insn_powerpc (bfd_vma memaddr,
 	continue;
 
       /* The instruction is valid.  */
-      (*info->fprintf_func) (info->stream, "%s", opcode->name);
       if (opcode->operands[0] != 0)
-	(*info->fprintf_func) (info->stream, "\t");
+	(*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
+      else
+	(*info->fprintf_func) (info->stream, "%s", opcode->name);
 
       /* Now extract and print the operands.  */
       need_comma = 0;
@@ -235,7 +236,8 @@ print_insn_powerpc (bfd_vma memaddr,
 	    }
 
 	  /* Print the operand as directed by the flags.  */
-	  if ((operand->flags & PPC_OPERAND_GPR) != 0)
+	  if ((operand->flags & PPC_OPERAND_GPR) != 0
+	      || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
 	    (*info->fprintf_func) (info->stream, "r%ld", value);
 	  else if ((operand->flags & PPC_OPERAND_FPR) != 0)
 	    (*info->fprintf_func) (info->stream, "f%ld", value);
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index d011edf7381..fa76c31d808 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1,5 +1,5 @@
 /* ppc-opc.c -- PowerPC opcode list
-   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
+   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004
    Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 
@@ -362,34 +362,38 @@ const struct powerpc_operand powerpc_operands[] =
 #define RA_MASK (0x1f << 16)
   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 
-  /* The RA field in the DQ form lq instruction, which has special 
+  /* As above, but 0 in the RA field means zero, not r0.  */
+#define RA0 RA + 1
+  { 5, 16, 0, 0, PPC_OPERAND_GPR_0 },
+
+  /* The RA field in the DQ form lq instruction, which has special
      value restrictions.  */
-#define RAQ RA + 1
-  { 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
+#define RAQ RA0 + 1
+  { 5, 16, insert_raq, 0, PPC_OPERAND_GPR_0 },
 
   /* The RA field in a D or X form instruction which is an updating
      load, which means that the RA field may not be zero and may not
      equal the RT field.  */
 #define RAL RAQ + 1
-  { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
+  { 5, 16, insert_ral, 0, PPC_OPERAND_GPR_0 },
 
   /* The RA field in an lmw instruction, which has special value
      restrictions.  */
 #define RAM RAL + 1
-  { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
+  { 5, 16, insert_ram, 0, PPC_OPERAND_GPR_0 },
 
   /* The RA field in a D or X form instruction which is an updating
      store or an updating floating point load, which means that the RA
      field may not be zero.  */
 #define RAS RAM + 1
-  { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
+  { 5, 16, insert_ras, 0, PPC_OPERAND_GPR_0 },
 
   /* The RA field of the tlbwe instruction, which is optional.  */
-#define RAO RAS + 1
-  { 5, 16, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL },
+#define RAOPT RAS + 1
+  { 5, 16, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 
   /* The RB field in an X, XO, M, or MDS form instruction.  */
-#define RB RAO + 1
+#define RB RAOPT + 1
 #define RB_MASK (0x1f << 11)
   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 
@@ -407,19 +411,19 @@ const struct powerpc_operand powerpc_operands[] =
 #define RT_MASK (0x1f << 21)
   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 
-  /* The RS field of the DS form stq instruction, which has special 
+  /* The RS field of the DS form stq instruction, which has special
      value restrictions.  */
 #define RSQ RS + 1
-  { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
+  { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR_0 },
 
   /* The RT field of the DQ form lq instruction, which has special
      value restrictions.  */
 #define RTQ RSQ + 1
-  { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
+  { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR_0 },
 
   /* The RS field of the tlbwe instruction, which is optional.  */
 #define RSO RTQ + 1
-  { 5, 21, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL },
+  { 5, 21, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 
   /* The SH field in an X or M form instruction.  */
 #define SH RSO + 1
@@ -1256,7 +1260,7 @@ insert_ram (unsigned long insn,
   return insn | ((value & 0x1f) << 16);
 }
 
-/* The RA field in the DQ form lq instruction, which has special 
+/* The RA field in the DQ form lq instruction, which has special
    value restrictions.  */
 
 static unsigned long
@@ -1326,7 +1330,7 @@ insert_rtq (unsigned long insn,
   return insn | ((value & 0x1f) << 21);
 }
 
-/* The RS field of the DS form stq instruction, which has special 
+/* The RS field of the DS form stq instruction, which has special
    value restrictions.  */
 
 static unsigned long
@@ -1478,11 +1482,11 @@ extract_tbr (unsigned long insn,
 
 /* An Context form instruction.  */
 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
-#define CTX_MASK       CTX(0x3f, 0x7)
+#define CTX_MASK CTX(0x3f, 0x7)
 
 /* An User Context form instruction.  */
 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
-#define UCTX_MASK      UCTX(0x3f, 0x1f)
+#define UCTX_MASK UCTX(0x3f, 0x1f)
 
 /* The main opcode mask with the RA field clear.  */
 #define DRA_MASK (OP_MASK | RA_MASK)
@@ -2373,16 +2377,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "li",	     OP(14),	DRA_MASK,	PPCCOM,		{ RT, SI } },
 { "lil",     OP(14),	DRA_MASK,	PWRCOM,		{ RT, SI } },
-{ "addi",    OP(14),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
-{ "cal",     OP(14),	OP_MASK,	PWRCOM,		{ RT, D, RA } },
-{ "subi",    OP(14),	OP_MASK,	PPCCOM,		{ RT, RA, NSI } },
-{ "la",	     OP(14),	OP_MASK,	PPCCOM,		{ RT, D, RA } },
+{ "addi",    OP(14),	OP_MASK,	PPCCOM,		{ RT, RA0, SI } },
+{ "cal",     OP(14),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
+{ "subi",    OP(14),	OP_MASK,	PPCCOM,		{ RT, RA0, NSI } },
+{ "la",	     OP(14),	OP_MASK,	PPCCOM,		{ RT, D, RA0 } },
 
 { "lis",     OP(15),	DRA_MASK,	PPCCOM,		{ RT, SISIGNOPT } },
 { "liu",     OP(15),	DRA_MASK,	PWRCOM,		{ RT, SISIGNOPT } },
-{ "addis",   OP(15),	OP_MASK,	PPCCOM,		{ RT,RA,SISIGNOPT } },
-{ "cau",     OP(15),	OP_MASK,	PWRCOM,		{ RT,RA,SISIGNOPT } },
-{ "subis",   OP(15),	OP_MASK,	PPCCOM,		{ RT, RA, NSI } },
+{ "addis",   OP(15),	OP_MASK,	PPCCOM,		{ RT,RA0,SISIGNOPT } },
+{ "cau",     OP(15),	OP_MASK,	PWRCOM,		{ RT,RA0,SISIGNOPT } },
+{ "subis",   OP(15),	OP_MASK,	PPCCOM,		{ RT, RA0, NSI } },
 
 { "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,	{ BDM } },
 { "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,	{ BDP } },
@@ -3215,14 +3219,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfcr",    X(31,19),	XRARB_MASK,	NOPOWER4,	{ RT } },
 { "mfcr",    X(31,19),	XFXFXM_MASK,	POWER4,		{ RT, FXM4 } },
 
-{ "lwarx",   X(31,20),	X_MASK,		PPC,		{ RT, RA, RB } },
+{ "lwarx",   X(31,20),	X_MASK,		PPC,		{ RT, RA0, RB } },
 
-{ "ldx",     X(31,21),	X_MASK,		PPC64,		{ RT, RA, RB } },
+{ "ldx",     X(31,21),	X_MASK,		PPC64,		{ RT, RA0, RB } },
 
 { "icbt",    X(31,22),	X_MASK,		BOOKE,		{ CT, RA, RB } },
 { "icbt",    X(31,262),	XRT_MASK,	PPC403,		{ RA, RB } },
 
-{ "lwzx",    X(31,23),	X_MASK,		PPCCOM,		{ RT, RA, RB } },
+{ "lwzx",    X(31,23),	X_MASK,		PPCCOM,		{ RT, RA0, RB } },
 { "lx",      X(31,23),	X_MASK,		PWRCOM,		{ RT, RA, RB } },
 
 { "slw",     XRC(31,24,0), X_MASK,	PPCCOM,		{ RA, RS, RB } },
@@ -3246,7 +3250,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "icbte",   X(31,30),	X_MASK,		BOOKE64,	{ CT, RA, RB } },
 
-{ "lwzxe",   X(31,31),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
+{ "lwzxe",   X(31,31),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
 
 { "cmplw",   XCMPL(31,32,0), XCMPL_MASK, PPCCOM,	{ OBF, RA, RB } },
 { "cmpld",   XCMPL(31,32,1), XCMPL_MASK, PPC64,		{ OBF, RA, RB } },
@@ -3308,15 +3312,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mfmsr",   X(31,83),	XRARB_MASK,	COM,		{ RT } },
 
-{ "ldarx",   X(31,84),	X_MASK,		PPC64,		{ RT, RA, RB } },
+{ "ldarx",   X(31,84),	X_MASK,		PPC64,		{ RT, RA0, RB } },
 
 { "dcbf",    X(31,86),	XRT_MASK,	PPC,		{ RA, RB } },
 
-{ "lbzx",    X(31,87),	X_MASK,		COM,		{ RT, RA, RB } },
+{ "lbzx",    X(31,87),	X_MASK,		COM,		{ RT, RA0, RB } },
 
 { "dcbfe",   X(31,94),	XRT_MASK,	BOOKE64,	{ RA, RB } },
 
-{ "lbzxe",   X(31,95),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
+{ "lbzxe",   X(31,95),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
 
 { "neg",     XO(31,104,0,0), XORB_MASK,	COM,		{ RT, RA } },
 { "neg.",    XO(31,104,0,1), XORB_MASK,	COM,		{ RT, RA } },
@@ -3339,7 +3343,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "not.",    XRC(31,124,1), X_MASK,	COM,		{ RA, RS, RBS } },
 { "nor.",    XRC(31,124,1), X_MASK,	COM,		{ RA, RS, RB } },
 
-{ "lwarxe",  X(31,126),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
+{ "lwarxe",  X(31,126),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
 
 { "lbzuxe",  X(31,127),	X_MASK,		BOOKE64,	{ RT, RAL, RB } },
 
@@ -3372,16 +3376,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mtmsr",   X(31,146),	XRARB_MASK,	COM,		{ RS } },
 
-{ "stdx",    X(31,149), X_MASK,		PPC64,		{ RS, RA, RB } },
+{ "stdx",    X(31,149), X_MASK,		PPC64,		{ RS, RA0, RB } },
 
-{ "stwcx.",  XRC(31,150,1), X_MASK,	PPC,		{ RS, RA, RB } },
+{ "stwcx.",  XRC(31,150,1), X_MASK,	PPC,		{ RS, RA0, RB } },
 
-{ "stwx",    X(31,151), X_MASK,		PPCCOM,		{ RS, RA, RB } },
+{ "stwx",    X(31,151), X_MASK,		PPCCOM,		{ RS, RA0, RB } },
 { "stx",     X(31,151), X_MASK,		PWRCOM,		{ RS, RA, RB } },
 
-{ "stwcxe.", XRC(31,158,1), X_MASK,	BOOKE64,	{ RS, RA, RB } },
+{ "stwcxe.", XRC(31,158,1), X_MASK,	BOOKE64,	{ RS, RA0, RB } },
 
-{ "stwxe",   X(31,159), X_MASK,		BOOKE64,	{ RS, RA, RB } },
+{ "stwxe",   X(31,159), X_MASK,		BOOKE64,	{ RS, RA0, RB } },
 
 { "slq",     XRC(31,152,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "slq.",    XRC(31,152,1), X_MASK,	M601,		{ RA, RS, RB } },
@@ -3399,7 +3403,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "stdux",   X(31,181),	X_MASK,		PPC64,		{ RS, RAS, RB } },
 
 { "stwux",   X(31,183),	X_MASK,		PPCCOM,		{ RS, RAS, RB } },
-{ "stux",    X(31,183),	X_MASK,		PWRCOM,		{ RS, RA, RB } },
+{ "stux",    X(31,183),	X_MASK,		PWRCOM,		{ RS, RA0, RB } },
 
 { "sliq",    XRC(31,184,0), X_MASK,	M601,		{ RA, RS, SH } },
 { "sliq.",   XRC(31,184,1), X_MASK,	M601,		{ RA, RS, SH } },
@@ -3426,9 +3430,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mtsr",    X(31,210),	XRB_MASK|(1<<20), COM32,	{ SR, RS } },
 
-{ "stdcx.",  XRC(31,214,1), X_MASK,	PPC64,		{ RS, RA, RB } },
+{ "stdcx.",  XRC(31,214,1), X_MASK,	PPC64,		{ RS, RA0, RB } },
 
-{ "stbx",    X(31,215),	X_MASK,		COM,		{ RS, RA, RB } },
+{ "stbx",    X(31,215),	X_MASK,		COM,		{ RS, RA0, RB } },
 
 { "sllq",    XRC(31,216,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "sllq.",   XRC(31,216,1), X_MASK,	M601,		{ RA, RS, RB } },
@@ -3436,7 +3440,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "sleq",    XRC(31,217,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "sleq.",   XRC(31,217,1), X_MASK,	M601,		{ RA, RS, RB } },
 
-{ "stbxe",   X(31,223),	X_MASK,		BOOKE64,	{ RS, RA, RB } },
+{ "stbxe",   X(31,223),	X_MASK,		BOOKE64,	{ RS, RA0, RB } },
 
 { "icblc",   X(31,230),	X_MASK,		PPCCHLK,	{ CT, RA, RB }},
 
@@ -3512,17 +3516,17 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "dcbt",    X(31,278),	XRT_MASK,	PPC,		{ CT, RA, RB } },
 
-{ "lhzx",    X(31,279),	X_MASK,		COM,		{ RT, RA, RB } },
+{ "lhzx",    X(31,279),	X_MASK,		COM,		{ RT, RA0, RB } },
 
 { "eqv",     XRC(31,284,0), X_MASK,	COM,		{ RA, RS, RB } },
 { "eqv.",    XRC(31,284,1), X_MASK,	COM,		{ RA, RS, RB } },
 
 { "dcbte",   X(31,286),	X_MASK,		BOOKE64,	{ CT, RA, RB } },
 
-{ "lhzxe",   X(31,287),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
+{ "lhzxe",   X(31,287),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
 
 { "tlbie",   X(31,306),	XRTLRA_MASK,	PPC,		{ RB, L } },
-{ "tlbi",    X(31,306),	XRT_MASK,	POWER,		{ RA, RB } },
+{ "tlbi",    X(31,306),	XRT_MASK,	POWER,		{ RA0, RB } },
 
 { "eciwx",   X(31,310), X_MASK,		PPC,		{ RT, RA, RB } },
 
@@ -3759,14 +3763,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,	{ RT } },
 { "mfspr",      X(31,339),	   X_MASK,    COM,	{ RT, SPR } },
 
-{ "lwax",    X(31,341),	X_MASK,		PPC64,		{ RT, RA, RB } },
+{ "lwax",    X(31,341),	X_MASK,		PPC64,		{ RT, RA0, RB } },
 
 { "dst",     XDSS(31,342,0), XDSS_MASK,	PPCVEC,		{ RA, RB, STRM } },
 { "dstt",    XDSS(31,342,1), XDSS_MASK,	PPCVEC,		{ RA, RB, STRM } },
 
-{ "lhax",    X(31,343),	X_MASK,		COM,		{ RT, RA, RB } },
+{ "lhax",    X(31,343),	X_MASK,		COM,		{ RT, RA0, RB } },
 
-{ "lhaxe",   X(31,351),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
+{ "lhaxe",   X(31,351),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
 
 { "dstst",   XDSS(31,374,0), XDSS_MASK,	PPCVEC,		{ RA, RB, STRM } },
 { "dststt",  XDSS(31,374,1), XDSS_MASK,	PPCVEC,		{ RA, RB, STRM } },
@@ -3805,7 +3809,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "slbmte",  X(31,402), XRA_MASK,	PPC64,		{ RS, RB } },
 
-{ "sthx",    X(31,407),	X_MASK,		COM,		{ RS, RA, RB } },
+{ "sthx",    X(31,407),	X_MASK,		COM,		{ RS, RA0, RB } },
 
 { "lfqx",    X(31,791),	X_MASK,		POWER2,		{ FRT, RA, RB } },
 
@@ -3821,7 +3825,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "sradi",   XS(31,413,0), XS_MASK,	PPC64,		{ RA, RS, SH6 } },
 { "sradi.",  XS(31,413,1), XS_MASK,	PPC64,		{ RA, RS, SH6 } },
 
-{ "sthxe",   X(31,415),	X_MASK,		BOOKE64,	{ RS, RA, RB } },
+{ "sthxe",   X(31,415),	X_MASK,		BOOKE64,	{ RS, RA0, RB } },
 
 { "slbie",   X(31,434),	XRTRA_MASK,	PPC64,		{ RB } },
 
@@ -4085,13 +4089,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "clcs",    X(31,531), XRB_MASK,	M601,		{ RT, RA } },
 
-{ "lswx",    X(31,533),	X_MASK,		PPCCOM,		{ RT, RA, RB } },
+{ "lswx",    X(31,533),	X_MASK,		PPCCOM,		{ RT, RA0, RB } },
 { "lsx",     X(31,533),	X_MASK,		PWRCOM,		{ RT, RA, RB } },
 
-{ "lwbrx",   X(31,534),	X_MASK,		PPCCOM,		{ RT, RA, RB } },
+{ "lwbrx",   X(31,534),	X_MASK,		PPCCOM,		{ RT, RA0, RB } },
 { "lbrx",    X(31,534),	X_MASK,		PWRCOM,		{ RT, RA, RB } },
 
-{ "lfsx",    X(31,535),	X_MASK,		COM,		{ FRT, RA, RB } },
+{ "lfsx",    X(31,535),	X_MASK,		COM,		{ FRT, RA0, RB } },
 
 { "srw",     XRC(31,536,0), X_MASK,	PPCCOM,		{ RA, RS, RB } },
 { "sr",      XRC(31,536,0), X_MASK,	PWRCOM,		{ RA, RS, RB } },
@@ -4107,11 +4111,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "maskir",  XRC(31,541,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "maskir.", XRC(31,541,1), X_MASK,	M601,		{ RA, RS, RB } },
 
-{ "lwbrxe",  X(31,542),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
+{ "lwbrxe",  X(31,542),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
 
-{ "lfsxe",   X(31,543),	X_MASK,		BOOKE64,	{ FRT, RA, RB } },
+{ "lfsxe",   X(31,543),	X_MASK,		BOOKE64,	{ FRT, RA0, RB } },
 
 { "bbelr",   X(31,550),	X_MASK,		PPCBRLK,	{ 0 }},
+
+{ "lsdx",    X(31,565),	X_MASK,		PPC64,		{ RT, RA0, RB } },
+
 { "tlbsync", X(31,566),	0xffffffff,	PPC,		{ 0 } },
 
 { "lfsux",   X(31,567),	X_MASK,		COM,		{ FRT, RAS, RB } },
@@ -4120,8 +4127,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mfsr",    X(31,595),	XRB_MASK|(1<<20), COM32,	{ RT, SR } },
 
-{ "lswi",    X(31,597),	X_MASK,		PPCCOM,		{ RT, RA, NB } },
-{ "lsi",     X(31,597),	X_MASK,		PWRCOM,		{ RT, RA, NB } },
+{ "lswi",    X(31,597),	X_MASK,		PPCCOM,		{ RT, RA0, NB } },
+{ "lsi",     X(31,597),	X_MASK,		PWRCOM,		{ RT, RA0, NB } },
 
 { "lwsync",  XSYNC(31,598,1), 0xffffffff, PPC,		{ 0 } },
 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,	{ 0 } },
@@ -4129,12 +4136,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "sync",    X(31,598), XSYNC_MASK,	PPCCOM,		{ LS } },
 { "dcs",     X(31,598), 0xffffffff,	PWRCOM,		{ 0 } },
 
-{ "lfdx",    X(31,599), X_MASK,		COM,		{ FRT, RA, RB } },
+{ "lfdx",    X(31,599), X_MASK,		COM,		{ FRT, RA0, RB } },
 
-{ "lfdxe",   X(31,607), X_MASK,		BOOKE64,	{ FRT, RA, RB } },
+{ "lfdxe",   X(31,607), X_MASK,		BOOKE64,	{ FRT, RA0, RB } },
 
 { "mfsri",   X(31,627), X_MASK,		PWRCOM,		{ RT, RA, RB } },
 
+{ "lsdi",    X(31,629),	X_MASK,		PPC64,		{ RT, RA0, NB } },
+
 { "dclst",   X(31,630), XRB_MASK,	PWRCOM,		{ RS, RA } },
 
 { "lfdux",   X(31,631), X_MASK,		COM,		{ FRT, RAS, RB } },
@@ -4143,13 +4152,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mfsrin",  X(31,659), XRA_MASK,	PPC32,		{ RT, RB } },
 
-{ "stswx",   X(31,661), X_MASK,		PPCCOM,		{ RS, RA, RB } },
-{ "stsx",    X(31,661), X_MASK,		PWRCOM,		{ RS, RA, RB } },
+{ "stswx",   X(31,661), X_MASK,		PPCCOM,		{ RS, RA0, RB } },
+{ "stsx",    X(31,661), X_MASK,		PWRCOM,		{ RS, RA0, RB } },
 
-{ "stwbrx",  X(31,662), X_MASK,		PPCCOM,		{ RS, RA, RB } },
-{ "stbrx",   X(31,662), X_MASK,		PWRCOM,		{ RS, RA, RB } },
+{ "stwbrx",  X(31,662), X_MASK,		PPCCOM,		{ RS, RA0, RB } },
+{ "stbrx",   X(31,662), X_MASK,		PWRCOM,		{ RS, RA0, RB } },
 
-{ "stfsx",   X(31,663), X_MASK,		COM,		{ FRS, RA, RB } },
+{ "stfsx",   X(31,663), X_MASK,		COM,		{ FRS, RA0, RB } },
 
 { "srq",     XRC(31,664,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "srq.",    XRC(31,664,1), X_MASK,	M601,		{ RA, RS, RB } },
@@ -4157,9 +4166,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "sre",     XRC(31,665,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "sre.",    XRC(31,665,1), X_MASK,	M601,		{ RA, RS, RB } },
 
-{ "stwbrxe", X(31,670), X_MASK,		BOOKE64,	{ RS, RA, RB } },
+{ "stwbrxe", X(31,670), X_MASK,		BOOKE64,	{ RS, RA0, RB } },
 
-{ "stfsxe",  X(31,671), X_MASK,		BOOKE64,	{ FRS, RA, RB } },
+{ "stfsxe",  X(31,671), X_MASK,		BOOKE64,	{ FRS, RA0, RB } },
+
+{ "stsdx",   X(31,693), X_MASK,		PPC64,		{ RS, RA0, RB } },
 
 { "stfsux",  X(31,695),	X_MASK,		COM,		{ FRS, RAS, RB } },
 
@@ -4168,10 +4179,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "stfsuxe", X(31,703),	X_MASK,		BOOKE64,	{ FRS, RAS, RB } },
 
-{ "stswi",   X(31,725),	X_MASK,		PPCCOM,		{ RS, RA, NB } },
-{ "stsi",    X(31,725),	X_MASK,		PWRCOM,		{ RS, RA, NB } },
+{ "stswi",   X(31,725),	X_MASK,		PPCCOM,		{ RS, RA0, NB } },
+{ "stsi",    X(31,725),	X_MASK,		PWRCOM,		{ RS, RA0, NB } },
 
-{ "stfdx",   X(31,727),	X_MASK,		COM,		{ FRS, RA, RB } },
+{ "stfdx",   X(31,727),	X_MASK,		COM,		{ FRS, RA0, RB } },
 
 { "srlq",    XRC(31,728,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "srlq.",   XRC(31,728,1), X_MASK,	M601,		{ RA, RS, RB } },
@@ -4179,7 +4190,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "sreq",    XRC(31,729,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "sreq.",   XRC(31,729,1), X_MASK,	M601,		{ RA, RS, RB } },
 
-{ "stfdxe",  X(31,735),	X_MASK,		BOOKE64,	{ FRS, RA, RB } },
+{ "stfdxe",  X(31,735),	X_MASK,		BOOKE64,	{ FRS, RA0, RB } },
+
+{ "stsdi",   X(31,757),	X_MASK,		PPC64,		{ RS, RA0, NB } },
 
 { "dcba",    X(31,758),	XRT_MASK,	PPC405 | BOOKE,	{ RA, RB } },
 
@@ -4195,7 +4208,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "tlbivax", X(31,786),	XRT_MASK,	BOOKE,		{ RA, RB } },
 { "tlbivaxe",X(31,787),	XRT_MASK,	BOOKE64,	{ RA, RB } },
 
-{ "lhbrx",   X(31,790),	X_MASK,		COM,		{ RT, RA, RB } },
+{ "lhbrx",   X(31,790),	X_MASK,		COM,		{ RT, RA0, RB } },
 
 { "sraw",    XRC(31,792,0), X_MASK,	PPCCOM,		{ RA, RS, RB } },
 { "sra",     XRC(31,792,0), X_MASK,	PWRCOM,		{ RA, RS, RB } },
@@ -4205,10 +4218,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "srad",    XRC(31,794,0), X_MASK,	PPC64,		{ RA, RS, RB } },
 { "srad.",   XRC(31,794,1), X_MASK,	PPC64,		{ RA, RS, RB } },
 
-{ "lhbrxe",  X(31,798),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
+{ "lhbrxe",  X(31,798),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
 
-{ "ldxe",    X(31,799),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
-{ "lduxe",   X(31,831),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
+{ "ldxe",    X(31,799),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
+{ "lduxe",   X(31,831),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
 
 { "rac",     X(31,818),	X_MASK,		PWRCOM,		{ RT, RA, RB } },
 
@@ -4234,7 +4247,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "slbmfee", X(31,915), XRA_MASK,	PPC64,		{ RT, RB } },
 
-{ "sthbrx",  X(31,918),	X_MASK,		COM,		{ RS, RA, RB } },
+{ "sthbrx",  X(31,918),	X_MASK,		COM,		{ RS, RA0, RB } },
 
 { "sraq",    XRC(31,920,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "sraq.",   XRC(31,920,1), X_MASK,	M601,		{ RA, RS, RB } },
@@ -4247,9 +4260,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "extsh.",  XRC(31,922,1), XRB_MASK,	PPCCOM,		{ RA, RS } },
 { "exts.",   XRC(31,922,1), XRB_MASK,	PWRCOM,		{ RA, RS } },
 
-{ "sthbrxe", X(31,926),	X_MASK,		BOOKE64,	{ RS, RA, RB } },
+{ "sthbrxe", X(31,926),	X_MASK,		BOOKE64,	{ RS, RA0, RB } },
 
-{ "stdxe",   X(31,927), X_MASK,		BOOKE64,	{ RS, RA, RB } },
+{ "stdxe",   X(31,927), X_MASK,		BOOKE64,	{ RS, RA0, RB } },
 
 { "tlbrehi", XTLB(31,946,0), XTLB_MASK,	PPC403,		{ RT, RA } },
 { "tlbrelo", XTLB(31,946,1), XTLB_MASK,	PPC403,		{ RT, RA } },
@@ -4268,12 +4281,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "tlbwehi", XTLB(31,978,0), XTLB_MASK,	PPC403,		{ RT, RA } },
 { "tlbwelo", XTLB(31,978,1), XTLB_MASK,	PPC403,		{ RT, RA } },
-{ "tlbwe",   X(31,978),	X_MASK,		PPC403|BOOKE,	{ RSO, RAO, SHO } },
+{ "tlbwe",   X(31,978),	X_MASK,		PPC403|BOOKE,	{ RSO, RAOPT, SHO } },
 { "tlbld",   X(31,978),	XRTRA_MASK,	PPC,		{ RB } },
 
 { "icbi",    X(31,982),	XRT_MASK,	PPC,		{ RA, RB } },
 
-{ "stfiwx",  X(31,983),	X_MASK,		PPC,		{ FRS, RA, RB } },
+{ "stfiwx",  X(31,983),	X_MASK,		PPC,		{ FRS, RA0, RB } },
 
 { "extsw",   XRC(31,986,0), XRB_MASK,	PPC64 | BOOKE64,{ RA, RS } },
 { "extsw.",  XRC(31,986,1), XRB_MASK,	PPC64,		{ RA, RS } },
@@ -4281,7 +4294,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "icread",  X(31,998),	XRT_MASK,	PPC403|PPC440,	{ RA, RB } },
 
 { "icbie",   X(31,990),	XRT_MASK,	BOOKE64,	{ RA, RB } },
-{ "stfiwxe", X(31,991),	X_MASK,		BOOKE64,	{ FRS, RA, RB } },
+{ "stfiwxe", X(31,991),	X_MASK,		BOOKE64,	{ FRS, RA0, RB } },
 
 { "tlbli",   X(31,1010), XRTRA_MASK,	PPC,		{ RB } },
 
@@ -4303,86 +4316,88 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "stvx",    X(31, 231), X_MASK,	PPCVEC,		{ VS, RA, RB } },
 { "stvxl",   X(31, 487), X_MASK,	PPCVEC,		{ VS, RA, RB } },
 
-{ "lwz",     OP(32),	OP_MASK,	PPCCOM,		{ RT, D, RA } },
-{ "l",	     OP(32),	OP_MASK,	PWRCOM,		{ RT, D, RA } },
+{ "lwz",     OP(32),	OP_MASK,	PPCCOM,		{ RT, D, RA0 } },
+{ "l",	     OP(32),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
 
 { "lwzu",    OP(33),	OP_MASK,	PPCCOM,		{ RT, D, RAL } },
-{ "lu",      OP(33),	OP_MASK,	PWRCOM,		{ RT, D, RA } },
+{ "lu",      OP(33),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
 
-{ "lbz",     OP(34),	OP_MASK,	COM,		{ RT, D, RA } },
+{ "lbz",     OP(34),	OP_MASK,	COM,		{ RT, D, RA0 } },
 
 { "lbzu",    OP(35),	OP_MASK,	COM,		{ RT, D, RAL } },
 
-{ "stw",     OP(36),	OP_MASK,	PPCCOM,		{ RS, D, RA } },
-{ "st",      OP(36),	OP_MASK,	PWRCOM,		{ RS, D, RA } },
+{ "stw",     OP(36),	OP_MASK,	PPCCOM,		{ RS, D, RA0 } },
+{ "st",      OP(36),	OP_MASK,	PWRCOM,		{ RS, D, RA0 } },
 
 { "stwu",    OP(37),	OP_MASK,	PPCCOM,		{ RS, D, RAS } },
-{ "stu",     OP(37),	OP_MASK,	PWRCOM,		{ RS, D, RA } },
+{ "stu",     OP(37),	OP_MASK,	PWRCOM,		{ RS, D, RA0 } },
 
-{ "stb",     OP(38),	OP_MASK,	COM,		{ RS, D, RA } },
+{ "stb",     OP(38),	OP_MASK,	COM,		{ RS, D, RA0 } },
 
 { "stbu",    OP(39),	OP_MASK,	COM,		{ RS, D, RAS } },
 
-{ "lhz",     OP(40),	OP_MASK,	COM,		{ RT, D, RA } },
+{ "lhz",     OP(40),	OP_MASK,	COM,		{ RT, D, RA0 } },
 
 { "lhzu",    OP(41),	OP_MASK,	COM,		{ RT, D, RAL } },
 
-{ "lha",     OP(42),	OP_MASK,	COM,		{ RT, D, RA } },
+{ "lha",     OP(42),	OP_MASK,	COM,		{ RT, D, RA0 } },
 
 { "lhau",    OP(43),	OP_MASK,	COM,		{ RT, D, RAL } },
 
-{ "sth",     OP(44),	OP_MASK,	COM,		{ RS, D, RA } },
+{ "sth",     OP(44),	OP_MASK,	COM,		{ RS, D, RA0 } },
 
 { "sthu",    OP(45),	OP_MASK,	COM,		{ RS, D, RAS } },
 
 { "lmw",     OP(46),	OP_MASK,	PPCCOM,		{ RT, D, RAM } },
-{ "lm",      OP(46),	OP_MASK,	PWRCOM,		{ RT, D, RA } },
+{ "lm",      OP(46),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
 
-{ "stmw",    OP(47),	OP_MASK,	PPCCOM,		{ RS, D, RA } },
-{ "stm",     OP(47),	OP_MASK,	PWRCOM,		{ RS, D, RA } },
+{ "stmw",    OP(47),	OP_MASK,	PPCCOM,		{ RS, D, RA0 } },
+{ "stm",     OP(47),	OP_MASK,	PWRCOM,		{ RS, D, RA0 } },
 
-{ "lfs",     OP(48),	OP_MASK,	COM,		{ FRT, D, RA } },
+{ "lfs",     OP(48),	OP_MASK,	COM,		{ FRT, D, RA0 } },
 
 { "lfsu",    OP(49),	OP_MASK,	COM,		{ FRT, D, RAS } },
 
-{ "lfd",     OP(50),	OP_MASK,	COM,		{ FRT, D, RA } },
+{ "lfd",     OP(50),	OP_MASK,	COM,		{ FRT, D, RA0 } },
 
 { "lfdu",    OP(51),	OP_MASK,	COM,		{ FRT, D, RAS } },
 
-{ "stfs",    OP(52),	OP_MASK,	COM,		{ FRS, D, RA } },
+{ "stfs",    OP(52),	OP_MASK,	COM,		{ FRS, D, RA0 } },
 
 { "stfsu",   OP(53),	OP_MASK,	COM,		{ FRS, D, RAS } },
 
-{ "stfd",    OP(54),	OP_MASK,	COM,		{ FRS, D, RA } },
+{ "stfd",    OP(54),	OP_MASK,	COM,		{ FRS, D, RA0 } },
 
 { "stfdu",   OP(55),	OP_MASK,	COM,		{ FRS, D, RAS } },
 
 { "lq",      OP(56),	OP_MASK,	POWER4,		{ RTQ, DQ, RAQ } },
 
-{ "lfq",     OP(56),	OP_MASK,	POWER2,		{ FRT, D, RA } },
+{ "lfq",     OP(56),	OP_MASK,	POWER2,		{ FRT, D, RA0 } },
 
-{ "lfqu",    OP(57),	OP_MASK,	POWER2,		{ FRT, D, RA } },
+{ "lfqu",    OP(57),	OP_MASK,	POWER2,		{ FRT, D, RA0 } },
 
-{ "lbze",    DEO(58,0), DE_MASK,	BOOKE64,	{ RT, DE, RA } },
+{ "lbze",    DEO(58,0), DE_MASK,	BOOKE64,	{ RT, DE, RA0 } },
 { "lbzue",   DEO(58,1), DE_MASK,	BOOKE64,	{ RT, DE, RAL } },
-{ "lhze",    DEO(58,2), DE_MASK,	BOOKE64,	{ RT, DE, RA } },
+{ "lhze",    DEO(58,2), DE_MASK,	BOOKE64,	{ RT, DE, RA0 } },
 { "lhzue",   DEO(58,3), DE_MASK,	BOOKE64,	{ RT, DE, RAL } },
-{ "lhae",    DEO(58,4), DE_MASK,	BOOKE64,	{ RT, DE, RA } },
+{ "lhae",    DEO(58,4), DE_MASK,	BOOKE64,	{ RT, DE, RA0 } },
 { "lhaue",   DEO(58,5), DE_MASK,	BOOKE64,	{ RT, DE, RAL } },
-{ "lwze",    DEO(58,6), DE_MASK,	BOOKE64,	{ RT, DE, RA } },
+{ "lwze",    DEO(58,6), DE_MASK,	BOOKE64,	{ RT, DE, RA0 } },
 { "lwzue",   DEO(58,7), DE_MASK,	BOOKE64,	{ RT, DE, RAL } },
-{ "stbe",    DEO(58,8), DE_MASK,	BOOKE64,	{ RS, DE, RA } },
+{ "stbe",    DEO(58,8), DE_MASK,	BOOKE64,	{ RS, DE, RA0 } },
 { "stbue",   DEO(58,9), DE_MASK,	BOOKE64,	{ RS, DE, RAS } },
-{ "sthe",    DEO(58,10), DE_MASK,	BOOKE64,	{ RS, DE, RA } },
+{ "sthe",    DEO(58,10), DE_MASK,	BOOKE64,	{ RS, DE, RA0 } },
 { "sthue",   DEO(58,11), DE_MASK,	BOOKE64,	{ RS, DE, RAS } },
-{ "stwe",    DEO(58,14), DE_MASK,	BOOKE64,	{ RS, DE, RA } },
+{ "stwe",    DEO(58,14), DE_MASK,	BOOKE64,	{ RS, DE, RA0 } },
 { "stwue",   DEO(58,15), DE_MASK,	BOOKE64,	{ RS, DE, RAS } },
 
-{ "ld",      DSO(58,0),	DS_MASK,	PPC64,		{ RT, DS, RA } },
+{ "ld",      DSO(58,0),	DS_MASK,	PPC64,		{ RT, DS, RA0 } },
 
 { "ldu",     DSO(58,1), DS_MASK,	PPC64,		{ RT, DS, RAL } },
 
-{ "lwa",     DSO(58,2), DS_MASK,	PPC64,		{ RT, DS, RA } },
+{ "lwa",     DSO(58,2), DS_MASK,	PPC64,		{ RT, DS, RA0 } },
+
+{ "lmd",     DSO(58,3),	DS_MASK,	PPC64,		{ RT, DS, RAM } },
 
 { "fdivs",   A(59,18,0), AFRC_MASK,	PPC,		{ FRT, FRA, FRB } },
 { "fdivs.",  A(59,18,1), AFRC_MASK,	PPC,		{ FRT, FRA, FRB } },
@@ -4418,24 +4433,26 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "stfqu",   OP(61),	OP_MASK,	POWER2,		{ FRS, D, RA } },
 
-{ "lde",     DEO(62,0), DE_MASK,	BOOKE64,	{ RT, DES, RA } },
-{ "ldue",    DEO(62,1), DE_MASK,	BOOKE64,	{ RT, DES, RA } },
-{ "lfse",    DEO(62,4), DE_MASK,	BOOKE64,	{ FRT, DES, RA } },
+{ "lde",     DEO(62,0), DE_MASK,	BOOKE64,	{ RT, DES, RA0 } },
+{ "ldue",    DEO(62,1), DE_MASK,	BOOKE64,	{ RT, DES, RA0 } },
+{ "lfse",    DEO(62,4), DE_MASK,	BOOKE64,	{ FRT, DES, RA0 } },
 { "lfsue",   DEO(62,5), DE_MASK,	BOOKE64,	{ FRT, DES, RAS } },
-{ "lfde",    DEO(62,6), DE_MASK,	BOOKE64,	{ FRT, DES, RA } },
+{ "lfde",    DEO(62,6), DE_MASK,	BOOKE64,	{ FRT, DES, RA0 } },
 { "lfdue",   DEO(62,7), DE_MASK,	BOOKE64,	{ FRT, DES, RAS } },
-{ "stde",    DEO(62,8), DE_MASK,	BOOKE64,	{ RS, DES, RA } },
+{ "stde",    DEO(62,8), DE_MASK,	BOOKE64,	{ RS, DES, RA0 } },
 { "stdue",   DEO(62,9), DE_MASK,	BOOKE64,	{ RS, DES, RAS } },
-{ "stfse",   DEO(62,12), DE_MASK,	BOOKE64,	{ FRS, DES, RA } },
+{ "stfse",   DEO(62,12), DE_MASK,	BOOKE64,	{ FRS, DES, RA0 } },
 { "stfsue",  DEO(62,13), DE_MASK,	BOOKE64,	{ FRS, DES, RAS } },
-{ "stfde",   DEO(62,14), DE_MASK,	BOOKE64,	{ FRS, DES, RA } },
+{ "stfde",   DEO(62,14), DE_MASK,	BOOKE64,	{ FRS, DES, RA0 } },
 { "stfdue",  DEO(62,15), DE_MASK,	BOOKE64,	{ FRS, DES, RAS } },
 
-{ "std",     DSO(62,0),	DS_MASK,	PPC64,		{ RS, DS, RA } },
+{ "std",     DSO(62,0),	DS_MASK,	PPC64,		{ RS, DS, RA0 } },
 
 { "stdu",    DSO(62,1),	DS_MASK,	PPC64,		{ RS, DS, RAS } },
 
-{ "stq",     DSO(62,2),	DS_MASK,	POWER4,		{ RSQ, DS, RA } },
+{ "stq",     DSO(62,2),	DS_MASK,	POWER4,		{ RSQ, DS, RA0 } },
+
+{ "stmd",    DSO(62,3),	DS_MASK,	PPC64,		{ RS, DS, RA0 } },
 
 { "fcmpu",   X(63,0),	X_MASK|(3<<21),	COM,		{ BF, FRA, FRB } },
author	Alan Modra <amodra@gmail.com>	2004-03-16 00:59:35 +0000
committer	Alan Modra <amodra@gmail.com>	2004-03-16 00:59:35 +0000
commit	974a217561b92209b973f8f06ac35b3cf6502a86 (patch)
tree	47b64ba7f50ef41611dc62324400aaca2a08ab16
parent	443600310d5b32102bfaa0495b4ee6a227933bb7 (diff)
download	binutils-gdb-974a217561b92209b973f8f06ac35b3cf6502a86.tar.gz