2006-09-06 Paul Brook <paul@codesourcery.com>

	gas/
	* config/tc-arm.c (parse_operands): Mark operand as present.

	gas/testsuite/
	* gas/arm/neon-omit.s: Test three-argument variants.
	* gas/arm/neon-omit.d: Update expected output.

4 files changed, 97 insertions, 0 deletions

diff --git a/ChangeLog.csl b/ChangeLog.csl
index f713e568362..165c9b0aa93 100644
--- a/ChangeLog.csl
+++ b/ChangeLog.csl
@@ -1,3 +1,12 @@
+2006-09-06  Paul Brook  <paul@codesourcery.com>
+
+	gas/
+	* config/tc-arm.c (parse_operands): Mark operand as present.
+
+	gas/testsuite/
+	* gas/arm/neon-omit.s: Test three-argument variants.
+	* gas/arm/neon-omit.d: Update expected output.
+
 2006-09-05  Julian Brown  <julian@codesourcery.com>
 
 	gas/
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index ebf3bf483ce..e6989747afd 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -5565,6 +5565,7 @@ parse_operands (char *str, const unsigned char *pattern)
         case OP_NILO:
           {
             po_reg_or_goto (REG_TYPE_NDQ, try_imm);
+	    inst.operands[i].present = 1;
             i++;
             skip_past_comma (&str);
             po_reg_or_goto (REG_TYPE_NDQ, one_reg_only);
diff --git a/gas/testsuite/gas/arm/neon-omit.d b/gas/testsuite/gas/arm/neon-omit.d
index 68b3921bf1e..b20c9544b59 100644
--- a/gas/testsuite/gas/arm/neon-omit.d
+++ b/gas/testsuite/gas/arm/neon-omit.d
@@ -51,3 +51,45 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> f3954554 	vsli\.16	q2, q2, #5
 0[0-9a-f]+ <[^>]+> f3bff69f 	vqshlu\.s64	d15, d15, #63
 0[0-9a-f]+ <[^>]+> f2b55306 	vext\.8	d5, d5, d6, #3
+0[0-9a-f]+ <[^>]+> f3042746 	vabd\.u8	q1, q2, q3
+0[0-9a-f]+ <[^>]+> f262c0c6 	vhadd\.s32	q14, q9, q3
+0[0-9a-f]+ <[^>]+> f22a2144 	vrhadd\.s32	q1, q5, q2
+0[0-9a-f]+ <[^>]+> f220a2ce 	vhsub\.s32	q5, q8, q7
+0[0-9a-f]+ <[^>]+> f318644a 	vshl\.u16	q3, q4, q5
+0[0-9a-f]+ <[^>]+> f32ca452 	vqshl\.u32	q5, q6, q1
+0[0-9a-f]+ <[^>]+> f200e1dc 	vand	q7, q8, q6
+0[0-9a-f]+ <[^>]+> f300e1dc 	veor	q7, q8, q6
+0[0-9a-f]+ <[^>]+> f3b5a146 	vceq\.i16	q5, q3, #0
+0[0-9a-f]+ <[^>]+> f316a85a 	vceq\.i16	q5, q3, q5
+0[0-9a-f]+ <[^>]+> f3b5a246 	vclt\.s16	q5, q3, #0
+0[0-9a-f]+ <[^>]+> f2231a20 	vpmax\.s32	d1, d3, d16
+0[0-9a-f]+ <[^>]+> f2275a34 	vpmin\.s32	d5, d7, d20
+0[0-9a-f]+ <[^>]+> f3031f07 	vpmax\.f32	d1, d3, d7
+0[0-9a-f]+ <[^>]+> f32c5f07 	vpmin\.f32	d5, d12, d7
+0[0-9a-f]+ <[^>]+> f2162b60 	vqdmulh\.s16	q1, q3, q8
+0[0-9a-f]+ <[^>]+> f3275b09 	vqrdmulh\.s32	d5, d7, d9
+0[0-9a-f]+ <[^>]+> f39c2c6d 	vqdmulh\.s16	q1, q6, d5\[3\]
+0[0-9a-f]+ <[^>]+> f21620d6 	vqadd\.s16	q1, q11, q3
+0[0-9a-f]+ <[^>]+> f227503f 	vqadd\.s32	d5, d7, d31
+0[0-9a-f]+ <[^>]+> f2242962 	vmla\.i32	q1, q2, q9
+0[0-9a-f]+ <[^>]+> f21a3b94 	vpadd\.i16	d3, d26, d4
+0[0-9a-f]+ <[^>]+> f328694a 	vmls\.i32	q3, q4, q5
+0[0-9a-f]+ <[^>]+> f3082e54 	vacge\.f32	q1, q4, q2
+0[0-9a-f]+ <[^>]+> f3226e58 	vacgt\.f32	q3, q1, q4
+0[0-9a-f]+ <[^>]+> f30cae72 	vacge\.f32	q5, q6, q9
+0[0-9a-f]+ <[^>]+> f320eed2 	vacgt\.f32	q7, q8, q1
+0[0-9a-f]+ <[^>]+> f320e3d6 	vcge\.u32	q7, q8, q3
+0[0-9a-f]+ <[^>]+> f320e3c6 	vcgt\.u32	q7, q8, q3
+0[0-9a-f]+ <[^>]+> f326e370 	vcge\.u32	q7, q3, q8
+0[0-9a-f]+ <[^>]+> f326e360 	vcgt\.u32	q7, q3, q8
+0[0-9a-f]+ <[^>]+> f3aa2102 	vaddw\.u32	q1, q5, d2
+0[0-9a-f]+ <[^>]+> f2a26304 	vsubw\.s32	q3, q1, d4
+0[0-9a-f]+ <[^>]+> f22648d6 	vtst\.32	q2, q11, q3
+0[0-9a-f]+ <[^>]+> f20e1f92 	vrecps\.f32	d1, d30, d2
+0[0-9a-f]+ <[^>]+> f29c207a 	vshr\.s16	q1, q13, #4
+0[0-9a-f]+ <[^>]+> f28b4272 	vrshr\.s8	q2, q9, #5
+0[0-9a-f]+ <[^>]+> f39a6152 	vsra\.u16	q3, q1, #6
+0[0-9a-f]+ <[^>]+> f3dae358 	vrsra\.u16	q15, q4, #6
+0[0-9a-f]+ <[^>]+> f3954556 	vsli\.16	q2, q3, #5
+0[0-9a-f]+ <[^>]+> f3bff6b7 	vqshlu\.s64	d15, d23, #63
+0[0-9a-f]+ <[^>]+> f2b25386 	vext\.8	d5, d18, d6, #3
diff --git a/gas/testsuite/gas/arm/neon-omit.s b/gas/testsuite/gas/arm/neon-omit.s
index 92cb717c75b..42a7e8903b1 100644
--- a/gas/testsuite/gas/arm/neon-omit.s
+++ b/gas/testsuite/gas/arm/neon-omit.s
@@ -50,3 +50,48 @@
 	vsli.16 q2,#5
 	vqshlu.s64 d15,#63
 	vext.8 d5,d6,#3
+
+@ Also test three-argument forms without omitted arguments
+
+	vabd.u8 q1,q2,q3
+	vhadd.s32 q14,q9,q3
+	vrhadd.s32 q1,q5,q2
+	vhsub.s32 q5,q8,q7
+	vshl.u16 q3,q4,q5
+	vqshl.u32 q5,q6,q1
+	vand.64 q7,q8,q6
+	veor.64 q7,q8,q6
+	vceq.i16 q5,q3,#0
+	vceq.i16 q5,q3,q5
+	vclt.s16 q5,q3,#0
+	vpmax.s32 d1,d3,d16
+	vpmin.s32 d5,d7,d20
+	vpmax.f32 d1,d3,d7
+	vpmin.f32 d5,d12,d7
+	vqdmulh.s16 q1,q3,q8
+	vqrdmulh.s32 d5,d7,d9
+	vqdmulh.s16 q1,q6,d5[3]
+	vqadd.s16 q1,q11,q3
+	vqadd.s32 d5,d7,d31
+	vmla.i32 q1,q2,q9
+	vpadd.i16 d3,d26,d4
+	vmls.s32 q3,q4,q5
+	vacge.f q1,q4,q2
+	vacgt.f q3,q1,q4
+	vacle.f q5,q9,q6
+	vaclt.f q7,q1,q8
+	vcge.u32 q7,q8,q3
+	vcgt.u32 q7,q8,q3
+	vcle.u32 q7,q8,q3
+	vclt.u32 q7,q8,q3
+	vaddw.u32 q1,q5,d2
+	vsubw.s32 q3,q1,d4
+	vtst.i32 q2,q11,q3
+	vrecps.f d1,d30,d2
+	vshr.s16 q1,q13,#4
+        vrshr.s8 q2,q9,#5
+	vsra.u16 q3,q1,#6
+        vrsra.u16 q15,q4,#6
+	vsli.16 q2,q3,#5
+	vqshlu.s64 d15,d23,#63
+	vext.8 d5,d18,d6,#3