Add -mrelax-relocations= to x86 assembler

The x86 relax relocations introduced in binutils 2.26 aren't supported
by linker on Solaris older than Solaris 12.  To use x86 assembler with
older Solaris linker, this patch adds

1. A command line option -mrelax-relocations= to x86 assembler to
control whether to generate relax relocations.
2. A configure option --enable-x86-relax-relocations to decide whether
x86 assembler should generate relax relocations by default.  It is
defaulted to yes, except for x86 Solaris targets older than Solaris 12.

gas/

	PR gas/19520
	* NEWS: Mention new command line option -mrelax-relocations and
	new configure option --enable-x86-relax-relocations for x86
	target.
	* config.in: Regenerated.
	* configure.ac: Add --enable-x86-relax-relocations.
	(ac_default_x86_relax_relocations): New.  Default to 1 except
	for x86 Solaris targets older than Solaris 12.
	(DEFAULT_GENERATE_X86_RELAX_RELOCATIONS): Define.
	* configure: Likewise.
	* config/tc-i386.c (generate_relax_relocations): New.
	(OPTION_MRELAX_RELOCATIONS): Likewise.
	(output_disp): Don't generate relax relocations if
	generate_relax_relocations is 0.
	(md_longopts): Add -mrelax-relocations.
	(md_show_usage): Likewise.
	(md_parse_option): Handle OPTION_MRELAX_RELOCATIONS.
	* doc/c-i386.texi: Document -mrelax-relocations=.
	* testsuite/gas/i386/got-no-relax.d: New file.
	* testsuite/gas/i386/x86-64-gotpcrel-no-relax.d: Likewise.
	* testsuite/gas/i386/got.d: Pass -mrelax-relocations=yes to as.
	* testsuite/gas/i386/localpic.d: Likewise.
	* testsuite/gas/i386/mixed-mode-reloc32.d: Likewise.
	* testsuite/gas/i386/reloc32.d: Likewise.
	* testsuite/gas/i386/x86-64-gotpcrel.d: Likewise.
	* testsuite/gas/i386/x86-64-localpic.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-gotpcrel.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise.
	* testsuite/gas/i386/i386.exp: Run got-no-relax and
	x86-64-gotpcrel-no-relax.

ld/

	PR gas/19520
	* testsuite/ld-i386/branch1.d: Pass -mrelax-relocations=yes to as.
	* testsuite/ld-i386/call1.d: Likewise.
	* testsuite/ld-i386/call2.d: Likewise.
	* testsuite/ld-i386/call3a.d: Likewise.
	* testsuite/ld-i386/call3b.d: Likewise.
	* testsuite/ld-i386/call3c.d: Likewise.
	* testsuite/ld-i386/call3d.d: Likewise.
	* testsuite/ld-i386/call3e.d: Likewise.
	* testsuite/ld-i386/call3f.d: Likewise.
	* testsuite/ld-i386/call3g.d: Likewise.
	* testsuite/ld-i386/call3h.d: Likewise.
	* testsuite/ld-i386/jmp1.d: Likewise.
	* testsuite/ld-i386/jmp2.d: Likewise.
	* testsuite/ld-i386/lea1c.d: Likewise.
	* testsuite/ld-i386/load1.d: Likewise.
	* testsuite/ld-i386/load2.d: Likewise.
	* testsuite/ld-i386/load3.d: Likewise.
	* testsuite/ld-i386/load4a.d: Likewise.
	* testsuite/ld-i386/load5a.d: Likewise.
	* testsuite/ld-i386/mov2b.d: Likewise.
	* testsuite/ld-i386/mov3.d: Likewise.
	* testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-5r-local-x86-64.d: Likewise.
	* testsuite/ld-x86-64/call1a.d: Likewise.
	* testsuite/ld-x86-64/call1b.d: Likewise.
	* testsuite/ld-x86-64/call1c.d: Likewise.
	* testsuite/ld-x86-64/call1d.d: Likewise.
	* testsuite/ld-x86-64/call1e.d: Likewise.
	* testsuite/ld-x86-64/call1f.d: Likewise.
	* testsuite/ld-x86-64/call1h.d: Likewise.
	* testsuite/ld-x86-64/call1i.d: Likewise.
	* testsuite/ld-x86-64/load1a.d: Likewise.
	* testsuite/ld-x86-64/load1b.d: Likewise.
	* testsuite/ld-i386/got1a.S: Load GOT into %ecx and use it.
	* testsuite/ld-i386/got1.dd: Updated.
	* testsuite/ld-i386/got1d.S (1): Removed.
	* testsuite/ld-i386/i386.exp: Add -Wa,-mrelax-relocations=yes.
	* testsuite/ld-x86-64/x86-64.exp: Likewise.

1 files changed, 27 insertions, 3 deletions

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 3a98b21d955..2bc76169509 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -556,6 +556,11 @@ static int omit_lock_prefix = 0;
    "lock addl $0, (%{re}sp)".  */
 static int avoid_fence = 0;
 
+/* 1 if the assembler should generate relax relocations.  */
+
+static int generate_relax_relocations
+  = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
+
 static enum check_kind
   {
     check_none = 0,
@@ -7267,9 +7272,14 @@ output_disp (fragS *insn_start_frag, offsetT insn_start_off)
 	      /* Check for "call/jmp *mem", "mov mem, %reg",
 		 "test %reg, mem" and "binop mem, %reg" where binop
 		 is one of adc, add, and, cmp, or, sbb, sub, xor
-		 instructions.  */
-	      if ((i.rm.mode == 2
-		   || (i.rm.mode == 0 && i.rm.regmem == 5))
+		 instructions.  Always generate R_386_GOT32X for
+		 "sym*GOT" operand in 32-bit mode.  */
+	      if ((generate_relax_relocations
+		   || (!object_64bit
+		       && i.rm.mode == 0
+		       && i.rm.regmem == 5))
+		  && (i.rm.mode == 2
+		      || (i.rm.mode == 0 && i.rm.regmem == 5))
 		  && ((i.operands == 1
 		       && i.tm.base_opcode == 0xff
 		       && (i.rm.reg == 2 || i.rm.reg == 4))
@@ -9643,6 +9653,7 @@ const char *md_shortopts = "qn";
 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
+#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
 
 struct option md_longopts[] =
 {
@@ -9675,6 +9686,7 @@ struct option md_longopts[] =
 #endif
   {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
   {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
+  {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
   {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
   {"mamd64", no_argument, NULL, OPTION_MAMD64},
   {"mintel64", no_argument, NULL, OPTION_MINTEL64},
@@ -10003,6 +10015,15 @@ md_parse_option (int c, char *arg)
         as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
       break;
 
+    case OPTION_MRELAX_RELOCATIONS:
+      if (strcasecmp (arg, "yes") == 0)
+        generate_relax_relocations = 1;
+      else if (strcasecmp (arg, "no") == 0)
+        generate_relax_relocations = 0;
+      else
+        as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
+      break;
+
     case OPTION_MAMD64:
       cpu_arch_flags.bitfield.cpuamd64 = 1;
       cpu_arch_flags.bitfield.cpuintel64 = 0;
@@ -10187,6 +10208,9 @@ md_show_usage (FILE *stream)
                           encode lfence, mfence and sfence as\n\
                            lock addl $0x0, (%%{re}sp)\n"));
   fprintf (stream, _("\
+  -mrelax-relocations=[no|yes]\n\
+                          generate relax relocations\n"));
+  fprintf (stream, _("\
   -mamd64                 accept only AMD64 ISA\n"));
   fprintf (stream, _("\
   -mintel64               accept only Intel64 ISA\n"));