aarch64: Add the SME2 FP<->int conversion instructions

This patch adds the SME2 versions of the FP<->integer conversion
instructions FCVT* and *CVTF.  It also adds FP rounding instructions
FRINT*, which share the same format.

7 files changed, 245 insertions, 0 deletions

diff --git a/gas/testsuite/gas/aarch64/sme2-23-invalid.d b/gas/testsuite/gas/aarch64/sme2-23-invalid.d
new file mode 100644
index 00000000000..b9deb8e1c04
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-23-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sme2-23-invalid.s
+#error_output: sme2-23-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sme2-23-invalid.l b/gas/testsuite/gas/aarch64/sme2-23-invalid.l
new file mode 100644
index 00000000000..b3e9312cd0f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-23-invalid.l
@@ -0,0 +1,14 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `fcvtzs 0,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `fcvtzs {z0\.s,z1\.s},0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtzs {z0\.s,z1\.s},{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvtzs {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtzs {z30\.h,z31\.h},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvtzs {z30\.s-z31\.s}, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtzs {z0\.d,z1\.d},{z30\.d-z31\.d}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvtzs {z0\.s-z1\.s}, {z30\.s-z31\.s}
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `fcvtzs {z1\.s,z2\.s},{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fcvtzs {z0\.s,z1\.s},{z29\.s-z30\.s}'
diff --git a/gas/testsuite/gas/aarch64/sme2-23-invalid.s b/gas/testsuite/gas/aarch64/sme2-23-invalid.s
new file mode 100644
index 00000000000..45ee01ea85e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-23-invalid.s
@@ -0,0 +1,8 @@
+	fcvtzs	0, { z0.s - z1.s }
+	fcvtzs	{ z0.s, z1.s }, 0
+
+	fcvtzs	{ z0.s, z1.s }, { z0.h - z1.h }
+	fcvtzs	{ z30.h, z31.h }, { z0.s - z1.s }
+	fcvtzs	{ z0.d, z1.d }, { z30.d - z31.d }
+	fcvtzs	{ z1.s, z2.s }, { z30.s - z31.s }
+	fcvtzs	{ z0.s, z1.s }, { z29.s - z30.s }
diff --git a/gas/testsuite/gas/aarch64/sme2-23-noarch.d b/gas/testsuite/gas/aarch64/sme2-23-noarch.d
new file mode 100644
index 00000000000..a30446f6aa7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-23-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme
+#source: sme2-23.s
+#error_output: sme2-23-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sme2-23-noarch.l b/gas/testsuite/gas/aarch64/sme2-23-noarch.l
new file mode 100644
index 00000000000..033e87a5b72
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-23-noarch.l
@@ -0,0 +1,65 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzs {z0\.s,z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzs {z30\.s,z31\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzs {z0\.s,z1\.s},{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzs {z10\.s,z11\.s},{z26\.s-z27\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzs {z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzs {z28\.s-z31\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzs {z0\.s-z3\.s},{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzs {z24\.s-z27\.s},{z8\.s-z11\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzu {z0\.s,z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzu {z30\.s,z31\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzu {z0\.s,z1\.s},{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzu {z12\.s,z13\.s},{z14\.s-z15\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzu {z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzu {z28\.s-z31\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzu {z0\.s-z3\.s},{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzu {z16\.s-z19\.s},{z12\.s-z15\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frinta {z0\.s,z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frinta {z30\.s,z31\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frinta {z0\.s,z1\.s},{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frinta {z10\.s,z11\.s},{z26\.s-z27\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frinta {z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frinta {z28\.s-z31\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frinta {z0\.s-z3\.s},{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frinta {z24\.s-z27\.s},{z8\.s-z11\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintm {z0\.s,z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintm {z30\.s,z31\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintm {z0\.s,z1\.s},{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintm {z10\.s,z11\.s},{z26\.s-z27\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintm {z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintm {z28\.s-z31\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintm {z0\.s-z3\.s},{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintm {z24\.s-z27\.s},{z8\.s-z11\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintn {z0\.s,z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintn {z30\.s,z31\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintn {z0\.s,z1\.s},{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintn {z10\.s,z11\.s},{z26\.s-z27\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintn {z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintn {z28\.s-z31\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintn {z0\.s-z3\.s},{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintn {z24\.s-z27\.s},{z8\.s-z11\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintp {z0\.s,z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintp {z30\.s,z31\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintp {z0\.s,z1\.s},{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintp {z10\.s,z11\.s},{z26\.s-z27\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintp {z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintp {z28\.s-z31\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintp {z0\.s-z3\.s},{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `frintp {z24\.s-z27\.s},{z8\.s-z11\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `scvtf {z0\.s,z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `scvtf {z30\.s,z31\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `scvtf {z0\.s,z1\.s},{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `scvtf {z10\.s,z11\.s},{z26\.s-z27\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `scvtf {z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `scvtf {z28\.s-z31\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `scvtf {z0\.s-z3\.s},{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `scvtf {z24\.s-z27\.s},{z8\.s-z11\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `ucvtf {z0\.s,z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `ucvtf {z30\.s,z31\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `ucvtf {z0\.s,z1\.s},{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `ucvtf {z10\.s,z11\.s},{z26\.s-z27\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `ucvtf {z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `ucvtf {z28\.s-z31\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `ucvtf {z0\.s-z3\.s},{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `ucvtf {z24\.s-z27\.s},{z8\.s-z11\.s}'
diff --git a/gas/testsuite/gas/aarch64/sme2-23.d b/gas/testsuite/gas/aarch64/sme2-23.d
new file mode 100644
index 00000000000..d82704b1874
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-23.d
@@ -0,0 +1,73 @@
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+:	c121e000 	fcvtzs	{z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c121e01e 	fcvtzs	{z30\.s-z31\.s}, {z0\.s-z1\.s}
+[^:]+:	c121e3c0 	fcvtzs	{z0\.s-z1\.s}, {z30\.s-z31\.s}
+[^:]+:	c121e34a 	fcvtzs	{z10\.s-z11\.s}, {z26\.s-z27\.s}
+[^:]+:	c131e000 	fcvtzs	{z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c131e01c 	fcvtzs	{z28\.s-z31\.s}, {z0\.s-z3\.s}
+[^:]+:	c131e380 	fcvtzs	{z0\.s-z3\.s}, {z28\.s-z31\.s}
+[^:]+:	c131e118 	fcvtzs	{z24\.s-z27\.s}, {z8\.s-z11\.s}
+[^:]+:	c121e020 	fcvtzu	{z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c121e03e 	fcvtzu	{z30\.s-z31\.s}, {z0\.s-z1\.s}
+[^:]+:	c121e3e0 	fcvtzu	{z0\.s-z1\.s}, {z30\.s-z31\.s}
+[^:]+:	c121e1ec 	fcvtzu	{z12\.s-z13\.s}, {z14\.s-z15\.s}
+[^:]+:	c131e020 	fcvtzu	{z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c131e03c 	fcvtzu	{z28\.s-z31\.s}, {z0\.s-z3\.s}
+[^:]+:	c131e3a0 	fcvtzu	{z0\.s-z3\.s}, {z28\.s-z31\.s}
+[^:]+:	c131e1b0 	fcvtzu	{z16\.s-z19\.s}, {z12\.s-z15\.s}
+[^:]+:	c1ace000 	frinta	{z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c1ace01e 	frinta	{z30\.s-z31\.s}, {z0\.s-z1\.s}
+[^:]+:	c1ace3c0 	frinta	{z0\.s-z1\.s}, {z30\.s-z31\.s}
+[^:]+:	c1ace34a 	frinta	{z10\.s-z11\.s}, {z26\.s-z27\.s}
+[^:]+:	c1bce000 	frinta	{z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c1bce01c 	frinta	{z28\.s-z31\.s}, {z0\.s-z3\.s}
+[^:]+:	c1bce380 	frinta	{z0\.s-z3\.s}, {z28\.s-z31\.s}
+[^:]+:	c1bce118 	frinta	{z24\.s-z27\.s}, {z8\.s-z11\.s}
+[^:]+:	c1aae000 	frintm	{z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c1aae01e 	frintm	{z30\.s-z31\.s}, {z0\.s-z1\.s}
+[^:]+:	c1aae3c0 	frintm	{z0\.s-z1\.s}, {z30\.s-z31\.s}
+[^:]+:	c1aae34a 	frintm	{z10\.s-z11\.s}, {z26\.s-z27\.s}
+[^:]+:	c1bae000 	frintm	{z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c1bae01c 	frintm	{z28\.s-z31\.s}, {z0\.s-z3\.s}
+[^:]+:	c1bae380 	frintm	{z0\.s-z3\.s}, {z28\.s-z31\.s}
+[^:]+:	c1bae118 	frintm	{z24\.s-z27\.s}, {z8\.s-z11\.s}
+[^:]+:	c1a8e000 	frintn	{z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c1a8e01e 	frintn	{z30\.s-z31\.s}, {z0\.s-z1\.s}
+[^:]+:	c1a8e3c0 	frintn	{z0\.s-z1\.s}, {z30\.s-z31\.s}
+[^:]+:	c1a8e34a 	frintn	{z10\.s-z11\.s}, {z26\.s-z27\.s}
+[^:]+:	c1b8e000 	frintn	{z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c1b8e01c 	frintn	{z28\.s-z31\.s}, {z0\.s-z3\.s}
+[^:]+:	c1b8e380 	frintn	{z0\.s-z3\.s}, {z28\.s-z31\.s}
+[^:]+:	c1b8e118 	frintn	{z24\.s-z27\.s}, {z8\.s-z11\.s}
+[^:]+:	c1a9e000 	frintp	{z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c1a9e01e 	frintp	{z30\.s-z31\.s}, {z0\.s-z1\.s}
+[^:]+:	c1a9e3c0 	frintp	{z0\.s-z1\.s}, {z30\.s-z31\.s}
+[^:]+:	c1a9e34a 	frintp	{z10\.s-z11\.s}, {z26\.s-z27\.s}
+[^:]+:	c1b9e000 	frintp	{z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c1b9e01c 	frintp	{z28\.s-z31\.s}, {z0\.s-z3\.s}
+[^:]+:	c1b9e380 	frintp	{z0\.s-z3\.s}, {z28\.s-z31\.s}
+[^:]+:	c1b9e118 	frintp	{z24\.s-z27\.s}, {z8\.s-z11\.s}
+[^:]+:	c122e000 	scvtf	{z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c122e01e 	scvtf	{z30\.s-z31\.s}, {z0\.s-z1\.s}
+[^:]+:	c122e3c0 	scvtf	{z0\.s-z1\.s}, {z30\.s-z31\.s}
+[^:]+:	c122e34a 	scvtf	{z10\.s-z11\.s}, {z26\.s-z27\.s}
+[^:]+:	c132e000 	scvtf	{z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c132e01c 	scvtf	{z28\.s-z31\.s}, {z0\.s-z3\.s}
+[^:]+:	c132e380 	scvtf	{z0\.s-z3\.s}, {z28\.s-z31\.s}
+[^:]+:	c132e118 	scvtf	{z24\.s-z27\.s}, {z8\.s-z11\.s}
+[^:]+:	c122e020 	ucvtf	{z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c122e03e 	ucvtf	{z30\.s-z31\.s}, {z0\.s-z1\.s}
+[^:]+:	c122e3e0 	ucvtf	{z0\.s-z1\.s}, {z30\.s-z31\.s}
+[^:]+:	c122e36a 	ucvtf	{z10\.s-z11\.s}, {z26\.s-z27\.s}
+[^:]+:	c132e020 	ucvtf	{z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c132e03c 	ucvtf	{z28\.s-z31\.s}, {z0\.s-z3\.s}
+[^:]+:	c132e3a0 	ucvtf	{z0\.s-z3\.s}, {z28\.s-z31\.s}
+[^:]+:	c132e138 	ucvtf	{z24\.s-z27\.s}, {z8\.s-z11\.s}
diff --git a/gas/testsuite/gas/aarch64/sme2-23.s b/gas/testsuite/gas/aarch64/sme2-23.s
new file mode 100644
index 00000000000..55ec0f8e203
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-23.s
@@ -0,0 +1,79 @@
+	fcvtzs	{ z0.s, z1.s }, { z0.s - z1.s }
+	fcvtzs	{ z30.s, z31.s }, { z0.s - z1.s }
+	fcvtzs	{ z0.s, z1.s }, { z30.s - z31.s }
+	fcvtzs	{ z10.s, z11.s }, { z26.s - z27.s }
+
+	fcvtzs	{ z0.s - z3.s }, { z0.s - z3.s }
+	fcvtzs	{ z28.s - z31.s }, { z0.s - z3.s }
+	fcvtzs	{ z0.s - z3.s }, { z28.s - z31.s }
+	fcvtzs	{ z24.s - z27.s }, { z8.s - z11.s }
+
+	fcvtzu	{ z0.s, z1.s }, { z0.s - z1.s }
+	fcvtzu	{ z30.s, z31.s }, { z0.s - z1.s }
+	fcvtzu	{ z0.s, z1.s }, { z30.s - z31.s }
+	fcvtzu	{ z12.s, z13.s }, { z14.s - z15.s }
+
+	fcvtzu	{ z0.s - z3.s }, { z0.s - z3.s }
+	fcvtzu	{ z28.s - z31.s }, { z0.s - z3.s }
+	fcvtzu	{ z0.s - z3.s }, { z28.s - z31.s }
+	fcvtzu	{ z16.s - z19.s }, { z12.s - z15.s }
+
+	frinta	{ z0.s, z1.s }, { z0.s - z1.s }
+	frinta	{ z30.s, z31.s }, { z0.s - z1.s }
+	frinta	{ z0.s, z1.s }, { z30.s - z31.s }
+	frinta	{ z10.s, z11.s }, { z26.s - z27.s }
+
+	frinta	{ z0.s - z3.s }, { z0.s - z3.s }
+	frinta	{ z28.s - z31.s }, { z0.s - z3.s }
+	frinta	{ z0.s - z3.s }, { z28.s - z31.s }
+	frinta	{ z24.s - z27.s }, { z8.s - z11.s }
+
+	frintm	{ z0.s, z1.s }, { z0.s - z1.s }
+	frintm	{ z30.s, z31.s }, { z0.s - z1.s }
+	frintm	{ z0.s, z1.s }, { z30.s - z31.s }
+	frintm	{ z10.s, z11.s }, { z26.s - z27.s }
+
+	frintm	{ z0.s - z3.s }, { z0.s - z3.s }
+	frintm	{ z28.s - z31.s }, { z0.s - z3.s }
+	frintm	{ z0.s - z3.s }, { z28.s - z31.s }
+	frintm	{ z24.s - z27.s }, { z8.s - z11.s }
+
+	frintn	{ z0.s, z1.s }, { z0.s - z1.s }
+	frintn	{ z30.s, z31.s }, { z0.s - z1.s }
+	frintn	{ z0.s, z1.s }, { z30.s - z31.s }
+	frintn	{ z10.s, z11.s }, { z26.s - z27.s }
+
+	frintn	{ z0.s - z3.s }, { z0.s - z3.s }
+	frintn	{ z28.s - z31.s }, { z0.s - z3.s }
+	frintn	{ z0.s - z3.s }, { z28.s - z31.s }
+	frintn	{ z24.s - z27.s }, { z8.s - z11.s }
+
+	frintp	{ z0.s, z1.s }, { z0.s - z1.s }
+	frintp	{ z30.s, z31.s }, { z0.s - z1.s }
+	frintp	{ z0.s, z1.s }, { z30.s - z31.s }
+	frintp	{ z10.s, z11.s }, { z26.s - z27.s }
+
+	frintp	{ z0.s - z3.s }, { z0.s - z3.s }
+	frintp	{ z28.s - z31.s }, { z0.s - z3.s }
+	frintp	{ z0.s - z3.s }, { z28.s - z31.s }
+	frintp	{ z24.s - z27.s }, { z8.s - z11.s }
+
+	scvtf	{ z0.s, z1.s }, { z0.s - z1.s }
+	scvtf	{ z30.s, z31.s }, { z0.s - z1.s }
+	scvtf	{ z0.s, z1.s }, { z30.s - z31.s }
+	scvtf	{ z10.s, z11.s }, { z26.s - z27.s }
+
+	scvtf	{ z0.s - z3.s }, { z0.s - z3.s }
+	scvtf	{ z28.s - z31.s }, { z0.s - z3.s }
+	scvtf	{ z0.s - z3.s }, { z28.s - z31.s }
+	scvtf	{ z24.s - z27.s }, { z8.s - z11.s }
+
+	ucvtf	{ z0.s, z1.s }, { z0.s - z1.s }
+	ucvtf	{ z30.s, z31.s }, { z0.s - z1.s }
+	ucvtf	{ z0.s, z1.s }, { z30.s - z31.s }
+	ucvtf	{ z10.s, z11.s }, { z26.s - z27.s }
+
+	ucvtf	{ z0.s - z3.s }, { z0.s - z3.s }
+	ucvtf	{ z28.s - z31.s }, { z0.s - z3.s }
+	ucvtf	{ z0.s - z3.s }, { z28.s - z31.s }
+	ucvtf	{ z24.s - z27.s }, { z8.s - z11.s }