aarch64: Add the SVE BFMLSL instructions

This patch adds the SVE BFMLSLB and BFMLSLT instructions,
which are available when FEAT_SME2 is implemented.

7 files changed, 143 insertions, 0 deletions

diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.d b/gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.d
new file mode 100644
index 00000000000..2d3dbdb187c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme2
+#source: sve2-sme2-3-invalid.s
+#error_output: sve2-sme2-3-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.l b/gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.l
new file mode 100644
index 00000000000..195931c7aad
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.l
@@ -0,0 +1,17 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `bfmlslb 0,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bfmlslb z0\.s,0,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bfmlslb z0\.s,z0\.h,0'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfmlslb z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlslb z0\.s,z0\.h,z0\.h\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlslb z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlslb z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	bfmlslb z0\.s, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlslb z0\.d,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	bfmlslb z0\.s, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Warning: output register of preceding `movprfx' used as input at operand 2 -- `bfmlslb z0\.s,z0\.h,z1\.h\[0\]'
+[^ :]+:[0-9]+: Warning: output register of preceding `movprfx' not used in current instruction at operand 1 -- `bfmlslb z0\.s,z1\.h,z2\.h\[0\]'
+[^ :]+:[0-9]+: Warning: predicated instruction expected after `movprfx' -- `bfmlslb z0\.s,z1\.h,z2\.h\[0\]'
+[^ :]+:[0-9]+: Warning: predicated instruction expected after `movprfx' -- `bfmlslb z0\.s,z1\.h,z2\.h\[0\]'
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.s b/gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.s
new file mode 100644
index 00000000000..f553e12d8f3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.s
@@ -0,0 +1,15 @@
+	bfmlslb	0, z0.h, z0.h[0]
+	bfmlslb	z0.s, 0, z0.h[0]
+	bfmlslb	z0.s, z0.h, 0
+
+	bfmlslb	z0.s, z0.h, z8.h[0]
+	bfmlslb	z0.s, z0.h, z0.h[-1]
+	bfmlslb	z0.s, z0.h, z0.h[8]
+	bfmlslb	z0.h, z0.h, z0.h[0]
+	bfmlslb	z0.d, z0.h, z0.h[0]
+
+	movprfx	z0, z1; bfmlslb z0.s, z0.h, z1.h[0]
+	movprfx	z0, z1; bfmlslb z0.s, z1.h, z0.h[0]
+	movprfx	z3, z4; bfmlslb z0.s, z1.h, z2.h[0]
+	movprfx	z0.s, p0/m, z1.s; bfmlslb z0.s, z1.h, z2.h[0]
+	movprfx	z0.s, p0/z, z1.s; bfmlslb z0.s, z1.h, z2.h[0]
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-3-noarch.d b/gas/testsuite/gas/aarch64/sve2-sme2-3-noarch.d
new file mode 100644
index 00000000000..6e7278ee00d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-3-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme
+#source: sve2-sme2-3.s
+#error_output: sve2-sme2-3-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-3-noarch.l b/gas/testsuite/gas/aarch64/sve2-sme2-3-noarch.l
new file mode 100644
index 00000000000..5015005aedb
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-3-noarch.l
@@ -0,0 +1,29 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb Z0\.S,Z0\.H,Z0\.H\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z31\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z31\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z0\.h,z7\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z0\.h,z0\.h\[7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z5\.s,z22\.h,z4\.h\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z1\.h,z1\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z31\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z31\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z0\.h,z31\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z25\.s,z13\.h,z6\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z1\.h,z2\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt Z0\.S,Z0\.H,Z0\.H\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z31\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z31\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z0\.h,z7\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z0\.h,z0\.h\[7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z5\.s,z22\.h,z4\.h\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z1\.h,z1\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z31\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z31\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z0\.h,z31\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z25\.s,z13\.h,z6\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z1\.h,z2\.h'
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-3.d b/gas/testsuite/gas/aarch64/sve2-sme2-3.d
new file mode 100644
index 00000000000..2095aba0e65
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-3.d
@@ -0,0 +1,41 @@
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+:	64e06000 	bfmlslb	z0\.s, z0\.h, z0\.h\[0\]
+[^:]+:	64e06000 	bfmlslb	z0\.s, z0\.h, z0\.h\[0\]
+[^:]+:	64e0601f 	bfmlslb	z31\.s, z0\.h, z0\.h\[0\]
+[^:]+:	64e063e0 	bfmlslb	z0\.s, z31\.h, z0\.h\[0\]
+[^:]+:	64e76000 	bfmlslb	z0\.s, z0\.h, z7\.h\[0\]
+[^:]+:	64f86800 	bfmlslb	z0\.s, z0\.h, z0\.h\[7\]
+[^:]+:	64ec6ac5 	bfmlslb	z5\.s, z22\.h, z4\.h\[3\]
+[^:]+:	0420bc20 	movprfx	z0, z1
+[^:]+:	64e16020 	bfmlslb	z0\.s, z1\.h, z1\.h\[0\]
+[^:]+:	64e0a000 	bfmlslb	z0\.s, z0\.h, z0\.h
+[^:]+:	64e0a01f 	bfmlslb	z31\.s, z0\.h, z0\.h
+[^:]+:	64e0a3e0 	bfmlslb	z0\.s, z31\.h, z0\.h
+[^:]+:	64ffa000 	bfmlslb	z0\.s, z0\.h, z31\.h
+[^:]+:	64e6a1b9 	bfmlslb	z25\.s, z13\.h, z6\.h
+[^:]+:	0420bc20 	movprfx	z0, z1
+[^:]+:	64e2a020 	bfmlslb	z0\.s, z1\.h, z2\.h
+[^:]+:	64e06400 	bfmlslt	z0\.s, z0\.h, z0\.h\[0\]
+[^:]+:	64e06400 	bfmlslt	z0\.s, z0\.h, z0\.h\[0\]
+[^:]+:	64e0641f 	bfmlslt	z31\.s, z0\.h, z0\.h\[0\]
+[^:]+:	64e067e0 	bfmlslt	z0\.s, z31\.h, z0\.h\[0\]
+[^:]+:	64e76400 	bfmlslt	z0\.s, z0\.h, z7\.h\[0\]
+[^:]+:	64f86c00 	bfmlslt	z0\.s, z0\.h, z0\.h\[7\]
+[^:]+:	64ec6ec5 	bfmlslt	z5\.s, z22\.h, z4\.h\[3\]
+[^:]+:	0420bc20 	movprfx	z0, z1
+[^:]+:	64e16420 	bfmlslt	z0\.s, z1\.h, z1\.h\[0\]
+[^:]+:	64e0a400 	bfmlslt	z0\.s, z0\.h, z0\.h
+[^:]+:	64e0a41f 	bfmlslt	z31\.s, z0\.h, z0\.h
+[^:]+:	64e0a7e0 	bfmlslt	z0\.s, z31\.h, z0\.h
+[^:]+:	64ffa400 	bfmlslt	z0\.s, z0\.h, z31\.h
+[^:]+:	64e6a5b9 	bfmlslt	z25\.s, z13\.h, z6\.h
+[^:]+:	0420bc20 	movprfx	z0, z1
+[^:]+:	64e2a420 	bfmlslt	z0\.s, z1\.h, z2\.h
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-3.s b/gas/testsuite/gas/aarch64/sve2-sme2-3.s
new file mode 100644
index 00000000000..2347efa27fc
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-3.s
@@ -0,0 +1,35 @@
+	bfmlslb	z0.s, z0.h, z0.h[0]
+	BFMLSLB	Z0.S, Z0.H, Z0.H[0]
+	bfmlslb	z31.s, z0.h, z0.h[0]
+	bfmlslb	z0.s, z31.h, z0.h[0]
+	bfmlslb	z0.s, z0.h, z7.h[0]
+	bfmlslb	z0.s, z0.h, z0.h[7]
+	bfmlslb	z5.s, z22.h, z4.h[3]
+
+	movprfx	z0, z1; bfmlslb	z0.s, z1.h, z1.h[0]
+
+	bfmlslb	z0.s, z0.h, z0.h
+	bfmlslb	z31.s, z0.h, z0.h
+	bfmlslb	z0.s, z31.h, z0.h
+	bfmlslb	z0.s, z0.h, z31.h
+	bfmlslb	z25.s, z13.h, z6.h
+
+	movprfx	z0, z1; bfmlslb	z0.s, z1.h, z2.h
+
+	bfmlslt	z0.s, z0.h, z0.h[0]
+	BFMLSLT	Z0.S, Z0.H, Z0.H[0]
+	bfmlslt	z31.s, z0.h, z0.h[0]
+	bfmlslt	z0.s, z31.h, z0.h[0]
+	bfmlslt	z0.s, z0.h, z7.h[0]
+	bfmlslt	z0.s, z0.h, z0.h[7]
+	bfmlslt	z5.s, z22.h, z4.h[3]
+
+	movprfx	z0, z1; bfmlslt	z0.s, z1.h, z1.h[0]
+
+	bfmlslt	z0.s, z0.h, z0.h
+	bfmlslt	z31.s, z0.h, z0.h
+	bfmlslt	z0.s, z31.h, z0.h
+	bfmlslt	z0.s, z0.h, z31.h
+	bfmlslt	z25.s, z13.h, z6.h
+
+	movprfx	z0, z1; bfmlslt	z0.s, z1.h, z2.h