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| author | Yvan Roux <yvan.roux@foss.st.com> | 2022-06-29 14:01:45 +0200 |
|---|---|---|
| committer | Yvan Roux <yvan.roux@foss.st.com> | 2022-06-29 14:03:26 +0200 |
| commit | 69b46464badb01340a88d0ee57cdef0b7fdf545e (patch) | |
| tree | 5f0e91db77fc88362c128ba2dc6724414e5878d7 /gdb/arch | |
| parent | 6837a663c55602490ed095e5891e0c4deff4b9db (diff) | |
| download | binutils-gdb-69b46464badb01340a88d0ee57cdef0b7fdf545e.tar.gz | |
gdb/arm: Only stack S16..S31 when FPU registers are secure
The FPCCR.TS bit is used to identify if FPU registers are considered
non-secure or secure. If they are secure, then callee saved registers
(S16 to S31) are stacked on exception entry or otherwise skipped.
Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
Signed-off-by: Yvan Roux <yvan.roux@foss.st.com>
Diffstat (limited to 'gdb/arch')
| -rw-r--r-- | gdb/arch/arm.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h index 4ad329f6f1f..36757493406 100644 --- a/gdb/arch/arm.h +++ b/gdb/arch/arm.h @@ -109,6 +109,15 @@ enum arm_m_profile_type { ARM_M_TYPE_INVALID }; +/* System control registers accessible through an addresses. */ +enum system_register_address : CORE_ADDR +{ + /* M-profile Floating-Point Context Control Register address, defined in + ARMv7-M (Section B3.2.2) and ARMv8-M (Section D1.2.99) reference + manuals. */ + FPCCR = 0xe000ef34 +}; + /* Instruction condition field values. */ #define INST_EQ 0x0 #define INST_NE 0x1 |