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| author | Yvan Roux <yvan.roux@foss.st.com> | 2022-06-29 14:01:45 +0200 |
|---|---|---|
| committer | Yvan Roux <yvan.roux@foss.st.com> | 2022-06-29 14:03:26 +0200 |
| commit | 69b46464badb01340a88d0ee57cdef0b7fdf545e (patch) | |
| tree | 5f0e91db77fc88362c128ba2dc6724414e5878d7 /gdb/arm-tdep.c | |
| parent | 6837a663c55602490ed095e5891e0c4deff4b9db (diff) | |
| download | binutils-gdb-69b46464badb01340a88d0ee57cdef0b7fdf545e.tar.gz | |
gdb/arm: Only stack S16..S31 when FPU registers are secure
The FPCCR.TS bit is used to identify if FPU registers are considered
non-secure or secure. If they are secure, then callee saved registers
(S16 to S31) are stacked on exception entry or otherwise skipped.
Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
Signed-off-by: Yvan Roux <yvan.roux@foss.st.com>
Diffstat (limited to 'gdb/arm-tdep.c')
| -rw-r--r-- | gdb/arm-tdep.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index e36bde9b3da..3a1b52c2380 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3573,6 +3573,13 @@ arm_m_exception_cache (struct frame_info *this_frame) { int i; int fpu_regs_stack_offset; + ULONGEST fpccr; + + /* Read FPCCR register. */ + gdb_assert (safe_read_memory_unsigned_integer (FPCCR, + ARM_INT_REGISTER_SIZE, + byte_order, &fpccr)); + bool fpccr_ts = bit (fpccr,26); /* This code does not take into account the lazy stacking, see "Lazy context save of FP state", in B1.5.7, also ARM AN298, supported @@ -3592,7 +3599,7 @@ arm_m_exception_cache (struct frame_info *this_frame) cache->saved_regs[ARM_FPSCR_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x60); fpu_regs_stack_offset += 4; - if (tdep->have_sec_ext && !default_callee_register_stacking) + if (tdep->have_sec_ext && !default_callee_register_stacking && fpccr_ts) { /* Handle floating-point callee saved registers. */ fpu_regs_stack_offset = unwound_sp + sp_r0_offset + 0x68; |