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| author | Luis Machado <luis.machado@arm.com> | 2022-10-26 13:00:17 +0100 |
|---|---|---|
| committer | Luis Machado <luis.machado@arm.com> | 2022-10-26 13:00:17 +0100 |
| commit | b2e9e754e122d97511bbd6b990e38a23dafb6176 (patch) | |
| tree | d9a7b718b8d4aaf9097c9e88cba9c93008453cc5 /gdb/arm-tdep.c | |
| parent | 8b73ee207c9c4b2d692a82a29d1cee2dcfa07394 (diff) | |
| download | binutils-gdb-b2e9e754e122d97511bbd6b990e38a23dafb6176.tar.gz | |
gdb/arm: fix IPSR field test in arm_m_exception_cache ()
Arm v8-M Architecture Reference Manual,
D1.2.141 IPSR, Interrupt Program Status Register reads
"Exception, bits [8:0]"
9 bits, not 8! It is uncommon but true!
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'gdb/arm-tdep.c')
| -rw-r--r-- | gdb/arm-tdep.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index ae0882f9c4a..247e5522b8e 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3441,7 +3441,7 @@ arm_m_exception_cache (frame_info_ptr this_frame) } ULONGEST xpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM); - if ((xpsr & 0xff) != 0) + if ((xpsr & 0x1ff) != 0) /* Handler mode: This is the mode that exceptions are handled in. */ arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_s_regnum); else |