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| author | jiawei <jiawei@iscas.ac.cn> | 2021-11-17 20:10:07 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2021-11-18 14:43:23 +0800 |
| commit | de83e5142d054218f476f7364f795bcaa30efd3f (patch) | |
| tree | ca33a98af3306f2a3373a7dc238d0247f6e2d703 /include | |
| parent | da05b70e56866fd39288f4ff531ddfa6cb988514 (diff) | |
| download | binutils-gdb-de83e5142d054218f476f7364f795bcaa30efd3f.tar.gz | |
RISC-V: Add instructions and operand set for z[fdq]inx
Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to
verify if z*inx enabled and use gpr instead of fpr when z*inx is enable.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Added support for
z*inx extension.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Added register choice for z*inx.
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx.
opcodes/ChangeLog:
* riscv-dis.c (riscv_disassemble_insn): Added disassemble check for
z*inx.
* riscv-opc.c: Reused INSN_CLASS_* for z*inx.
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index eb734d0a54c..8cb4fd23756 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -369,6 +369,9 @@ enum riscv_insn_class INSN_CLASS_ZICSR, INSN_CLASS_ZIFENCEI, INSN_CLASS_ZIHINTPAUSE, + INSN_CLASS_F_OR_ZFINX, + INSN_CLASS_D_OR_ZDINX, + INSN_CLASS_Q_OR_ZQINX, INSN_CLASS_ZBA, INSN_CLASS_ZBB, INSN_CLASS_ZBC, |