RISC-V: Don't generate the ELF privilege attributes when no CSR are used.

	gas/
	* config/tc-riscv.c (explicit_csr): New static boolean.
	Used to indicate CSR are explictly used.
	(riscv_ip): Set explicit_csr to TRUE if any CSR is used.
	(riscv_write_out_attrs): If we already have set elf priv
	attributes, then generate them.  Otherwise, don't generate
	them when no CSR are used.

	* testsuite/gas/riscv/attribute-01.d: Remove the priv attributes.
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: Likewise.
	* testsuite/gas/riscv/attribute-10.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-11.s: New testcase.
	* testsuite/gas/riscv/attribute-11.d: New testcase.  The CSR is
	used, so we should output the ELF priv attributes.
	* testsuite/gas/riscv/attribute-12.d: New testcase.  The CSR is
	used, so output the priv attributes according to the -mpriv-spec.
	* testsuite/gas/riscv/attribute-13.d: New testcase.  The CSR isn't
	used, so ignore the -mpriv-spec setting.

	ld/
	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
	* testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.

11 files changed, 15 insertions, 27 deletions

diff --git a/ld/ChangeLog b/ld/ChangeLog
index 00066c59c07..5b6805a31bc 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,17 @@
+2020-06-05  Nelson Chu  <nelson.chu@sifive.com>
+
+	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: The CSR isn't used,
+	so ignore the -mpriv-spec setting.
+	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
+	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
+	* testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.
+
 2020-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR ld/26080
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
index 032f9641ad2..5baaba4c16f 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
@@ -7,6 +7,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: "rv32i2p0_m2p0"
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
index 54a7621f2c3..a7d79a1ea2b 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
@@ -7,6 +7,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: "rv32i2p0_m2p0"
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
index 67f0437e328..d46dee808de 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
@@ -7,6 +7,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0"
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
index 5585fac3b7b..e4d965a3e99 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
@@ -8,6 +8,4 @@ Attribute Section: riscv
 File Attributes
   Tag_RISCV_stack_align: 16-bytes
   Tag_RISCV_arch: [a-zA-Z0-9_\"].*
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
 #...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
index 91011a2ba4d..10399307bbb 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
@@ -8,6 +8,3 @@ Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: [a-zA-Z0-9_\"].*
   Tag_RISCV_unaligned_access: Unaligned access
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
index 5bdea27948b..12ca1c4dd31 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
@@ -8,6 +8,3 @@ Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: [a-zA-Z0-9_\"].*
   Tag_RISCV_unaligned_access: Unaligned access
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
index ac886fb7681..e41351da011 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
@@ -8,6 +8,3 @@ Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: [a-zA-Z0-9_\"].*
   Tag_RISCV_unaligned_access: Unaligned access
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
index dd45f76317a..ac2a766cfca 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
@@ -7,6 +7,3 @@
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: [a-zA-Z0-9_\"].*
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
index ef0c154a121..608c05e8c38 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
@@ -8,6 +8,3 @@ Attribute Section: riscv
 File Attributes
   Tag_RISCV_arch: [a-zA-Z0-9_\"].*
   Tag_RISCV_unaligned_access: Unaligned access
-  Tag_RISCV_priv_spec: [0-9_\"].*
-  Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d
index 46d9c84f35f..597ff675353 100644
--- a/ld/testsuite/ld-riscv-elf/call-relax.d
+++ b/ld/testsuite/ld-riscv-elf/call-relax.d
@@ -3,7 +3,7 @@
 #source: call-relax-1.s
 #source: call-relax-2.s
 #source: call-relax-3.s
-#as: -march=rv32ic
+#as: -march=rv32ic -mno-arch-attr
 #ld: -melf32lriscv
 #objdump: -d
 #pass