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| author | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:22 +0100 |
|---|---|---|
| committer | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:22 +0100 |
| commit | 3c17238bc9fe8a078a6199470291f07bab9c64c8 (patch) | |
| tree | 31443cb03fc7932249004d085552ab29ab5a9556 /opcodes/aarch64-asm.c | |
| parent | cd50a87ae29f163e7d254729a902a5e51fcccbbc (diff) | |
| download | binutils-gdb-3c17238bc9fe8a078a6199470291f07bab9c64c8.tar.gz | |
[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.
Include a new iclass to extract the variant from the most significant 3
bits of this operand.
Instructions such as rshrnb include a constant shift amount as an
operand, where the most significant three bits of this operand determine
what size elements the instruction is operating on.
The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in
bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that
the SVE qualifier is encoded in bits 22:20-19.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
operand.
(enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-asm.c (aarch64_ins_sve_shrimm):
(aarch64_encode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass decode.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHRIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
operand.
Diffstat (limited to 'opcodes/aarch64-asm.c')
| -rw-r--r-- | opcodes/aarch64-asm.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 0ec27b24928..6be17f9246e 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1241,8 +1241,9 @@ aarch64_ins_sve_shrimm (const aarch64_operand *self, const aarch64_opnd_info *prev_operand; unsigned int esize; - assert (info->idx > 0); - prev_operand = &inst->operands[info->idx - 1]; + unsigned int opnd_backshift = get_operand_specific_data (self); + assert (info->idx >= (int)opnd_backshift); + prev_operand = &inst->operands[info->idx - opnd_backshift]; esize = aarch64_get_qualifier_esize (prev_operand->qualifier); insert_all_fields (self, code, 16 * esize - info->imm.value); return TRUE; @@ -1624,6 +1625,7 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) case sve_index: case sve_shift_pred: case sve_shift_unpred: + case sve_shift_tsz_hsd: /* For indices and shift amounts, the variant is encoded as part of the immediate. */ break; |