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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:11 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:11 +0100 |
| commit | 503fae12992e5dbf48b4e30cea8d35f31d87effe (patch) | |
| tree | c1bd390a4f96d3ac0632de6ce917683fccf56667 /opcodes/aarch64-asm.c | |
| parent | 586c62819f6eb9a77978628afd53ba12c91a11e7 (diff) | |
| download | binutils-gdb-503fae12992e5dbf48b4e30cea8d35f31d87effe.tar.gz | |
aarch64: Add support for predicate-as-counter registers
SME2 adds a new format for the existing SVE predicate registers:
predicates as counters rather than predicates as masks. In assembly
code, operands that interpret predicates as counters are written
pn<N> rather than p<N>.
This patch adds support for these registers and extends some
existing instructions to support them. Since the new forms
are just a programmer convenience, there's no need to make them
more restrictive than the earlier predicate-as-mask forms.
Diffstat (limited to 'opcodes/aarch64-asm.c')
| -rw-r--r-- | opcodes/aarch64-asm.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 5a9ca5a980d..10b70824b05 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1643,6 +1643,7 @@ do_misc_encoding (aarch64_inst *inst) encode_asisd_fcvtxn (inst); break; case OP_MOV_P_P: + case OP_MOV_PN_PN: case OP_MOVS_P_P: /* Copy Pn to Pm and Pg. */ value = extract_field (FLD_SVE_Pn, inst->value, 0); |