aarch64: Add the SME2 multivector LD1 and ST1 instructions

SME2 adds LD1 and ST1 variants for lists of 2 and 4 registers.
The registers can be consecutive or strided.  In the strided case,
2-register lists have a stride of 8, starting at register x0xxx.
4-register lists have a stride of 4, starting at register x00xx.

The instructions are predicated on a predicate-as-counter register in
the range pn8-pn15.  Although we already had register fields with upper
bounds of 7 and 15, this is the first plain register operand to have a
nonzero lower bound.  The patch uses the operand-specific data field
to record the minimum value, rather than having separate inserters
and extractors for each lower bound.  This in turn required adding
an extra bit to the field.

1 files changed, 22 insertions, 1 deletions

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 516aa8ecb81..42cc6f75677 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -96,7 +96,8 @@ aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info,
 		   const aarch64_inst *inst ATTRIBUTE_UNUSED,
 		   aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {
-  insert_field (self->fields[0], code, info->reg.regno, 0);
+  int val = info->reg.regno - get_operand_specific_data (self);
+  insert_field (self->fields[0], code, val, 0);
   return true;
 }
 
@@ -1245,6 +1246,26 @@ aarch64_ins_sve_reglist (const aarch64_operand *self,
   return true;
 }
 
+/* Encode a strided register list.  The first field holds the top bit
+   (0 or 16) and the second field holds the lower bits.  The stride is
+   16 divided by the list length.  */
+bool
+aarch64_ins_sve_strided_reglist (const aarch64_operand *self,
+				 const aarch64_opnd_info *info,
+				 aarch64_insn *code,
+				 const aarch64_inst *inst ATTRIBUTE_UNUSED,
+				 aarch64_operand_error *errors
+				   ATTRIBUTE_UNUSED)
+{
+  unsigned int num_regs = get_operand_specific_data (self);
+  unsigned int mask = 16 | (16 / num_regs - 1);
+  unsigned int val = info->reglist.first_regno;
+  assert ((val & mask) == val);
+  insert_field (self->fields[0], code, val >> 4, 0);
+  insert_field (self->fields[1], code, val & 15, 0);
+  return true;
+}
+
 /* Encode <pattern>{, MUL #<amount>}.  The fields array specifies which
    fields to use for <pattern>.  <amount> - 1 is encoded in the SVE_imm4
    field.  */