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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 20:26:53 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 20:27:42 +0000 |
| commit | d3de0860104b8bb8d496527fbb042c3b4c5c82dc (patch) | |
| tree | d639da6b0a9e7bc01d3331c170d7e15099299203 /opcodes/aarch64-asm.c | |
| parent | 8f1bfdb44894423680a6d56a0994dafb4b82efca (diff) | |
| download | binutils-gdb-d3de0860104b8bb8d496527fbb042c3b4c5c82dc.tar.gz | |
aarch64: [SME] SVE2 instructions added to support SME
This patch is adding new SVE2 instructions added to support SME extension.
The following SVE2 instructions are added by the SME architecture:
* PSEL,
* REVD, SCLAMP and UCLAMP.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sme_pred_reg_with_index):
New parser.
(parse_operands): New parser.
* testsuite/gas/aarch64/sme-9-illegal.d: New test.
* testsuite/gas/aarch64/sme-9-illegal.l: New test.
* testsuite/gas/aarch64/sme-9-illegal.s: New test.
* testsuite/gas/aarch64/sme-9.d: New test.
* testsuite/gas/aarch64/sme-9.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New operand
AARCH64_OPND_SME_PnT_Wm_imm.
opcodes/ChangeLog:
* aarch64-asm.c (aarch64_ins_sme_pred_reg_with_index):
New inserter.
* aarch64-dis.c (aarch64_ext_sme_pred_reg_with_index):
New extractor.
* aarch64-opc.c (aarch64_print_operand): Printout of
OPND_SME_PnT_Wm_imm.
* aarch64-opc.h (enum aarch64_field_kind): New bitfields
FLD_SME_Rm, FLD_SME_i1, FLD_SME_tszh, FLD_SME_tszl.
* aarch64-tbl.h (OP_SVE_NN_BHSD): New qualifier.
(OP_SVE_QMQ): New qualifier.
(struct aarch64_opcode): New instructions PSEL, REVD,
SCLAMP and UCLAMP.
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
Diffstat (limited to 'opcodes/aarch64-asm.c')
| -rw-r--r-- | opcodes/aarch64-asm.c | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index b9aff950a03..fd5412aa38b 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1452,6 +1452,73 @@ aarch64_ins_sme_sm_za (const aarch64_operand *self, return true; } +/* Encode source scalable predicate register (Pn), name of the index base + register W12-W15 (Rm), and optional element index, defaulting to 0, in the + range 0 to one less than the number of vector elements in a 128-bit vector + register, encoded in "i1:tszh:tszl". +*/ +bool +aarch64_ins_sme_pred_reg_with_index (const aarch64_operand *self, + const aarch64_opnd_info *info, + aarch64_insn *code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + int fld_pn = info->za_tile_vector.regno; + int fld_rm = info->za_tile_vector.index.regno - 12; + int imm = info->za_tile_vector.index.imm; + int fld_i1, fld_tszh, fld_tshl; + + insert_field (self->fields[0], code, fld_rm, 0); + insert_field (self->fields[1], code, fld_pn, 0); + + /* Optional element index, defaulting to 0, in the range 0 to one less than + the number of vector elements in a 128-bit vector register, encoded in + "i1:tszh:tszl". + + i1 tszh tszl <T> + 0 0 000 RESERVED + x x xx1 B + x x x10 H + x x 100 S + x 1 000 D + */ + switch (info->qualifier) + { + case AARCH64_OPND_QLF_S_B: + /* <imm> is 4 bit value. */ + fld_i1 = (imm >> 3) & 0x1; + fld_tszh = (imm >> 2) & 0x1; + fld_tshl = ((imm << 1) | 0x1) & 0x7; + break; + case AARCH64_OPND_QLF_S_H: + /* <imm> is 3 bit value. */ + fld_i1 = (imm >> 2) & 0x1; + fld_tszh = (imm >> 1) & 0x1; + fld_tshl = ((imm << 2) | 0x2) & 0x7; + break; + case AARCH64_OPND_QLF_S_S: + /* <imm> is 2 bit value. */ + fld_i1 = (imm >> 1) & 0x1; + fld_tszh = imm & 0x1; + fld_tshl = 0x4; + break; + case AARCH64_OPND_QLF_S_D: + /* <imm> is 1 bit value. */ + fld_i1 = imm & 0x1; + fld_tszh = 0x1; + fld_tshl = 0x0; + break; + default: + assert (0); + } + + insert_field (self->fields[2], code, fld_i1, 0); + insert_field (self->fields[3], code, fld_tszh, 0); + insert_field (self->fields[4], code, fld_tshl, 0); + return true; +} + /* Miscellaneous encoding functions. */ /* Encode size[0], i.e. bit 22, for |